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Constant tests for mulhdu, mulhw, mulhwu, mulld, mulli, mullw, neg, nor, ori, rldicl.

This commit is contained in:
gibbed 2015-05-13 02:38:56 -05:00
parent 6aec2c0d02
commit 5ebd4984ba
10 changed files with 564 additions and 0 deletions
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45
src/xenia/cpu/frontend/test/instr_mulhdu.s
View File

@ -7,6 +7,15 @@ test_mulhdu_1:
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhdu_1_constant:
li r4, 1
li r5, 0
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhdu_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
@ -16,6 +25,15 @@ test_mulhdu_2:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhdu_2_constant:
li r4, -1
li r5, 1
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhdu_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 2
@ -25,6 +43,15 @@ test_mulhdu_3:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mulhdu_3_constant:
li r4, -1
li r5, 2
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mulhdu_4:
#_ REGISTER_IN r4 0x8000000000000000
#_ REGISTER_IN r5 1
@ -34,6 +61,15 @@ test_mulhdu_4:
#_ REGISTER_OUT r4 0x8000000000000000
#_ REGISTER_OUT r5 1
test_mulhdu_4_constant:
li r5, 1
sldi r4, r5, 63
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x8000000000000000
#_ REGISTER_OUT r5 1
test_mulhdu_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
@ -42,3 +78,12 @@ test_mulhdu_5:
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_mulhdu_5_constant:
li r4, -1
li r5, -1
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF

60
src/xenia/cpu/frontend/test/instr_mulhw.s
View File

@ -7,6 +7,15 @@ test_mulhw_1:
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhw_1_constant:
li r4, 1
li r5, 0
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhw_2:
#_ REGISTER_IN r4 0x00000000FFFFFFFF
#_ REGISTER_IN r5 1
@ -16,6 +25,16 @@ test_mulhw_2:
#_ REGISTER_OUT r4 0x00000000FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_2_constant:
li r4, -1
clrldi r4, r4, 32
li r5, 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x00000000FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_3:
#_ REGISTER_IN r4 0x00000001FFFFFFFF
#_ REGISTER_IN r5 1
@ -25,6 +44,16 @@ test_mulhw_3:
#_ REGISTER_OUT r4 0x00000001FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_3_constant:
li r4, -1
clrldi r4, r4, 31
li r5, 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x00000001FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_4:
#_ REGISTER_IN r4 0x800000007FFFFFFF
#_ REGISTER_IN r5 1
@ -34,6 +63,19 @@ test_mulhw_4:
#_ REGISTER_OUT r4 0x800000007FFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_4_constant:
li r4, -1
clrldi r4, r4, 33
li r5, 1
sldi r5, r5, 63
or r4, r4, r5
li r5, 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x800000007FFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
@ -43,6 +85,15 @@ test_mulhw_5:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_5_constant:
li r4, -1
li r5, 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
@ -51,3 +102,12 @@ test_mulhw_6:
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_mulhw_6_constant:
li r4, -1
li r5, -1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF

60
src/xenia/cpu/frontend/test/instr_mulhwu.s
View File

@ -7,6 +7,15 @@ test_mulhwu_1:
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhwu_1_constant:
li r4, 1
li r5, 0
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhwu_2:
#_ REGISTER_IN r4 0x00000000FFFFFFFF
#_ REGISTER_IN r5 1
@ -16,6 +25,16 @@ test_mulhwu_2:
#_ REGISTER_OUT r4 0x00000000FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_2_constant:
li r4, -1
clrldi r4, r4, 32
li r5, 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x00000000FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_3:
#_ REGISTER_IN r4 0x00000001FFFFFFFF
#_ REGISTER_IN r5 1
@ -25,6 +44,16 @@ test_mulhwu_3:
#_ REGISTER_OUT r4 0x00000001FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_3_constant:
li r4, -1
clrldi r4, r4, 31
li r5, 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x00000001FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_4:
#_ REGISTER_IN r4 0x800000007FFFFFFF
#_ REGISTER_IN r5 1
@ -34,6 +63,19 @@ test_mulhwu_4:
#_ REGISTER_OUT r4 0x800000007FFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_4_constant:
li r4, -1
clrldi r4, r4, 33
li r5, 1
sldi r5, r5, 63
or r4, r4, r5
li r5, 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x800000007FFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
@ -43,6 +85,15 @@ test_mulhwu_5:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_5_constant:
li r4, -1
li r5, 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
@ -51,3 +102,12 @@ test_mulhwu_6:
#_ REGISTER_OUT r3 0x00000000FFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_mulhwu_6_constant:
li r4, -1
li r5, -1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF

71
src/xenia/cpu/frontend/test/instr_mulld.s
View File

@ -7,6 +7,15 @@ test_mulld_1:
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulld_1_constant:
li r4, 1
li r5, 0
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulld_2:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 1
@ -16,6 +25,15 @@ test_mulld_2:
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 1
test_mulld_2_constant:
li r4, 1
li r5, 1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 1
test_mulld_3:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 -1
@ -25,6 +43,15 @@ test_mulld_3:
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mulld_3_constant:
li r4, 1
li r5, -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mulld_4:
#_ REGISTER_IN r4 123
#_ REGISTER_IN r5 -1
@ -34,6 +61,15 @@ test_mulld_4:
#_ REGISTER_OUT r4 123
#_ REGISTER_OUT r5 -1
test_mulld_4_constant:
li r4, 123
li r5, -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 -123
#_ REGISTER_OUT r4 123
#_ REGISTER_OUT r5 -1
test_mulld_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
@ -43,6 +79,15 @@ test_mulld_5:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulld_5_constant:
li r4, -1
li r5, 1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulld_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 2
@ -52,6 +97,15 @@ test_mulld_6:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mulld_6_constant:
li r4, -1
li r5, 2
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mulld_7:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 -1
@ -61,6 +115,15 @@ test_mulld_7:
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mulld_7_constant:
li r4, 1
li r5, -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mulld_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 -1
@ -70,3 +133,11 @@ test_mulld_8:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 -1
test_mulld_8_constant:
li r4, -1
li r5, -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 -1

55
src/xenia/cpu/frontend/test/instr_mulli.s
View File

@ -5,6 +5,13 @@ test_mulli_1:
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_mulli_1_constant:
li r4, 1
mulli r3, r4, 0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_mulli_2:
#_ REGISTER_IN r4 1
mulli r3, r4, 1
@ -12,6 +19,13 @@ test_mulli_2:
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
test_mulli_2_constant:
li r4, 1
mulli r3, r4, 1
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
test_mulli_3:
#_ REGISTER_IN r4 1
mulli r3, r4, -1
@ -19,6 +33,13 @@ test_mulli_3:
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 1
test_mulli_3_constant:
li r4, 1
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 1
test_mulli_4:
#_ REGISTER_IN r4 123
mulli r3, r4, -1
@ -26,6 +47,13 @@ test_mulli_4:
#_ REGISTER_OUT r3 -123
#_ REGISTER_OUT r4 123
test_mulli_4_constant:
li r4, 123
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 -123
#_ REGISTER_OUT r4 123
test_mulli_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
mulli r3, r4, 1
@ -33,6 +61,13 @@ test_mulli_5:
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
test_mulli_5_constant:
li r4, -1
mulli r3, r4, 1
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
test_mulli_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
mulli r3, r4, 2
@ -40,6 +75,13 @@ test_mulli_6:
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
test_mulli_6_constant:
li r4, -1
mulli r3, r4, 2
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
test_mulli_7:
#_ REGISTER_IN r4 1
mulli r3, r4, -1
@ -47,6 +89,13 @@ test_mulli_7:
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 1
test_mulli_7_constant:
li r4, 1
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 1
test_mulli_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
mulli r3, r4, -1
@ -54,3 +103,9 @@ test_mulli_8:
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
test_mulli_8_constant:
li r4, -1
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF

101
src/xenia/cpu/frontend/test/instr_mullw.s
View File

@ -7,6 +7,15 @@ test_mullw_1:
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mullw_1_constant:
li r4, 1
li r5, 0
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mullw_2:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 1
@ -16,6 +25,15 @@ test_mullw_2:
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 1
test_mullw_2_constant:
li r4, 1
li r5, 1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 1
test_mullw_3:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 -1
@ -25,6 +43,15 @@ test_mullw_3:
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mullw_3_constant:
li r4, 1
li r5, -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mullw_4:
#_ REGISTER_IN r4 123
#_ REGISTER_IN r5 -1
@ -34,6 +61,15 @@ test_mullw_4:
#_ REGISTER_OUT r4 123
#_ REGISTER_OUT r5 -1
test_mullw_4_constant:
li r4, 123
li r5, -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 -123
#_ REGISTER_OUT r4 123
#_ REGISTER_OUT r5 -1
test_mullw_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
@ -43,6 +79,15 @@ test_mullw_5:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mullw_5_constant:
li r4, -1
li r5, 1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mullw_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 2
@ -52,6 +97,15 @@ test_mullw_6:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mullw_6_constant:
li r4, -1
li r5, 2
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mullw_7:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 -1
@ -61,6 +115,15 @@ test_mullw_7:
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mullw_7_constant:
li r4, 1
li r5, -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mullw_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 -1
@ -70,6 +133,15 @@ test_mullw_8:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 -1
test_mullw_8_constant:
li r4, -1
li r5, -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 -1
test_mullw_9:
#_ REGISTER_IN r4 0xFFFFFFFF00000000
#_ REGISTER_IN r5 1
@ -79,6 +151,16 @@ test_mullw_9:
#_ REGISTER_OUT r4 0xFFFFFFFF00000000
#_ REGISTER_OUT r5 1
test_mullw_9_constant:
li r4, -1
sldi r4, r4, 32
li r5, 1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFF00000000
#_ REGISTER_OUT r5 1
test_mullw_10:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0xFFFFFFFF00000000
@ -88,6 +170,16 @@ test_mullw_10:
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0xFFFFFFFF00000000
test_mullw_10_constant:
li r4, 1
li r5, -1
sldi r5, r5, 32
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0xFFFFFFFF00000000
test_mullw_11:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0x000000007FFFFFFF
@ -97,3 +189,12 @@ test_mullw_11:
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0x000000007FFFFFFF
test_mullw_11_constant:
li r4, 1
li r5, -1
clrldi r5, r5, 33
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x000000007FFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0x000000007FFFFFFF

20
src/xenia/cpu/frontend/test/instr_neg.s
View File

@ -4,14 +4,34 @@ test_neg_1:
blr
#_ REGISTER_OUT r3 0xFFFFFFFF80000000
test_neg_1_constant:
li r3, 1
sldi r3, r3, 31
neg r3, r3
blr
#_ REGISTER_OUT r3 0xFFFFFFFF80000000
test_neg_2:
#_ REGISTER_IN r3 0x8000000000000000
neg r3, r3
blr
#_ REGISTER_OUT r3 0x8000000000000000
test_neg_2_constant:
li r3, 1
sldi r3, r3, 63
neg r3, r3
blr
#_ REGISTER_OUT r3 0x8000000000000000
test_neg_3:
#_ REGISTER_IN r3 0x0000000000000005
neg r3, r3
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFB
test_neg_3_constant:
li r3, 5
neg r3, r3
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFB

11
src/xenia/cpu/frontend/test/instr_nor.s
View File

@ -7,3 +7,14 @@ test_nor_cr_1:
.nor_cr_1_ne:
blr
#_ REGISTER_OUT r3 1
test_nor_cr_1_constant:
li r3, -1
clrldi r3, r3, 32
nor. r3, r3, r3
li r3, 0
bne .nor_cr_1_constant_ne
li r3, 1
.nor_cr_1_constant_ne:
blr
#_ REGISTER_OUT r3 1

25
src/xenia/cpu/frontend/test/instr_ori.s
View File

@ -1,3 +1,9 @@
.macro make_test_constant dest
lis \dest, 0xDEAD
ori \dest, \dest, 0xBEEF
sldi \dest, \dest, 32
.endm
test_ori_1:
#_ REGISTER_IN r4 0xDEADBEEF00000000
@ -7,6 +13,14 @@ test_ori_1:
#_ REGISTER_OUT r3 0xDEADBEEF0000FEDC
#_ REGISTER_OUT r4 0xDEADBEEF00000000
test_ori_1_constant:
make_test_constant r4
ori r3, r4, 0xFEDC
blr
#_ REGISTER_OUT r3 0xDEADBEEF0000FEDC
#_ REGISTER_OUT r4 0xDEADBEEF00000000
test_ori_2:
#_ REGISTER_IN r4 0xDEADBEEF10000000
@ -15,3 +29,14 @@ test_ori_2:
blr
#_ REGISTER_OUT r3 0xDEADBEEF1000FEDC
#_ REGISTER_OUT r4 0xDEADBEEF10000000
test_ori_2_constant:
make_test_constant r4
lis r3, 0x1000
or r4, r4, r3
ori r3, r4, 0xFEDC
blr
#_ REGISTER_OUT r3 0xDEADBEEF1000FEDC
#_ REGISTER_OUT r4 0xDEADBEEF10000000

116
src/xenia/cpu/frontend/test/instr_rldicl.s
View File

@ -1,3 +1,13 @@
.macro make_test_constant dest
lis \dest, 0x0123
ori \dest, \dest, 0x4567
sldi \dest, \dest, 32
lis r3, 0x89AB
ori r3, r3, 0xCDEF
clrldi r3, r3, 32
or \dest, \dest, r3
.endm
test_rldicl_1:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 24, 0
@ -5,6 +15,13 @@ test_rldicl_1:
#_ REGISTER_OUT r3 0x6789abcdef012345
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_1_constant:
make_test_constant r4
rldicl r3, r4, 24, 0
blr
#_ REGISTER_OUT r3 0x6789abcdef012345
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_2:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 24, 8
@ -12,6 +29,13 @@ test_rldicl_2:
#_ REGISTER_OUT r3 0x0089abcdef012345
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_2_constant:
make_test_constant r4
rldicl r3, r4, 24, 8
blr
#_ REGISTER_OUT r3 0x0089abcdef012345
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_3:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 24, 63
@ -19,6 +43,13 @@ test_rldicl_3:
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_3_constant:
make_test_constant r4
rldicl r3, r4, 24, 63
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_4:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 0, 0
@ -26,6 +57,13 @@ test_rldicl_4:
#_ REGISTER_OUT r3 0x0123456789abcdef
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_4_constant:
make_test_constant r4
rldicl r3, r4, 0, 0
blr
#_ REGISTER_OUT r3 0x0123456789abcdef
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_5:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 0, 63
@ -33,6 +71,13 @@ test_rldicl_5:
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_5_constant:
make_test_constant r4
rldicl r3, r4, 0, 63
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_6:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 0, 8
@ -40,6 +85,13 @@ test_rldicl_6:
#_ REGISTER_OUT r3 0x0023456789abcdef
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_6_constant:
make_test_constant r4
rldicl r3, r4, 0, 8
blr
#_ REGISTER_OUT r3 0x0023456789abcdef
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_7:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 63, 0
@ -47,6 +99,13 @@ test_rldicl_7:
#_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_7_constant:
make_test_constant r4
rldicl r3, r4, 63, 0
blr
#_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_8:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 63, 63
@ -54,6 +113,13 @@ test_rldicl_8:
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_8_constant:
make_test_constant r4
rldicl r3, r4, 63, 63
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_9:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 31, 0
@ -61,6 +127,13 @@ test_rldicl_9:
#_ REGISTER_OUT r3 0xc4d5e6f78091a2b3
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_9_constant:
make_test_constant r4
rldicl r3, r4, 31, 0
blr
#_ REGISTER_OUT r3 0xc4d5e6f78091a2b3
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_10:
#_ REGISTER_IN r4 0x16300000
rldicl r3, r4, 58, 6
@ -68,6 +141,13 @@ test_rldicl_10:
#_ REGISTER_OUT r3 0x58C000
#_ REGISTER_OUT r4 0x16300000
test_rldicl_10_constant:
lis r4, 0x1630
rldicl r3, r4, 58, 6
blr
#_ REGISTER_OUT r3 0x58C000
#_ REGISTER_OUT r4 0x16300000
test_srdi_1:
#_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r4 0x0123456789ABCDEF
@ -77,6 +157,15 @@ test_srdi_1:
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_srdi_1_constant:
make_test_constant r4
li r3, -1
srdi r3, r3, 0
srdi r4, r4, 0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_srdi_2:
#_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r4 0x0123456789ABCDEF
@ -86,6 +175,15 @@ test_srdi_2:
#_ REGISTER_OUT r3 0x7fffffffffffffff
#_ REGISTER_OUT r4 0x0091a2b3c4d5e6f7
test_srdi_2_constant:
make_test_constant r4
li r3, -1
srdi r3, r3, 1
srdi r4, r4, 1
blr
#_ REGISTER_OUT r3 0x7fffffffffffffff
#_ REGISTER_OUT r4 0x0091a2b3c4d5e6f7
test_srdi_3:
#_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r4 0x0123456789ABCDEF
@ -95,6 +193,15 @@ test_srdi_3:
#_ REGISTER_OUT r3 0x00000000ffffffff
#_ REGISTER_OUT r4 0x0000000001234567
test_srdi_3_constant:
make_test_constant r4
li r3, -1
srdi r3, r3, 32
srdi r4, r4, 32
blr
#_ REGISTER_OUT r3 0x00000000ffffffff
#_ REGISTER_OUT r4 0x0000000001234567
test_srdi_4:
#_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r4 0x0123456789ABCDEF
@ -103,3 +210,12 @@ test_srdi_4:
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0000000000000000
test_srdi_4_constant:
make_test_constant r4
li r3, -1
srdi r3, r3, 63
srdi r4, r4, 63
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0000000000000000