From 577ab0a4f166bc65b9e4c40898c7aceada3af015 Mon Sep 17 00:00:00 2001 From: Ben Vanik Date: Sat, 20 Dec 2014 22:17:57 -0800 Subject: [PATCH] Main window, empty GPU files. --- src/poly/sources.gypi | 1 + src/poly/threading.cc | 18 + src/poly/threading.h | 26 +- src/poly/threading_mac.cc | 2 +- src/poly/threading_posix.cc | 2 +- src/poly/threading_win.cc | 2 +- src/poly/ui/loop.h | 1 + src/poly/ui/win32/win32_loop.cc | 18 +- src/poly/ui/win32/win32_loop.h | 8 +- src/poly/ui/win32/win32_window.cc | 32 +- src/poly/ui/win32/win32_window.h | 8 + src/xenia/emulator.cc | 6 +- src/xenia/gpu/buffer_resource.cc | 56 - src/xenia/gpu/buffer_resource.h | 99 - src/xenia/gpu/command_processor.cc | 804 --- src/xenia/gpu/command_processor.h | 81 - src/xenia/gpu/draw_command.h | 74 - .../gl4_gpu-private.h} | 18 +- .../gpu/{nop/nop_gpu.cc => gl4/gl4_gpu.cc} | 30 +- .../gpu/{nop/nop_gpu.h => gl4/gl4_gpu.h} | 18 +- src/xenia/gpu/gl4/sources.gypi | 8 + src/xenia/gpu/gpu-private.h | 4 - src/xenia/gpu/gpu.cc | 45 +- src/xenia/gpu/gpu.h | 6 +- src/xenia/gpu/graphics_driver.cc | 307 - src/xenia/gpu/graphics_driver.h | 67 - src/xenia/gpu/graphics_system.cc | 173 +- src/xenia/gpu/graphics_system.h | 35 +- src/xenia/gpu/nop/nop_graphics_driver.cc | 38 - src/xenia/gpu/nop/nop_graphics_driver.h | 43 - src/xenia/gpu/nop/nop_graphics_system.cc | 72 - src/xenia/gpu/nop/nop_graphics_system.h | 43 - src/xenia/gpu/nop/sources.gypi | 12 - src/xenia/gpu/register_file.cc | 11 +- src/xenia/gpu/register_file.h | 15 +- src/xenia/gpu/{xenos => }/register_table.inc | 4956 ++++++++--------- src/xenia/gpu/resource.cc | 37 - src/xenia/gpu/resource.h | 100 - src/xenia/gpu/resource_cache.cc | 120 - src/xenia/gpu/resource_cache.h | 124 - src/xenia/gpu/sampler_state_resource.cc | 32 - src/xenia/gpu/sampler_state_resource.h | 68 - src/xenia/gpu/shader_resource.cc | 280 - src/xenia/gpu/shader_resource.h | 130 - src/xenia/gpu/sources.gypi | 33 +- src/xenia/gpu/texture_resource.cc | 363 -- src/xenia/gpu/texture_resource.h | 110 - src/xenia/gpu/{xenos => }/ucode.h | 1116 ++-- .../gpu/{xenos => }/ucode_disassembler.cc | 1519 +++-- .../gpu/{xenos => }/ucode_disassembler.h | 60 +- src/xenia/gpu/{xenos => }/xenos.h | 542 +- src/xenia/gpu/xenos/packets.h | 87 - src/xenia/gpu/xenos/sources.gypi | 11 - src/xenia/kernel/xboxkrnl_video.cc | 4 +- src/xenia/ui/main_window.cc | 48 +- src/xenia/ui/main_window.h | 11 +- src/xenia/xenia_main.cc | 67 +- 57 files changed, 4403 insertions(+), 7598 deletions(-) create mode 100644 src/poly/threading.cc delete mode 100644 src/xenia/gpu/buffer_resource.cc delete mode 100644 src/xenia/gpu/buffer_resource.h delete mode 100644 src/xenia/gpu/command_processor.cc delete mode 100644 src/xenia/gpu/command_processor.h delete mode 100644 src/xenia/gpu/draw_command.h rename src/xenia/gpu/{nop/nop_gpu-private.h => gl4/gl4_gpu-private.h} (73%) rename src/xenia/gpu/{nop/nop_gpu.cc => gl4/gl4_gpu.cc} (56%) rename src/xenia/gpu/{nop/nop_gpu.h => gl4/gl4_gpu.h} (68%) create mode 100644 src/xenia/gpu/gl4/sources.gypi delete mode 100644 src/xenia/gpu/graphics_driver.cc delete mode 100644 src/xenia/gpu/graphics_driver.h delete mode 100644 src/xenia/gpu/nop/nop_graphics_driver.cc delete mode 100644 src/xenia/gpu/nop/nop_graphics_driver.h delete mode 100644 src/xenia/gpu/nop/nop_graphics_system.cc delete mode 100644 src/xenia/gpu/nop/nop_graphics_system.h delete mode 100644 src/xenia/gpu/nop/sources.gypi rename src/xenia/gpu/{xenos => }/register_table.inc (98%) delete mode 100644 src/xenia/gpu/resource.cc delete mode 100644 src/xenia/gpu/resource.h delete mode 100644 src/xenia/gpu/resource_cache.cc delete mode 100644 src/xenia/gpu/resource_cache.h delete mode 100644 src/xenia/gpu/sampler_state_resource.cc delete mode 100644 src/xenia/gpu/sampler_state_resource.h delete mode 100644 src/xenia/gpu/shader_resource.cc delete mode 100644 src/xenia/gpu/shader_resource.h delete mode 100644 src/xenia/gpu/texture_resource.cc delete mode 100644 src/xenia/gpu/texture_resource.h rename src/xenia/gpu/{xenos => }/ucode.h (95%) rename src/xenia/gpu/{xenos => }/ucode_disassembler.cc (58%) rename src/xenia/gpu/{xenos => }/ucode_disassembler.h (57%) rename src/xenia/gpu/{xenos => }/xenos.h (55%) delete mode 100644 src/xenia/gpu/xenos/packets.h delete mode 100644 src/xenia/gpu/xenos/sources.gypi diff --git a/src/poly/sources.gypi b/src/poly/sources.gypi index c17b8b463..876712daf 100644 --- a/src/poly/sources.gypi +++ b/src/poly/sources.gypi @@ -20,6 +20,7 @@ 'poly.h', 'string.cc', 'string.h', + 'threading.cc', 'threading.h', ], diff --git a/src/poly/threading.cc b/src/poly/threading.cc new file mode 100644 index 000000000..f879097d3 --- /dev/null +++ b/src/poly/threading.cc @@ -0,0 +1,18 @@ +/** + ****************************************************************************** + * Xenia : Xbox 360 Emulator Research Project * + ****************************************************************************** + * Copyright 2014 Ben Vanik. All rights reserved. * + * Released under the BSD license - see LICENSE in the root for more details. * + ****************************************************************************** + */ + +#include + +namespace poly { +namespace threading { + +// + +} // namespace threading +} // namespace poly diff --git a/src/poly/threading.h b/src/poly/threading.h index d2208f6b1..a82eb6138 100644 --- a/src/poly/threading.h +++ b/src/poly/threading.h @@ -10,8 +10,11 @@ #ifndef POLY_THREADING_H_ #define POLY_THREADING_H_ +#include #include +#include #include +#include #include #include @@ -20,6 +23,27 @@ namespace poly { namespace threading { +class Fence { + public: + Fence() : signaled_(false) {} + void Signal() { + std::unique_lock lock(mutex_); + signaled_.store(true); + cond_.notify_all(); + } + void Wait() { + std::unique_lock lock(mutex_); + while (!signaled_.load()) { + cond_.wait(lock); + } + } + + private: + std::mutex mutex_; + std::condition_variable cond_; + std::atomic signaled_; +}; + // Gets the current high-performance tick count. uint64_t ticks(); @@ -35,7 +59,7 @@ void set_name(const std::string& name); void set_name(std::thread::native_handle_type handle, const std::string& name); // Yields the current thread to the scheduler. Maybe. -void Yield(); +void MaybeYield(); // Sleeps the current thread for at least as long as the given duration. void Sleep(std::chrono::microseconds duration); diff --git a/src/poly/threading_mac.cc b/src/poly/threading_mac.cc index 6d448315c..ae25099de 100644 --- a/src/poly/threading_mac.cc +++ b/src/poly/threading_mac.cc @@ -32,7 +32,7 @@ void set_name(std::thread::native_handle_type handle, const std::string& name) { // ? } -void Yield() { pthread_yield_np(); } +void MaybeYield() { pthread_yield_np(); } void Sleep(std::chrono::microseconds duration) { timespec rqtp = {duration.count() / 1000000, duration.count() % 1000}; diff --git a/src/poly/threading_posix.cc b/src/poly/threading_posix.cc index 005a708d6..815414f52 100644 --- a/src/poly/threading_posix.cc +++ b/src/poly/threading_posix.cc @@ -30,7 +30,7 @@ void set_name(std::thread::native_handle_type handle, const std::string& name) { pthread_setname_np(pthread_self(), name.c_str()); } -void Yield() { pthread_yield_np(); } +void MaybeYield() { pthread_yield_np(); } void Sleep(std::chrono::microseconds duration) { timespec rqtp = {duration.count() / 1000000, duration.count() % 1000}; diff --git a/src/poly/threading_win.cc b/src/poly/threading_win.cc index a75c73fac..949f68749 100644 --- a/src/poly/threading_win.cc +++ b/src/poly/threading_win.cc @@ -61,7 +61,7 @@ void set_name(std::thread::native_handle_type handle, const std::string& name) { set_name(GetThreadId(handle), name); } -void Yield() { SwitchToThread(); } +void MaybeYield() { SwitchToThread(); } void Sleep(std::chrono::microseconds duration) { if (duration.count() < 100) { diff --git a/src/poly/ui/loop.h b/src/poly/ui/loop.h index e5ae3cf72..9cf2415fb 100644 --- a/src/poly/ui/loop.h +++ b/src/poly/ui/loop.h @@ -23,6 +23,7 @@ class Loop { virtual void Post(std::function fn) = 0; virtual void Quit() = 0; + virtual void AwaitQuit() = 0; }; } // namespace ui diff --git a/src/poly/ui/win32/win32_loop.cc b/src/poly/ui/win32/win32_loop.cc index 4b9883733..426fa3f53 100644 --- a/src/poly/ui/win32/win32_loop.cc +++ b/src/poly/ui/win32/win32_loop.cc @@ -9,6 +9,8 @@ #include +#include + namespace poly { namespace ui { namespace win32 { @@ -26,10 +28,18 @@ class PostedFn { }; Win32Loop::Win32Loop() : thread_id_(0) { - thread_ = std::thread([this]() { + poly::threading::Fence init_fence; + thread_ = std::thread([&]() { + poly::threading::set_name("Win32 Loop"); thread_id_ = GetCurrentThreadId(); + + init_fence.Signal(); + ThreadMain(); + + quit_fence_.Signal(); }); + init_fence.Wait(); } Win32Loop::~Win32Loop() = default; @@ -57,16 +67,22 @@ void Win32Loop::ThreadMain() { } void Win32Loop::Post(std::function fn) { + assert_true(thread_id_ != 0); PostThreadMessage(thread_id_, kWmWin32LoopPost, reinterpret_cast(this), reinterpret_cast(new PostedFn(std::move(fn)))); } void Win32Loop::Quit() { + assert_true(thread_id_ != 0); PostThreadMessage(thread_id_, kWmWin32LoopQuit, reinterpret_cast(this), 0); } +void Win32Loop::AwaitQuit() { + quit_fence_.Wait(); +} + } // namespace win32 } // namespace ui } // namespace poly diff --git a/src/poly/ui/win32/win32_loop.h b/src/poly/ui/win32/win32_loop.h index f750e625d..629c2ee44 100644 --- a/src/poly/ui/win32/win32_loop.h +++ b/src/poly/ui/win32/win32_loop.h @@ -13,8 +13,12 @@ #include #include +#include +#include +#include #include +#include #include namespace poly { @@ -24,17 +28,19 @@ namespace win32 { class Win32Loop : public Loop { public: Win32Loop(); - ~Win32Loop(); + ~Win32Loop() override; void Post(std::function fn) override; void Quit() override; + void AwaitQuit() override; private: void ThreadMain(); std::thread thread_; DWORD thread_id_; + poly::threading::Fence quit_fence_; }; } // namespace win32 diff --git a/src/poly/ui/win32/win32_window.cc b/src/poly/ui/win32/win32_window.cc index bf62454d6..076e56de6 100644 --- a/src/poly/ui/win32/win32_window.cc +++ b/src/poly/ui/win32/win32_window.cc @@ -24,6 +24,11 @@ Win32Window::Win32Window(const std::wstring& title) Win32Window::~Win32Window() {} +bool Win32Window::Initialize() { + CreateHWND(); + return true; +} + bool Win32Window::CreateHWND() { HINSTANCE hInstance = GetModuleHandle(nullptr); @@ -62,6 +67,7 @@ bool Win32Window::CreateHWND() { } main_menu_ = CreateMenu(); + AppendMenu(main_menu_, MF_STRING, 0, L"TODO"); SetMenu(hwnd_, main_menu_); // Disable flicks. @@ -130,13 +136,25 @@ bool Win32Window::set_title(const std::wstring& title) { return true; } -// bool Win32Window::SetSize(uint32_t width, uint32_t height) { -// RECT rc = {0, 0, static_cast(width), static_cast(height)}; -// AdjustWindowRect(&rc, WS_OVERLAPPEDWINDOW, FALSE); -// // TODO(benvanik): center? -// MoveWindow(handle_, 0, 0, rc.right - rc.left, rc.bottom - rc.top, TRUE); -// return true; -// } +void Win32Window::Resize(int32_t width, int32_t height) { + RECT rc = {0, 0, width, height}; + bool has_menu = main_menu_ ? true : false; + AdjustWindowRect(&rc, WS_OVERLAPPEDWINDOW, has_menu); + Window::Resize(rc.right - rc.left, rc.bottom - rc.top); +} + +void Win32Window::Resize(int32_t left, int32_t top, int32_t right, + int32_t bottom) { + RECT rc = {left, top, right, bottom}; + bool has_menu = main_menu_ ? true : false; + AdjustWindowRect(&rc, WS_OVERLAPPEDWINDOW, has_menu); + Window::Resize(rc.left, rc.top, rc.right, rc.bottom); +} + +void Win32Window::ResizeToFill(int32_t pad_left, int32_t pad_top, + int32_t pad_right, int32_t pad_bottom) { + // TODO(benvanik): fullscreen. +} void Win32Window::OnClose() { if (!closing_ && hwnd_) { diff --git a/src/poly/ui/win32/win32_window.h b/src/poly/ui/win32/win32_window.h index 63a15ddf9..0573627aa 100644 --- a/src/poly/ui/win32/win32_window.h +++ b/src/poly/ui/win32/win32_window.h @@ -24,8 +24,16 @@ class Win32Window : public Window { Win32Window(const std::wstring& title); ~Win32Window() override; + bool Initialize() override; + bool set_title(const std::wstring& title) override; + void Resize(int32_t width, int32_t height) override; + void Resize(int32_t left, int32_t top, int32_t right, + int32_t bottom) override; + void ResizeToFill(int32_t pad_left, int32_t pad_top, int32_t pad_right, + int32_t pad_bottom) override; + protected: bool CreateHWND() override; diff --git a/src/xenia/emulator.cc b/src/xenia/emulator.cc index 912099163..048e5f9cb 100644 --- a/src/xenia/emulator.cc +++ b/src/xenia/emulator.cc @@ -71,10 +71,8 @@ X_STATUS Emulator::Setup() { X_STATUS result = X_STATUS_UNSUCCESSFUL; // Create the main window. Other parts will hook into this. - main_window_ = std::make_unique(); - if (!main_window_->Initialize()) { - return result; - } + main_window_ = std::make_unique(this); + main_window_->Start(); debug_agent_.reset(new DebugAgent(this)); result = debug_agent_->Initialize(); diff --git a/src/xenia/gpu/buffer_resource.cc b/src/xenia/gpu/buffer_resource.cc deleted file mode 100644 index 67a8f8004..000000000 --- a/src/xenia/gpu/buffer_resource.cc +++ /dev/null @@ -1,56 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#include - - -using namespace std; -using namespace xe; -using namespace xe::gpu; -using namespace xe::gpu::xenos; - - -BufferResource::BufferResource(const MemoryRange& memory_range) - : PagedResource(memory_range) { -} - -BufferResource::~BufferResource() = default; - -int BufferResource::Prepare() { - if (!handle()) { - if (CreateHandle()) { - XELOGE("Unable to create buffer handle"); - return 1; - } - } - - //if (!dirtied_) { - // return 0; - //} - //dirtied_ = false; - - // pass dirty regions? - return InvalidateRegion(memory_range_); -} - -IndexBufferResource::IndexBufferResource(const MemoryRange& memory_range, - const Info& info) - : BufferResource(memory_range), - info_(info) { -} - -IndexBufferResource::~IndexBufferResource() = default; - -VertexBufferResource::VertexBufferResource(const MemoryRange& memory_range, - const Info& info) - : BufferResource(memory_range), - info_(info) { -} - -VertexBufferResource::~VertexBufferResource() = default; diff --git a/src/xenia/gpu/buffer_resource.h b/src/xenia/gpu/buffer_resource.h deleted file mode 100644 index a88d1ae06..000000000 --- a/src/xenia/gpu/buffer_resource.h +++ /dev/null @@ -1,99 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef XENIA_GPU_BUFFER_RESOURCE_H_ -#define XENIA_GPU_BUFFER_RESOURCE_H_ - -#include -#include -#include - - -namespace xe { -namespace gpu { - - -class BufferResource : public PagedResource { -public: - BufferResource(const MemoryRange& memory_range); - ~BufferResource() override; - - virtual int Prepare(); - -protected: - virtual int CreateHandle() = 0; - virtual int InvalidateRegion(const MemoryRange& memory_range) = 0; -}; - - -enum IndexFormat { - INDEX_FORMAT_16BIT = 0, - INDEX_FORMAT_32BIT = 1, -}; - -class IndexBufferResource : public BufferResource { -public: - struct Info { - IndexFormat format; - xenos::XE_GPU_ENDIAN endianness; - }; - - IndexBufferResource(const MemoryRange& memory_range, - const Info& info); - ~IndexBufferResource() override; - - const Info& info() const { return info_; } - - bool Equals(const void* info_ptr, size_t info_length) override { - return info_length == sizeof(Info) && - memcmp(info_ptr, &info_, info_length) == 0; - } - -protected: - Info info_; -}; - - -class VertexBufferResource : public BufferResource { -public: - struct DeclElement { - xenos::instr_fetch_vtx_t vtx_fetch; - uint32_t format; - uint32_t offset_words; - uint32_t size_words; - bool is_signed; - bool is_normalized; - }; - struct Info { - uint32_t stride_words; - uint32_t element_count; - DeclElement elements[16]; - }; - - VertexBufferResource(const MemoryRange& memory_range, - const Info& info); - ~VertexBufferResource() override; - - const Info& info() const { return info_; } - - bool Equals(const void* info_ptr, size_t info_length) override { - return info_length == sizeof(Info) && - memcmp(info_ptr, &info_, info_length) == 0; - } - -protected: - Info info_; -}; - - -} // namespace gpu -} // namespace xe - - -#endif // XENIA_GPU_BUFFER_RESOURCE_H_ diff --git a/src/xenia/gpu/command_processor.cc b/src/xenia/gpu/command_processor.cc deleted file mode 100644 index edb6138fa..000000000 --- a/src/xenia/gpu/command_processor.cc +++ /dev/null @@ -1,804 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#include - -#include - -#include -#include -#include -#include - - -using namespace xe; -using namespace xe::gpu; -using namespace xe::gpu::xenos; - - -#define XETRACECP(fmt, ...) if (FLAGS_trace_ring_buffer) XELOGGPU(fmt, ##__VA_ARGS__) - - -CommandProcessor::CommandProcessor( - GraphicsSystem* graphics_system, Memory* memory) : - graphics_system_(graphics_system), memory_(memory), driver_(0) { - write_ptr_index_event_ = CreateEvent(NULL, FALSE, FALSE, NULL); - - primary_buffer_ptr_ = 0; - primary_buffer_size_ = 0; - read_ptr_index_ = 0; - read_ptr_update_freq_ = 0; - read_ptr_writeback_ptr_ = 0; - write_ptr_index_ = 0; - write_ptr_max_index_ = 0; - - LARGE_INTEGER perf_counter; - QueryPerformanceCounter(&perf_counter); - time_base_ = perf_counter.QuadPart; - counter_ = 0; -} - -CommandProcessor::~CommandProcessor() { - SetEvent(write_ptr_index_event_); - CloseHandle(write_ptr_index_event_); -} - -uint64_t CommandProcessor::QueryTime() { - LARGE_INTEGER perf_counter; - QueryPerformanceCounter(&perf_counter); - return perf_counter.QuadPart - time_base_; -} - -void CommandProcessor::Initialize(GraphicsDriver* driver, - uint32_t ptr, uint32_t page_count) { - driver_ = driver; - primary_buffer_ptr_ = ptr; - // Not sure this is correct, but it's a way to take the page_count back to - // the number of bytes allocated by the physical alloc. - uint32_t original_size = 1 << (0x1C - page_count - 1); - primary_buffer_size_ = original_size; - read_ptr_index_ = 0; -} - -void CommandProcessor::EnableReadPointerWriteBack(uint32_t ptr, - uint32_t block_size) { - // CP_RB_RPTR_ADDR Ring Buffer Read Pointer Address 0x70C - // ptr = RB_RPTR_ADDR, pointer to write back the address to. - read_ptr_writeback_ptr_ = (primary_buffer_ptr_ & ~0x1FFFFFFF) + ptr; - // CP_RB_CNTL Ring Buffer Control 0x704 - // block_size = RB_BLKSZ, number of quadwords read between updates of the - // read pointer. - read_ptr_update_freq_ = (uint32_t)pow(2.0, (double)block_size) / 4; -} - -void CommandProcessor::UpdateWritePointer(uint32_t value) { - write_ptr_max_index_ = - std::max(static_cast(write_ptr_max_index_), value); - write_ptr_index_ = value; - SetEvent(write_ptr_index_event_); -} - -void CommandProcessor::Pump() { - uint8_t* p = memory_->membase(); - - while (write_ptr_index_ == 0xBAADF00D || - read_ptr_index_ == write_ptr_index_) { - // Check if the pointer has moved. - // We wait a short bit here to yield time. Since we are also running the - // main window display we don't want to pause too long, though. - // YieldProcessor(); - const int wait_time_ms = 1; - if (WaitForSingleObject(write_ptr_index_event_, - wait_time_ms) == WAIT_TIMEOUT) { - return; - } - } - - // Bring local so we don't have to worry about them changing out from under - // us. - uint32_t write_ptr_index = write_ptr_index_; - uint32_t write_ptr_max_index = write_ptr_max_index_; - if (read_ptr_index_ == write_ptr_index) { - return; - } - - // Process the new commands. - XETRACECP("Command processor thread work"); - - // Execute. Note that we handle wraparound transparently. - ExecutePrimaryBuffer(read_ptr_index_, write_ptr_index); - read_ptr_index_ = write_ptr_index; - - // TODO(benvanik): use read_ptr_update_freq_ and only issue after moving - // that many indices. - if (read_ptr_writeback_ptr_) { - poly::store_and_swap(p + read_ptr_writeback_ptr_, read_ptr_index_); - } -} - -void CommandProcessor::ExecutePrimaryBuffer( - uint32_t start_index, uint32_t end_index) { - SCOPE_profile_cpu_f("gpu"); - - // Adjust pointer base. - uint32_t ptr = primary_buffer_ptr_ + start_index * 4; - ptr = (primary_buffer_ptr_ & ~0x1FFFFFFF) | (ptr & 0x1FFFFFFF); - uint32_t end_ptr = primary_buffer_ptr_ + end_index * 4; - end_ptr = (primary_buffer_ptr_ & ~0x1FFFFFFF) | (end_ptr & 0x1FFFFFFF); - - XETRACECP("[%.8X] ExecutePrimaryBuffer(%dw -> %dw)", - ptr, start_index, end_index); - - // Execute commands! - PacketArgs args; - args.ptr = ptr; - args.base_ptr = primary_buffer_ptr_; - args.max_address = primary_buffer_ptr_ + primary_buffer_size_; - args.ptr_mask = (primary_buffer_size_ / 4) - 1; - uint32_t n = 0; - while (args.ptr != end_ptr) { - n += ExecutePacket(args); - assert_true(args.ptr < args.max_address); - } - if (end_index > start_index) { - assert_true(n == (end_index - start_index)); - } - - XETRACECP(" ExecutePrimaryBuffer End"); -} - -void CommandProcessor::ExecuteIndirectBuffer(uint32_t ptr, uint32_t length) { - XETRACECP("[%.8X] ExecuteIndirectBuffer(%dw)", ptr, length); - - // Execute commands! - PacketArgs args; - args.ptr = ptr; - args.base_ptr = ptr; - args.max_address = ptr + length * 4; - args.ptr_mask = 0; - for (uint32_t n = 0; n < length;) { - n += ExecutePacket(args); - assert_true(n <= length); - } - - XETRACECP(" ExecuteIndirectBuffer End"); -} - -#define LOG_DATA(count) \ - for (uint32_t __m = 0; __m < count; __m++) { \ - XETRACECP("[%.8X] %.8X", \ - packet_ptr + (1 + __m) * 4, \ - poly::load_and_swap(packet_base + 1 * 4 + __m * 4)); \ - } - -void CommandProcessor::AdvancePtr(PacketArgs& args, uint32_t n) { - args.ptr = args.ptr + n * 4; - if (args.ptr_mask) { - args.ptr = - args.base_ptr + (((args.ptr - args.base_ptr) / 4) & args.ptr_mask) * 4; - } -} -#define ADVANCE_PTR(n) AdvancePtr(args, n) -#define PEEK_PTR() \ - poly::load_and_swap(p + args.ptr) -#define READ_PTR() \ - poly::load_and_swap(p + args.ptr); ADVANCE_PTR(1); - -uint32_t CommandProcessor::ExecutePacket(PacketArgs& args) { - uint8_t* p = memory_->membase(); - RegisterFile* regs = driver_->register_file(); - - uint32_t packet_ptr = args.ptr; - const uint8_t* packet_base = p + packet_ptr; - const uint32_t packet = PEEK_PTR(); - ADVANCE_PTR(1); - const uint32_t packet_type = packet >> 30; - if (packet == 0) { - XETRACECP("[%.8X] Packet(%.8X): 0?", - packet_ptr, packet); - return 1; - } - - switch (packet_type) { - case 0x00: - { - // Type-0 packet. - // Write count registers in sequence to the registers starting at - // (base_index << 2). - XETRACECP("[%.8X] Packet(%.8X): set registers:", - packet_ptr, packet); - uint32_t count = ((packet >> 16) & 0x3FFF) + 1; - uint32_t base_index = (packet & 0x7FFF); - uint32_t write_one_reg = (packet >> 15) & 0x1; - for (uint32_t m = 0; m < count; m++) { - uint32_t reg_data = PEEK_PTR(); - uint32_t target_index = write_one_reg ? base_index : base_index + m; - const char* reg_name = regs->GetRegisterName(target_index); - XETRACECP("[%.8X] %.8X -> %.4X %s", - args.ptr, - reg_data, target_index, reg_name ? reg_name : ""); - ADVANCE_PTR(1); - WriteRegister(packet_ptr, target_index, reg_data); - } - return 1 + count; - } - break; - case 0x01: - { - // Type-1 packet. - // Contains two registers of data. Type-0 should be more common. - XETRACECP("[%.8X] Packet(%.8X): set registers:", - packet_ptr, packet); - uint32_t reg_index_1 = packet & 0x7FF; - uint32_t reg_index_2 = (packet >> 11) & 0x7FF; - uint32_t reg_ptr_1 = args.ptr; - uint32_t reg_data_1 = READ_PTR(); - uint32_t reg_ptr_2 = args.ptr; - uint32_t reg_data_2 = READ_PTR(); - const char* reg_name_1 = regs->GetRegisterName(reg_index_1); - const char* reg_name_2 = regs->GetRegisterName(reg_index_2); - XETRACECP("[%.8X] %.8X -> %.4X %s", - reg_ptr_1, - reg_data_1, reg_index_1, reg_name_1 ? reg_name_1 : ""); - XETRACECP("[%.8X] %.8X -> %.4X %s", - reg_ptr_2, - reg_data_2, reg_index_2, reg_name_2 ? reg_name_2 : ""); - WriteRegister(packet_ptr, reg_index_1, reg_data_1); - WriteRegister(packet_ptr, reg_index_2, reg_data_2); - return 1 + 2; - } - break; - case 0x02: - // Type-2 packet. - // No-op. Do nothing. - XETRACECP("[%.8X] Packet(%.8X): padding", - packet_ptr, packet); - return 1; - case 0x03: - { - // Type-3 packet. - uint32_t count = ((packet >> 16) & 0x3FFF) + 1; - uint32_t opcode = (packet >> 8) & 0x7F; - // & 1 == predicate, maybe? - - switch (opcode) { - case PM4_ME_INIT: - // initialize CP's micro-engine - XETRACECP("[%.8X] Packet(%.8X): PM4_ME_INIT", - packet_ptr, packet); - LOG_DATA(count); - ADVANCE_PTR(count); - break; - - case PM4_NOP: - // skip N 32-bit words to get to the next packet - // No-op, ignore some data. - XETRACECP("[%.8X] Packet(%.8X): PM4_NOP", - packet_ptr, packet); - LOG_DATA(count); - ADVANCE_PTR(count); - break; - - case PM4_INTERRUPT: - // generate interrupt from the command stream - { - XETRACECP("[%.8X] Packet(%.8X): PM4_INTERRUPT", - packet_ptr, packet); - LOG_DATA(count); - uint32_t cpu_mask = READ_PTR(); - for (int n = 0; n < 6; n++) { - if (cpu_mask & (1 << n)) { - graphics_system_->DispatchInterruptCallback(1, n); - } - } - } - break; - - case PM4_XE_SWAP: - // Xenia-specific VdSwap hook. - // VdSwap will post this to tell us we need to swap the screen/fire an interrupt. - XETRACECP("[%.8X] Packet(%.8X): PM4_XE_SWAP", - packet_ptr, packet); - LOG_DATA(count); - ADVANCE_PTR(count); - graphics_system_->Swap(); - break; - - case PM4_INDIRECT_BUFFER: - // indirect buffer dispatch - { - uint32_t list_ptr = READ_PTR(); - uint32_t list_length = READ_PTR(); - XETRACECP("[%.8X] Packet(%.8X): PM4_INDIRECT_BUFFER %.8X (%dw)", - packet_ptr, packet, list_ptr, list_length); - ExecuteIndirectBuffer(GpuToCpu(list_ptr), list_length); - } - break; - - case PM4_WAIT_REG_MEM: - // wait until a register or memory location is a specific value - { - XETRACECP("[%.8X] Packet(%.8X): PM4_WAIT_REG_MEM", - packet_ptr, packet); - LOG_DATA(count); - uint32_t wait_info = READ_PTR(); - uint32_t poll_reg_addr = READ_PTR(); - uint32_t ref = READ_PTR(); - uint32_t mask = READ_PTR(); - uint32_t wait = READ_PTR(); - bool matched = false; - do { - uint32_t value; - if (wait_info & 0x10) { - // Memory. - XE_GPU_ENDIAN endianness = (XE_GPU_ENDIAN)(poll_reg_addr & 0x3); - poll_reg_addr &= ~0x3; - value = poly::load(p + GpuToCpu(packet_ptr, poll_reg_addr)); - value = GpuSwap(value, endianness); - } else { - // Register. - assert_true(poll_reg_addr < RegisterFile::kRegisterCount); - value = regs->values[poll_reg_addr].u32; - if (poll_reg_addr == XE_GPU_REG_COHER_STATUS_HOST) { - MakeCoherent(); - value = regs->values[poll_reg_addr].u32; - } - } - switch (wait_info & 0x7) { - case 0x0: // Never. - matched = false; - break; - case 0x1: // Less than reference. - matched = (value & mask) < ref; - break; - case 0x2: // Less than or equal to reference. - matched = (value & mask) <= ref; - break; - case 0x3: // Equal to reference. - matched = (value & mask) == ref; - break; - case 0x4: // Not equal to reference. - matched = (value & mask) != ref; - break; - case 0x5: // Greater than or equal to reference. - matched = (value & mask) >= ref; - break; - case 0x6: // Greater than reference. - matched = (value & mask) > ref; - break; - case 0x7: // Always - matched = true; - break; - } - if (!matched) { - // Wait. - if (wait >= 0x100) { - Sleep(wait / 0x100); - } else { - SwitchToThread(); - } - } - } while (!matched); - } - break; - - case PM4_REG_RMW: - // register read/modify/write - // ? (used during shader upload and edram setup) - { - XETRACECP("[%.8X] Packet(%.8X): PM4_REG_RMW", - packet_ptr, packet); - LOG_DATA(count); - uint32_t rmw_info = READ_PTR(); - uint32_t and_mask = READ_PTR(); - uint32_t or_mask = READ_PTR(); - uint32_t value = regs->values[rmw_info & 0x1FFF].u32; - if ((rmw_info >> 30) & 0x1) { - // | reg - value |= regs->values[or_mask & 0x1FFF].u32; - } else { - // | imm - value |= or_mask; - } - if ((rmw_info >> 31) & 0x1) { - // & reg - value &= regs->values[and_mask & 0x1FFF].u32; - } else { - // & imm - value &= and_mask; - } - WriteRegister(packet_ptr, rmw_info & 0x1FFF, value); - } - break; - - case PM4_COND_WRITE: - // conditional write to memory or register - { - XETRACECP("[%.8X] Packet(%.8X): PM4_COND_WRITE", - packet_ptr, packet); - LOG_DATA(count); - uint32_t wait_info = READ_PTR(); - uint32_t poll_reg_addr = READ_PTR(); - uint32_t ref = READ_PTR(); - uint32_t mask = READ_PTR(); - uint32_t write_reg_addr = READ_PTR(); - uint32_t write_data = READ_PTR(); - uint32_t value; - if (wait_info & 0x10) { - // Memory. - XE_GPU_ENDIAN endianness = (XE_GPU_ENDIAN)(poll_reg_addr & 0x3); - poll_reg_addr &= ~0x3; - value = poly::load(p + GpuToCpu(packet_ptr, poll_reg_addr)); - value = GpuSwap(value, endianness); - } else { - // Register. - assert_true(poll_reg_addr < RegisterFile::kRegisterCount); - value = regs->values[poll_reg_addr].u32; - } - bool matched = false; - switch (wait_info & 0x7) { - case 0x0: // Never. - matched = false; - break; - case 0x1: // Less than reference. - matched = (value & mask) < ref; - break; - case 0x2: // Less than or equal to reference. - matched = (value & mask) <= ref; - break; - case 0x3: // Equal to reference. - matched = (value & mask) == ref; - break; - case 0x4: // Not equal to reference. - matched = (value & mask) != ref; - break; - case 0x5: // Greater than or equal to reference. - matched = (value & mask) >= ref; - break; - case 0x6: // Greater than reference. - matched = (value & mask) > ref; - break; - case 0x7: // Always - matched = true; - break; - } - if (matched) { - // Write. - if (wait_info & 0x100) { - // Memory. - XE_GPU_ENDIAN endianness = (XE_GPU_ENDIAN)(write_reg_addr & 0x3); - write_reg_addr &= ~0x3; - write_data = GpuSwap(write_data, endianness); - poly::store(p + GpuToCpu(packet_ptr, write_reg_addr), - write_data); - } else { - // Register. - WriteRegister(packet_ptr, write_reg_addr, write_data); - } - } - } - break; - - case PM4_EVENT_WRITE: - // generate an event that creates a write to memory when completed - { - XETRACECP("[%.8X] Packet(%.8X): PM4_EVENT_WRITE (unimplemented!)", - packet_ptr, packet); - LOG_DATA(count); - uint32_t initiator = READ_PTR(); - if (count == 1) { - // Just an event flag? Where does this write? - } else { - // Write to an address. - assert_always(); - ADVANCE_PTR(count - 1); - } - } - break; - case PM4_EVENT_WRITE_SHD: - // generate a VS|PS_done event - { - XETRACECP("[%.8X] Packet(%.8X): PM4_EVENT_WRITE_SHD", - packet_ptr, packet); - LOG_DATA(count); - uint32_t initiator = READ_PTR(); - uint32_t address = READ_PTR(); - uint32_t value = READ_PTR(); - // Writeback initiator. - WriteRegister(packet_ptr, XE_GPU_REG_VGT_EVENT_INITIATOR, - initiator & 0x3F); - uint32_t data_value; - if ((initiator >> 31) & 0x1) { - // Write counter (GPU vblank counter?). - data_value = counter_; - } else { - // Write value. - data_value = value; - } - XE_GPU_ENDIAN endianness = (XE_GPU_ENDIAN)(address & 0x3); - address &= ~0x3; - data_value = GpuSwap(data_value, endianness); - poly::store(p + GpuToCpu(address), data_value); - } - break; - - case PM4_DRAW_INDX: - // initiate fetch of index buffer and draw - { - XETRACECP("[%.8X] Packet(%.8X): PM4_DRAW_INDX", - packet_ptr, packet); - LOG_DATA(count); - // d0 = viz query info - uint32_t d0 = READ_PTR(); - uint32_t d1 = READ_PTR(); - uint32_t index_count = d1 >> 16; - uint32_t prim_type = d1 & 0x3F; - uint32_t src_sel = (d1 >> 6) & 0x3; - if (!driver_->PrepareDraw(draw_command_)) { - draw_command_.prim_type = (XE_GPU_PRIMITIVE_TYPE)prim_type; - draw_command_.start_index = 0; - draw_command_.index_count = index_count; - draw_command_.base_vertex = 0; - if (src_sel == 0x0) { - // Indexed draw. - // TODO(benvanik): detect subregions of larger index buffers! - uint32_t index_base = READ_PTR(); - uint32_t index_size = READ_PTR(); - uint32_t endianness = index_size >> 30; - index_size &= 0x00FFFFFF; - bool index_32bit = (d1 >> 11) & 0x1; - index_size *= index_32bit ? 4 : 2; - driver_->PrepareDrawIndexBuffer( - draw_command_, - index_base, index_size, - (XE_GPU_ENDIAN)endianness, - index_32bit ? INDEX_FORMAT_32BIT : INDEX_FORMAT_16BIT); - } else if (src_sel == 0x2) { - // Auto draw. - draw_command_.index_buffer = nullptr; - } else { - // Unknown source select. - assert_always(); - } - driver_->Draw(draw_command_); - } else { - if (src_sel == 0x0) { - ADVANCE_PTR(2); // skip - } - } - } - break; - case PM4_DRAW_INDX_2: - // draw using supplied indices in packet - { - XETRACECP("[%.8X] Packet(%.8X): PM4_DRAW_INDX_2", - packet_ptr, packet); - LOG_DATA(count); - uint32_t d0 = READ_PTR(); - uint32_t index_count = d0 >> 16; - uint32_t prim_type = d0 & 0x3F; - uint32_t src_sel = (d0 >> 6) & 0x3; - assert_true(src_sel == 0x2); // 'SrcSel=AutoIndex' - if (!driver_->PrepareDraw(draw_command_)) { - draw_command_.prim_type = (XE_GPU_PRIMITIVE_TYPE)prim_type; - draw_command_.start_index = 0; - draw_command_.index_count = index_count; - draw_command_.base_vertex = 0; - draw_command_.index_buffer = nullptr; - driver_->Draw(draw_command_); - } - } - break; - - case PM4_SET_CONSTANT: - // load constant into chip and to memory - { - XETRACECP("[%.8X] Packet(%.8X): PM4_SET_CONSTANT", - packet_ptr, packet); - // PM4_REG(reg) ((0x4 << 16) | (GSL_HAL_SUBBLOCK_OFFSET(reg))) - // reg - 0x2000 - uint32_t offset_type = READ_PTR(); - uint32_t index = offset_type & 0x7FF; - uint32_t type = (offset_type >> 16) & 0xFF; - switch (type) { - case 0x4: // REGISTER - index += 0x2000; // registers - for (uint32_t n = 0; n < count - 1; n++, index++) { - uint32_t data = READ_PTR(); - const char* reg_name = regs->GetRegisterName(index); - XETRACECP("[%.8X] %.8X -> %.4X %s", - packet_ptr + (1 + n) * 4, - data, index, reg_name ? reg_name : ""); - WriteRegister(packet_ptr, index, data); - } - break; - default: - assert_always(); - break; - } - } - break; - case PM4_LOAD_ALU_CONSTANT: - // load constants from memory - { - XETRACECP("[%.8X] Packet(%.8X): PM4_LOAD_ALU_CONSTANT", - packet_ptr, packet); - uint32_t address = READ_PTR(); - address &= 0x3FFFFFFF; - uint32_t offset_type = READ_PTR(); - uint32_t index = offset_type & 0x7FF; - uint32_t size = READ_PTR(); - size &= 0xFFF; - index += 0x4000; // alu constants - for (uint32_t n = 0; n < size; n++, index++) { - uint32_t data = poly::load_and_swap( - p + GpuToCpu(packet_ptr, address + n * 4)); - const char* reg_name = regs->GetRegisterName(index); - XETRACECP("[%.8X] %.8X -> %.4X %s", - packet_ptr, - data, index, reg_name ? reg_name : ""); - WriteRegister(packet_ptr, index, data); - } - } - break; - - case PM4_IM_LOAD: - // load sequencer instruction memory (pointer-based) - { - XETRACECP("[%.8X] Packet(%.8X): PM4_IM_LOAD", - packet_ptr, packet); - LOG_DATA(count); - uint32_t addr_type = READ_PTR(); - uint32_t type = addr_type & 0x3; - uint32_t addr = addr_type & ~0x3; - uint32_t start_size = READ_PTR(); - uint32_t start = start_size >> 16; - uint32_t size = start_size & 0xFFFF; // dwords - assert_true(start == 0); - driver_->LoadShader((XE_GPU_SHADER_TYPE)type, - GpuToCpu(packet_ptr, addr), size * 4, start); - } - break; - case PM4_IM_LOAD_IMMEDIATE: - // load sequencer instruction memory (code embedded in packet) - { - XETRACECP("[%.8X] Packet(%.8X): PM4_IM_LOAD_IMMEDIATE", - packet_ptr, packet); - LOG_DATA(count); - uint32_t type = READ_PTR(); - uint32_t start_size = READ_PTR(); - uint32_t start = start_size >> 16; - uint32_t size = start_size & 0xFFFF; // dwords - assert_true(start == 0); - // TODO(benvanik): figure out if this could wrap. - assert_true(args.ptr + size * 4 < args.max_address); - driver_->LoadShader((XE_GPU_SHADER_TYPE)type, - args.ptr, size * 4, start); - ADVANCE_PTR(size); - } - break; - - case PM4_INVALIDATE_STATE: - // selective invalidation of state pointers - { - XETRACECP("[%.8X] Packet(%.8X): PM4_INVALIDATE_STATE", - packet_ptr, packet); - LOG_DATA(count); - uint32_t mask = READ_PTR(); - //driver_->InvalidateState(mask); - } - break; - - case PM4_SET_BIN_MASK_LO: - { - uint32_t value = READ_PTR(); - XETRACECP("[%.8X] Packet(%.8X): PM4_SET_BIN_MASK_LO = %.8X", - packet_ptr, packet, value); - } - break; - case PM4_SET_BIN_MASK_HI: - { - uint32_t value = READ_PTR(); - XETRACECP("[%.8X] Packet(%.8X): PM4_SET_BIN_MASK_HI = %.8X", - packet_ptr, packet, value); - } - break; - case PM4_SET_BIN_SELECT_LO: - { - uint32_t value = READ_PTR(); - XETRACECP("[%.8X] Packet(%.8X): PM4_SET_BIN_SELECT_LO = %.8X", - packet_ptr, packet, value); - } - break; - case PM4_SET_BIN_SELECT_HI: - { - uint32_t value = READ_PTR(); - XETRACECP("[%.8X] Packet(%.8X): PM4_SET_BIN_SELECT_HI = %.8X", - packet_ptr, packet, value); - } - break; - - // Ignored packets - useful if breaking on the default handler below. - case 0x50: // 0xC0015000 usually 2 words, 0xFFFFFFFF / 0x00000000 - XETRACECP("[%.8X] Packet(%.8X): unknown!", - packet_ptr, packet); - LOG_DATA(count); - ADVANCE_PTR(count); - break; - - default: - XETRACECP("[%.8X] Packet(%.8X): unknown!", - packet_ptr, packet); - LOG_DATA(count); - ADVANCE_PTR(count); - break; - } - - return 1 + count; - } - break; - } - - return 0; -} - -void CommandProcessor::WriteRegister( - uint32_t packet_ptr, uint32_t index, uint32_t value) { - RegisterFile* regs = driver_->register_file(); - assert_true(index < RegisterFile::kRegisterCount); - regs->values[index].u32 = value; - - // If this is a COHER register, set the dirty flag. - // This will block the command processor the next time it WAIT_MEM_REGs and - // allow us to synchronize the memory. - if (index == XE_GPU_REG_COHER_STATUS_HOST) { - regs->values[index].u32 |= 0x80000000ul; - } - - // Scratch register writeback. - if (index >= XE_GPU_REG_SCRATCH_REG0 && index <= XE_GPU_REG_SCRATCH_REG7) { - uint32_t scratch_reg = index - XE_GPU_REG_SCRATCH_REG0; - if ((1 << scratch_reg) & regs->values[XE_GPU_REG_SCRATCH_UMSK].u32) { - // Enabled - write to address. - uint8_t* p = memory_->membase(); - uint32_t scratch_addr = regs->values[XE_GPU_REG_SCRATCH_ADDR].u32; - uint32_t mem_addr = scratch_addr + (scratch_reg * 4); - poly::store_and_swap(p + GpuToCpu(primary_buffer_ptr_, mem_addr), value); - } - } -} - -void CommandProcessor::MakeCoherent() { - // Status host often has 0x01000000 or 0x03000000. - // This is likely toggling VC (vertex cache) or TC (texture cache). - // Or, it also has a direction in here maybe - there is probably - // some way to check for dest coherency (what all the COHER_DEST_BASE_* - // registers are for). - // Best docs I've found on this are here: - // http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/10/R6xx_R7xx_3D.pdf - // http://cgit.freedesktop.org/xorg/driver/xf86-video-radeonhd/tree/src/r6xx_accel.c?id=3f8b6eccd9dba116cc4801e7f80ce21a879c67d2#n454 - - RegisterFile* regs = driver_->register_file(); - auto status_host = regs->values[XE_GPU_REG_COHER_STATUS_HOST].u32; - auto base_host = regs->values[XE_GPU_REG_COHER_BASE_HOST].u32; - auto size_host = regs->values[XE_GPU_REG_COHER_SIZE_HOST].u32; - - if (!(status_host & 0x80000000ul)) { - return; - } - - // TODO(benvanik): notify resource cache of base->size and type. - XETRACECP("Make %.8X -> %.8X (%db) coherent", - base_host, base_host + size_host, size_host); - driver_->resource_cache()->SyncRange(base_host, size_host); - - // Mark coherent. - status_host &= ~0x80000000ul; - regs->values[XE_GPU_REG_COHER_STATUS_HOST].u32 = status_host; -} diff --git a/src/xenia/gpu/command_processor.h b/src/xenia/gpu/command_processor.h deleted file mode 100644 index ebe06be91..000000000 --- a/src/xenia/gpu/command_processor.h +++ /dev/null @@ -1,81 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef XENIA_GPU_COMMAND_PROCESSOR_H_ -#define XENIA_GPU_COMMAND_PROCESSOR_H_ - -#include -#include -#include -#include - -namespace xe { -namespace gpu { - -class GraphicsDriver; -class GraphicsSystem; - -class CommandProcessor { -public: - CommandProcessor(GraphicsSystem* graphics_system, Memory* memory); - virtual ~CommandProcessor(); - - Memory* memory() const { return memory_; } - - uint64_t QueryTime(); - uint32_t counter() const { return counter_; } - void increment_counter() { counter_++; } - - void Initialize(GraphicsDriver* driver, uint32_t ptr, uint32_t page_count); - void EnableReadPointerWriteBack(uint32_t ptr, uint32_t block_size); - - void UpdateWritePointer(uint32_t value); - - void Pump(); - -private: - typedef struct { - uint32_t ptr; - uint32_t base_ptr; - uint32_t max_address; - uint32_t ptr_mask; - } PacketArgs; - - void AdvancePtr(PacketArgs& args, uint32_t n); - void ExecutePrimaryBuffer(uint32_t start_index, uint32_t end_index); - void ExecuteIndirectBuffer(uint32_t ptr, uint32_t length); - uint32_t ExecutePacket(PacketArgs& args); - void WriteRegister(uint32_t packet_ptr, uint32_t index, uint32_t value); - void MakeCoherent(); - - Memory* memory_; - GraphicsSystem* graphics_system_; - GraphicsDriver* driver_; - - uint64_t time_base_; - uint32_t counter_; - - uint32_t primary_buffer_ptr_; - uint32_t primary_buffer_size_; - - uint32_t read_ptr_index_; - uint32_t read_ptr_update_freq_; - uint32_t read_ptr_writeback_ptr_; - - HANDLE write_ptr_index_event_; - volatile uint32_t write_ptr_index_; - volatile uint32_t write_ptr_max_index_; - - DrawCommand draw_command_; -}; - -} // namespace gpu -} // namespace xe - -#endif // XENIA_GPU_COMMAND_PROCESSOR_H_ diff --git a/src/xenia/gpu/draw_command.h b/src/xenia/gpu/draw_command.h deleted file mode 100644 index 081641ff5..000000000 --- a/src/xenia/gpu/draw_command.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef XENIA_GPU_DRAW_COMMAND_H_ -#define XENIA_GPU_DRAW_COMMAND_H_ - -#include -#include -#include -#include -#include -#include - -namespace xe { -namespace gpu { - -// TODO(benvanik): move more of the enums in here? -struct DrawCommand { - xenos::XE_GPU_PRIMITIVE_TYPE prim_type; - uint32_t start_index; - uint32_t index_count; - uint32_t base_vertex; - - VertexShaderResource* vertex_shader; - PixelShaderResource* pixel_shader; - - // TODO(benvanik): dirty tracking/max ranges/etc. - struct { - float* values; - size_t count; - } float4_constants; - struct { - uint32_t* values; - size_t count; - } loop_constants; - struct { - uint32_t* values; - size_t count; - } bool_constants; - - // Index buffer, if present. If index_count > 0 then auto draw. - IndexBufferResource* index_buffer; - - // Vertex buffers. - struct { - uint32_t input_index; - VertexBufferResource* buffer; - uint32_t stride; - uint32_t offset; - } vertex_buffers[96]; - size_t vertex_buffer_count; - - // Texture samplers. - struct SamplerInput { - uint32_t input_index; - TextureResource* texture; - SamplerStateResource* sampler_state; - }; - SamplerInput vertex_shader_samplers[32]; - size_t vertex_shader_sampler_count; - SamplerInput pixel_shader_samplers[32]; - size_t pixel_shader_sampler_count; -}; - -} // namespace gpu -} // namespace xe - -#endif // XENIA_GPU_DRAW_COMMAND_H_ diff --git a/src/xenia/gpu/nop/nop_gpu-private.h b/src/xenia/gpu/gl4/gl4_gpu-private.h similarity index 73% rename from src/xenia/gpu/nop/nop_gpu-private.h rename to src/xenia/gpu/gl4/gl4_gpu-private.h index 8631c82fc..a19e7a092 100644 --- a/src/xenia/gpu/nop/nop_gpu-private.h +++ b/src/xenia/gpu/gl4/gl4_gpu-private.h @@ -7,22 +7,22 @@ ****************************************************************************** */ -#ifndef XENIA_GPU_NOP_NOP_GPU_PRIVATE_H_ -#define XENIA_GPU_NOP_NOP_GPU_PRIVATE_H_ +#ifndef XENIA_GPU_GL4_GL4_GPU_PRIVATE_H_ +#define XENIA_GPU_GL4_GL4_GPU_PRIVATE_H_ + +// GL headers #include -#include +#include namespace xe { namespace gpu { -namespace nop { +namespace gl4 { +// - - - -} // namespace nop +} // namespace gl4 } // namespace gpu } // namespace xe -#endif // XENIA_GPU_NOP_NOP_PRIVATE_H_ +#endif // XENIA_GPU_GL4_GL4_GPU_PRIVATE_H_ diff --git a/src/xenia/gpu/nop/nop_gpu.cc b/src/xenia/gpu/gl4/gl4_gpu.cc similarity index 56% rename from src/xenia/gpu/nop/nop_gpu.cc rename to src/xenia/gpu/gl4/gl4_gpu.cc index e9281f404..a6518d891 100644 --- a/src/xenia/gpu/nop/nop_gpu.cc +++ b/src/xenia/gpu/gl4/gl4_gpu.cc @@ -2,20 +2,19 @@ ****************************************************************************** * Xenia : Xbox 360 Emulator Research Project * ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * + * Copyright 2014 Ben Vanik. All rights reserved. * * Released under the BSD license - see LICENSE in the root for more details. * ****************************************************************************** */ -#include +#include -#include +//#include -using namespace xe; -using namespace xe::gpu; -using namespace xe::gpu::nop; +namespace xe { +namespace gpu { +namespace gl4 { -namespace { void InitializeIfNeeded(); void CleanupOnShutdown(); @@ -32,9 +31,18 @@ void InitializeIfNeeded() { } void CleanupOnShutdown() {} + +class GL4GraphicsSystem : public GraphicsSystem { + public: + GL4GraphicsSystem(Emulator* emulator) : GraphicsSystem(emulator) {} + ~GL4GraphicsSystem() override = default; +}; + +std::unique_ptr Create(Emulator* emulator) { + InitializeIfNeeded(); + return std::make_unique(emulator); } -std::unique_ptr xe::gpu::nop::Create(Emulator* emulator) { - InitializeIfNeeded(); - return std::make_unique(emulator); -} +} // namespace gl4 +} // namespace gpu +} // namespace xe diff --git a/src/xenia/gpu/nop/nop_gpu.h b/src/xenia/gpu/gl4/gl4_gpu.h similarity index 68% rename from src/xenia/gpu/nop/nop_gpu.h rename to src/xenia/gpu/gl4/gl4_gpu.h index fadea2079..65c3dfaa6 100644 --- a/src/xenia/gpu/nop/nop_gpu.h +++ b/src/xenia/gpu/gl4/gl4_gpu.h @@ -2,31 +2,27 @@ ****************************************************************************** * Xenia : Xbox 360 Emulator Research Project * ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * + * Copyright 2014 Ben Vanik. All rights reserved. * * Released under the BSD license - see LICENSE in the root for more details. * ****************************************************************************** */ -#ifndef XENIA_GPU_NOP_NOP_GPU_H_ -#define XENIA_GPU_NOP_NOP_GPU_H_ +#ifndef XENIA_GPU_GL4_GL4_GPU_H_ +#define XENIA_GPU_GL4_GL4_GPU_H_ #include #include - -namespace xe { -class Emulator; -} // namespace xe +#include namespace xe { namespace gpu { -class GraphicsSystem; -namespace nop { +namespace gl4 { std::unique_ptr Create(Emulator* emulator); -} // namespace nop +} // namespace gl4 } // namespace gpu } // namespace xe -#endif // XENIA_GPU_NOP_NOP_GPU_H_ +#endif // XENIA_GPU_GL4_GL4_GPU_H_ diff --git a/src/xenia/gpu/gl4/sources.gypi b/src/xenia/gpu/gl4/sources.gypi new file mode 100644 index 000000000..fd63ebcbc --- /dev/null +++ b/src/xenia/gpu/gl4/sources.gypi @@ -0,0 +1,8 @@ +# Copyright 2014 Ben Vanik. All Rights Reserved. +{ + 'sources': [ + 'gl4_gpu-private.h', + 'gl4_gpu.cc', + 'gl4_gpu.h', + ], +} diff --git a/src/xenia/gpu/gpu-private.h b/src/xenia/gpu/gpu-private.h index cdaf4346d..aafa820fd 100644 --- a/src/xenia/gpu/gpu-private.h +++ b/src/xenia/gpu/gpu-private.h @@ -12,13 +12,9 @@ #include - DECLARE_string(gpu); DECLARE_bool(trace_ring_buffer); DECLARE_string(dump_shaders); -DECLARE_uint64(max_draw_elements); - - #endif // XENIA_GPU_PRIVATE_H_ diff --git a/src/xenia/gpu/gpu.cc b/src/xenia/gpu/gpu.cc index 8462cc65c..66a1688de 100644 --- a/src/xenia/gpu/gpu.cc +++ b/src/xenia/gpu/gpu.cc @@ -10,49 +10,34 @@ #include #include -using namespace xe; -using namespace xe::gpu; +// TODO(benvanik): based on platform. +#include -DEFINE_string(gpu, "any", "Graphics system. Use: [any, nop, d3d11]"); +namespace xe { +namespace gpu { + +DEFINE_string(gpu, "any", "Graphics system. Use: [any, gl4]"); DEFINE_bool(trace_ring_buffer, false, "Trace GPU ring buffer packets."); DEFINE_string(dump_shaders, "", "Path to write GPU shaders to as they are compiled."); -DEFINE_uint64(max_draw_elements, 0, - "Maximum element count; anything over this is ignored."); - -#include -std::unique_ptr xe::gpu::CreateNop(Emulator* emulator) { - return xe::gpu::nop::Create(emulator); -} - -#if XE_PLATFORM_WIN32 -#include -std::unique_ptr xe::gpu::CreateD3D11(Emulator* emulator) { - return xe::gpu::d3d11::Create(emulator); -} -#endif // WIN32 - -std::unique_ptr xe::gpu::Create(Emulator* emulator) { - if (FLAGS_gpu.compare("nop") == 0) { - return CreateNop(emulator); -#if XE_PLATFORM_WIN32 - } else if (FLAGS_gpu.compare("d3d11") == 0) { - return CreateD3D11(emulator); -#endif // WIN32 +std::unique_ptr Create(Emulator* emulator) { + if (FLAGS_gpu.compare("gl4") == 0) { + return xe::gpu::gl4::Create(emulator); } else { // Create best available. std::unique_ptr best; -#if XE_PLATFORM_WIN32 - best = CreateD3D11(emulator); + best = xe::gpu::gl4::Create(emulator); if (best) { return best; } -#endif // WIN32 - // Fallback to nop. - return CreateNop(emulator); + // Nothing! + return nullptr; } } + +} // namespace gpu +} // namespace xe diff --git a/src/xenia/gpu/gpu.h b/src/xenia/gpu/gpu.h index 43690f1e2..1a3aa06a7 100644 --- a/src/xenia/gpu/gpu.h +++ b/src/xenia/gpu/gpu.h @@ -23,11 +23,7 @@ namespace gpu { std::unique_ptr Create(Emulator* emulator); -std::unique_ptr CreateNop(Emulator* emulator); - -#if XE_PLATFORM_WIN32 -std::unique_ptr CreateD3D11(Emulator* emulator); -#endif // WIN32 +std::unique_ptr CreateGL4(Emulator* emulator); } // namespace gpu } // namespace xe diff --git a/src/xenia/gpu/graphics_driver.cc b/src/xenia/gpu/graphics_driver.cc deleted file mode 100644 index d5a631f28..000000000 --- a/src/xenia/gpu/graphics_driver.cc +++ /dev/null @@ -1,307 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#include - - -using namespace xe; -using namespace xe::gpu; -using namespace xe::gpu::xenos; - -GraphicsDriver::GraphicsDriver(Memory* memory) : memory_(memory) {} - -GraphicsDriver::~GraphicsDriver() = default; - -int GraphicsDriver::LoadShader(XE_GPU_SHADER_TYPE type, - uint32_t address, uint32_t length, - uint32_t start) { - MemoryRange memory_range( - memory_->Translate(address), - address, length); - - ShaderResource* shader = nullptr; - if (type == XE_GPU_SHADER_TYPE_VERTEX) { - VertexShaderResource::Info info; - shader = vertex_shader_ = resource_cache()->FetchVertexShader(memory_range, - info); - if (!vertex_shader_) { - XELOGE("Unable to fetch vertex shader"); - return 1; - } - } else { - PixelShaderResource::Info info; - shader = pixel_shader_ = resource_cache()->FetchPixelShader(memory_range, - info); - if (!pixel_shader_) { - XELOGE("Unable to fetch pixel shader"); - return 1; - } - } - - if (!shader->is_prepared()) { - // Disassemble. - const char* source = shader->disasm_src(); - XELOGGPU("Set shader %d at %0.8X (%db):\n%s", - type, address, length, - source ? source : ""); - } - - return 0; -} - -int GraphicsDriver::PrepareDraw(DrawCommand& command) { - SCOPE_profile_cpu_f("gpu"); - - // Ignore copies for now. - uint32_t enable_mode = register_file_[XE_GPU_REG_RB_MODECONTROL].u32 & 0x7; - if (enable_mode != 4) { - XELOGW("GPU: ignoring draw with enable mode %d", enable_mode); - return 1; - } - - // Reset the things we don't modify so that we have clean state. - command.prim_type = XE_GPU_PRIMITIVE_TYPE_POINT_LIST; - command.index_count = 0; - command.index_buffer = nullptr; - - // Generic stuff. - command.start_index = register_file_[XE_GPU_REG_VGT_INDX_OFFSET].u32; - command.base_vertex = 0; - - int ret; - ret = PopulateState(command); - if (ret) { - XELOGE("Unable to prepare draw state"); - return ret; - } - ret = PopulateConstantBuffers(command); - if (ret) { - XELOGE("Unable to prepare draw constant buffers"); - return ret; - } - ret = PopulateShaders(command); - if (ret) { - XELOGE("Unable to prepare draw shaders"); - return ret; - } - ret = PopulateInputAssembly(command); - if (ret) { - XELOGE("Unable to prepare draw input assembly"); - return ret; - } - ret = PopulateSamplers(command); - if (ret) { - XELOGE("Unable to prepare draw samplers"); - return ret; - } - return 0; -} - -int GraphicsDriver::PrepareDrawIndexBuffer( - DrawCommand& command, - uint32_t address, uint32_t length, - xenos::XE_GPU_ENDIAN endianness, - IndexFormat format) { - SCOPE_profile_cpu_f("gpu"); - - MemoryRange memory_range(memory_->Translate(address), address, length); - - IndexBufferResource::Info info; - info.endianness = endianness; - info.format = format; - - command.index_buffer = - resource_cache()->FetchIndexBuffer(memory_range, info); - if (!command.index_buffer) { - return 1; - } - return 0; -} - -int GraphicsDriver::PopulateState(DrawCommand& command) { - return 0; -} - -int GraphicsDriver::PopulateConstantBuffers(DrawCommand& command) { - command.float4_constants.count = 512; - command.float4_constants.values = - ®ister_file_[XE_GPU_REG_SHADER_CONSTANT_000_X].f32; - command.loop_constants.count = 32; - command.loop_constants.values = - ®ister_file_[XE_GPU_REG_SHADER_CONSTANT_LOOP_00].u32; - command.bool_constants.count = 8; - command.bool_constants.values = - ®ister_file_[XE_GPU_REG_SHADER_CONSTANT_BOOL_000_031].u32; - return 0; -} - -int GraphicsDriver::PopulateShaders(DrawCommand& command) { - SCOPE_profile_cpu_f("gpu"); - - if (!vertex_shader_) { - XELOGE("No vertex shader bound; ignoring"); - return 1; - } - if (!pixel_shader_) { - XELOGE("No pixel shader bound; ignoring"); - return 1; - } - - xe_gpu_program_cntl_t program_cntl; - program_cntl.dword_0 = register_file_[XE_GPU_REG_SQ_PROGRAM_CNTL].u32; - if (!vertex_shader_->is_prepared()) { - if (vertex_shader_->Prepare(program_cntl)) { - XELOGE("Unable to prepare vertex shader"); - return 1; - } - } - if (!pixel_shader_->is_prepared()) { - if (pixel_shader_->Prepare(program_cntl, vertex_shader_)) { - XELOGE("Unable to prepare pixel shader"); - return 1; - } - } - - command.vertex_shader = vertex_shader_; - command.pixel_shader = pixel_shader_; - - return 0; -} - -int GraphicsDriver::PopulateInputAssembly(DrawCommand& command) { - SCOPE_profile_cpu_f("gpu"); - - const auto& buffer_inputs = command.vertex_shader->buffer_inputs(); - command.vertex_buffer_count = buffer_inputs.count; - for (size_t n = 0; n < buffer_inputs.count; n++) { - const auto& desc = buffer_inputs.descs[n]; - - int r = XE_GPU_REG_SHADER_CONSTANT_FETCH_00_0 + (desc.fetch_slot / 3) * 6; - auto group = reinterpret_cast(®ister_file_.values[r]); - xe_gpu_vertex_fetch_t* fetch = nullptr; - switch (desc.fetch_slot % 3) { - case 0: - fetch = &group->vertex_fetch_0; - break; - case 1: - fetch = &group->vertex_fetch_1; - break; - case 2: - fetch = &group->vertex_fetch_2; - break; - } - assert_not_null(fetch); - assert_true(fetch->type == 0x3); // must be of type vertex - // TODO(benvanik): some games have type 2, which is texture - maybe - // fetch_slot wrong? - assert_not_zero(fetch->size); - - const auto& info = desc.info; - - MemoryRange memory_range; - memory_range.guest_base = fetch->address << 2; - memory_range.host_base = memory_->Translate(memory_range.guest_base); - memory_range.length = fetch->size * 4; - // TODO(benvanik): if the memory range is within the command buffer, we - // should use a cached transient buffer. - - auto buffer = resource_cache()->FetchVertexBuffer(memory_range, info); - if (!buffer) { - XELOGE("Unable to create vertex fetch buffer"); - return 1; - } - - command.vertex_buffers[n].input_index = desc.input_index; - command.vertex_buffers[n].buffer = buffer; - command.vertex_buffers[n].stride = desc.info.stride_words * 4; - command.vertex_buffers[n].offset = 0; - } - return 0; -} - -int GraphicsDriver::PopulateSamplers(DrawCommand& command) { - SCOPE_profile_cpu_f("gpu"); - - // Vertex texture samplers. - const auto& vertex_sampler_inputs = command.vertex_shader->sampler_inputs(); - command.vertex_shader_sampler_count = vertex_sampler_inputs.count; - for (size_t i = 0; i < command.vertex_shader_sampler_count; ++i) { - if (PopulateSamplerSet(vertex_sampler_inputs.descs[i], - command.vertex_shader_samplers[i])) { - return 1; - } - } - - // Pixel shader texture sampler. - const auto& pixel_sampler_inputs = command.pixel_shader->sampler_inputs(); - command.pixel_shader_sampler_count = pixel_sampler_inputs.count; - for (size_t i = 0; i < command.pixel_shader_sampler_count; ++i) { - if (PopulateSamplerSet(pixel_sampler_inputs.descs[i], - command.pixel_shader_samplers[i])) { - return 1; - } - } - - return 0; -} - -int GraphicsDriver::PopulateSamplerSet( - const ShaderResource::SamplerDesc& src_input, - DrawCommand::SamplerInput& dst_input) { - int r = XE_GPU_REG_SHADER_CONSTANT_FETCH_00_0 + src_input.fetch_slot * 6; - const auto group = (const xe_gpu_fetch_group_t*)®ister_file_.values[r]; - const xenos::xe_gpu_texture_fetch_t& fetch = group->texture_fetch; - if (fetch.type != 0x2) { - return 0; - } - - dst_input.input_index = src_input.input_index; - dst_input.texture = nullptr; - dst_input.sampler_state = nullptr; - - TextureResource::Info info; - if (!TextureResource::Info::Prepare(fetch, info)) { - XELOGE("D3D11: unable to parse texture fetcher info"); - return 0; // invalid texture used - } - if (info.format == DXGI_FORMAT_UNKNOWN) { - XELOGW("D3D11: unknown texture format %d", info.format); - return 0; // invalid texture used - } - - // TODO(benvanik): quick validate without refetching intraframe. - // Fetch texture from the cache. - MemoryRange memory_range; - memory_range.guest_base = fetch.address << 12; - memory_range.host_base = memory_->Translate(memory_range.guest_base); - memory_range.length = info.input_length; - - auto texture = resource_cache()->FetchTexture(memory_range, info); - if (!texture) { - XELOGW("D3D11: unable to fetch texture"); - return 0; // invalid texture used - } - - SamplerStateResource::Info sampler_info; - if (!SamplerStateResource::Info::Prepare(fetch, - src_input.tex_fetch, - sampler_info)) { - XELOGW("D3D11: unable to parse sampler info"); - return 0; // invalid texture used - } - auto sampler_state = resource_cache()->FetchSamplerState(sampler_info); - if (!sampler_state) { - XELOGW("D3D11: unable to fetch sampler"); - return 0; // invalid texture used - } - - dst_input.texture = texture; - dst_input.sampler_state = sampler_state; - return 0; -} diff --git a/src/xenia/gpu/graphics_driver.h b/src/xenia/gpu/graphics_driver.h deleted file mode 100644 index dd48a04ce..000000000 --- a/src/xenia/gpu/graphics_driver.h +++ /dev/null @@ -1,67 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef XENIA_GPU_GRAPHICS_DRIVER_H_ -#define XENIA_GPU_GRAPHICS_DRIVER_H_ - -#include -#include -#include -#include -#include - -namespace xe { -namespace gpu { - -class GraphicsDriver { -public: - virtual ~GraphicsDriver(); - - Memory* memory() const { return memory_; } - virtual ResourceCache* resource_cache() const = 0; - RegisterFile* register_file() { return ®ister_file_; }; - - virtual int Initialize() = 0; - - int LoadShader(xenos::XE_GPU_SHADER_TYPE type, - uint32_t address, uint32_t length, - uint32_t start); - - int PrepareDraw(DrawCommand& command); - int PrepareDrawIndexBuffer(DrawCommand& command, - uint32_t address, uint32_t length, - xenos::XE_GPU_ENDIAN endianness, - IndexFormat format); - virtual int Draw(const DrawCommand& command) = 0; - - virtual int Resolve() = 0; - -private: - int PopulateState(DrawCommand& command); - int PopulateConstantBuffers(DrawCommand& command); - int PopulateShaders(DrawCommand& command); - int PopulateInputAssembly(DrawCommand& command); - int PopulateSamplers(DrawCommand& command); - int PopulateSamplerSet(const ShaderResource::SamplerDesc& src_input, - DrawCommand::SamplerInput& dst_input); - -protected: - GraphicsDriver(Memory* memory); - - Memory* memory_; - RegisterFile register_file_; - - VertexShaderResource* vertex_shader_; - PixelShaderResource* pixel_shader_; -}; - -} // namespace gpu -} // namespace xe - -#endif // XENIA_GPU_GRAPHICS_DRIVER_H_ diff --git a/src/xenia/gpu/graphics_system.cc b/src/xenia/gpu/graphics_system.cc index acc587b81..e416a3e0d 100644 --- a/src/xenia/gpu/graphics_system.cc +++ b/src/xenia/gpu/graphics_system.cc @@ -12,111 +12,26 @@ #include #include #include -#include #include -#include -#include +namespace xe { +namespace gpu { -using namespace xe; -using namespace xe::cpu; -using namespace xe::gpu; -using namespace xe::gpu::xenos; +GraphicsSystem::GraphicsSystem(Emulator* emulator) + : emulator_(emulator), + memory_(emulator->memory()), + interrupt_callback_(0), + interrupt_callback_data_(0) {} - -GraphicsSystem::GraphicsSystem(Emulator* emulator) : - emulator_(emulator), memory_(emulator->memory()), - running_(false), driver_(nullptr), - command_processor_(nullptr), - interrupt_callback_(0), interrupt_callback_data_(0), - thread_wait_(nullptr) { - // Create the run loop used for any windows/etc. - // This must be done on the thread we create the driver. - run_loop_ = xe_run_loop_create(); - thread_wait_ = CreateEvent(NULL, TRUE, FALSE, NULL); -} - -GraphicsSystem::~GraphicsSystem() { - CloseHandle(thread_wait_); -} +GraphicsSystem::~GraphicsSystem() {} X_STATUS GraphicsSystem::Setup() { processor_ = emulator_->processor(); - // Create worker. - command_processor_ = new CommandProcessor(this, memory_); - - // Let the processor know we want register access callbacks. - emulator_->memory()->AddMappedRange( - 0x7FC80000, - 0xFFFF0000, - 0x0000FFFF, - this, - reinterpret_cast(MMIOReadRegisterThunk), - reinterpret_cast(MMIOWriteRegisterThunk)); - - // Create worker thread. - // This will initialize the graphics system. - // Init needs to happen there so that any thread-local stuff - // is created on the right thread. - running_ = true; - thread_ = std::thread(std::bind(&GraphicsSystem::ThreadStart, this)); - WaitForSingleObject(thread_wait_, INFINITE); return X_STATUS_SUCCESS; } -void GraphicsSystem::ThreadStart() { - poly::threading::set_name("GraphicsSystemThread"); - xe::Profiler::ThreadEnter("GraphicsSystemThread"); - - xe_run_loop_ref run_loop = xe_run_loop_retain(run_loop_); - - // Initialize driver and ringbuffer. - Initialize(); - assert_not_null(driver_); - SetEvent(thread_wait_); - - // Main run loop. - while (running_) { - // Peek main run loop. - { - SCOPE_profile_cpu_i("gpu", "GraphicsSystemRunLoopPump"); - if (xe_run_loop_pump(run_loop)) { - break; - } - } - if (!running_) { - break; - } - - // Pump worker. - command_processor_->Pump(); - - if (!running_) { - break; - } - - // Pump graphics system. - Pump(); - } - running_ = false; - - xe_run_loop_release(run_loop); - - xe::Profiler::ThreadExit(); -} - -void GraphicsSystem::Initialize() { -} - -void GraphicsSystem::Shutdown() { - running_ = false; - thread_.join(); - - delete command_processor_; - - xe_run_loop_release(run_loop_); -} +void GraphicsSystem::Shutdown() {} void GraphicsSystem::SetInterruptCallback(uint32_t callback, uint32_t user_data) { @@ -126,70 +41,15 @@ void GraphicsSystem::SetInterruptCallback(uint32_t callback, } void GraphicsSystem::InitializeRingBuffer(uint32_t ptr, uint32_t page_count) { - // TODO(benvanik): an event? - while (!driver_) { - Sleep(0); - } - assert_not_null(driver_); - command_processor_->Initialize(driver_, ptr, page_count); + // } void GraphicsSystem::EnableReadPointerWriteBack(uint32_t ptr, uint32_t block_size) { - command_processor_->EnableReadPointerWriteBack(ptr, block_size); + // } -uint64_t GraphicsSystem::ReadRegister(uint64_t addr) { - uint32_t r = addr & 0xFFFF; - if (FLAGS_trace_ring_buffer) { - XELOGGPU("ReadRegister(%.4X)", r); - } - - RegisterFile* regs = driver_->register_file(); - - switch (r) { - case 0x6530: // ???? - return 1; - case 0x6544: // ? vblank pending? - return 1; - case 0x6584: // ???? - return 1; - } - - assert_true(r >= 0 && r < RegisterFile::kRegisterCount); - return regs->values[r].u32; -} - -void GraphicsSystem::WriteRegister(uint64_t addr, uint64_t value) { - uint32_t r = addr & 0xFFFF; - if (FLAGS_trace_ring_buffer) { - XELOGGPU("WriteRegister(%.4X, %.8X)", r, value); - } - - RegisterFile* regs = driver_->register_file(); - - switch (r) { - case 0x0714: // CP_RB_WPTR - command_processor_->UpdateWritePointer((uint32_t)value); - break; - case 0x6110: // ? swap related? - XELOGW("Unimplemented GPU register %.4X write: %.8X", r, value); - return; - default: - XELOGW("Unknown GPU register %.4X write: %.8X", r, value); - break; - } - - assert_true(r >= 0 && r < RegisterFile::kRegisterCount); - regs->values[r].u32 = (uint32_t)value; -} - -void GraphicsSystem::MarkVblank() { - command_processor_->increment_counter(); -} - -void GraphicsSystem::DispatchInterruptCallback( - uint32_t source, uint32_t cpu) { +void GraphicsSystem::DispatchInterruptCallback(uint32_t source, uint32_t cpu) { // Pick a CPU, if needed. We're going to guess 2. Because. if (cpu == 0xFFFFFFFF) { cpu = 2; @@ -202,7 +62,10 @@ void GraphicsSystem::DispatchInterruptCallback( if (!interrupt_callback_) { return; } - uint64_t args[] = { source, interrupt_callback_data_ }; - processor_->ExecuteInterrupt( - cpu, interrupt_callback_, args, poly::countof(args)); + uint64_t args[] = {source, interrupt_callback_data_}; + processor_->ExecuteInterrupt(cpu, interrupt_callback_, args, + poly::countof(args)); } + +} // namespace gpu +} // namespace xe diff --git a/src/xenia/gpu/graphics_system.h b/src/xenia/gpu/graphics_system.h index e983cdc72..7839d0180 100644 --- a/src/xenia/gpu/graphics_system.h +++ b/src/xenia/gpu/graphics_system.h @@ -20,9 +20,6 @@ namespace xe { namespace gpu { -class CommandProcessor; -class GraphicsDriver; - class GraphicsSystem { public: virtual ~GraphicsSystem(); @@ -38,45 +35,17 @@ class GraphicsSystem { void InitializeRingBuffer(uint32_t ptr, uint32_t page_count); void EnableReadPointerWriteBack(uint32_t ptr, uint32_t block_size); - virtual uint64_t ReadRegister(uint64_t addr); - virtual void WriteRegister(uint64_t addr, uint64_t value); - - void MarkVblank(); - void DispatchInterruptCallback(uint32_t source, uint32_t cpu = 0xFFFFFFFF); - virtual void Swap() = 0; - - protected: - virtual void Initialize(); - virtual void Pump() = 0; - - private: - void ThreadStart(); - - static uint64_t MMIOReadRegisterThunk(GraphicsSystem* gs, uint64_t addr) { - return gs->ReadRegister(addr); - } - static void MMIOWriteRegisterThunk(GraphicsSystem* gs, uint64_t addr, - uint64_t value) { - gs->WriteRegister(addr, value); - } - protected: GraphicsSystem(Emulator* emulator); + void DispatchInterruptCallback(uint32_t source, uint32_t cpu); + Emulator* emulator_; Memory* memory_; cpu::Processor* processor_; - xe_run_loop_ref run_loop_; - std::thread thread_; - std::atomic running_; - - GraphicsDriver* driver_; - CommandProcessor* command_processor_; - uint32_t interrupt_callback_; uint32_t interrupt_callback_data_; - HANDLE thread_wait_; }; } // namespace gpu diff --git a/src/xenia/gpu/nop/nop_graphics_driver.cc b/src/xenia/gpu/nop/nop_graphics_driver.cc deleted file mode 100644 index b710b85e4..000000000 --- a/src/xenia/gpu/nop/nop_graphics_driver.cc +++ /dev/null @@ -1,38 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#include - -#include - - -using namespace xe; -using namespace xe::gpu; -using namespace xe::gpu::nop; -using namespace xe::gpu::xenos; - - -NopGraphicsDriver::NopGraphicsDriver(Memory* memory) - : GraphicsDriver(memory), resource_cache_(nullptr) { -} - -NopGraphicsDriver::~NopGraphicsDriver() { -} - -int NopGraphicsDriver::Initialize() { - return 0; -} - -int NopGraphicsDriver::Draw(const DrawCommand& command) { - return 0; -} - -int NopGraphicsDriver::Resolve() { - return 0; -} diff --git a/src/xenia/gpu/nop/nop_graphics_driver.h b/src/xenia/gpu/nop/nop_graphics_driver.h deleted file mode 100644 index 457105159..000000000 --- a/src/xenia/gpu/nop/nop_graphics_driver.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef XENIA_GPU_NOP_NOP_GRAPHICS_DRIVER_H_ -#define XENIA_GPU_NOP_NOP_GRAPHICS_DRIVER_H_ - -#include -#include -#include -#include - -namespace xe { -namespace gpu { -namespace nop { - -class NopGraphicsDriver : public GraphicsDriver { -public: - NopGraphicsDriver(Memory* memory); - virtual ~NopGraphicsDriver(); - - ResourceCache* resource_cache() const override { return resource_cache_; } - - int Initialize() override; - - int Draw(const DrawCommand& command) override; - - int Resolve() override; - -protected: - ResourceCache* resource_cache_; -}; - -} // namespace nop -} // namespace gpu -} // namespace xe - -#endif // XENIA_GPU_NOP_NOP_GRAPHICS_DRIVER_H_ diff --git a/src/xenia/gpu/nop/nop_graphics_system.cc b/src/xenia/gpu/nop/nop_graphics_system.cc deleted file mode 100644 index 8e470375d..000000000 --- a/src/xenia/gpu/nop/nop_graphics_system.cc +++ /dev/null @@ -1,72 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#include - -#include -#include - - -using namespace xe; -using namespace xe::gpu; -using namespace xe::gpu::nop; - - -namespace { - -void __stdcall NopGraphicsSystemVsyncCallback(NopGraphicsSystem* gs, BOOLEAN) { - gs->MarkVblank(); - gs->DispatchInterruptCallback(0); -} - -} - - -NopGraphicsSystem::NopGraphicsSystem(Emulator* emulator) : - GraphicsSystem(emulator), - timer_queue_(NULL), - vsync_timer_(NULL) { -} - -NopGraphicsSystem::~NopGraphicsSystem() { -} - -void NopGraphicsSystem::Initialize() { - GraphicsSystem::Initialize(); - - assert_null(driver_); - driver_ = new NopGraphicsDriver(memory_); - - assert_null(timer_queue_); - assert_null(vsync_timer_); - - timer_queue_ = CreateTimerQueue(); - CreateTimerQueueTimer( - &vsync_timer_, - timer_queue_, - (WAITORTIMERCALLBACK)NopGraphicsSystemVsyncCallback, - this, - 16, - 100, - WT_EXECUTEINTIMERTHREAD); -} - -void NopGraphicsSystem::Pump() { -} - -void NopGraphicsSystem::Shutdown() { - if (vsync_timer_) { - DeleteTimerQueueTimer(timer_queue_, vsync_timer_, NULL); - } - if (timer_queue_) { - DeleteTimerQueueEx(timer_queue_, NULL); - } - - GraphicsSystem::Shutdown(); -} diff --git a/src/xenia/gpu/nop/nop_graphics_system.h b/src/xenia/gpu/nop/nop_graphics_system.h deleted file mode 100644 index 0252826b7..000000000 --- a/src/xenia/gpu/nop/nop_graphics_system.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef XENIA_GPU_NOP_NOP_GRAPHICS_SYSTEM_H_ -#define XENIA_GPU_NOP_NOP_GRAPHICS_SYSTEM_H_ - -#include -#include -#include - -namespace xe { -namespace gpu { -namespace nop { - -class NopGraphicsSystem : public GraphicsSystem { -public: - NopGraphicsSystem(Emulator* emulator); - virtual ~NopGraphicsSystem(); - - virtual void Shutdown(); - - void Swap() override {} - -protected: - virtual void Initialize(); - virtual void Pump(); - -private: - HANDLE timer_queue_; - HANDLE vsync_timer_; -}; - -} // namespace nop -} // namespace gpu -} // namespace xe - -#endif // XENIA_GPU_NOP_NOP_GRAPHICS_SYSTEM_H_ diff --git a/src/xenia/gpu/nop/sources.gypi b/src/xenia/gpu/nop/sources.gypi deleted file mode 100644 index 28892e9b3..000000000 --- a/src/xenia/gpu/nop/sources.gypi +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright 2013 Ben Vanik. All Rights Reserved. -{ - 'sources': [ - 'nop_gpu-private.h', - 'nop_gpu.cc', - 'nop_gpu.h', - 'nop_graphics_driver.cc', - 'nop_graphics_driver.h', - 'nop_graphics_system.cc', - 'nop_graphics_system.h', - ], -} diff --git a/src/xenia/gpu/register_file.cc b/src/xenia/gpu/register_file.cc index a2eec25fe..e388d926f 100644 --- a/src/xenia/gpu/register_file.cc +++ b/src/xenia/gpu/register_file.cc @@ -9,8 +9,8 @@ #include -using namespace xe; -using namespace xe::gpu; +namespace xe { +namespace gpu { RegisterFile::RegisterFile() { memset(values, 0, sizeof(values)); } @@ -19,9 +19,12 @@ const char* RegisterFile::GetRegisterName(uint32_t index) { #define XE_GPU_REGISTER(index, type, name) \ case index: \ return #name; -#include +#include #undef XE_GPU_REGISTER default: - return NULL; + return nullptr; } } + +} // namespace gpu +} // namespace xe diff --git a/src/xenia/gpu/register_file.h b/src/xenia/gpu/register_file.h index 929536f73..0b4b84ca5 100644 --- a/src/xenia/gpu/register_file.h +++ b/src/xenia/gpu/register_file.h @@ -16,28 +16,25 @@ namespace xe { namespace gpu { enum Register { -#define XE_GPU_REGISTER(index, type, name) \ - XE_GPU_REG_##name = index, -#include +#define XE_GPU_REGISTER(index, type, name) XE_GPU_REG_##name = index, +#include #undef XE_GPU_REGISTER }; class RegisterFile { -public: + public: RegisterFile(); const char* GetRegisterName(uint32_t index); static const size_t kRegisterCount = 0x5003; union RegisterValue { - uint32_t u32; - float f32; + uint32_t u32; + float f32; }; RegisterValue values[kRegisterCount]; - RegisterValue& operator[](Register reg) { - return values[reg]; - } + RegisterValue& operator[](Register reg) { return values[reg]; } }; } // namespace gpu diff --git a/src/xenia/gpu/xenos/register_table.inc b/src/xenia/gpu/register_table.inc similarity index 98% rename from src/xenia/gpu/xenos/register_table.inc rename to src/xenia/gpu/register_table.inc index 25a5890a0..e3d8c5758 100644 --- a/src/xenia/gpu/xenos/register_table.inc +++ b/src/xenia/gpu/register_table.inc @@ -1,2478 +1,2478 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -// This is a partial file designed to be included by other files when -// constructing various tables. - -// Almost all of these values are taken directly from: -// https://github.com/freedreno/amd-gpu/blob/master/include/reg/yamato/22/yamato_offset.h - -//#define XE_GPU_REGISTER(index, type, name) - -XE_GPU_REGISTER(0x01DD, dword, SCRATCH_ADDR) -XE_GPU_REGISTER(0x01DC, dword, SCRATCH_UMSK) - -XE_GPU_REGISTER(0x0578, dword, SCRATCH_REG0) // interrupt sync -XE_GPU_REGISTER(0x0579, dword, SCRATCH_REG1) // present interval -XE_GPU_REGISTER(0x057A, dword, SCRATCH_REG2) -XE_GPU_REGISTER(0x057B, dword, SCRATCH_REG3) -XE_GPU_REGISTER(0x057C, dword, CALLBACK_ADDRESS) -XE_GPU_REGISTER(0x057D, dword, CALLBACK_CONTEXT) -XE_GPU_REGISTER(0x057E, dword, SCRATCH_REG6) -XE_GPU_REGISTER(0x057F, dword, SCRATCH_REG7) - -XE_GPU_REGISTER(0x05C8, dword, WAIT_UNTIL) - -XE_GPU_REGISTER(0x0A02, dword, UNKNOWN_0A02) -XE_GPU_REGISTER(0x0A03, dword, UNKNOWN_0A03) -XE_GPU_REGISTER(0x0A04, dword, UNKNOWN_0A04) -XE_GPU_REGISTER(0x0A05, dword, UNKNOWN_0A05) - -XE_GPU_REGISTER(0x0A2F, dword, COHER_SIZE_HOST) -XE_GPU_REGISTER(0x0A30, dword, COHER_BASE_HOST) -XE_GPU_REGISTER(0x0A31, dword, COHER_STATUS_HOST) - -XE_GPU_REGISTER(0x0D00, dword, SQ_GPR_MANAGEMENT) -XE_GPU_REGISTER(0x0D01, dword, SQ_FLOW_CONTROL) -XE_GPU_REGISTER(0x0D02, dword, SQ_INST_STORE_MANAGMENT) -XE_GPU_REGISTER(0x0D04, dword, SQ_EO_RT) - -XE_GPU_REGISTER(0x0C85, dword, PA_CL_ENHANCE) - -XE_GPU_REGISTER(0x0E42, dword, UNKNOWN_0E42) - -XE_GPU_REGISTER(0x0F01, dword, RB_BC_CONTROL) - -XE_GPU_REGISTER(0x2000, dword, RB_SURFACE_INFO) -XE_GPU_REGISTER(0x2001, dword, RB_COLOR_INFO) -XE_GPU_REGISTER(0x2002, dword, RB_DEPTH_INFO) -XE_GPU_REGISTER(0x2003, dword, RB_COLOR1_INFO) -XE_GPU_REGISTER(0x2004, dword, RB_COLOR2_INFO) -XE_GPU_REGISTER(0x2005, dword, RB_COLOR3_INFO) -XE_GPU_REGISTER(0x2006, dword, COHER_DEST_BASE_0) -XE_GPU_REGISTER(0x2007, dword, COHER_DEST_BASE_1) -XE_GPU_REGISTER(0x2008, dword, COHER_DEST_BASE_2) -XE_GPU_REGISTER(0x2009, dword, COHER_DEST_BASE_3) -XE_GPU_REGISTER(0x200A, dword, COHER_DEST_BASE_4) -XE_GPU_REGISTER(0x200B, dword, COHER_DEST_BASE_5) -XE_GPU_REGISTER(0x200C, dword, COHER_DEST_BASE_6) -XE_GPU_REGISTER(0x200D, dword, COHER_DEST_BASE_7) -XE_GPU_REGISTER(0x200E, dword, PA_SC_SCREEN_SCISSOR_TL) -XE_GPU_REGISTER(0x200F, dword, PA_SC_SCREEN_SCISSOR_BR) - -XE_GPU_REGISTER(0x2080, dword, PA_SC_WINDOW_OFFSET) -XE_GPU_REGISTER(0x2081, dword, PA_SC_WINDOW_SCISSOR_TL) -XE_GPU_REGISTER(0x2082, dword, PA_SC_WINDOW_SCISSOR_BR) - -XE_GPU_REGISTER(0x2100, dword, VGT_MAX_VTX_INDX) -XE_GPU_REGISTER(0x2101, dword, VGT_MIN_VTX_INDX) -XE_GPU_REGISTER(0x2102, dword, VGT_INDX_OFFSET) -XE_GPU_REGISTER(0x2103, dword, VGT_MULTI_PRIM_IB_RESET_INDX) -XE_GPU_REGISTER(0x2104, dword, RB_COLOR_MASK) -XE_GPU_REGISTER(0x2105, float, RB_BLEND_RED) -XE_GPU_REGISTER(0x2106, float, RB_BLEND_GREEN) -XE_GPU_REGISTER(0x2107, float, RB_BLEND_BLUE) -XE_GPU_REGISTER(0x2108, float, RB_BLEND_ALPHA) -XE_GPU_REGISTER(0x2109, float, RB_FOG_COLOR_RED) -XE_GPU_REGISTER(0x210A, float, RB_FOG_COLOR_GREEN) -XE_GPU_REGISTER(0x210B, float, RB_FOG_COLOR_BLUE) -XE_GPU_REGISTER(0x210C, dword, RB_STENCILREFMASK_BF) -XE_GPU_REGISTER(0x210D, dword, RB_STENCILREFMASK) -XE_GPU_REGISTER(0x210E, float, RB_ALPHA_REF) -XE_GPU_REGISTER(0x210F, float, PA_CL_VPORT_XSCALE) -XE_GPU_REGISTER(0x2110, float, PA_CL_VPORT_XOFFSET) -XE_GPU_REGISTER(0x2111, float, PA_CL_VPORT_YSCALE) -XE_GPU_REGISTER(0x2112, float, PA_CL_VPORT_YOFFSET) -XE_GPU_REGISTER(0x2113, float, PA_CL_VPORT_ZSCALE) -XE_GPU_REGISTER(0x2114, float, PA_CL_VPORT_ZOFFSET) - -XE_GPU_REGISTER(0x2180, dword, SQ_PROGRAM_CNTL) -XE_GPU_REGISTER(0x2181, dword, SQ_CONTEXT_MISC) -XE_GPU_REGISTER(0x2182, dword, SQ_INTERPOLATOR_CNTL) -XE_GPU_REGISTER(0x2183, dword, SQ_WRAPPING_0) -XE_GPU_REGISTER(0x2184, dword, SQ_WRAPPING_1) - -XE_GPU_REGISTER(0x21F9, dword, VGT_EVENT_INITIATOR) - -XE_GPU_REGISTER(0x2200, dword, RB_DEPTHCONTROL) -XE_GPU_REGISTER(0x2201, dword, RB_BLENDCONTROL_0) -XE_GPU_REGISTER(0x2202, dword, RB_COLORCONTROL) -XE_GPU_REGISTER(0x2203, dword, RB_TILECONTROL) -XE_GPU_REGISTER(0x2204, dword, PA_CL_CLIP_CNTL) -XE_GPU_REGISTER(0x2205, dword, PA_SU_SC_MODE_CNTL) -XE_GPU_REGISTER(0x2206, dword, PA_CL_VTE_CNTL) -XE_GPU_REGISTER(0x2207, dword, VGT_CURRENT_BIN_ID_MIN) -XE_GPU_REGISTER(0x2208, dword, RB_MODECONTROL) -XE_GPU_REGISTER(0x2209, dword, RB_BLENDCONTROL_1) -XE_GPU_REGISTER(0x220A, dword, RB_BLENDCONTROL_2) -XE_GPU_REGISTER(0x220B, dword, RB_BLENDCONTROL_3) - -XE_GPU_REGISTER(0x2280, dword, PA_SU_POINT_SIZE) -XE_GPU_REGISTER(0x2281, dword, PA_SU_POINT_MINMAX) -XE_GPU_REGISTER(0x2282, dword, PA_SU_LINE_CNTL) -XE_GPU_REGISTER(0x2283, dword, PA_SC_LINE_STIPPLE) -XE_GPU_REGISTER(0x2284, dword, VGT_OUTPUT_PATH_CNTL) -XE_GPU_REGISTER(0x2285, dword, VGT_HOS_CNTL) -XE_GPU_REGISTER(0x2286, float, VGT_HOS_MAX_TESS_LEVEL) -XE_GPU_REGISTER(0x2287, float, VGT_HOS_MIN_TESS_LEVEL) -XE_GPU_REGISTER(0x2288, dword, VGT_HOS_REUSE_DEPTH) -XE_GPU_REGISTER(0x2289, dword, VGT_GROUP_PRIM_TYPE) -XE_GPU_REGISTER(0x228A, dword, VGT_GROUP_FIRST_DECR) -XE_GPU_REGISTER(0x228B, dword, VGT_GROUP_DECR) -XE_GPU_REGISTER(0x228C, dword, VGT_GROUP_VECT_0_CNTL) -XE_GPU_REGISTER(0x228D, dword, VGT_GROUP_VECT_1_CNTL) -XE_GPU_REGISTER(0x228E, dword, VGT_GROUP_VECT_0_FMT_CNTL) -XE_GPU_REGISTER(0x228F, dword, VGT_GROUP_VECT_1_FMT_CNTL) -XE_GPU_REGISTER(0x2290, dword, UNKNOWN_2290) -XE_GPU_REGISTER(0x2291, dword, UNKNOWN_2291) -XE_GPU_REGISTER(0x2292, dword, PA_SC_MPASS_PS_CNTL) -XE_GPU_REGISTER(0x2293, dword, PA_SC_VIZ_QUERY) -XE_GPU_REGISTER(0x2294, dword, VGT_ENHANCE) - -XE_GPU_REGISTER(0x2300, dword, PA_SC_LINE_CNTL) -XE_GPU_REGISTER(0x2301, dword, PA_SC_AA_CONFIG) -XE_GPU_REGISTER(0x2302, dword, PA_SU_VTX_CNTL) -XE_GPU_REGISTER(0x2303, float, PA_CL_GB_VERT_CLIP_ADJ) -XE_GPU_REGISTER(0x2304, float, PA_CL_GB_VERT_DISC_ADJ) -XE_GPU_REGISTER(0x2305, float, PA_CL_GB_HORZ_CLIP_ADJ) -XE_GPU_REGISTER(0x2306, float, PA_CL_GB_HORZ_DISC_ADJ) -XE_GPU_REGISTER(0x2307, dword, SQ_VS_CONST) -XE_GPU_REGISTER(0x2308, dword, SQ_PS_CONST) -XE_GPU_REGISTER(0x2309, dword, SQ_DEBUG_MISC_0) -XE_GPU_REGISTER(0x230A, dword, SQ_DEBUG_MISC_1) -XE_GPU_REGISTER(0x230B, dword, UNKNOWN_230B) -XE_GPU_REGISTER(0x230C, dword, UNKNOWN_230C) -XE_GPU_REGISTER(0x230D, dword, UNKNOWN_230D) -XE_GPU_REGISTER(0x230E, dword, UNKNOWN_230E) -XE_GPU_REGISTER(0x230F, dword, UNKNOWN_230F) -XE_GPU_REGISTER(0x2310, dword, UNKNOWN_2310) -XE_GPU_REGISTER(0x2311, dword, UNKNOWN_2311) -XE_GPU_REGISTER(0x2312, dword, PA_SC_AA_MASK) -XE_GPU_REGISTER(0x2313, dword, UNKNOWN_2313) -XE_GPU_REGISTER(0x2314, dword, UNKNOWN_2314) -XE_GPU_REGISTER(0x2315, dword, SQ_CF_PROGRAM_SIZE) -XE_GPU_REGISTER(0x2316, dword, VGT_VERTEX_REUSE_BLOCK_CNTL) -XE_GPU_REGISTER(0x2317, dword, VGT_OUT_DEALLOC_CNTL) -XE_GPU_REGISTER(0x2318, dword, RB_COPY_CONTROL) -XE_GPU_REGISTER(0x2319, dword, RB_COPY_DEST_BASE) -XE_GPU_REGISTER(0x231A, dword, RB_COPY_DEST_PITCH) -XE_GPU_REGISTER(0x231B, dword, RB_COPY_DEST_INFO) -XE_GPU_REGISTER(0x231C, dword, RB_TILE_CLEAR) -XE_GPU_REGISTER(0x231D, dword, RB_DEPTH_CLEAR) -XE_GPU_REGISTER(0x231E, dword, RB_COLOR_CLEAR) -XE_GPU_REGISTER(0x231F, dword, RB_COLOR_CLEAR_LOW) -XE_GPU_REGISTER(0x2320, dword, RB_COPY_FUNC) -XE_GPU_REGISTER(0x2321, dword, RB_COPY_REF) -XE_GPU_REGISTER(0x2322, dword, RB_COPY_MASK) -XE_GPU_REGISTER(0x2323, dword, RB_COPY_SURFACE_SLICE) -XE_GPU_REGISTER(0x2324, dword, RB_SAMPLE_COUNT_CTL) -XE_GPU_REGISTER(0x2325, dword, RB_SAMPLE_COUNT_ADDR) - -XE_GPU_REGISTER(0x2380, float, PA_SU_POLY_OFFSET_FRONT_SCALE) -XE_GPU_REGISTER(0x2381, float, PA_SU_POLY_OFFSET_FRONT_OFFSET) -XE_GPU_REGISTER(0x2382, float, PA_SU_POLY_OFFSET_BACK_SCALE) -XE_GPU_REGISTER(0x2383, float, PA_SU_POLY_OFFSET_BACK_OFFSET) -XE_GPU_REGISTER(0x2384, float, PA_CL_POINT_X_RAD) -XE_GPU_REGISTER(0x2385, float, PA_CL_POINT_Y_RAD) -XE_GPU_REGISTER(0x2386, float, PA_CL_POINT_SIZE) -XE_GPU_REGISTER(0x2387, float, PA_CL_POINT_CULL_RAD) - -XE_GPU_REGISTER(0x4000, float, SHADER_CONSTANT_000_X) -XE_GPU_REGISTER(0x4001, float, SHADER_CONSTANT_000_Y) -XE_GPU_REGISTER(0x4002, float, SHADER_CONSTANT_000_Z) -XE_GPU_REGISTER(0x4003, float, SHADER_CONSTANT_000_W) -XE_GPU_REGISTER(0x4004, float, SHADER_CONSTANT_001_X) -XE_GPU_REGISTER(0x4005, float, SHADER_CONSTANT_001_Y) -XE_GPU_REGISTER(0x4006, float, SHADER_CONSTANT_001_Z) -XE_GPU_REGISTER(0x4007, float, SHADER_CONSTANT_001_W) -XE_GPU_REGISTER(0x4008, float, SHADER_CONSTANT_002_X) -XE_GPU_REGISTER(0x4009, float, SHADER_CONSTANT_002_Y) -XE_GPU_REGISTER(0x400A, float, SHADER_CONSTANT_002_Z) -XE_GPU_REGISTER(0x400B, float, SHADER_CONSTANT_002_W) -XE_GPU_REGISTER(0x400C, float, SHADER_CONSTANT_003_X) -XE_GPU_REGISTER(0x400D, float, SHADER_CONSTANT_003_Y) -XE_GPU_REGISTER(0x400E, float, SHADER_CONSTANT_003_Z) -XE_GPU_REGISTER(0x400F, float, SHADER_CONSTANT_003_W) -XE_GPU_REGISTER(0x4010, float, SHADER_CONSTANT_004_X) -XE_GPU_REGISTER(0x4011, float, SHADER_CONSTANT_004_Y) -XE_GPU_REGISTER(0x4012, float, SHADER_CONSTANT_004_Z) -XE_GPU_REGISTER(0x4013, float, SHADER_CONSTANT_004_W) -XE_GPU_REGISTER(0x4014, float, SHADER_CONSTANT_005_X) -XE_GPU_REGISTER(0x4015, float, SHADER_CONSTANT_005_Y) -XE_GPU_REGISTER(0x4016, float, SHADER_CONSTANT_005_Z) -XE_GPU_REGISTER(0x4017, float, SHADER_CONSTANT_005_W) -XE_GPU_REGISTER(0x4018, float, SHADER_CONSTANT_006_X) -XE_GPU_REGISTER(0x4019, float, SHADER_CONSTANT_006_Y) -XE_GPU_REGISTER(0x401A, float, SHADER_CONSTANT_006_Z) -XE_GPU_REGISTER(0x401B, float, SHADER_CONSTANT_006_W) -XE_GPU_REGISTER(0x401C, float, SHADER_CONSTANT_007_X) -XE_GPU_REGISTER(0x401D, float, SHADER_CONSTANT_007_Y) -XE_GPU_REGISTER(0x401E, float, SHADER_CONSTANT_007_Z) -XE_GPU_REGISTER(0x401F, float, SHADER_CONSTANT_007_W) -XE_GPU_REGISTER(0x4020, float, SHADER_CONSTANT_008_X) -XE_GPU_REGISTER(0x4021, float, SHADER_CONSTANT_008_Y) -XE_GPU_REGISTER(0x4022, float, SHADER_CONSTANT_008_Z) -XE_GPU_REGISTER(0x4023, float, SHADER_CONSTANT_008_W) -XE_GPU_REGISTER(0x4024, float, SHADER_CONSTANT_009_X) -XE_GPU_REGISTER(0x4025, float, SHADER_CONSTANT_009_Y) -XE_GPU_REGISTER(0x4026, float, SHADER_CONSTANT_009_Z) -XE_GPU_REGISTER(0x4027, float, SHADER_CONSTANT_009_W) -XE_GPU_REGISTER(0x4028, float, SHADER_CONSTANT_010_X) -XE_GPU_REGISTER(0x4029, float, SHADER_CONSTANT_010_Y) -XE_GPU_REGISTER(0x402A, float, SHADER_CONSTANT_010_Z) -XE_GPU_REGISTER(0x402B, float, SHADER_CONSTANT_010_W) -XE_GPU_REGISTER(0x402C, float, SHADER_CONSTANT_011_X) -XE_GPU_REGISTER(0x402D, float, SHADER_CONSTANT_011_Y) -XE_GPU_REGISTER(0x402E, float, SHADER_CONSTANT_011_Z) -XE_GPU_REGISTER(0x402F, float, SHADER_CONSTANT_011_W) -XE_GPU_REGISTER(0x4030, float, SHADER_CONSTANT_012_X) -XE_GPU_REGISTER(0x4031, float, SHADER_CONSTANT_012_Y) -XE_GPU_REGISTER(0x4032, float, SHADER_CONSTANT_012_Z) -XE_GPU_REGISTER(0x4033, float, SHADER_CONSTANT_012_W) -XE_GPU_REGISTER(0x4034, float, SHADER_CONSTANT_013_X) -XE_GPU_REGISTER(0x4035, float, SHADER_CONSTANT_013_Y) -XE_GPU_REGISTER(0x4036, float, SHADER_CONSTANT_013_Z) -XE_GPU_REGISTER(0x4037, float, SHADER_CONSTANT_013_W) -XE_GPU_REGISTER(0x4038, float, SHADER_CONSTANT_014_X) -XE_GPU_REGISTER(0x4039, float, SHADER_CONSTANT_014_Y) -XE_GPU_REGISTER(0x403A, float, SHADER_CONSTANT_014_Z) -XE_GPU_REGISTER(0x403B, float, SHADER_CONSTANT_014_W) -XE_GPU_REGISTER(0x403C, float, SHADER_CONSTANT_015_X) -XE_GPU_REGISTER(0x403D, float, SHADER_CONSTANT_015_Y) -XE_GPU_REGISTER(0x403E, float, SHADER_CONSTANT_015_Z) -XE_GPU_REGISTER(0x403F, float, SHADER_CONSTANT_015_W) -XE_GPU_REGISTER(0x4040, float, SHADER_CONSTANT_016_X) -XE_GPU_REGISTER(0x4041, float, SHADER_CONSTANT_016_Y) -XE_GPU_REGISTER(0x4042, float, SHADER_CONSTANT_016_Z) -XE_GPU_REGISTER(0x4043, float, SHADER_CONSTANT_016_W) -XE_GPU_REGISTER(0x4044, float, SHADER_CONSTANT_017_X) -XE_GPU_REGISTER(0x4045, float, SHADER_CONSTANT_017_Y) -XE_GPU_REGISTER(0x4046, float, SHADER_CONSTANT_017_Z) -XE_GPU_REGISTER(0x4047, float, SHADER_CONSTANT_017_W) -XE_GPU_REGISTER(0x4048, float, SHADER_CONSTANT_018_X) -XE_GPU_REGISTER(0x4049, float, SHADER_CONSTANT_018_Y) -XE_GPU_REGISTER(0x404A, float, SHADER_CONSTANT_018_Z) -XE_GPU_REGISTER(0x404B, float, SHADER_CONSTANT_018_W) -XE_GPU_REGISTER(0x404C, float, SHADER_CONSTANT_019_X) -XE_GPU_REGISTER(0x404D, float, SHADER_CONSTANT_019_Y) -XE_GPU_REGISTER(0x404E, float, SHADER_CONSTANT_019_Z) -XE_GPU_REGISTER(0x404F, float, SHADER_CONSTANT_019_W) -XE_GPU_REGISTER(0x4050, float, SHADER_CONSTANT_020_X) -XE_GPU_REGISTER(0x4051, float, SHADER_CONSTANT_020_Y) -XE_GPU_REGISTER(0x4052, float, SHADER_CONSTANT_020_Z) -XE_GPU_REGISTER(0x4053, float, SHADER_CONSTANT_020_W) -XE_GPU_REGISTER(0x4054, float, SHADER_CONSTANT_021_X) -XE_GPU_REGISTER(0x4055, float, SHADER_CONSTANT_021_Y) -XE_GPU_REGISTER(0x4056, float, SHADER_CONSTANT_021_Z) -XE_GPU_REGISTER(0x4057, float, SHADER_CONSTANT_021_W) -XE_GPU_REGISTER(0x4058, float, SHADER_CONSTANT_022_X) -XE_GPU_REGISTER(0x4059, float, SHADER_CONSTANT_022_Y) -XE_GPU_REGISTER(0x405A, float, SHADER_CONSTANT_022_Z) -XE_GPU_REGISTER(0x405B, float, SHADER_CONSTANT_022_W) -XE_GPU_REGISTER(0x405C, float, SHADER_CONSTANT_023_X) -XE_GPU_REGISTER(0x405D, float, SHADER_CONSTANT_023_Y) -XE_GPU_REGISTER(0x405E, float, SHADER_CONSTANT_023_Z) -XE_GPU_REGISTER(0x405F, float, SHADER_CONSTANT_023_W) -XE_GPU_REGISTER(0x4060, float, SHADER_CONSTANT_024_X) -XE_GPU_REGISTER(0x4061, float, SHADER_CONSTANT_024_Y) -XE_GPU_REGISTER(0x4062, float, SHADER_CONSTANT_024_Z) -XE_GPU_REGISTER(0x4063, float, SHADER_CONSTANT_024_W) -XE_GPU_REGISTER(0x4064, float, SHADER_CONSTANT_025_X) -XE_GPU_REGISTER(0x4065, float, SHADER_CONSTANT_025_Y) -XE_GPU_REGISTER(0x4066, float, SHADER_CONSTANT_025_Z) -XE_GPU_REGISTER(0x4067, float, SHADER_CONSTANT_025_W) -XE_GPU_REGISTER(0x4068, float, SHADER_CONSTANT_026_X) -XE_GPU_REGISTER(0x4069, float, SHADER_CONSTANT_026_Y) -XE_GPU_REGISTER(0x406A, float, SHADER_CONSTANT_026_Z) -XE_GPU_REGISTER(0x406B, float, SHADER_CONSTANT_026_W) -XE_GPU_REGISTER(0x406C, float, SHADER_CONSTANT_027_X) -XE_GPU_REGISTER(0x406D, float, SHADER_CONSTANT_027_Y) -XE_GPU_REGISTER(0x406E, float, SHADER_CONSTANT_027_Z) -XE_GPU_REGISTER(0x406F, float, SHADER_CONSTANT_027_W) -XE_GPU_REGISTER(0x4070, float, SHADER_CONSTANT_028_X) -XE_GPU_REGISTER(0x4071, float, SHADER_CONSTANT_028_Y) -XE_GPU_REGISTER(0x4072, float, SHADER_CONSTANT_028_Z) -XE_GPU_REGISTER(0x4073, float, SHADER_CONSTANT_028_W) -XE_GPU_REGISTER(0x4074, float, SHADER_CONSTANT_029_X) -XE_GPU_REGISTER(0x4075, float, SHADER_CONSTANT_029_Y) -XE_GPU_REGISTER(0x4076, float, SHADER_CONSTANT_029_Z) -XE_GPU_REGISTER(0x4077, float, SHADER_CONSTANT_029_W) -XE_GPU_REGISTER(0x4078, float, SHADER_CONSTANT_030_X) -XE_GPU_REGISTER(0x4079, float, SHADER_CONSTANT_030_Y) -XE_GPU_REGISTER(0x407A, float, SHADER_CONSTANT_030_Z) -XE_GPU_REGISTER(0x407B, float, SHADER_CONSTANT_030_W) -XE_GPU_REGISTER(0x407C, float, SHADER_CONSTANT_031_X) -XE_GPU_REGISTER(0x407D, float, SHADER_CONSTANT_031_Y) -XE_GPU_REGISTER(0x407E, float, SHADER_CONSTANT_031_Z) -XE_GPU_REGISTER(0x407F, float, SHADER_CONSTANT_031_W) -XE_GPU_REGISTER(0x4080, float, SHADER_CONSTANT_032_X) -XE_GPU_REGISTER(0x4081, float, SHADER_CONSTANT_032_Y) -XE_GPU_REGISTER(0x4082, float, SHADER_CONSTANT_032_Z) -XE_GPU_REGISTER(0x4083, float, SHADER_CONSTANT_032_W) -XE_GPU_REGISTER(0x4084, float, SHADER_CONSTANT_033_X) -XE_GPU_REGISTER(0x4085, float, SHADER_CONSTANT_033_Y) -XE_GPU_REGISTER(0x4086, float, SHADER_CONSTANT_033_Z) -XE_GPU_REGISTER(0x4087, float, SHADER_CONSTANT_033_W) -XE_GPU_REGISTER(0x4088, float, SHADER_CONSTANT_034_X) -XE_GPU_REGISTER(0x4089, float, SHADER_CONSTANT_034_Y) -XE_GPU_REGISTER(0x408A, float, SHADER_CONSTANT_034_Z) -XE_GPU_REGISTER(0x408B, float, SHADER_CONSTANT_034_W) -XE_GPU_REGISTER(0x408C, float, SHADER_CONSTANT_035_X) -XE_GPU_REGISTER(0x408D, float, SHADER_CONSTANT_035_Y) -XE_GPU_REGISTER(0x408E, float, SHADER_CONSTANT_035_Z) -XE_GPU_REGISTER(0x408F, float, SHADER_CONSTANT_035_W) -XE_GPU_REGISTER(0x4090, float, SHADER_CONSTANT_036_X) -XE_GPU_REGISTER(0x4091, float, SHADER_CONSTANT_036_Y) -XE_GPU_REGISTER(0x4092, float, SHADER_CONSTANT_036_Z) -XE_GPU_REGISTER(0x4093, float, SHADER_CONSTANT_036_W) -XE_GPU_REGISTER(0x4094, float, SHADER_CONSTANT_037_X) -XE_GPU_REGISTER(0x4095, float, SHADER_CONSTANT_037_Y) -XE_GPU_REGISTER(0x4096, float, SHADER_CONSTANT_037_Z) -XE_GPU_REGISTER(0x4097, float, SHADER_CONSTANT_037_W) -XE_GPU_REGISTER(0x4098, float, SHADER_CONSTANT_038_X) -XE_GPU_REGISTER(0x4099, float, SHADER_CONSTANT_038_Y) -XE_GPU_REGISTER(0x409A, float, SHADER_CONSTANT_038_Z) -XE_GPU_REGISTER(0x409B, float, SHADER_CONSTANT_038_W) -XE_GPU_REGISTER(0x409C, float, SHADER_CONSTANT_039_X) -XE_GPU_REGISTER(0x409D, float, SHADER_CONSTANT_039_Y) -XE_GPU_REGISTER(0x409E, float, SHADER_CONSTANT_039_Z) -XE_GPU_REGISTER(0x409F, float, SHADER_CONSTANT_039_W) -XE_GPU_REGISTER(0x40A0, float, SHADER_CONSTANT_040_X) -XE_GPU_REGISTER(0x40A1, float, SHADER_CONSTANT_040_Y) -XE_GPU_REGISTER(0x40A2, float, SHADER_CONSTANT_040_Z) -XE_GPU_REGISTER(0x40A3, float, SHADER_CONSTANT_040_W) -XE_GPU_REGISTER(0x40A4, float, SHADER_CONSTANT_041_X) -XE_GPU_REGISTER(0x40A5, float, SHADER_CONSTANT_041_Y) -XE_GPU_REGISTER(0x40A6, float, SHADER_CONSTANT_041_Z) -XE_GPU_REGISTER(0x40A7, float, SHADER_CONSTANT_041_W) -XE_GPU_REGISTER(0x40A8, float, SHADER_CONSTANT_042_X) -XE_GPU_REGISTER(0x40A9, float, SHADER_CONSTANT_042_Y) -XE_GPU_REGISTER(0x40AA, float, SHADER_CONSTANT_042_Z) -XE_GPU_REGISTER(0x40AB, float, SHADER_CONSTANT_042_W) -XE_GPU_REGISTER(0x40AC, float, SHADER_CONSTANT_043_X) -XE_GPU_REGISTER(0x40AD, float, SHADER_CONSTANT_043_Y) -XE_GPU_REGISTER(0x40AE, float, SHADER_CONSTANT_043_Z) -XE_GPU_REGISTER(0x40AF, float, SHADER_CONSTANT_043_W) -XE_GPU_REGISTER(0x40B0, float, SHADER_CONSTANT_044_X) -XE_GPU_REGISTER(0x40B1, float, SHADER_CONSTANT_044_Y) -XE_GPU_REGISTER(0x40B2, float, SHADER_CONSTANT_044_Z) -XE_GPU_REGISTER(0x40B3, float, SHADER_CONSTANT_044_W) -XE_GPU_REGISTER(0x40B4, float, SHADER_CONSTANT_045_X) -XE_GPU_REGISTER(0x40B5, float, SHADER_CONSTANT_045_Y) -XE_GPU_REGISTER(0x40B6, float, SHADER_CONSTANT_045_Z) -XE_GPU_REGISTER(0x40B7, float, SHADER_CONSTANT_045_W) -XE_GPU_REGISTER(0x40B8, float, SHADER_CONSTANT_046_X) -XE_GPU_REGISTER(0x40B9, float, SHADER_CONSTANT_046_Y) -XE_GPU_REGISTER(0x40BA, float, SHADER_CONSTANT_046_Z) -XE_GPU_REGISTER(0x40BB, float, SHADER_CONSTANT_046_W) -XE_GPU_REGISTER(0x40BC, float, SHADER_CONSTANT_047_X) -XE_GPU_REGISTER(0x40BD, float, SHADER_CONSTANT_047_Y) -XE_GPU_REGISTER(0x40BE, float, SHADER_CONSTANT_047_Z) -XE_GPU_REGISTER(0x40BF, float, SHADER_CONSTANT_047_W) -XE_GPU_REGISTER(0x40C0, float, SHADER_CONSTANT_048_X) -XE_GPU_REGISTER(0x40C1, float, SHADER_CONSTANT_048_Y) -XE_GPU_REGISTER(0x40C2, float, SHADER_CONSTANT_048_Z) -XE_GPU_REGISTER(0x40C3, float, SHADER_CONSTANT_048_W) -XE_GPU_REGISTER(0x40C4, float, SHADER_CONSTANT_049_X) -XE_GPU_REGISTER(0x40C5, float, SHADER_CONSTANT_049_Y) -XE_GPU_REGISTER(0x40C6, float, SHADER_CONSTANT_049_Z) -XE_GPU_REGISTER(0x40C7, float, SHADER_CONSTANT_049_W) -XE_GPU_REGISTER(0x40C8, float, SHADER_CONSTANT_050_X) -XE_GPU_REGISTER(0x40C9, float, SHADER_CONSTANT_050_Y) -XE_GPU_REGISTER(0x40CA, float, SHADER_CONSTANT_050_Z) -XE_GPU_REGISTER(0x40CB, float, SHADER_CONSTANT_050_W) -XE_GPU_REGISTER(0x40CC, float, SHADER_CONSTANT_051_X) -XE_GPU_REGISTER(0x40CD, float, SHADER_CONSTANT_051_Y) -XE_GPU_REGISTER(0x40CE, float, SHADER_CONSTANT_051_Z) -XE_GPU_REGISTER(0x40CF, float, SHADER_CONSTANT_051_W) -XE_GPU_REGISTER(0x40D0, float, SHADER_CONSTANT_052_X) -XE_GPU_REGISTER(0x40D1, float, SHADER_CONSTANT_052_Y) -XE_GPU_REGISTER(0x40D2, float, SHADER_CONSTANT_052_Z) -XE_GPU_REGISTER(0x40D3, float, SHADER_CONSTANT_052_W) -XE_GPU_REGISTER(0x40D4, float, SHADER_CONSTANT_053_X) -XE_GPU_REGISTER(0x40D5, float, SHADER_CONSTANT_053_Y) -XE_GPU_REGISTER(0x40D6, float, SHADER_CONSTANT_053_Z) -XE_GPU_REGISTER(0x40D7, float, SHADER_CONSTANT_053_W) -XE_GPU_REGISTER(0x40D8, float, SHADER_CONSTANT_054_X) -XE_GPU_REGISTER(0x40D9, float, SHADER_CONSTANT_054_Y) -XE_GPU_REGISTER(0x40DA, float, SHADER_CONSTANT_054_Z) -XE_GPU_REGISTER(0x40DB, float, SHADER_CONSTANT_054_W) -XE_GPU_REGISTER(0x40DC, float, SHADER_CONSTANT_055_X) -XE_GPU_REGISTER(0x40DD, float, SHADER_CONSTANT_055_Y) -XE_GPU_REGISTER(0x40DE, float, SHADER_CONSTANT_055_Z) -XE_GPU_REGISTER(0x40DF, float, SHADER_CONSTANT_055_W) -XE_GPU_REGISTER(0x40E0, float, SHADER_CONSTANT_056_X) -XE_GPU_REGISTER(0x40E1, float, SHADER_CONSTANT_056_Y) -XE_GPU_REGISTER(0x40E2, float, SHADER_CONSTANT_056_Z) -XE_GPU_REGISTER(0x40E3, float, SHADER_CONSTANT_056_W) -XE_GPU_REGISTER(0x40E4, float, SHADER_CONSTANT_057_X) -XE_GPU_REGISTER(0x40E5, float, SHADER_CONSTANT_057_Y) -XE_GPU_REGISTER(0x40E6, float, SHADER_CONSTANT_057_Z) -XE_GPU_REGISTER(0x40E7, float, SHADER_CONSTANT_057_W) -XE_GPU_REGISTER(0x40E8, float, SHADER_CONSTANT_058_X) -XE_GPU_REGISTER(0x40E9, float, SHADER_CONSTANT_058_Y) -XE_GPU_REGISTER(0x40EA, float, SHADER_CONSTANT_058_Z) -XE_GPU_REGISTER(0x40EB, float, SHADER_CONSTANT_058_W) -XE_GPU_REGISTER(0x40EC, float, SHADER_CONSTANT_059_X) -XE_GPU_REGISTER(0x40ED, float, SHADER_CONSTANT_059_Y) -XE_GPU_REGISTER(0x40EE, float, SHADER_CONSTANT_059_Z) -XE_GPU_REGISTER(0x40EF, float, SHADER_CONSTANT_059_W) -XE_GPU_REGISTER(0x40F0, float, SHADER_CONSTANT_060_X) -XE_GPU_REGISTER(0x40F1, float, SHADER_CONSTANT_060_Y) -XE_GPU_REGISTER(0x40F2, float, SHADER_CONSTANT_060_Z) -XE_GPU_REGISTER(0x40F3, float, SHADER_CONSTANT_060_W) -XE_GPU_REGISTER(0x40F4, float, SHADER_CONSTANT_061_X) -XE_GPU_REGISTER(0x40F5, float, SHADER_CONSTANT_061_Y) -XE_GPU_REGISTER(0x40F6, float, SHADER_CONSTANT_061_Z) -XE_GPU_REGISTER(0x40F7, float, SHADER_CONSTANT_061_W) -XE_GPU_REGISTER(0x40F8, float, SHADER_CONSTANT_062_X) -XE_GPU_REGISTER(0x40F9, float, SHADER_CONSTANT_062_Y) -XE_GPU_REGISTER(0x40FA, float, SHADER_CONSTANT_062_Z) -XE_GPU_REGISTER(0x40FB, float, SHADER_CONSTANT_062_W) -XE_GPU_REGISTER(0x40FC, float, SHADER_CONSTANT_063_X) -XE_GPU_REGISTER(0x40FD, float, SHADER_CONSTANT_063_Y) -XE_GPU_REGISTER(0x40FE, float, SHADER_CONSTANT_063_Z) -XE_GPU_REGISTER(0x40FF, float, SHADER_CONSTANT_063_W) -XE_GPU_REGISTER(0x4100, float, SHADER_CONSTANT_064_X) -XE_GPU_REGISTER(0x4101, float, SHADER_CONSTANT_064_Y) -XE_GPU_REGISTER(0x4102, float, SHADER_CONSTANT_064_Z) -XE_GPU_REGISTER(0x4103, float, SHADER_CONSTANT_064_W) -XE_GPU_REGISTER(0x4104, float, SHADER_CONSTANT_065_X) -XE_GPU_REGISTER(0x4105, float, SHADER_CONSTANT_065_Y) -XE_GPU_REGISTER(0x4106, float, SHADER_CONSTANT_065_Z) -XE_GPU_REGISTER(0x4107, float, SHADER_CONSTANT_065_W) -XE_GPU_REGISTER(0x4108, float, SHADER_CONSTANT_066_X) -XE_GPU_REGISTER(0x4109, float, SHADER_CONSTANT_066_Y) -XE_GPU_REGISTER(0x410A, float, SHADER_CONSTANT_066_Z) -XE_GPU_REGISTER(0x410B, float, SHADER_CONSTANT_066_W) -XE_GPU_REGISTER(0x410C, float, SHADER_CONSTANT_067_X) -XE_GPU_REGISTER(0x410D, float, SHADER_CONSTANT_067_Y) -XE_GPU_REGISTER(0x410E, float, SHADER_CONSTANT_067_Z) -XE_GPU_REGISTER(0x410F, float, SHADER_CONSTANT_067_W) -XE_GPU_REGISTER(0x4110, float, SHADER_CONSTANT_068_X) -XE_GPU_REGISTER(0x4111, float, SHADER_CONSTANT_068_Y) -XE_GPU_REGISTER(0x4112, float, SHADER_CONSTANT_068_Z) -XE_GPU_REGISTER(0x4113, float, SHADER_CONSTANT_068_W) -XE_GPU_REGISTER(0x4114, float, SHADER_CONSTANT_069_X) -XE_GPU_REGISTER(0x4115, float, SHADER_CONSTANT_069_Y) -XE_GPU_REGISTER(0x4116, float, SHADER_CONSTANT_069_Z) -XE_GPU_REGISTER(0x4117, float, SHADER_CONSTANT_069_W) -XE_GPU_REGISTER(0x4118, float, SHADER_CONSTANT_070_X) -XE_GPU_REGISTER(0x4119, float, SHADER_CONSTANT_070_Y) -XE_GPU_REGISTER(0x411A, float, SHADER_CONSTANT_070_Z) -XE_GPU_REGISTER(0x411B, float, SHADER_CONSTANT_070_W) -XE_GPU_REGISTER(0x411C, float, SHADER_CONSTANT_071_X) -XE_GPU_REGISTER(0x411D, float, SHADER_CONSTANT_071_Y) -XE_GPU_REGISTER(0x411E, float, SHADER_CONSTANT_071_Z) -XE_GPU_REGISTER(0x411F, float, SHADER_CONSTANT_071_W) -XE_GPU_REGISTER(0x4120, float, SHADER_CONSTANT_072_X) -XE_GPU_REGISTER(0x4121, float, SHADER_CONSTANT_072_Y) -XE_GPU_REGISTER(0x4122, float, SHADER_CONSTANT_072_Z) -XE_GPU_REGISTER(0x4123, float, SHADER_CONSTANT_072_W) -XE_GPU_REGISTER(0x4124, float, SHADER_CONSTANT_073_X) -XE_GPU_REGISTER(0x4125, float, SHADER_CONSTANT_073_Y) -XE_GPU_REGISTER(0x4126, float, SHADER_CONSTANT_073_Z) -XE_GPU_REGISTER(0x4127, float, SHADER_CONSTANT_073_W) -XE_GPU_REGISTER(0x4128, float, SHADER_CONSTANT_074_X) -XE_GPU_REGISTER(0x4129, float, SHADER_CONSTANT_074_Y) -XE_GPU_REGISTER(0x412A, float, SHADER_CONSTANT_074_Z) -XE_GPU_REGISTER(0x412B, float, SHADER_CONSTANT_074_W) -XE_GPU_REGISTER(0x412C, float, SHADER_CONSTANT_075_X) -XE_GPU_REGISTER(0x412D, float, SHADER_CONSTANT_075_Y) -XE_GPU_REGISTER(0x412E, float, SHADER_CONSTANT_075_Z) -XE_GPU_REGISTER(0x412F, float, SHADER_CONSTANT_075_W) -XE_GPU_REGISTER(0x4130, float, SHADER_CONSTANT_076_X) -XE_GPU_REGISTER(0x4131, float, SHADER_CONSTANT_076_Y) -XE_GPU_REGISTER(0x4132, float, SHADER_CONSTANT_076_Z) -XE_GPU_REGISTER(0x4133, float, SHADER_CONSTANT_076_W) -XE_GPU_REGISTER(0x4134, float, SHADER_CONSTANT_077_X) -XE_GPU_REGISTER(0x4135, float, SHADER_CONSTANT_077_Y) -XE_GPU_REGISTER(0x4136, float, SHADER_CONSTANT_077_Z) -XE_GPU_REGISTER(0x4137, float, SHADER_CONSTANT_077_W) -XE_GPU_REGISTER(0x4138, float, SHADER_CONSTANT_078_X) -XE_GPU_REGISTER(0x4139, float, SHADER_CONSTANT_078_Y) -XE_GPU_REGISTER(0x413A, float, SHADER_CONSTANT_078_Z) -XE_GPU_REGISTER(0x413B, float, SHADER_CONSTANT_078_W) -XE_GPU_REGISTER(0x413C, float, SHADER_CONSTANT_079_X) -XE_GPU_REGISTER(0x413D, float, SHADER_CONSTANT_079_Y) -XE_GPU_REGISTER(0x413E, float, SHADER_CONSTANT_079_Z) -XE_GPU_REGISTER(0x413F, float, SHADER_CONSTANT_079_W) -XE_GPU_REGISTER(0x4140, float, SHADER_CONSTANT_080_X) -XE_GPU_REGISTER(0x4141, float, SHADER_CONSTANT_080_Y) -XE_GPU_REGISTER(0x4142, float, SHADER_CONSTANT_080_Z) -XE_GPU_REGISTER(0x4143, float, SHADER_CONSTANT_080_W) -XE_GPU_REGISTER(0x4144, float, SHADER_CONSTANT_081_X) -XE_GPU_REGISTER(0x4145, float, SHADER_CONSTANT_081_Y) -XE_GPU_REGISTER(0x4146, float, SHADER_CONSTANT_081_Z) -XE_GPU_REGISTER(0x4147, float, SHADER_CONSTANT_081_W) -XE_GPU_REGISTER(0x4148, float, SHADER_CONSTANT_082_X) -XE_GPU_REGISTER(0x4149, float, SHADER_CONSTANT_082_Y) -XE_GPU_REGISTER(0x414A, float, SHADER_CONSTANT_082_Z) -XE_GPU_REGISTER(0x414B, float, SHADER_CONSTANT_082_W) -XE_GPU_REGISTER(0x414C, float, SHADER_CONSTANT_083_X) -XE_GPU_REGISTER(0x414D, float, SHADER_CONSTANT_083_Y) -XE_GPU_REGISTER(0x414E, float, SHADER_CONSTANT_083_Z) -XE_GPU_REGISTER(0x414F, float, SHADER_CONSTANT_083_W) -XE_GPU_REGISTER(0x4150, float, SHADER_CONSTANT_084_X) -XE_GPU_REGISTER(0x4151, float, SHADER_CONSTANT_084_Y) -XE_GPU_REGISTER(0x4152, float, SHADER_CONSTANT_084_Z) -XE_GPU_REGISTER(0x4153, float, SHADER_CONSTANT_084_W) -XE_GPU_REGISTER(0x4154, float, SHADER_CONSTANT_085_X) -XE_GPU_REGISTER(0x4155, float, SHADER_CONSTANT_085_Y) -XE_GPU_REGISTER(0x4156, float, SHADER_CONSTANT_085_Z) -XE_GPU_REGISTER(0x4157, float, SHADER_CONSTANT_085_W) -XE_GPU_REGISTER(0x4158, float, SHADER_CONSTANT_086_X) -XE_GPU_REGISTER(0x4159, float, SHADER_CONSTANT_086_Y) -XE_GPU_REGISTER(0x415A, float, SHADER_CONSTANT_086_Z) -XE_GPU_REGISTER(0x415B, float, SHADER_CONSTANT_086_W) -XE_GPU_REGISTER(0x415C, float, SHADER_CONSTANT_087_X) -XE_GPU_REGISTER(0x415D, float, SHADER_CONSTANT_087_Y) -XE_GPU_REGISTER(0x415E, float, SHADER_CONSTANT_087_Z) -XE_GPU_REGISTER(0x415F, float, SHADER_CONSTANT_087_W) -XE_GPU_REGISTER(0x4160, float, SHADER_CONSTANT_088_X) -XE_GPU_REGISTER(0x4161, float, SHADER_CONSTANT_088_Y) -XE_GPU_REGISTER(0x4162, float, SHADER_CONSTANT_088_Z) -XE_GPU_REGISTER(0x4163, float, SHADER_CONSTANT_088_W) -XE_GPU_REGISTER(0x4164, float, SHADER_CONSTANT_089_X) -XE_GPU_REGISTER(0x4165, float, SHADER_CONSTANT_089_Y) -XE_GPU_REGISTER(0x4166, float, SHADER_CONSTANT_089_Z) -XE_GPU_REGISTER(0x4167, float, SHADER_CONSTANT_089_W) -XE_GPU_REGISTER(0x4168, float, SHADER_CONSTANT_090_X) -XE_GPU_REGISTER(0x4169, float, SHADER_CONSTANT_090_Y) -XE_GPU_REGISTER(0x416A, float, SHADER_CONSTANT_090_Z) -XE_GPU_REGISTER(0x416B, float, SHADER_CONSTANT_090_W) -XE_GPU_REGISTER(0x416C, float, SHADER_CONSTANT_091_X) -XE_GPU_REGISTER(0x416D, float, SHADER_CONSTANT_091_Y) -XE_GPU_REGISTER(0x416E, float, SHADER_CONSTANT_091_Z) -XE_GPU_REGISTER(0x416F, float, SHADER_CONSTANT_091_W) -XE_GPU_REGISTER(0x4170, float, SHADER_CONSTANT_092_X) -XE_GPU_REGISTER(0x4171, float, SHADER_CONSTANT_092_Y) -XE_GPU_REGISTER(0x4172, float, SHADER_CONSTANT_092_Z) -XE_GPU_REGISTER(0x4173, float, SHADER_CONSTANT_092_W) -XE_GPU_REGISTER(0x4174, float, SHADER_CONSTANT_093_X) -XE_GPU_REGISTER(0x4175, float, SHADER_CONSTANT_093_Y) -XE_GPU_REGISTER(0x4176, float, SHADER_CONSTANT_093_Z) -XE_GPU_REGISTER(0x4177, float, SHADER_CONSTANT_093_W) -XE_GPU_REGISTER(0x4178, float, SHADER_CONSTANT_094_X) -XE_GPU_REGISTER(0x4179, float, SHADER_CONSTANT_094_Y) -XE_GPU_REGISTER(0x417A, float, SHADER_CONSTANT_094_Z) -XE_GPU_REGISTER(0x417B, float, SHADER_CONSTANT_094_W) -XE_GPU_REGISTER(0x417C, float, SHADER_CONSTANT_095_X) -XE_GPU_REGISTER(0x417D, float, SHADER_CONSTANT_095_Y) -XE_GPU_REGISTER(0x417E, float, SHADER_CONSTANT_095_Z) -XE_GPU_REGISTER(0x417F, float, SHADER_CONSTANT_095_W) -XE_GPU_REGISTER(0x4180, float, SHADER_CONSTANT_096_X) -XE_GPU_REGISTER(0x4181, float, SHADER_CONSTANT_096_Y) -XE_GPU_REGISTER(0x4182, float, SHADER_CONSTANT_096_Z) -XE_GPU_REGISTER(0x4183, float, SHADER_CONSTANT_096_W) -XE_GPU_REGISTER(0x4184, float, SHADER_CONSTANT_097_X) -XE_GPU_REGISTER(0x4185, float, SHADER_CONSTANT_097_Y) -XE_GPU_REGISTER(0x4186, float, SHADER_CONSTANT_097_Z) -XE_GPU_REGISTER(0x4187, float, SHADER_CONSTANT_097_W) -XE_GPU_REGISTER(0x4188, float, SHADER_CONSTANT_098_X) -XE_GPU_REGISTER(0x4189, float, SHADER_CONSTANT_098_Y) -XE_GPU_REGISTER(0x418A, float, SHADER_CONSTANT_098_Z) -XE_GPU_REGISTER(0x418B, float, SHADER_CONSTANT_098_W) -XE_GPU_REGISTER(0x418C, float, SHADER_CONSTANT_099_X) -XE_GPU_REGISTER(0x418D, float, SHADER_CONSTANT_099_Y) -XE_GPU_REGISTER(0x418E, float, SHADER_CONSTANT_099_Z) -XE_GPU_REGISTER(0x418F, float, SHADER_CONSTANT_099_W) -XE_GPU_REGISTER(0x4190, float, SHADER_CONSTANT_100_X) -XE_GPU_REGISTER(0x4191, float, SHADER_CONSTANT_100_Y) -XE_GPU_REGISTER(0x4192, float, SHADER_CONSTANT_100_Z) -XE_GPU_REGISTER(0x4193, float, SHADER_CONSTANT_100_W) -XE_GPU_REGISTER(0x4194, float, SHADER_CONSTANT_101_X) -XE_GPU_REGISTER(0x4195, float, SHADER_CONSTANT_101_Y) -XE_GPU_REGISTER(0x4196, float, SHADER_CONSTANT_101_Z) -XE_GPU_REGISTER(0x4197, float, SHADER_CONSTANT_101_W) -XE_GPU_REGISTER(0x4198, float, SHADER_CONSTANT_102_X) -XE_GPU_REGISTER(0x4199, float, SHADER_CONSTANT_102_Y) -XE_GPU_REGISTER(0x419A, float, SHADER_CONSTANT_102_Z) -XE_GPU_REGISTER(0x419B, float, SHADER_CONSTANT_102_W) -XE_GPU_REGISTER(0x419C, float, SHADER_CONSTANT_103_X) -XE_GPU_REGISTER(0x419D, float, SHADER_CONSTANT_103_Y) -XE_GPU_REGISTER(0x419E, float, SHADER_CONSTANT_103_Z) -XE_GPU_REGISTER(0x419F, float, SHADER_CONSTANT_103_W) -XE_GPU_REGISTER(0x41A0, float, SHADER_CONSTANT_104_X) -XE_GPU_REGISTER(0x41A1, float, SHADER_CONSTANT_104_Y) -XE_GPU_REGISTER(0x41A2, float, SHADER_CONSTANT_104_Z) -XE_GPU_REGISTER(0x41A3, float, SHADER_CONSTANT_104_W) -XE_GPU_REGISTER(0x41A4, float, SHADER_CONSTANT_105_X) -XE_GPU_REGISTER(0x41A5, float, SHADER_CONSTANT_105_Y) -XE_GPU_REGISTER(0x41A6, float, SHADER_CONSTANT_105_Z) -XE_GPU_REGISTER(0x41A7, float, SHADER_CONSTANT_105_W) -XE_GPU_REGISTER(0x41A8, float, SHADER_CONSTANT_106_X) -XE_GPU_REGISTER(0x41A9, float, SHADER_CONSTANT_106_Y) -XE_GPU_REGISTER(0x41AA, float, SHADER_CONSTANT_106_Z) -XE_GPU_REGISTER(0x41AB, float, SHADER_CONSTANT_106_W) -XE_GPU_REGISTER(0x41AC, float, SHADER_CONSTANT_107_X) -XE_GPU_REGISTER(0x41AD, float, SHADER_CONSTANT_107_Y) -XE_GPU_REGISTER(0x41AE, float, SHADER_CONSTANT_107_Z) -XE_GPU_REGISTER(0x41AF, float, SHADER_CONSTANT_107_W) -XE_GPU_REGISTER(0x41B0, float, SHADER_CONSTANT_108_X) -XE_GPU_REGISTER(0x41B1, float, SHADER_CONSTANT_108_Y) -XE_GPU_REGISTER(0x41B2, float, SHADER_CONSTANT_108_Z) -XE_GPU_REGISTER(0x41B3, float, SHADER_CONSTANT_108_W) -XE_GPU_REGISTER(0x41B4, float, SHADER_CONSTANT_109_X) -XE_GPU_REGISTER(0x41B5, float, SHADER_CONSTANT_109_Y) -XE_GPU_REGISTER(0x41B6, float, SHADER_CONSTANT_109_Z) -XE_GPU_REGISTER(0x41B7, float, SHADER_CONSTANT_109_W) -XE_GPU_REGISTER(0x41B8, float, SHADER_CONSTANT_110_X) -XE_GPU_REGISTER(0x41B9, float, SHADER_CONSTANT_110_Y) -XE_GPU_REGISTER(0x41BA, float, SHADER_CONSTANT_110_Z) -XE_GPU_REGISTER(0x41BB, float, SHADER_CONSTANT_110_W) -XE_GPU_REGISTER(0x41BC, float, SHADER_CONSTANT_111_X) -XE_GPU_REGISTER(0x41BD, float, SHADER_CONSTANT_111_Y) -XE_GPU_REGISTER(0x41BE, float, SHADER_CONSTANT_111_Z) -XE_GPU_REGISTER(0x41BF, float, SHADER_CONSTANT_111_W) -XE_GPU_REGISTER(0x41C0, float, SHADER_CONSTANT_112_X) -XE_GPU_REGISTER(0x41C1, float, SHADER_CONSTANT_112_Y) -XE_GPU_REGISTER(0x41C2, float, SHADER_CONSTANT_112_Z) -XE_GPU_REGISTER(0x41C3, float, SHADER_CONSTANT_112_W) -XE_GPU_REGISTER(0x41C4, float, SHADER_CONSTANT_113_X) -XE_GPU_REGISTER(0x41C5, float, SHADER_CONSTANT_113_Y) -XE_GPU_REGISTER(0x41C6, float, SHADER_CONSTANT_113_Z) -XE_GPU_REGISTER(0x41C7, float, SHADER_CONSTANT_113_W) -XE_GPU_REGISTER(0x41C8, float, SHADER_CONSTANT_114_X) -XE_GPU_REGISTER(0x41C9, float, SHADER_CONSTANT_114_Y) -XE_GPU_REGISTER(0x41CA, float, SHADER_CONSTANT_114_Z) -XE_GPU_REGISTER(0x41CB, float, SHADER_CONSTANT_114_W) -XE_GPU_REGISTER(0x41CC, float, SHADER_CONSTANT_115_X) -XE_GPU_REGISTER(0x41CD, float, SHADER_CONSTANT_115_Y) -XE_GPU_REGISTER(0x41CE, float, SHADER_CONSTANT_115_Z) -XE_GPU_REGISTER(0x41CF, float, SHADER_CONSTANT_115_W) -XE_GPU_REGISTER(0x41D0, float, SHADER_CONSTANT_116_X) -XE_GPU_REGISTER(0x41D1, float, SHADER_CONSTANT_116_Y) -XE_GPU_REGISTER(0x41D2, float, SHADER_CONSTANT_116_Z) -XE_GPU_REGISTER(0x41D3, float, SHADER_CONSTANT_116_W) -XE_GPU_REGISTER(0x41D4, float, SHADER_CONSTANT_117_X) -XE_GPU_REGISTER(0x41D5, float, SHADER_CONSTANT_117_Y) -XE_GPU_REGISTER(0x41D6, float, SHADER_CONSTANT_117_Z) -XE_GPU_REGISTER(0x41D7, float, SHADER_CONSTANT_117_W) -XE_GPU_REGISTER(0x41D8, float, SHADER_CONSTANT_118_X) -XE_GPU_REGISTER(0x41D9, float, SHADER_CONSTANT_118_Y) -XE_GPU_REGISTER(0x41DA, float, SHADER_CONSTANT_118_Z) -XE_GPU_REGISTER(0x41DB, float, SHADER_CONSTANT_118_W) -XE_GPU_REGISTER(0x41DC, float, SHADER_CONSTANT_119_X) -XE_GPU_REGISTER(0x41DD, float, SHADER_CONSTANT_119_Y) -XE_GPU_REGISTER(0x41DE, float, SHADER_CONSTANT_119_Z) -XE_GPU_REGISTER(0x41DF, float, SHADER_CONSTANT_119_W) -XE_GPU_REGISTER(0x41E0, float, SHADER_CONSTANT_120_X) -XE_GPU_REGISTER(0x41E1, float, SHADER_CONSTANT_120_Y) -XE_GPU_REGISTER(0x41E2, float, SHADER_CONSTANT_120_Z) -XE_GPU_REGISTER(0x41E3, float, SHADER_CONSTANT_120_W) -XE_GPU_REGISTER(0x41E4, float, SHADER_CONSTANT_121_X) -XE_GPU_REGISTER(0x41E5, float, SHADER_CONSTANT_121_Y) -XE_GPU_REGISTER(0x41E6, float, SHADER_CONSTANT_121_Z) -XE_GPU_REGISTER(0x41E7, float, SHADER_CONSTANT_121_W) -XE_GPU_REGISTER(0x41E8, float, SHADER_CONSTANT_122_X) -XE_GPU_REGISTER(0x41E9, float, SHADER_CONSTANT_122_Y) -XE_GPU_REGISTER(0x41EA, float, SHADER_CONSTANT_122_Z) -XE_GPU_REGISTER(0x41EB, float, SHADER_CONSTANT_122_W) -XE_GPU_REGISTER(0x41EC, float, SHADER_CONSTANT_123_X) -XE_GPU_REGISTER(0x41ED, float, SHADER_CONSTANT_123_Y) -XE_GPU_REGISTER(0x41EE, float, SHADER_CONSTANT_123_Z) -XE_GPU_REGISTER(0x41EF, float, SHADER_CONSTANT_123_W) -XE_GPU_REGISTER(0x41F0, float, SHADER_CONSTANT_124_X) -XE_GPU_REGISTER(0x41F1, float, SHADER_CONSTANT_124_Y) -XE_GPU_REGISTER(0x41F2, float, SHADER_CONSTANT_124_Z) -XE_GPU_REGISTER(0x41F3, float, SHADER_CONSTANT_124_W) -XE_GPU_REGISTER(0x41F4, float, SHADER_CONSTANT_125_X) -XE_GPU_REGISTER(0x41F5, float, SHADER_CONSTANT_125_Y) -XE_GPU_REGISTER(0x41F6, float, SHADER_CONSTANT_125_Z) -XE_GPU_REGISTER(0x41F7, float, SHADER_CONSTANT_125_W) -XE_GPU_REGISTER(0x41F8, float, SHADER_CONSTANT_126_X) -XE_GPU_REGISTER(0x41F9, float, SHADER_CONSTANT_126_Y) -XE_GPU_REGISTER(0x41FA, float, SHADER_CONSTANT_126_Z) -XE_GPU_REGISTER(0x41FB, float, SHADER_CONSTANT_126_W) -XE_GPU_REGISTER(0x41FC, float, SHADER_CONSTANT_127_X) -XE_GPU_REGISTER(0x41FD, float, SHADER_CONSTANT_127_Y) -XE_GPU_REGISTER(0x41FE, float, SHADER_CONSTANT_127_Z) -XE_GPU_REGISTER(0x41FF, float, SHADER_CONSTANT_127_W) -XE_GPU_REGISTER(0x4200, float, SHADER_CONSTANT_128_X) -XE_GPU_REGISTER(0x4201, float, SHADER_CONSTANT_128_Y) -XE_GPU_REGISTER(0x4202, float, SHADER_CONSTANT_128_Z) -XE_GPU_REGISTER(0x4203, float, SHADER_CONSTANT_128_W) -XE_GPU_REGISTER(0x4204, float, SHADER_CONSTANT_129_X) -XE_GPU_REGISTER(0x4205, float, SHADER_CONSTANT_129_Y) -XE_GPU_REGISTER(0x4206, float, SHADER_CONSTANT_129_Z) -XE_GPU_REGISTER(0x4207, float, SHADER_CONSTANT_129_W) -XE_GPU_REGISTER(0x4208, float, SHADER_CONSTANT_130_X) -XE_GPU_REGISTER(0x4209, float, SHADER_CONSTANT_130_Y) -XE_GPU_REGISTER(0x420A, float, SHADER_CONSTANT_130_Z) -XE_GPU_REGISTER(0x420B, float, SHADER_CONSTANT_130_W) -XE_GPU_REGISTER(0x420C, float, SHADER_CONSTANT_131_X) -XE_GPU_REGISTER(0x420D, float, SHADER_CONSTANT_131_Y) -XE_GPU_REGISTER(0x420E, float, SHADER_CONSTANT_131_Z) -XE_GPU_REGISTER(0x420F, float, SHADER_CONSTANT_131_W) -XE_GPU_REGISTER(0x4210, float, SHADER_CONSTANT_132_X) -XE_GPU_REGISTER(0x4211, float, SHADER_CONSTANT_132_Y) -XE_GPU_REGISTER(0x4212, float, SHADER_CONSTANT_132_Z) -XE_GPU_REGISTER(0x4213, float, SHADER_CONSTANT_132_W) -XE_GPU_REGISTER(0x4214, float, SHADER_CONSTANT_133_X) -XE_GPU_REGISTER(0x4215, float, SHADER_CONSTANT_133_Y) -XE_GPU_REGISTER(0x4216, float, SHADER_CONSTANT_133_Z) -XE_GPU_REGISTER(0x4217, float, SHADER_CONSTANT_133_W) -XE_GPU_REGISTER(0x4218, float, SHADER_CONSTANT_134_X) -XE_GPU_REGISTER(0x4219, float, SHADER_CONSTANT_134_Y) -XE_GPU_REGISTER(0x421A, float, SHADER_CONSTANT_134_Z) -XE_GPU_REGISTER(0x421B, float, SHADER_CONSTANT_134_W) -XE_GPU_REGISTER(0x421C, float, SHADER_CONSTANT_135_X) -XE_GPU_REGISTER(0x421D, float, SHADER_CONSTANT_135_Y) -XE_GPU_REGISTER(0x421E, float, SHADER_CONSTANT_135_Z) -XE_GPU_REGISTER(0x421F, float, SHADER_CONSTANT_135_W) -XE_GPU_REGISTER(0x4220, float, SHADER_CONSTANT_136_X) -XE_GPU_REGISTER(0x4221, float, SHADER_CONSTANT_136_Y) -XE_GPU_REGISTER(0x4222, float, SHADER_CONSTANT_136_Z) -XE_GPU_REGISTER(0x4223, float, SHADER_CONSTANT_136_W) -XE_GPU_REGISTER(0x4224, float, SHADER_CONSTANT_137_X) -XE_GPU_REGISTER(0x4225, float, SHADER_CONSTANT_137_Y) -XE_GPU_REGISTER(0x4226, float, SHADER_CONSTANT_137_Z) -XE_GPU_REGISTER(0x4227, float, SHADER_CONSTANT_137_W) -XE_GPU_REGISTER(0x4228, float, SHADER_CONSTANT_138_X) -XE_GPU_REGISTER(0x4229, float, SHADER_CONSTANT_138_Y) -XE_GPU_REGISTER(0x422A, float, SHADER_CONSTANT_138_Z) -XE_GPU_REGISTER(0x422B, float, SHADER_CONSTANT_138_W) -XE_GPU_REGISTER(0x422C, float, SHADER_CONSTANT_139_X) -XE_GPU_REGISTER(0x422D, float, SHADER_CONSTANT_139_Y) -XE_GPU_REGISTER(0x422E, float, SHADER_CONSTANT_139_Z) -XE_GPU_REGISTER(0x422F, float, SHADER_CONSTANT_139_W) -XE_GPU_REGISTER(0x4230, float, SHADER_CONSTANT_140_X) -XE_GPU_REGISTER(0x4231, float, SHADER_CONSTANT_140_Y) -XE_GPU_REGISTER(0x4232, float, SHADER_CONSTANT_140_Z) -XE_GPU_REGISTER(0x4233, float, SHADER_CONSTANT_140_W) -XE_GPU_REGISTER(0x4234, float, SHADER_CONSTANT_141_X) -XE_GPU_REGISTER(0x4235, float, SHADER_CONSTANT_141_Y) -XE_GPU_REGISTER(0x4236, float, SHADER_CONSTANT_141_Z) -XE_GPU_REGISTER(0x4237, float, SHADER_CONSTANT_141_W) -XE_GPU_REGISTER(0x4238, float, SHADER_CONSTANT_142_X) -XE_GPU_REGISTER(0x4239, float, SHADER_CONSTANT_142_Y) -XE_GPU_REGISTER(0x423A, float, SHADER_CONSTANT_142_Z) -XE_GPU_REGISTER(0x423B, float, SHADER_CONSTANT_142_W) -XE_GPU_REGISTER(0x423C, float, SHADER_CONSTANT_143_X) -XE_GPU_REGISTER(0x423D, float, SHADER_CONSTANT_143_Y) -XE_GPU_REGISTER(0x423E, float, SHADER_CONSTANT_143_Z) -XE_GPU_REGISTER(0x423F, float, SHADER_CONSTANT_143_W) -XE_GPU_REGISTER(0x4240, float, SHADER_CONSTANT_144_X) -XE_GPU_REGISTER(0x4241, float, SHADER_CONSTANT_144_Y) -XE_GPU_REGISTER(0x4242, float, SHADER_CONSTANT_144_Z) -XE_GPU_REGISTER(0x4243, float, SHADER_CONSTANT_144_W) -XE_GPU_REGISTER(0x4244, float, SHADER_CONSTANT_145_X) -XE_GPU_REGISTER(0x4245, float, SHADER_CONSTANT_145_Y) -XE_GPU_REGISTER(0x4246, float, SHADER_CONSTANT_145_Z) -XE_GPU_REGISTER(0x4247, float, SHADER_CONSTANT_145_W) -XE_GPU_REGISTER(0x4248, float, SHADER_CONSTANT_146_X) -XE_GPU_REGISTER(0x4249, float, SHADER_CONSTANT_146_Y) -XE_GPU_REGISTER(0x424A, float, SHADER_CONSTANT_146_Z) -XE_GPU_REGISTER(0x424B, float, SHADER_CONSTANT_146_W) -XE_GPU_REGISTER(0x424C, float, SHADER_CONSTANT_147_X) -XE_GPU_REGISTER(0x424D, float, SHADER_CONSTANT_147_Y) -XE_GPU_REGISTER(0x424E, float, SHADER_CONSTANT_147_Z) -XE_GPU_REGISTER(0x424F, float, SHADER_CONSTANT_147_W) -XE_GPU_REGISTER(0x4250, float, SHADER_CONSTANT_148_X) -XE_GPU_REGISTER(0x4251, float, SHADER_CONSTANT_148_Y) -XE_GPU_REGISTER(0x4252, float, SHADER_CONSTANT_148_Z) -XE_GPU_REGISTER(0x4253, float, SHADER_CONSTANT_148_W) -XE_GPU_REGISTER(0x4254, float, SHADER_CONSTANT_149_X) -XE_GPU_REGISTER(0x4255, float, SHADER_CONSTANT_149_Y) -XE_GPU_REGISTER(0x4256, float, SHADER_CONSTANT_149_Z) -XE_GPU_REGISTER(0x4257, float, SHADER_CONSTANT_149_W) -XE_GPU_REGISTER(0x4258, float, SHADER_CONSTANT_150_X) -XE_GPU_REGISTER(0x4259, float, SHADER_CONSTANT_150_Y) -XE_GPU_REGISTER(0x425A, float, SHADER_CONSTANT_150_Z) -XE_GPU_REGISTER(0x425B, float, SHADER_CONSTANT_150_W) -XE_GPU_REGISTER(0x425C, float, SHADER_CONSTANT_151_X) -XE_GPU_REGISTER(0x425D, float, SHADER_CONSTANT_151_Y) -XE_GPU_REGISTER(0x425E, float, SHADER_CONSTANT_151_Z) -XE_GPU_REGISTER(0x425F, float, SHADER_CONSTANT_151_W) -XE_GPU_REGISTER(0x4260, float, SHADER_CONSTANT_152_X) -XE_GPU_REGISTER(0x4261, float, SHADER_CONSTANT_152_Y) -XE_GPU_REGISTER(0x4262, float, SHADER_CONSTANT_152_Z) -XE_GPU_REGISTER(0x4263, float, SHADER_CONSTANT_152_W) -XE_GPU_REGISTER(0x4264, float, SHADER_CONSTANT_153_X) -XE_GPU_REGISTER(0x4265, float, SHADER_CONSTANT_153_Y) -XE_GPU_REGISTER(0x4266, float, SHADER_CONSTANT_153_Z) -XE_GPU_REGISTER(0x4267, float, SHADER_CONSTANT_153_W) -XE_GPU_REGISTER(0x4268, float, SHADER_CONSTANT_154_X) -XE_GPU_REGISTER(0x4269, float, SHADER_CONSTANT_154_Y) -XE_GPU_REGISTER(0x426A, float, SHADER_CONSTANT_154_Z) -XE_GPU_REGISTER(0x426B, float, SHADER_CONSTANT_154_W) -XE_GPU_REGISTER(0x426C, float, SHADER_CONSTANT_155_X) -XE_GPU_REGISTER(0x426D, float, SHADER_CONSTANT_155_Y) -XE_GPU_REGISTER(0x426E, float, SHADER_CONSTANT_155_Z) -XE_GPU_REGISTER(0x426F, float, SHADER_CONSTANT_155_W) -XE_GPU_REGISTER(0x4270, float, SHADER_CONSTANT_156_X) -XE_GPU_REGISTER(0x4271, float, SHADER_CONSTANT_156_Y) -XE_GPU_REGISTER(0x4272, float, SHADER_CONSTANT_156_Z) -XE_GPU_REGISTER(0x4273, float, SHADER_CONSTANT_156_W) -XE_GPU_REGISTER(0x4274, float, SHADER_CONSTANT_157_X) -XE_GPU_REGISTER(0x4275, float, SHADER_CONSTANT_157_Y) -XE_GPU_REGISTER(0x4276, float, SHADER_CONSTANT_157_Z) -XE_GPU_REGISTER(0x4277, float, SHADER_CONSTANT_157_W) -XE_GPU_REGISTER(0x4278, float, SHADER_CONSTANT_158_X) -XE_GPU_REGISTER(0x4279, float, SHADER_CONSTANT_158_Y) -XE_GPU_REGISTER(0x427A, float, SHADER_CONSTANT_158_Z) -XE_GPU_REGISTER(0x427B, float, SHADER_CONSTANT_158_W) -XE_GPU_REGISTER(0x427C, float, SHADER_CONSTANT_159_X) -XE_GPU_REGISTER(0x427D, float, SHADER_CONSTANT_159_Y) -XE_GPU_REGISTER(0x427E, float, SHADER_CONSTANT_159_Z) -XE_GPU_REGISTER(0x427F, float, SHADER_CONSTANT_159_W) -XE_GPU_REGISTER(0x4280, float, SHADER_CONSTANT_160_X) -XE_GPU_REGISTER(0x4281, float, SHADER_CONSTANT_160_Y) -XE_GPU_REGISTER(0x4282, float, SHADER_CONSTANT_160_Z) -XE_GPU_REGISTER(0x4283, float, SHADER_CONSTANT_160_W) -XE_GPU_REGISTER(0x4284, float, SHADER_CONSTANT_161_X) -XE_GPU_REGISTER(0x4285, float, SHADER_CONSTANT_161_Y) -XE_GPU_REGISTER(0x4286, float, SHADER_CONSTANT_161_Z) -XE_GPU_REGISTER(0x4287, float, SHADER_CONSTANT_161_W) -XE_GPU_REGISTER(0x4288, float, SHADER_CONSTANT_162_X) -XE_GPU_REGISTER(0x4289, float, SHADER_CONSTANT_162_Y) -XE_GPU_REGISTER(0x428A, float, SHADER_CONSTANT_162_Z) -XE_GPU_REGISTER(0x428B, float, SHADER_CONSTANT_162_W) -XE_GPU_REGISTER(0x428C, float, SHADER_CONSTANT_163_X) -XE_GPU_REGISTER(0x428D, float, SHADER_CONSTANT_163_Y) -XE_GPU_REGISTER(0x428E, float, SHADER_CONSTANT_163_Z) -XE_GPU_REGISTER(0x428F, float, SHADER_CONSTANT_163_W) -XE_GPU_REGISTER(0x4290, float, SHADER_CONSTANT_164_X) -XE_GPU_REGISTER(0x4291, float, SHADER_CONSTANT_164_Y) -XE_GPU_REGISTER(0x4292, float, SHADER_CONSTANT_164_Z) -XE_GPU_REGISTER(0x4293, float, SHADER_CONSTANT_164_W) -XE_GPU_REGISTER(0x4294, float, SHADER_CONSTANT_165_X) -XE_GPU_REGISTER(0x4295, float, SHADER_CONSTANT_165_Y) -XE_GPU_REGISTER(0x4296, float, SHADER_CONSTANT_165_Z) -XE_GPU_REGISTER(0x4297, float, SHADER_CONSTANT_165_W) -XE_GPU_REGISTER(0x4298, float, SHADER_CONSTANT_166_X) -XE_GPU_REGISTER(0x4299, float, SHADER_CONSTANT_166_Y) -XE_GPU_REGISTER(0x429A, float, SHADER_CONSTANT_166_Z) -XE_GPU_REGISTER(0x429B, float, SHADER_CONSTANT_166_W) -XE_GPU_REGISTER(0x429C, float, SHADER_CONSTANT_167_X) -XE_GPU_REGISTER(0x429D, float, SHADER_CONSTANT_167_Y) -XE_GPU_REGISTER(0x429E, float, SHADER_CONSTANT_167_Z) -XE_GPU_REGISTER(0x429F, float, SHADER_CONSTANT_167_W) -XE_GPU_REGISTER(0x42A0, float, SHADER_CONSTANT_168_X) -XE_GPU_REGISTER(0x42A1, float, SHADER_CONSTANT_168_Y) -XE_GPU_REGISTER(0x42A2, float, SHADER_CONSTANT_168_Z) -XE_GPU_REGISTER(0x42A3, float, SHADER_CONSTANT_168_W) -XE_GPU_REGISTER(0x42A4, float, SHADER_CONSTANT_169_X) -XE_GPU_REGISTER(0x42A5, float, SHADER_CONSTANT_169_Y) -XE_GPU_REGISTER(0x42A6, float, SHADER_CONSTANT_169_Z) -XE_GPU_REGISTER(0x42A7, float, SHADER_CONSTANT_169_W) -XE_GPU_REGISTER(0x42A8, float, SHADER_CONSTANT_170_X) -XE_GPU_REGISTER(0x42A9, float, SHADER_CONSTANT_170_Y) -XE_GPU_REGISTER(0x42AA, float, SHADER_CONSTANT_170_Z) -XE_GPU_REGISTER(0x42AB, float, SHADER_CONSTANT_170_W) -XE_GPU_REGISTER(0x42AC, float, SHADER_CONSTANT_171_X) -XE_GPU_REGISTER(0x42AD, float, SHADER_CONSTANT_171_Y) -XE_GPU_REGISTER(0x42AE, float, SHADER_CONSTANT_171_Z) -XE_GPU_REGISTER(0x42AF, float, SHADER_CONSTANT_171_W) -XE_GPU_REGISTER(0x42B0, float, SHADER_CONSTANT_172_X) -XE_GPU_REGISTER(0x42B1, float, SHADER_CONSTANT_172_Y) -XE_GPU_REGISTER(0x42B2, float, SHADER_CONSTANT_172_Z) -XE_GPU_REGISTER(0x42B3, float, SHADER_CONSTANT_172_W) -XE_GPU_REGISTER(0x42B4, float, SHADER_CONSTANT_173_X) -XE_GPU_REGISTER(0x42B5, float, SHADER_CONSTANT_173_Y) -XE_GPU_REGISTER(0x42B6, float, SHADER_CONSTANT_173_Z) -XE_GPU_REGISTER(0x42B7, float, SHADER_CONSTANT_173_W) -XE_GPU_REGISTER(0x42B8, float, SHADER_CONSTANT_174_X) -XE_GPU_REGISTER(0x42B9, float, SHADER_CONSTANT_174_Y) -XE_GPU_REGISTER(0x42BA, float, SHADER_CONSTANT_174_Z) -XE_GPU_REGISTER(0x42BB, float, SHADER_CONSTANT_174_W) -XE_GPU_REGISTER(0x42BC, float, SHADER_CONSTANT_175_X) -XE_GPU_REGISTER(0x42BD, float, SHADER_CONSTANT_175_Y) -XE_GPU_REGISTER(0x42BE, float, SHADER_CONSTANT_175_Z) -XE_GPU_REGISTER(0x42BF, float, SHADER_CONSTANT_175_W) -XE_GPU_REGISTER(0x42C0, float, SHADER_CONSTANT_176_X) -XE_GPU_REGISTER(0x42C1, float, SHADER_CONSTANT_176_Y) -XE_GPU_REGISTER(0x42C2, float, SHADER_CONSTANT_176_Z) -XE_GPU_REGISTER(0x42C3, float, SHADER_CONSTANT_176_W) -XE_GPU_REGISTER(0x42C4, float, SHADER_CONSTANT_177_X) -XE_GPU_REGISTER(0x42C5, float, SHADER_CONSTANT_177_Y) -XE_GPU_REGISTER(0x42C6, float, SHADER_CONSTANT_177_Z) -XE_GPU_REGISTER(0x42C7, float, SHADER_CONSTANT_177_W) -XE_GPU_REGISTER(0x42C8, float, SHADER_CONSTANT_178_X) -XE_GPU_REGISTER(0x42C9, float, SHADER_CONSTANT_178_Y) -XE_GPU_REGISTER(0x42CA, float, SHADER_CONSTANT_178_Z) -XE_GPU_REGISTER(0x42CB, float, SHADER_CONSTANT_178_W) -XE_GPU_REGISTER(0x42CC, float, SHADER_CONSTANT_179_X) -XE_GPU_REGISTER(0x42CD, float, SHADER_CONSTANT_179_Y) -XE_GPU_REGISTER(0x42CE, float, SHADER_CONSTANT_179_Z) -XE_GPU_REGISTER(0x42CF, float, SHADER_CONSTANT_179_W) -XE_GPU_REGISTER(0x42D0, float, SHADER_CONSTANT_180_X) -XE_GPU_REGISTER(0x42D1, float, SHADER_CONSTANT_180_Y) -XE_GPU_REGISTER(0x42D2, float, SHADER_CONSTANT_180_Z) -XE_GPU_REGISTER(0x42D3, float, SHADER_CONSTANT_180_W) -XE_GPU_REGISTER(0x42D4, float, SHADER_CONSTANT_181_X) -XE_GPU_REGISTER(0x42D5, float, SHADER_CONSTANT_181_Y) -XE_GPU_REGISTER(0x42D6, float, SHADER_CONSTANT_181_Z) -XE_GPU_REGISTER(0x42D7, float, SHADER_CONSTANT_181_W) -XE_GPU_REGISTER(0x42D8, float, SHADER_CONSTANT_182_X) -XE_GPU_REGISTER(0x42D9, float, SHADER_CONSTANT_182_Y) -XE_GPU_REGISTER(0x42DA, float, SHADER_CONSTANT_182_Z) -XE_GPU_REGISTER(0x42DB, float, SHADER_CONSTANT_182_W) -XE_GPU_REGISTER(0x42DC, float, SHADER_CONSTANT_183_X) -XE_GPU_REGISTER(0x42DD, float, SHADER_CONSTANT_183_Y) -XE_GPU_REGISTER(0x42DE, float, SHADER_CONSTANT_183_Z) -XE_GPU_REGISTER(0x42DF, float, SHADER_CONSTANT_183_W) -XE_GPU_REGISTER(0x42E0, float, SHADER_CONSTANT_184_X) -XE_GPU_REGISTER(0x42E1, float, SHADER_CONSTANT_184_Y) -XE_GPU_REGISTER(0x42E2, float, SHADER_CONSTANT_184_Z) -XE_GPU_REGISTER(0x42E3, float, SHADER_CONSTANT_184_W) -XE_GPU_REGISTER(0x42E4, float, SHADER_CONSTANT_185_X) -XE_GPU_REGISTER(0x42E5, float, SHADER_CONSTANT_185_Y) -XE_GPU_REGISTER(0x42E6, float, SHADER_CONSTANT_185_Z) -XE_GPU_REGISTER(0x42E7, float, SHADER_CONSTANT_185_W) -XE_GPU_REGISTER(0x42E8, float, SHADER_CONSTANT_186_X) -XE_GPU_REGISTER(0x42E9, float, SHADER_CONSTANT_186_Y) -XE_GPU_REGISTER(0x42EA, float, SHADER_CONSTANT_186_Z) -XE_GPU_REGISTER(0x42EB, float, SHADER_CONSTANT_186_W) -XE_GPU_REGISTER(0x42EC, float, SHADER_CONSTANT_187_X) -XE_GPU_REGISTER(0x42ED, float, SHADER_CONSTANT_187_Y) -XE_GPU_REGISTER(0x42EE, float, SHADER_CONSTANT_187_Z) -XE_GPU_REGISTER(0x42EF, float, SHADER_CONSTANT_187_W) -XE_GPU_REGISTER(0x42F0, float, SHADER_CONSTANT_188_X) -XE_GPU_REGISTER(0x42F1, float, SHADER_CONSTANT_188_Y) -XE_GPU_REGISTER(0x42F2, float, SHADER_CONSTANT_188_Z) -XE_GPU_REGISTER(0x42F3, float, SHADER_CONSTANT_188_W) -XE_GPU_REGISTER(0x42F4, float, SHADER_CONSTANT_189_X) -XE_GPU_REGISTER(0x42F5, float, SHADER_CONSTANT_189_Y) -XE_GPU_REGISTER(0x42F6, float, SHADER_CONSTANT_189_Z) -XE_GPU_REGISTER(0x42F7, float, SHADER_CONSTANT_189_W) -XE_GPU_REGISTER(0x42F8, float, SHADER_CONSTANT_190_X) -XE_GPU_REGISTER(0x42F9, float, SHADER_CONSTANT_190_Y) -XE_GPU_REGISTER(0x42FA, float, SHADER_CONSTANT_190_Z) -XE_GPU_REGISTER(0x42FB, float, SHADER_CONSTANT_190_W) -XE_GPU_REGISTER(0x42FC, float, SHADER_CONSTANT_191_X) -XE_GPU_REGISTER(0x42FD, float, SHADER_CONSTANT_191_Y) -XE_GPU_REGISTER(0x42FE, float, SHADER_CONSTANT_191_Z) -XE_GPU_REGISTER(0x42FF, float, SHADER_CONSTANT_191_W) -XE_GPU_REGISTER(0x4300, float, SHADER_CONSTANT_192_X) -XE_GPU_REGISTER(0x4301, float, SHADER_CONSTANT_192_Y) -XE_GPU_REGISTER(0x4302, float, SHADER_CONSTANT_192_Z) -XE_GPU_REGISTER(0x4303, float, SHADER_CONSTANT_192_W) -XE_GPU_REGISTER(0x4304, float, SHADER_CONSTANT_193_X) -XE_GPU_REGISTER(0x4305, float, SHADER_CONSTANT_193_Y) -XE_GPU_REGISTER(0x4306, float, SHADER_CONSTANT_193_Z) -XE_GPU_REGISTER(0x4307, float, SHADER_CONSTANT_193_W) -XE_GPU_REGISTER(0x4308, float, SHADER_CONSTANT_194_X) -XE_GPU_REGISTER(0x4309, float, SHADER_CONSTANT_194_Y) -XE_GPU_REGISTER(0x430A, float, SHADER_CONSTANT_194_Z) -XE_GPU_REGISTER(0x430B, float, SHADER_CONSTANT_194_W) -XE_GPU_REGISTER(0x430C, float, SHADER_CONSTANT_195_X) -XE_GPU_REGISTER(0x430D, float, SHADER_CONSTANT_195_Y) -XE_GPU_REGISTER(0x430E, float, SHADER_CONSTANT_195_Z) -XE_GPU_REGISTER(0x430F, float, SHADER_CONSTANT_195_W) -XE_GPU_REGISTER(0x4310, float, SHADER_CONSTANT_196_X) -XE_GPU_REGISTER(0x4311, float, SHADER_CONSTANT_196_Y) -XE_GPU_REGISTER(0x4312, float, SHADER_CONSTANT_196_Z) -XE_GPU_REGISTER(0x4313, float, SHADER_CONSTANT_196_W) -XE_GPU_REGISTER(0x4314, float, SHADER_CONSTANT_197_X) -XE_GPU_REGISTER(0x4315, float, SHADER_CONSTANT_197_Y) -XE_GPU_REGISTER(0x4316, float, SHADER_CONSTANT_197_Z) -XE_GPU_REGISTER(0x4317, float, SHADER_CONSTANT_197_W) -XE_GPU_REGISTER(0x4318, float, SHADER_CONSTANT_198_X) -XE_GPU_REGISTER(0x4319, float, SHADER_CONSTANT_198_Y) -XE_GPU_REGISTER(0x431A, float, SHADER_CONSTANT_198_Z) -XE_GPU_REGISTER(0x431B, float, SHADER_CONSTANT_198_W) -XE_GPU_REGISTER(0x431C, float, SHADER_CONSTANT_199_X) -XE_GPU_REGISTER(0x431D, float, SHADER_CONSTANT_199_Y) -XE_GPU_REGISTER(0x431E, float, SHADER_CONSTANT_199_Z) -XE_GPU_REGISTER(0x431F, float, SHADER_CONSTANT_199_W) -XE_GPU_REGISTER(0x4320, float, SHADER_CONSTANT_200_X) -XE_GPU_REGISTER(0x4321, float, SHADER_CONSTANT_200_Y) -XE_GPU_REGISTER(0x4322, float, SHADER_CONSTANT_200_Z) -XE_GPU_REGISTER(0x4323, float, SHADER_CONSTANT_200_W) -XE_GPU_REGISTER(0x4324, float, SHADER_CONSTANT_201_X) -XE_GPU_REGISTER(0x4325, float, SHADER_CONSTANT_201_Y) -XE_GPU_REGISTER(0x4326, float, SHADER_CONSTANT_201_Z) -XE_GPU_REGISTER(0x4327, float, SHADER_CONSTANT_201_W) -XE_GPU_REGISTER(0x4328, float, SHADER_CONSTANT_202_X) -XE_GPU_REGISTER(0x4329, float, SHADER_CONSTANT_202_Y) -XE_GPU_REGISTER(0x432A, float, SHADER_CONSTANT_202_Z) -XE_GPU_REGISTER(0x432B, float, SHADER_CONSTANT_202_W) -XE_GPU_REGISTER(0x432C, float, SHADER_CONSTANT_203_X) -XE_GPU_REGISTER(0x432D, float, SHADER_CONSTANT_203_Y) -XE_GPU_REGISTER(0x432E, float, SHADER_CONSTANT_203_Z) -XE_GPU_REGISTER(0x432F, float, SHADER_CONSTANT_203_W) -XE_GPU_REGISTER(0x4330, float, SHADER_CONSTANT_204_X) -XE_GPU_REGISTER(0x4331, float, SHADER_CONSTANT_204_Y) -XE_GPU_REGISTER(0x4332, float, SHADER_CONSTANT_204_Z) -XE_GPU_REGISTER(0x4333, float, SHADER_CONSTANT_204_W) -XE_GPU_REGISTER(0x4334, float, SHADER_CONSTANT_205_X) -XE_GPU_REGISTER(0x4335, float, SHADER_CONSTANT_205_Y) -XE_GPU_REGISTER(0x4336, float, SHADER_CONSTANT_205_Z) -XE_GPU_REGISTER(0x4337, float, SHADER_CONSTANT_205_W) -XE_GPU_REGISTER(0x4338, float, SHADER_CONSTANT_206_X) -XE_GPU_REGISTER(0x4339, float, SHADER_CONSTANT_206_Y) -XE_GPU_REGISTER(0x433A, float, SHADER_CONSTANT_206_Z) -XE_GPU_REGISTER(0x433B, float, SHADER_CONSTANT_206_W) -XE_GPU_REGISTER(0x433C, float, SHADER_CONSTANT_207_X) -XE_GPU_REGISTER(0x433D, float, SHADER_CONSTANT_207_Y) -XE_GPU_REGISTER(0x433E, float, SHADER_CONSTANT_207_Z) -XE_GPU_REGISTER(0x433F, float, SHADER_CONSTANT_207_W) -XE_GPU_REGISTER(0x4340, float, SHADER_CONSTANT_208_X) -XE_GPU_REGISTER(0x4341, float, SHADER_CONSTANT_208_Y) -XE_GPU_REGISTER(0x4342, float, SHADER_CONSTANT_208_Z) -XE_GPU_REGISTER(0x4343, float, SHADER_CONSTANT_208_W) -XE_GPU_REGISTER(0x4344, float, SHADER_CONSTANT_209_X) -XE_GPU_REGISTER(0x4345, float, SHADER_CONSTANT_209_Y) -XE_GPU_REGISTER(0x4346, float, SHADER_CONSTANT_209_Z) -XE_GPU_REGISTER(0x4347, float, SHADER_CONSTANT_209_W) -XE_GPU_REGISTER(0x4348, float, SHADER_CONSTANT_210_X) -XE_GPU_REGISTER(0x4349, float, SHADER_CONSTANT_210_Y) -XE_GPU_REGISTER(0x434A, float, SHADER_CONSTANT_210_Z) -XE_GPU_REGISTER(0x434B, float, SHADER_CONSTANT_210_W) -XE_GPU_REGISTER(0x434C, float, SHADER_CONSTANT_211_X) -XE_GPU_REGISTER(0x434D, float, SHADER_CONSTANT_211_Y) -XE_GPU_REGISTER(0x434E, float, SHADER_CONSTANT_211_Z) -XE_GPU_REGISTER(0x434F, float, SHADER_CONSTANT_211_W) -XE_GPU_REGISTER(0x4350, float, SHADER_CONSTANT_212_X) -XE_GPU_REGISTER(0x4351, float, SHADER_CONSTANT_212_Y) -XE_GPU_REGISTER(0x4352, float, SHADER_CONSTANT_212_Z) -XE_GPU_REGISTER(0x4353, float, SHADER_CONSTANT_212_W) -XE_GPU_REGISTER(0x4354, float, SHADER_CONSTANT_213_X) -XE_GPU_REGISTER(0x4355, float, SHADER_CONSTANT_213_Y) -XE_GPU_REGISTER(0x4356, float, SHADER_CONSTANT_213_Z) -XE_GPU_REGISTER(0x4357, float, SHADER_CONSTANT_213_W) -XE_GPU_REGISTER(0x4358, float, SHADER_CONSTANT_214_X) -XE_GPU_REGISTER(0x4359, float, SHADER_CONSTANT_214_Y) -XE_GPU_REGISTER(0x435A, float, SHADER_CONSTANT_214_Z) -XE_GPU_REGISTER(0x435B, float, SHADER_CONSTANT_214_W) -XE_GPU_REGISTER(0x435C, float, SHADER_CONSTANT_215_X) -XE_GPU_REGISTER(0x435D, float, SHADER_CONSTANT_215_Y) -XE_GPU_REGISTER(0x435E, float, SHADER_CONSTANT_215_Z) -XE_GPU_REGISTER(0x435F, float, SHADER_CONSTANT_215_W) -XE_GPU_REGISTER(0x4360, float, SHADER_CONSTANT_216_X) -XE_GPU_REGISTER(0x4361, float, SHADER_CONSTANT_216_Y) -XE_GPU_REGISTER(0x4362, float, SHADER_CONSTANT_216_Z) -XE_GPU_REGISTER(0x4363, float, SHADER_CONSTANT_216_W) -XE_GPU_REGISTER(0x4364, float, SHADER_CONSTANT_217_X) -XE_GPU_REGISTER(0x4365, float, SHADER_CONSTANT_217_Y) -XE_GPU_REGISTER(0x4366, float, SHADER_CONSTANT_217_Z) -XE_GPU_REGISTER(0x4367, float, SHADER_CONSTANT_217_W) -XE_GPU_REGISTER(0x4368, float, SHADER_CONSTANT_218_X) -XE_GPU_REGISTER(0x4369, float, SHADER_CONSTANT_218_Y) -XE_GPU_REGISTER(0x436A, float, SHADER_CONSTANT_218_Z) -XE_GPU_REGISTER(0x436B, float, SHADER_CONSTANT_218_W) -XE_GPU_REGISTER(0x436C, float, SHADER_CONSTANT_219_X) -XE_GPU_REGISTER(0x436D, float, SHADER_CONSTANT_219_Y) -XE_GPU_REGISTER(0x436E, float, SHADER_CONSTANT_219_Z) -XE_GPU_REGISTER(0x436F, float, SHADER_CONSTANT_219_W) -XE_GPU_REGISTER(0x4370, float, SHADER_CONSTANT_220_X) -XE_GPU_REGISTER(0x4371, float, SHADER_CONSTANT_220_Y) -XE_GPU_REGISTER(0x4372, float, SHADER_CONSTANT_220_Z) -XE_GPU_REGISTER(0x4373, float, SHADER_CONSTANT_220_W) -XE_GPU_REGISTER(0x4374, float, SHADER_CONSTANT_221_X) -XE_GPU_REGISTER(0x4375, float, SHADER_CONSTANT_221_Y) -XE_GPU_REGISTER(0x4376, float, SHADER_CONSTANT_221_Z) -XE_GPU_REGISTER(0x4377, float, SHADER_CONSTANT_221_W) -XE_GPU_REGISTER(0x4378, float, SHADER_CONSTANT_222_X) -XE_GPU_REGISTER(0x4379, float, SHADER_CONSTANT_222_Y) -XE_GPU_REGISTER(0x437A, float, SHADER_CONSTANT_222_Z) -XE_GPU_REGISTER(0x437B, float, SHADER_CONSTANT_222_W) -XE_GPU_REGISTER(0x437C, float, SHADER_CONSTANT_223_X) -XE_GPU_REGISTER(0x437D, float, SHADER_CONSTANT_223_Y) -XE_GPU_REGISTER(0x437E, float, SHADER_CONSTANT_223_Z) -XE_GPU_REGISTER(0x437F, float, SHADER_CONSTANT_223_W) -XE_GPU_REGISTER(0x4380, float, SHADER_CONSTANT_224_X) -XE_GPU_REGISTER(0x4381, float, SHADER_CONSTANT_224_Y) -XE_GPU_REGISTER(0x4382, float, SHADER_CONSTANT_224_Z) -XE_GPU_REGISTER(0x4383, float, SHADER_CONSTANT_224_W) -XE_GPU_REGISTER(0x4384, float, SHADER_CONSTANT_225_X) -XE_GPU_REGISTER(0x4385, float, SHADER_CONSTANT_225_Y) -XE_GPU_REGISTER(0x4386, float, SHADER_CONSTANT_225_Z) -XE_GPU_REGISTER(0x4387, float, SHADER_CONSTANT_225_W) -XE_GPU_REGISTER(0x4388, float, SHADER_CONSTANT_226_X) -XE_GPU_REGISTER(0x4389, float, SHADER_CONSTANT_226_Y) -XE_GPU_REGISTER(0x438A, float, SHADER_CONSTANT_226_Z) -XE_GPU_REGISTER(0x438B, float, SHADER_CONSTANT_226_W) -XE_GPU_REGISTER(0x438C, float, SHADER_CONSTANT_227_X) -XE_GPU_REGISTER(0x438D, float, SHADER_CONSTANT_227_Y) -XE_GPU_REGISTER(0x438E, float, SHADER_CONSTANT_227_Z) -XE_GPU_REGISTER(0x438F, float, SHADER_CONSTANT_227_W) -XE_GPU_REGISTER(0x4390, float, SHADER_CONSTANT_228_X) -XE_GPU_REGISTER(0x4391, float, SHADER_CONSTANT_228_Y) -XE_GPU_REGISTER(0x4392, float, SHADER_CONSTANT_228_Z) -XE_GPU_REGISTER(0x4393, float, SHADER_CONSTANT_228_W) -XE_GPU_REGISTER(0x4394, float, SHADER_CONSTANT_229_X) -XE_GPU_REGISTER(0x4395, float, SHADER_CONSTANT_229_Y) -XE_GPU_REGISTER(0x4396, float, SHADER_CONSTANT_229_Z) -XE_GPU_REGISTER(0x4397, float, SHADER_CONSTANT_229_W) -XE_GPU_REGISTER(0x4398, float, SHADER_CONSTANT_230_X) -XE_GPU_REGISTER(0x4399, float, SHADER_CONSTANT_230_Y) -XE_GPU_REGISTER(0x439A, float, SHADER_CONSTANT_230_Z) -XE_GPU_REGISTER(0x439B, float, SHADER_CONSTANT_230_W) -XE_GPU_REGISTER(0x439C, float, SHADER_CONSTANT_231_X) -XE_GPU_REGISTER(0x439D, float, SHADER_CONSTANT_231_Y) -XE_GPU_REGISTER(0x439E, float, SHADER_CONSTANT_231_Z) -XE_GPU_REGISTER(0x439F, float, SHADER_CONSTANT_231_W) -XE_GPU_REGISTER(0x43A0, float, SHADER_CONSTANT_232_X) -XE_GPU_REGISTER(0x43A1, float, SHADER_CONSTANT_232_Y) -XE_GPU_REGISTER(0x43A2, float, SHADER_CONSTANT_232_Z) -XE_GPU_REGISTER(0x43A3, float, SHADER_CONSTANT_232_W) -XE_GPU_REGISTER(0x43A4, float, SHADER_CONSTANT_233_X) -XE_GPU_REGISTER(0x43A5, float, SHADER_CONSTANT_233_Y) -XE_GPU_REGISTER(0x43A6, float, SHADER_CONSTANT_233_Z) -XE_GPU_REGISTER(0x43A7, float, SHADER_CONSTANT_233_W) -XE_GPU_REGISTER(0x43A8, float, SHADER_CONSTANT_234_X) -XE_GPU_REGISTER(0x43A9, float, SHADER_CONSTANT_234_Y) -XE_GPU_REGISTER(0x43AA, float, SHADER_CONSTANT_234_Z) -XE_GPU_REGISTER(0x43AB, float, SHADER_CONSTANT_234_W) -XE_GPU_REGISTER(0x43AC, float, SHADER_CONSTANT_235_X) -XE_GPU_REGISTER(0x43AD, float, SHADER_CONSTANT_235_Y) -XE_GPU_REGISTER(0x43AE, float, SHADER_CONSTANT_235_Z) -XE_GPU_REGISTER(0x43AF, float, SHADER_CONSTANT_235_W) -XE_GPU_REGISTER(0x43B0, float, SHADER_CONSTANT_236_X) -XE_GPU_REGISTER(0x43B1, float, SHADER_CONSTANT_236_Y) -XE_GPU_REGISTER(0x43B2, float, SHADER_CONSTANT_236_Z) -XE_GPU_REGISTER(0x43B3, float, SHADER_CONSTANT_236_W) -XE_GPU_REGISTER(0x43B4, float, SHADER_CONSTANT_237_X) -XE_GPU_REGISTER(0x43B5, float, SHADER_CONSTANT_237_Y) -XE_GPU_REGISTER(0x43B6, float, SHADER_CONSTANT_237_Z) -XE_GPU_REGISTER(0x43B7, float, SHADER_CONSTANT_237_W) -XE_GPU_REGISTER(0x43B8, float, SHADER_CONSTANT_238_X) -XE_GPU_REGISTER(0x43B9, float, SHADER_CONSTANT_238_Y) -XE_GPU_REGISTER(0x43BA, float, SHADER_CONSTANT_238_Z) -XE_GPU_REGISTER(0x43BB, float, SHADER_CONSTANT_238_W) -XE_GPU_REGISTER(0x43BC, float, SHADER_CONSTANT_239_X) -XE_GPU_REGISTER(0x43BD, float, SHADER_CONSTANT_239_Y) -XE_GPU_REGISTER(0x43BE, float, SHADER_CONSTANT_239_Z) -XE_GPU_REGISTER(0x43BF, float, SHADER_CONSTANT_239_W) -XE_GPU_REGISTER(0x43C0, float, SHADER_CONSTANT_240_X) -XE_GPU_REGISTER(0x43C1, float, SHADER_CONSTANT_240_Y) -XE_GPU_REGISTER(0x43C2, float, SHADER_CONSTANT_240_Z) -XE_GPU_REGISTER(0x43C3, float, SHADER_CONSTANT_240_W) -XE_GPU_REGISTER(0x43C4, float, SHADER_CONSTANT_241_X) -XE_GPU_REGISTER(0x43C5, float, SHADER_CONSTANT_241_Y) -XE_GPU_REGISTER(0x43C6, float, SHADER_CONSTANT_241_Z) -XE_GPU_REGISTER(0x43C7, float, SHADER_CONSTANT_241_W) -XE_GPU_REGISTER(0x43C8, float, SHADER_CONSTANT_242_X) -XE_GPU_REGISTER(0x43C9, float, SHADER_CONSTANT_242_Y) -XE_GPU_REGISTER(0x43CA, float, SHADER_CONSTANT_242_Z) -XE_GPU_REGISTER(0x43CB, float, SHADER_CONSTANT_242_W) -XE_GPU_REGISTER(0x43CC, float, SHADER_CONSTANT_243_X) -XE_GPU_REGISTER(0x43CD, float, SHADER_CONSTANT_243_Y) -XE_GPU_REGISTER(0x43CE, float, SHADER_CONSTANT_243_Z) -XE_GPU_REGISTER(0x43CF, float, SHADER_CONSTANT_243_W) -XE_GPU_REGISTER(0x43D0, float, SHADER_CONSTANT_244_X) -XE_GPU_REGISTER(0x43D1, float, SHADER_CONSTANT_244_Y) -XE_GPU_REGISTER(0x43D2, float, SHADER_CONSTANT_244_Z) -XE_GPU_REGISTER(0x43D3, float, SHADER_CONSTANT_244_W) -XE_GPU_REGISTER(0x43D4, float, SHADER_CONSTANT_245_X) -XE_GPU_REGISTER(0x43D5, float, SHADER_CONSTANT_245_Y) -XE_GPU_REGISTER(0x43D6, float, SHADER_CONSTANT_245_Z) -XE_GPU_REGISTER(0x43D7, float, SHADER_CONSTANT_245_W) -XE_GPU_REGISTER(0x43D8, float, SHADER_CONSTANT_246_X) -XE_GPU_REGISTER(0x43D9, float, SHADER_CONSTANT_246_Y) -XE_GPU_REGISTER(0x43DA, float, SHADER_CONSTANT_246_Z) -XE_GPU_REGISTER(0x43DB, float, SHADER_CONSTANT_246_W) -XE_GPU_REGISTER(0x43DC, float, SHADER_CONSTANT_247_X) -XE_GPU_REGISTER(0x43DD, float, SHADER_CONSTANT_247_Y) -XE_GPU_REGISTER(0x43DE, float, SHADER_CONSTANT_247_Z) -XE_GPU_REGISTER(0x43DF, float, SHADER_CONSTANT_247_W) -XE_GPU_REGISTER(0x43E0, float, SHADER_CONSTANT_248_X) -XE_GPU_REGISTER(0x43E1, float, SHADER_CONSTANT_248_Y) -XE_GPU_REGISTER(0x43E2, float, SHADER_CONSTANT_248_Z) -XE_GPU_REGISTER(0x43E3, float, SHADER_CONSTANT_248_W) -XE_GPU_REGISTER(0x43E4, float, SHADER_CONSTANT_249_X) -XE_GPU_REGISTER(0x43E5, float, SHADER_CONSTANT_249_Y) -XE_GPU_REGISTER(0x43E6, float, SHADER_CONSTANT_249_Z) -XE_GPU_REGISTER(0x43E7, float, SHADER_CONSTANT_249_W) -XE_GPU_REGISTER(0x43E8, float, SHADER_CONSTANT_250_X) -XE_GPU_REGISTER(0x43E9, float, SHADER_CONSTANT_250_Y) -XE_GPU_REGISTER(0x43EA, float, SHADER_CONSTANT_250_Z) -XE_GPU_REGISTER(0x43EB, float, SHADER_CONSTANT_250_W) -XE_GPU_REGISTER(0x43EC, float, SHADER_CONSTANT_251_X) -XE_GPU_REGISTER(0x43ED, float, SHADER_CONSTANT_251_Y) -XE_GPU_REGISTER(0x43EE, float, SHADER_CONSTANT_251_Z) -XE_GPU_REGISTER(0x43EF, float, SHADER_CONSTANT_251_W) -XE_GPU_REGISTER(0x43F0, float, SHADER_CONSTANT_252_X) -XE_GPU_REGISTER(0x43F1, float, SHADER_CONSTANT_252_Y) -XE_GPU_REGISTER(0x43F2, float, SHADER_CONSTANT_252_Z) -XE_GPU_REGISTER(0x43F3, float, SHADER_CONSTANT_252_W) -XE_GPU_REGISTER(0x43F4, float, SHADER_CONSTANT_253_X) -XE_GPU_REGISTER(0x43F5, float, SHADER_CONSTANT_253_Y) -XE_GPU_REGISTER(0x43F6, float, SHADER_CONSTANT_253_Z) -XE_GPU_REGISTER(0x43F7, float, SHADER_CONSTANT_253_W) -XE_GPU_REGISTER(0x43F8, float, SHADER_CONSTANT_254_X) -XE_GPU_REGISTER(0x43F9, float, SHADER_CONSTANT_254_Y) -XE_GPU_REGISTER(0x43FA, float, SHADER_CONSTANT_254_Z) -XE_GPU_REGISTER(0x43FB, float, SHADER_CONSTANT_254_W) -XE_GPU_REGISTER(0x43FC, float, SHADER_CONSTANT_255_X) -XE_GPU_REGISTER(0x43FD, float, SHADER_CONSTANT_255_Y) -XE_GPU_REGISTER(0x43FE, float, SHADER_CONSTANT_255_Z) -XE_GPU_REGISTER(0x43FF, float, SHADER_CONSTANT_255_W) -XE_GPU_REGISTER(0x4400, float, SHADER_CONSTANT_256_X) -XE_GPU_REGISTER(0x4401, float, SHADER_CONSTANT_256_Y) -XE_GPU_REGISTER(0x4402, float, SHADER_CONSTANT_256_Z) -XE_GPU_REGISTER(0x4403, float, SHADER_CONSTANT_256_W) -XE_GPU_REGISTER(0x4404, float, SHADER_CONSTANT_257_X) -XE_GPU_REGISTER(0x4405, float, SHADER_CONSTANT_257_Y) -XE_GPU_REGISTER(0x4406, float, SHADER_CONSTANT_257_Z) -XE_GPU_REGISTER(0x4407, float, SHADER_CONSTANT_257_W) -XE_GPU_REGISTER(0x4408, float, SHADER_CONSTANT_258_X) -XE_GPU_REGISTER(0x4409, float, SHADER_CONSTANT_258_Y) -XE_GPU_REGISTER(0x440A, float, SHADER_CONSTANT_258_Z) -XE_GPU_REGISTER(0x440B, float, SHADER_CONSTANT_258_W) -XE_GPU_REGISTER(0x440C, float, SHADER_CONSTANT_259_X) -XE_GPU_REGISTER(0x440D, float, SHADER_CONSTANT_259_Y) -XE_GPU_REGISTER(0x440E, float, SHADER_CONSTANT_259_Z) -XE_GPU_REGISTER(0x440F, float, SHADER_CONSTANT_259_W) -XE_GPU_REGISTER(0x4410, float, SHADER_CONSTANT_260_X) -XE_GPU_REGISTER(0x4411, float, SHADER_CONSTANT_260_Y) -XE_GPU_REGISTER(0x4412, float, SHADER_CONSTANT_260_Z) -XE_GPU_REGISTER(0x4413, float, SHADER_CONSTANT_260_W) -XE_GPU_REGISTER(0x4414, float, SHADER_CONSTANT_261_X) -XE_GPU_REGISTER(0x4415, float, SHADER_CONSTANT_261_Y) -XE_GPU_REGISTER(0x4416, float, SHADER_CONSTANT_261_Z) -XE_GPU_REGISTER(0x4417, float, SHADER_CONSTANT_261_W) -XE_GPU_REGISTER(0x4418, float, SHADER_CONSTANT_262_X) -XE_GPU_REGISTER(0x4419, float, SHADER_CONSTANT_262_Y) -XE_GPU_REGISTER(0x441A, float, SHADER_CONSTANT_262_Z) -XE_GPU_REGISTER(0x441B, float, SHADER_CONSTANT_262_W) -XE_GPU_REGISTER(0x441C, float, SHADER_CONSTANT_263_X) -XE_GPU_REGISTER(0x441D, float, SHADER_CONSTANT_263_Y) -XE_GPU_REGISTER(0x441E, float, SHADER_CONSTANT_263_Z) -XE_GPU_REGISTER(0x441F, float, SHADER_CONSTANT_263_W) -XE_GPU_REGISTER(0x4420, float, SHADER_CONSTANT_264_X) -XE_GPU_REGISTER(0x4421, float, SHADER_CONSTANT_264_Y) -XE_GPU_REGISTER(0x4422, float, SHADER_CONSTANT_264_Z) -XE_GPU_REGISTER(0x4423, float, SHADER_CONSTANT_264_W) -XE_GPU_REGISTER(0x4424, float, SHADER_CONSTANT_265_X) -XE_GPU_REGISTER(0x4425, float, SHADER_CONSTANT_265_Y) -XE_GPU_REGISTER(0x4426, float, SHADER_CONSTANT_265_Z) -XE_GPU_REGISTER(0x4427, float, SHADER_CONSTANT_265_W) -XE_GPU_REGISTER(0x4428, float, SHADER_CONSTANT_266_X) -XE_GPU_REGISTER(0x4429, float, SHADER_CONSTANT_266_Y) -XE_GPU_REGISTER(0x442A, float, SHADER_CONSTANT_266_Z) -XE_GPU_REGISTER(0x442B, float, SHADER_CONSTANT_266_W) -XE_GPU_REGISTER(0x442C, float, SHADER_CONSTANT_267_X) -XE_GPU_REGISTER(0x442D, float, SHADER_CONSTANT_267_Y) -XE_GPU_REGISTER(0x442E, float, SHADER_CONSTANT_267_Z) -XE_GPU_REGISTER(0x442F, float, SHADER_CONSTANT_267_W) -XE_GPU_REGISTER(0x4430, float, SHADER_CONSTANT_268_X) -XE_GPU_REGISTER(0x4431, float, SHADER_CONSTANT_268_Y) -XE_GPU_REGISTER(0x4432, float, SHADER_CONSTANT_268_Z) -XE_GPU_REGISTER(0x4433, float, SHADER_CONSTANT_268_W) -XE_GPU_REGISTER(0x4434, float, SHADER_CONSTANT_269_X) -XE_GPU_REGISTER(0x4435, float, SHADER_CONSTANT_269_Y) -XE_GPU_REGISTER(0x4436, float, SHADER_CONSTANT_269_Z) -XE_GPU_REGISTER(0x4437, float, SHADER_CONSTANT_269_W) -XE_GPU_REGISTER(0x4438, float, SHADER_CONSTANT_270_X) -XE_GPU_REGISTER(0x4439, float, SHADER_CONSTANT_270_Y) -XE_GPU_REGISTER(0x443A, float, SHADER_CONSTANT_270_Z) -XE_GPU_REGISTER(0x443B, float, SHADER_CONSTANT_270_W) -XE_GPU_REGISTER(0x443C, float, SHADER_CONSTANT_271_X) -XE_GPU_REGISTER(0x443D, float, SHADER_CONSTANT_271_Y) -XE_GPU_REGISTER(0x443E, float, SHADER_CONSTANT_271_Z) -XE_GPU_REGISTER(0x443F, float, SHADER_CONSTANT_271_W) -XE_GPU_REGISTER(0x4440, float, SHADER_CONSTANT_272_X) -XE_GPU_REGISTER(0x4441, float, SHADER_CONSTANT_272_Y) -XE_GPU_REGISTER(0x4442, float, SHADER_CONSTANT_272_Z) -XE_GPU_REGISTER(0x4443, float, SHADER_CONSTANT_272_W) -XE_GPU_REGISTER(0x4444, float, SHADER_CONSTANT_273_X) -XE_GPU_REGISTER(0x4445, float, SHADER_CONSTANT_273_Y) -XE_GPU_REGISTER(0x4446, float, SHADER_CONSTANT_273_Z) -XE_GPU_REGISTER(0x4447, float, SHADER_CONSTANT_273_W) -XE_GPU_REGISTER(0x4448, float, SHADER_CONSTANT_274_X) -XE_GPU_REGISTER(0x4449, float, SHADER_CONSTANT_274_Y) -XE_GPU_REGISTER(0x444A, float, SHADER_CONSTANT_274_Z) -XE_GPU_REGISTER(0x444B, float, SHADER_CONSTANT_274_W) -XE_GPU_REGISTER(0x444C, float, SHADER_CONSTANT_275_X) -XE_GPU_REGISTER(0x444D, float, SHADER_CONSTANT_275_Y) -XE_GPU_REGISTER(0x444E, float, SHADER_CONSTANT_275_Z) -XE_GPU_REGISTER(0x444F, float, SHADER_CONSTANT_275_W) -XE_GPU_REGISTER(0x4450, float, SHADER_CONSTANT_276_X) -XE_GPU_REGISTER(0x4451, float, SHADER_CONSTANT_276_Y) -XE_GPU_REGISTER(0x4452, float, SHADER_CONSTANT_276_Z) -XE_GPU_REGISTER(0x4453, float, SHADER_CONSTANT_276_W) -XE_GPU_REGISTER(0x4454, float, SHADER_CONSTANT_277_X) -XE_GPU_REGISTER(0x4455, float, SHADER_CONSTANT_277_Y) -XE_GPU_REGISTER(0x4456, float, SHADER_CONSTANT_277_Z) -XE_GPU_REGISTER(0x4457, float, SHADER_CONSTANT_277_W) -XE_GPU_REGISTER(0x4458, float, SHADER_CONSTANT_278_X) -XE_GPU_REGISTER(0x4459, float, SHADER_CONSTANT_278_Y) -XE_GPU_REGISTER(0x445A, float, SHADER_CONSTANT_278_Z) -XE_GPU_REGISTER(0x445B, float, SHADER_CONSTANT_278_W) -XE_GPU_REGISTER(0x445C, float, SHADER_CONSTANT_279_X) -XE_GPU_REGISTER(0x445D, float, SHADER_CONSTANT_279_Y) -XE_GPU_REGISTER(0x445E, float, SHADER_CONSTANT_279_Z) -XE_GPU_REGISTER(0x445F, float, SHADER_CONSTANT_279_W) -XE_GPU_REGISTER(0x4460, float, SHADER_CONSTANT_280_X) -XE_GPU_REGISTER(0x4461, float, SHADER_CONSTANT_280_Y) -XE_GPU_REGISTER(0x4462, float, SHADER_CONSTANT_280_Z) -XE_GPU_REGISTER(0x4463, float, SHADER_CONSTANT_280_W) -XE_GPU_REGISTER(0x4464, float, SHADER_CONSTANT_281_X) -XE_GPU_REGISTER(0x4465, float, SHADER_CONSTANT_281_Y) -XE_GPU_REGISTER(0x4466, float, SHADER_CONSTANT_281_Z) -XE_GPU_REGISTER(0x4467, float, SHADER_CONSTANT_281_W) -XE_GPU_REGISTER(0x4468, float, SHADER_CONSTANT_282_X) -XE_GPU_REGISTER(0x4469, float, SHADER_CONSTANT_282_Y) -XE_GPU_REGISTER(0x446A, float, SHADER_CONSTANT_282_Z) -XE_GPU_REGISTER(0x446B, float, SHADER_CONSTANT_282_W) -XE_GPU_REGISTER(0x446C, float, SHADER_CONSTANT_283_X) -XE_GPU_REGISTER(0x446D, float, SHADER_CONSTANT_283_Y) -XE_GPU_REGISTER(0x446E, float, SHADER_CONSTANT_283_Z) -XE_GPU_REGISTER(0x446F, float, SHADER_CONSTANT_283_W) -XE_GPU_REGISTER(0x4470, float, SHADER_CONSTANT_284_X) -XE_GPU_REGISTER(0x4471, float, SHADER_CONSTANT_284_Y) -XE_GPU_REGISTER(0x4472, float, SHADER_CONSTANT_284_Z) -XE_GPU_REGISTER(0x4473, float, SHADER_CONSTANT_284_W) -XE_GPU_REGISTER(0x4474, float, SHADER_CONSTANT_285_X) -XE_GPU_REGISTER(0x4475, float, SHADER_CONSTANT_285_Y) -XE_GPU_REGISTER(0x4476, float, SHADER_CONSTANT_285_Z) -XE_GPU_REGISTER(0x4477, float, SHADER_CONSTANT_285_W) -XE_GPU_REGISTER(0x4478, float, SHADER_CONSTANT_286_X) -XE_GPU_REGISTER(0x4479, float, SHADER_CONSTANT_286_Y) -XE_GPU_REGISTER(0x447A, float, SHADER_CONSTANT_286_Z) -XE_GPU_REGISTER(0x447B, float, SHADER_CONSTANT_286_W) -XE_GPU_REGISTER(0x447C, float, SHADER_CONSTANT_287_X) -XE_GPU_REGISTER(0x447D, float, SHADER_CONSTANT_287_Y) -XE_GPU_REGISTER(0x447E, float, SHADER_CONSTANT_287_Z) -XE_GPU_REGISTER(0x447F, float, SHADER_CONSTANT_287_W) -XE_GPU_REGISTER(0x4480, float, SHADER_CONSTANT_288_X) -XE_GPU_REGISTER(0x4481, float, SHADER_CONSTANT_288_Y) -XE_GPU_REGISTER(0x4482, float, SHADER_CONSTANT_288_Z) -XE_GPU_REGISTER(0x4483, float, SHADER_CONSTANT_288_W) -XE_GPU_REGISTER(0x4484, float, SHADER_CONSTANT_289_X) -XE_GPU_REGISTER(0x4485, float, SHADER_CONSTANT_289_Y) -XE_GPU_REGISTER(0x4486, float, SHADER_CONSTANT_289_Z) -XE_GPU_REGISTER(0x4487, float, SHADER_CONSTANT_289_W) -XE_GPU_REGISTER(0x4488, float, SHADER_CONSTANT_290_X) -XE_GPU_REGISTER(0x4489, float, SHADER_CONSTANT_290_Y) -XE_GPU_REGISTER(0x448A, float, SHADER_CONSTANT_290_Z) -XE_GPU_REGISTER(0x448B, float, SHADER_CONSTANT_290_W) -XE_GPU_REGISTER(0x448C, float, SHADER_CONSTANT_291_X) -XE_GPU_REGISTER(0x448D, float, SHADER_CONSTANT_291_Y) -XE_GPU_REGISTER(0x448E, float, SHADER_CONSTANT_291_Z) -XE_GPU_REGISTER(0x448F, float, SHADER_CONSTANT_291_W) -XE_GPU_REGISTER(0x4490, float, SHADER_CONSTANT_292_X) -XE_GPU_REGISTER(0x4491, float, SHADER_CONSTANT_292_Y) -XE_GPU_REGISTER(0x4492, float, SHADER_CONSTANT_292_Z) -XE_GPU_REGISTER(0x4493, float, SHADER_CONSTANT_292_W) -XE_GPU_REGISTER(0x4494, float, SHADER_CONSTANT_293_X) -XE_GPU_REGISTER(0x4495, float, SHADER_CONSTANT_293_Y) -XE_GPU_REGISTER(0x4496, float, SHADER_CONSTANT_293_Z) -XE_GPU_REGISTER(0x4497, float, SHADER_CONSTANT_293_W) -XE_GPU_REGISTER(0x4498, float, SHADER_CONSTANT_294_X) -XE_GPU_REGISTER(0x4499, float, SHADER_CONSTANT_294_Y) -XE_GPU_REGISTER(0x449A, float, SHADER_CONSTANT_294_Z) -XE_GPU_REGISTER(0x449B, float, SHADER_CONSTANT_294_W) -XE_GPU_REGISTER(0x449C, float, SHADER_CONSTANT_295_X) -XE_GPU_REGISTER(0x449D, float, SHADER_CONSTANT_295_Y) -XE_GPU_REGISTER(0x449E, float, SHADER_CONSTANT_295_Z) -XE_GPU_REGISTER(0x449F, float, SHADER_CONSTANT_295_W) -XE_GPU_REGISTER(0x44A0, float, SHADER_CONSTANT_296_X) -XE_GPU_REGISTER(0x44A1, float, SHADER_CONSTANT_296_Y) -XE_GPU_REGISTER(0x44A2, float, SHADER_CONSTANT_296_Z) -XE_GPU_REGISTER(0x44A3, float, SHADER_CONSTANT_296_W) -XE_GPU_REGISTER(0x44A4, float, SHADER_CONSTANT_297_X) -XE_GPU_REGISTER(0x44A5, float, SHADER_CONSTANT_297_Y) -XE_GPU_REGISTER(0x44A6, float, SHADER_CONSTANT_297_Z) -XE_GPU_REGISTER(0x44A7, float, SHADER_CONSTANT_297_W) -XE_GPU_REGISTER(0x44A8, float, SHADER_CONSTANT_298_X) -XE_GPU_REGISTER(0x44A9, float, SHADER_CONSTANT_298_Y) -XE_GPU_REGISTER(0x44AA, float, SHADER_CONSTANT_298_Z) -XE_GPU_REGISTER(0x44AB, float, SHADER_CONSTANT_298_W) -XE_GPU_REGISTER(0x44AC, float, SHADER_CONSTANT_299_X) -XE_GPU_REGISTER(0x44AD, float, SHADER_CONSTANT_299_Y) -XE_GPU_REGISTER(0x44AE, float, SHADER_CONSTANT_299_Z) -XE_GPU_REGISTER(0x44AF, float, SHADER_CONSTANT_299_W) -XE_GPU_REGISTER(0x44B0, float, SHADER_CONSTANT_300_X) -XE_GPU_REGISTER(0x44B1, float, SHADER_CONSTANT_300_Y) -XE_GPU_REGISTER(0x44B2, float, SHADER_CONSTANT_300_Z) -XE_GPU_REGISTER(0x44B3, float, SHADER_CONSTANT_300_W) -XE_GPU_REGISTER(0x44B4, float, SHADER_CONSTANT_301_X) -XE_GPU_REGISTER(0x44B5, float, SHADER_CONSTANT_301_Y) -XE_GPU_REGISTER(0x44B6, float, SHADER_CONSTANT_301_Z) -XE_GPU_REGISTER(0x44B7, float, SHADER_CONSTANT_301_W) -XE_GPU_REGISTER(0x44B8, float, SHADER_CONSTANT_302_X) -XE_GPU_REGISTER(0x44B9, float, SHADER_CONSTANT_302_Y) -XE_GPU_REGISTER(0x44BA, float, SHADER_CONSTANT_302_Z) -XE_GPU_REGISTER(0x44BB, float, SHADER_CONSTANT_302_W) -XE_GPU_REGISTER(0x44BC, float, SHADER_CONSTANT_303_X) -XE_GPU_REGISTER(0x44BD, float, SHADER_CONSTANT_303_Y) -XE_GPU_REGISTER(0x44BE, float, SHADER_CONSTANT_303_Z) -XE_GPU_REGISTER(0x44BF, float, SHADER_CONSTANT_303_W) -XE_GPU_REGISTER(0x44C0, float, SHADER_CONSTANT_304_X) -XE_GPU_REGISTER(0x44C1, float, SHADER_CONSTANT_304_Y) -XE_GPU_REGISTER(0x44C2, float, SHADER_CONSTANT_304_Z) -XE_GPU_REGISTER(0x44C3, float, SHADER_CONSTANT_304_W) -XE_GPU_REGISTER(0x44C4, float, SHADER_CONSTANT_305_X) -XE_GPU_REGISTER(0x44C5, float, SHADER_CONSTANT_305_Y) -XE_GPU_REGISTER(0x44C6, float, SHADER_CONSTANT_305_Z) -XE_GPU_REGISTER(0x44C7, float, SHADER_CONSTANT_305_W) -XE_GPU_REGISTER(0x44C8, float, SHADER_CONSTANT_306_X) -XE_GPU_REGISTER(0x44C9, float, SHADER_CONSTANT_306_Y) -XE_GPU_REGISTER(0x44CA, float, SHADER_CONSTANT_306_Z) -XE_GPU_REGISTER(0x44CB, float, SHADER_CONSTANT_306_W) -XE_GPU_REGISTER(0x44CC, float, SHADER_CONSTANT_307_X) -XE_GPU_REGISTER(0x44CD, float, SHADER_CONSTANT_307_Y) -XE_GPU_REGISTER(0x44CE, float, SHADER_CONSTANT_307_Z) -XE_GPU_REGISTER(0x44CF, float, SHADER_CONSTANT_307_W) -XE_GPU_REGISTER(0x44D0, float, SHADER_CONSTANT_308_X) -XE_GPU_REGISTER(0x44D1, float, SHADER_CONSTANT_308_Y) -XE_GPU_REGISTER(0x44D2, float, SHADER_CONSTANT_308_Z) -XE_GPU_REGISTER(0x44D3, float, SHADER_CONSTANT_308_W) -XE_GPU_REGISTER(0x44D4, float, SHADER_CONSTANT_309_X) -XE_GPU_REGISTER(0x44D5, float, SHADER_CONSTANT_309_Y) -XE_GPU_REGISTER(0x44D6, float, SHADER_CONSTANT_309_Z) -XE_GPU_REGISTER(0x44D7, float, SHADER_CONSTANT_309_W) -XE_GPU_REGISTER(0x44D8, float, SHADER_CONSTANT_310_X) -XE_GPU_REGISTER(0x44D9, float, SHADER_CONSTANT_310_Y) -XE_GPU_REGISTER(0x44DA, float, SHADER_CONSTANT_310_Z) -XE_GPU_REGISTER(0x44DB, float, SHADER_CONSTANT_310_W) -XE_GPU_REGISTER(0x44DC, float, SHADER_CONSTANT_311_X) -XE_GPU_REGISTER(0x44DD, float, SHADER_CONSTANT_311_Y) -XE_GPU_REGISTER(0x44DE, float, SHADER_CONSTANT_311_Z) -XE_GPU_REGISTER(0x44DF, float, SHADER_CONSTANT_311_W) -XE_GPU_REGISTER(0x44E0, float, SHADER_CONSTANT_312_X) -XE_GPU_REGISTER(0x44E1, float, SHADER_CONSTANT_312_Y) -XE_GPU_REGISTER(0x44E2, float, SHADER_CONSTANT_312_Z) -XE_GPU_REGISTER(0x44E3, float, SHADER_CONSTANT_312_W) -XE_GPU_REGISTER(0x44E4, float, SHADER_CONSTANT_313_X) -XE_GPU_REGISTER(0x44E5, float, SHADER_CONSTANT_313_Y) -XE_GPU_REGISTER(0x44E6, float, SHADER_CONSTANT_313_Z) -XE_GPU_REGISTER(0x44E7, float, SHADER_CONSTANT_313_W) -XE_GPU_REGISTER(0x44E8, float, SHADER_CONSTANT_314_X) -XE_GPU_REGISTER(0x44E9, float, SHADER_CONSTANT_314_Y) -XE_GPU_REGISTER(0x44EA, float, SHADER_CONSTANT_314_Z) -XE_GPU_REGISTER(0x44EB, float, SHADER_CONSTANT_314_W) -XE_GPU_REGISTER(0x44EC, float, SHADER_CONSTANT_315_X) -XE_GPU_REGISTER(0x44ED, float, SHADER_CONSTANT_315_Y) -XE_GPU_REGISTER(0x44EE, float, SHADER_CONSTANT_315_Z) -XE_GPU_REGISTER(0x44EF, float, SHADER_CONSTANT_315_W) -XE_GPU_REGISTER(0x44F0, float, SHADER_CONSTANT_316_X) -XE_GPU_REGISTER(0x44F1, float, SHADER_CONSTANT_316_Y) -XE_GPU_REGISTER(0x44F2, float, SHADER_CONSTANT_316_Z) -XE_GPU_REGISTER(0x44F3, float, SHADER_CONSTANT_316_W) -XE_GPU_REGISTER(0x44F4, float, SHADER_CONSTANT_317_X) -XE_GPU_REGISTER(0x44F5, float, SHADER_CONSTANT_317_Y) -XE_GPU_REGISTER(0x44F6, float, SHADER_CONSTANT_317_Z) -XE_GPU_REGISTER(0x44F7, float, SHADER_CONSTANT_317_W) -XE_GPU_REGISTER(0x44F8, float, SHADER_CONSTANT_318_X) -XE_GPU_REGISTER(0x44F9, float, SHADER_CONSTANT_318_Y) -XE_GPU_REGISTER(0x44FA, float, SHADER_CONSTANT_318_Z) -XE_GPU_REGISTER(0x44FB, float, SHADER_CONSTANT_318_W) -XE_GPU_REGISTER(0x44FC, float, SHADER_CONSTANT_319_X) -XE_GPU_REGISTER(0x44FD, float, SHADER_CONSTANT_319_Y) -XE_GPU_REGISTER(0x44FE, float, SHADER_CONSTANT_319_Z) -XE_GPU_REGISTER(0x44FF, float, SHADER_CONSTANT_319_W) -XE_GPU_REGISTER(0x4500, float, SHADER_CONSTANT_320_X) -XE_GPU_REGISTER(0x4501, float, SHADER_CONSTANT_320_Y) -XE_GPU_REGISTER(0x4502, float, SHADER_CONSTANT_320_Z) -XE_GPU_REGISTER(0x4503, float, SHADER_CONSTANT_320_W) -XE_GPU_REGISTER(0x4504, float, SHADER_CONSTANT_321_X) -XE_GPU_REGISTER(0x4505, float, SHADER_CONSTANT_321_Y) -XE_GPU_REGISTER(0x4506, float, SHADER_CONSTANT_321_Z) -XE_GPU_REGISTER(0x4507, float, SHADER_CONSTANT_321_W) -XE_GPU_REGISTER(0x4508, float, SHADER_CONSTANT_322_X) -XE_GPU_REGISTER(0x4509, float, SHADER_CONSTANT_322_Y) -XE_GPU_REGISTER(0x450A, float, SHADER_CONSTANT_322_Z) -XE_GPU_REGISTER(0x450B, float, SHADER_CONSTANT_322_W) -XE_GPU_REGISTER(0x450C, float, SHADER_CONSTANT_323_X) -XE_GPU_REGISTER(0x450D, float, SHADER_CONSTANT_323_Y) -XE_GPU_REGISTER(0x450E, float, SHADER_CONSTANT_323_Z) -XE_GPU_REGISTER(0x450F, float, SHADER_CONSTANT_323_W) -XE_GPU_REGISTER(0x4510, float, SHADER_CONSTANT_324_X) -XE_GPU_REGISTER(0x4511, float, SHADER_CONSTANT_324_Y) -XE_GPU_REGISTER(0x4512, float, SHADER_CONSTANT_324_Z) -XE_GPU_REGISTER(0x4513, float, SHADER_CONSTANT_324_W) -XE_GPU_REGISTER(0x4514, float, SHADER_CONSTANT_325_X) -XE_GPU_REGISTER(0x4515, float, SHADER_CONSTANT_325_Y) -XE_GPU_REGISTER(0x4516, float, SHADER_CONSTANT_325_Z) -XE_GPU_REGISTER(0x4517, float, SHADER_CONSTANT_325_W) -XE_GPU_REGISTER(0x4518, float, SHADER_CONSTANT_326_X) -XE_GPU_REGISTER(0x4519, float, SHADER_CONSTANT_326_Y) -XE_GPU_REGISTER(0x451A, float, SHADER_CONSTANT_326_Z) -XE_GPU_REGISTER(0x451B, float, SHADER_CONSTANT_326_W) -XE_GPU_REGISTER(0x451C, float, SHADER_CONSTANT_327_X) -XE_GPU_REGISTER(0x451D, float, SHADER_CONSTANT_327_Y) -XE_GPU_REGISTER(0x451E, float, SHADER_CONSTANT_327_Z) -XE_GPU_REGISTER(0x451F, float, SHADER_CONSTANT_327_W) -XE_GPU_REGISTER(0x4520, float, SHADER_CONSTANT_328_X) -XE_GPU_REGISTER(0x4521, float, SHADER_CONSTANT_328_Y) -XE_GPU_REGISTER(0x4522, float, SHADER_CONSTANT_328_Z) -XE_GPU_REGISTER(0x4523, float, SHADER_CONSTANT_328_W) -XE_GPU_REGISTER(0x4524, float, SHADER_CONSTANT_329_X) -XE_GPU_REGISTER(0x4525, float, SHADER_CONSTANT_329_Y) -XE_GPU_REGISTER(0x4526, float, SHADER_CONSTANT_329_Z) -XE_GPU_REGISTER(0x4527, float, SHADER_CONSTANT_329_W) -XE_GPU_REGISTER(0x4528, float, SHADER_CONSTANT_330_X) -XE_GPU_REGISTER(0x4529, float, SHADER_CONSTANT_330_Y) -XE_GPU_REGISTER(0x452A, float, SHADER_CONSTANT_330_Z) -XE_GPU_REGISTER(0x452B, float, SHADER_CONSTANT_330_W) -XE_GPU_REGISTER(0x452C, float, SHADER_CONSTANT_331_X) -XE_GPU_REGISTER(0x452D, float, SHADER_CONSTANT_331_Y) -XE_GPU_REGISTER(0x452E, float, SHADER_CONSTANT_331_Z) -XE_GPU_REGISTER(0x452F, float, SHADER_CONSTANT_331_W) -XE_GPU_REGISTER(0x4530, float, SHADER_CONSTANT_332_X) -XE_GPU_REGISTER(0x4531, float, SHADER_CONSTANT_332_Y) -XE_GPU_REGISTER(0x4532, float, SHADER_CONSTANT_332_Z) -XE_GPU_REGISTER(0x4533, float, SHADER_CONSTANT_332_W) -XE_GPU_REGISTER(0x4534, float, SHADER_CONSTANT_333_X) -XE_GPU_REGISTER(0x4535, float, SHADER_CONSTANT_333_Y) -XE_GPU_REGISTER(0x4536, float, SHADER_CONSTANT_333_Z) -XE_GPU_REGISTER(0x4537, float, SHADER_CONSTANT_333_W) -XE_GPU_REGISTER(0x4538, float, SHADER_CONSTANT_334_X) -XE_GPU_REGISTER(0x4539, float, SHADER_CONSTANT_334_Y) -XE_GPU_REGISTER(0x453A, float, SHADER_CONSTANT_334_Z) -XE_GPU_REGISTER(0x453B, float, SHADER_CONSTANT_334_W) -XE_GPU_REGISTER(0x453C, float, SHADER_CONSTANT_335_X) -XE_GPU_REGISTER(0x453D, float, SHADER_CONSTANT_335_Y) -XE_GPU_REGISTER(0x453E, float, SHADER_CONSTANT_335_Z) -XE_GPU_REGISTER(0x453F, float, SHADER_CONSTANT_335_W) -XE_GPU_REGISTER(0x4540, float, SHADER_CONSTANT_336_X) -XE_GPU_REGISTER(0x4541, float, SHADER_CONSTANT_336_Y) -XE_GPU_REGISTER(0x4542, float, SHADER_CONSTANT_336_Z) -XE_GPU_REGISTER(0x4543, float, SHADER_CONSTANT_336_W) -XE_GPU_REGISTER(0x4544, float, SHADER_CONSTANT_337_X) -XE_GPU_REGISTER(0x4545, float, SHADER_CONSTANT_337_Y) -XE_GPU_REGISTER(0x4546, float, SHADER_CONSTANT_337_Z) -XE_GPU_REGISTER(0x4547, float, SHADER_CONSTANT_337_W) -XE_GPU_REGISTER(0x4548, float, SHADER_CONSTANT_338_X) -XE_GPU_REGISTER(0x4549, float, SHADER_CONSTANT_338_Y) -XE_GPU_REGISTER(0x454A, float, SHADER_CONSTANT_338_Z) -XE_GPU_REGISTER(0x454B, float, SHADER_CONSTANT_338_W) -XE_GPU_REGISTER(0x454C, float, SHADER_CONSTANT_339_X) -XE_GPU_REGISTER(0x454D, float, SHADER_CONSTANT_339_Y) -XE_GPU_REGISTER(0x454E, float, SHADER_CONSTANT_339_Z) -XE_GPU_REGISTER(0x454F, float, SHADER_CONSTANT_339_W) -XE_GPU_REGISTER(0x4550, float, SHADER_CONSTANT_340_X) -XE_GPU_REGISTER(0x4551, float, SHADER_CONSTANT_340_Y) -XE_GPU_REGISTER(0x4552, float, SHADER_CONSTANT_340_Z) -XE_GPU_REGISTER(0x4553, float, SHADER_CONSTANT_340_W) -XE_GPU_REGISTER(0x4554, float, SHADER_CONSTANT_341_X) -XE_GPU_REGISTER(0x4555, float, SHADER_CONSTANT_341_Y) -XE_GPU_REGISTER(0x4556, float, SHADER_CONSTANT_341_Z) -XE_GPU_REGISTER(0x4557, float, SHADER_CONSTANT_341_W) -XE_GPU_REGISTER(0x4558, float, SHADER_CONSTANT_342_X) -XE_GPU_REGISTER(0x4559, float, SHADER_CONSTANT_342_Y) -XE_GPU_REGISTER(0x455A, float, SHADER_CONSTANT_342_Z) -XE_GPU_REGISTER(0x455B, float, SHADER_CONSTANT_342_W) -XE_GPU_REGISTER(0x455C, float, SHADER_CONSTANT_343_X) -XE_GPU_REGISTER(0x455D, float, SHADER_CONSTANT_343_Y) -XE_GPU_REGISTER(0x455E, float, SHADER_CONSTANT_343_Z) -XE_GPU_REGISTER(0x455F, float, SHADER_CONSTANT_343_W) -XE_GPU_REGISTER(0x4560, float, SHADER_CONSTANT_344_X) -XE_GPU_REGISTER(0x4561, float, SHADER_CONSTANT_344_Y) -XE_GPU_REGISTER(0x4562, float, SHADER_CONSTANT_344_Z) -XE_GPU_REGISTER(0x4563, float, SHADER_CONSTANT_344_W) -XE_GPU_REGISTER(0x4564, float, SHADER_CONSTANT_345_X) -XE_GPU_REGISTER(0x4565, float, SHADER_CONSTANT_345_Y) -XE_GPU_REGISTER(0x4566, float, SHADER_CONSTANT_345_Z) -XE_GPU_REGISTER(0x4567, float, SHADER_CONSTANT_345_W) -XE_GPU_REGISTER(0x4568, float, SHADER_CONSTANT_346_X) -XE_GPU_REGISTER(0x4569, float, SHADER_CONSTANT_346_Y) -XE_GPU_REGISTER(0x456A, float, SHADER_CONSTANT_346_Z) -XE_GPU_REGISTER(0x456B, float, SHADER_CONSTANT_346_W) -XE_GPU_REGISTER(0x456C, float, SHADER_CONSTANT_347_X) -XE_GPU_REGISTER(0x456D, float, SHADER_CONSTANT_347_Y) -XE_GPU_REGISTER(0x456E, float, SHADER_CONSTANT_347_Z) -XE_GPU_REGISTER(0x456F, float, SHADER_CONSTANT_347_W) -XE_GPU_REGISTER(0x4570, float, SHADER_CONSTANT_348_X) -XE_GPU_REGISTER(0x4571, float, SHADER_CONSTANT_348_Y) -XE_GPU_REGISTER(0x4572, float, SHADER_CONSTANT_348_Z) -XE_GPU_REGISTER(0x4573, float, SHADER_CONSTANT_348_W) -XE_GPU_REGISTER(0x4574, float, SHADER_CONSTANT_349_X) -XE_GPU_REGISTER(0x4575, float, SHADER_CONSTANT_349_Y) -XE_GPU_REGISTER(0x4576, float, SHADER_CONSTANT_349_Z) -XE_GPU_REGISTER(0x4577, float, SHADER_CONSTANT_349_W) -XE_GPU_REGISTER(0x4578, float, SHADER_CONSTANT_350_X) -XE_GPU_REGISTER(0x4579, float, SHADER_CONSTANT_350_Y) -XE_GPU_REGISTER(0x457A, float, SHADER_CONSTANT_350_Z) -XE_GPU_REGISTER(0x457B, float, SHADER_CONSTANT_350_W) -XE_GPU_REGISTER(0x457C, float, SHADER_CONSTANT_351_X) -XE_GPU_REGISTER(0x457D, float, SHADER_CONSTANT_351_Y) -XE_GPU_REGISTER(0x457E, float, SHADER_CONSTANT_351_Z) -XE_GPU_REGISTER(0x457F, float, SHADER_CONSTANT_351_W) -XE_GPU_REGISTER(0x4580, float, SHADER_CONSTANT_352_X) -XE_GPU_REGISTER(0x4581, float, SHADER_CONSTANT_352_Y) -XE_GPU_REGISTER(0x4582, float, SHADER_CONSTANT_352_Z) -XE_GPU_REGISTER(0x4583, float, SHADER_CONSTANT_352_W) -XE_GPU_REGISTER(0x4584, float, SHADER_CONSTANT_353_X) -XE_GPU_REGISTER(0x4585, float, SHADER_CONSTANT_353_Y) -XE_GPU_REGISTER(0x4586, float, SHADER_CONSTANT_353_Z) -XE_GPU_REGISTER(0x4587, float, SHADER_CONSTANT_353_W) -XE_GPU_REGISTER(0x4588, float, SHADER_CONSTANT_354_X) -XE_GPU_REGISTER(0x4589, float, SHADER_CONSTANT_354_Y) -XE_GPU_REGISTER(0x458A, float, SHADER_CONSTANT_354_Z) -XE_GPU_REGISTER(0x458B, float, SHADER_CONSTANT_354_W) -XE_GPU_REGISTER(0x458C, float, SHADER_CONSTANT_355_X) -XE_GPU_REGISTER(0x458D, float, SHADER_CONSTANT_355_Y) -XE_GPU_REGISTER(0x458E, float, SHADER_CONSTANT_355_Z) -XE_GPU_REGISTER(0x458F, float, SHADER_CONSTANT_355_W) -XE_GPU_REGISTER(0x4590, float, SHADER_CONSTANT_356_X) -XE_GPU_REGISTER(0x4591, float, SHADER_CONSTANT_356_Y) -XE_GPU_REGISTER(0x4592, float, SHADER_CONSTANT_356_Z) -XE_GPU_REGISTER(0x4593, float, SHADER_CONSTANT_356_W) -XE_GPU_REGISTER(0x4594, float, SHADER_CONSTANT_357_X) -XE_GPU_REGISTER(0x4595, float, SHADER_CONSTANT_357_Y) -XE_GPU_REGISTER(0x4596, float, SHADER_CONSTANT_357_Z) -XE_GPU_REGISTER(0x4597, float, SHADER_CONSTANT_357_W) -XE_GPU_REGISTER(0x4598, float, SHADER_CONSTANT_358_X) -XE_GPU_REGISTER(0x4599, float, SHADER_CONSTANT_358_Y) -XE_GPU_REGISTER(0x459A, float, SHADER_CONSTANT_358_Z) -XE_GPU_REGISTER(0x459B, float, SHADER_CONSTANT_358_W) -XE_GPU_REGISTER(0x459C, float, SHADER_CONSTANT_359_X) -XE_GPU_REGISTER(0x459D, float, SHADER_CONSTANT_359_Y) -XE_GPU_REGISTER(0x459E, float, SHADER_CONSTANT_359_Z) -XE_GPU_REGISTER(0x459F, float, SHADER_CONSTANT_359_W) -XE_GPU_REGISTER(0x45A0, float, SHADER_CONSTANT_360_X) -XE_GPU_REGISTER(0x45A1, float, SHADER_CONSTANT_360_Y) -XE_GPU_REGISTER(0x45A2, float, SHADER_CONSTANT_360_Z) -XE_GPU_REGISTER(0x45A3, float, SHADER_CONSTANT_360_W) -XE_GPU_REGISTER(0x45A4, float, SHADER_CONSTANT_361_X) -XE_GPU_REGISTER(0x45A5, float, SHADER_CONSTANT_361_Y) -XE_GPU_REGISTER(0x45A6, float, SHADER_CONSTANT_361_Z) -XE_GPU_REGISTER(0x45A7, float, SHADER_CONSTANT_361_W) -XE_GPU_REGISTER(0x45A8, float, SHADER_CONSTANT_362_X) -XE_GPU_REGISTER(0x45A9, float, SHADER_CONSTANT_362_Y) -XE_GPU_REGISTER(0x45AA, float, SHADER_CONSTANT_362_Z) -XE_GPU_REGISTER(0x45AB, float, SHADER_CONSTANT_362_W) -XE_GPU_REGISTER(0x45AC, float, SHADER_CONSTANT_363_X) -XE_GPU_REGISTER(0x45AD, float, SHADER_CONSTANT_363_Y) -XE_GPU_REGISTER(0x45AE, float, SHADER_CONSTANT_363_Z) -XE_GPU_REGISTER(0x45AF, float, SHADER_CONSTANT_363_W) -XE_GPU_REGISTER(0x45B0, float, SHADER_CONSTANT_364_X) -XE_GPU_REGISTER(0x45B1, float, SHADER_CONSTANT_364_Y) -XE_GPU_REGISTER(0x45B2, float, SHADER_CONSTANT_364_Z) -XE_GPU_REGISTER(0x45B3, float, SHADER_CONSTANT_364_W) -XE_GPU_REGISTER(0x45B4, float, SHADER_CONSTANT_365_X) -XE_GPU_REGISTER(0x45B5, float, SHADER_CONSTANT_365_Y) -XE_GPU_REGISTER(0x45B6, float, SHADER_CONSTANT_365_Z) -XE_GPU_REGISTER(0x45B7, float, SHADER_CONSTANT_365_W) -XE_GPU_REGISTER(0x45B8, float, SHADER_CONSTANT_366_X) -XE_GPU_REGISTER(0x45B9, float, SHADER_CONSTANT_366_Y) -XE_GPU_REGISTER(0x45BA, float, SHADER_CONSTANT_366_Z) -XE_GPU_REGISTER(0x45BB, float, SHADER_CONSTANT_366_W) -XE_GPU_REGISTER(0x45BC, float, SHADER_CONSTANT_367_X) -XE_GPU_REGISTER(0x45BD, float, SHADER_CONSTANT_367_Y) -XE_GPU_REGISTER(0x45BE, float, SHADER_CONSTANT_367_Z) -XE_GPU_REGISTER(0x45BF, float, SHADER_CONSTANT_367_W) -XE_GPU_REGISTER(0x45C0, float, SHADER_CONSTANT_368_X) -XE_GPU_REGISTER(0x45C1, float, SHADER_CONSTANT_368_Y) -XE_GPU_REGISTER(0x45C2, float, SHADER_CONSTANT_368_Z) -XE_GPU_REGISTER(0x45C3, float, SHADER_CONSTANT_368_W) -XE_GPU_REGISTER(0x45C4, float, SHADER_CONSTANT_369_X) -XE_GPU_REGISTER(0x45C5, float, SHADER_CONSTANT_369_Y) -XE_GPU_REGISTER(0x45C6, float, SHADER_CONSTANT_369_Z) -XE_GPU_REGISTER(0x45C7, float, SHADER_CONSTANT_369_W) -XE_GPU_REGISTER(0x45C8, float, SHADER_CONSTANT_370_X) -XE_GPU_REGISTER(0x45C9, float, SHADER_CONSTANT_370_Y) -XE_GPU_REGISTER(0x45CA, float, SHADER_CONSTANT_370_Z) -XE_GPU_REGISTER(0x45CB, float, SHADER_CONSTANT_370_W) -XE_GPU_REGISTER(0x45CC, float, SHADER_CONSTANT_371_X) -XE_GPU_REGISTER(0x45CD, float, SHADER_CONSTANT_371_Y) -XE_GPU_REGISTER(0x45CE, float, SHADER_CONSTANT_371_Z) -XE_GPU_REGISTER(0x45CF, float, SHADER_CONSTANT_371_W) -XE_GPU_REGISTER(0x45D0, float, SHADER_CONSTANT_372_X) -XE_GPU_REGISTER(0x45D1, float, SHADER_CONSTANT_372_Y) -XE_GPU_REGISTER(0x45D2, float, SHADER_CONSTANT_372_Z) -XE_GPU_REGISTER(0x45D3, float, SHADER_CONSTANT_372_W) -XE_GPU_REGISTER(0x45D4, float, SHADER_CONSTANT_373_X) -XE_GPU_REGISTER(0x45D5, float, SHADER_CONSTANT_373_Y) -XE_GPU_REGISTER(0x45D6, float, SHADER_CONSTANT_373_Z) -XE_GPU_REGISTER(0x45D7, float, SHADER_CONSTANT_373_W) -XE_GPU_REGISTER(0x45D8, float, SHADER_CONSTANT_374_X) -XE_GPU_REGISTER(0x45D9, float, SHADER_CONSTANT_374_Y) -XE_GPU_REGISTER(0x45DA, float, SHADER_CONSTANT_374_Z) -XE_GPU_REGISTER(0x45DB, float, SHADER_CONSTANT_374_W) -XE_GPU_REGISTER(0x45DC, float, SHADER_CONSTANT_375_X) -XE_GPU_REGISTER(0x45DD, float, SHADER_CONSTANT_375_Y) -XE_GPU_REGISTER(0x45DE, float, SHADER_CONSTANT_375_Z) -XE_GPU_REGISTER(0x45DF, float, SHADER_CONSTANT_375_W) -XE_GPU_REGISTER(0x45E0, float, SHADER_CONSTANT_376_X) -XE_GPU_REGISTER(0x45E1, float, SHADER_CONSTANT_376_Y) -XE_GPU_REGISTER(0x45E2, float, SHADER_CONSTANT_376_Z) -XE_GPU_REGISTER(0x45E3, float, SHADER_CONSTANT_376_W) -XE_GPU_REGISTER(0x45E4, float, SHADER_CONSTANT_377_X) -XE_GPU_REGISTER(0x45E5, float, SHADER_CONSTANT_377_Y) -XE_GPU_REGISTER(0x45E6, float, SHADER_CONSTANT_377_Z) -XE_GPU_REGISTER(0x45E7, float, SHADER_CONSTANT_377_W) -XE_GPU_REGISTER(0x45E8, float, SHADER_CONSTANT_378_X) -XE_GPU_REGISTER(0x45E9, float, SHADER_CONSTANT_378_Y) -XE_GPU_REGISTER(0x45EA, float, SHADER_CONSTANT_378_Z) -XE_GPU_REGISTER(0x45EB, float, SHADER_CONSTANT_378_W) -XE_GPU_REGISTER(0x45EC, float, SHADER_CONSTANT_379_X) -XE_GPU_REGISTER(0x45ED, float, SHADER_CONSTANT_379_Y) -XE_GPU_REGISTER(0x45EE, float, SHADER_CONSTANT_379_Z) -XE_GPU_REGISTER(0x45EF, float, SHADER_CONSTANT_379_W) -XE_GPU_REGISTER(0x45F0, float, SHADER_CONSTANT_380_X) -XE_GPU_REGISTER(0x45F1, float, SHADER_CONSTANT_380_Y) -XE_GPU_REGISTER(0x45F2, float, SHADER_CONSTANT_380_Z) -XE_GPU_REGISTER(0x45F3, float, SHADER_CONSTANT_380_W) -XE_GPU_REGISTER(0x45F4, float, SHADER_CONSTANT_381_X) -XE_GPU_REGISTER(0x45F5, float, SHADER_CONSTANT_381_Y) -XE_GPU_REGISTER(0x45F6, float, SHADER_CONSTANT_381_Z) -XE_GPU_REGISTER(0x45F7, float, SHADER_CONSTANT_381_W) -XE_GPU_REGISTER(0x45F8, float, SHADER_CONSTANT_382_X) -XE_GPU_REGISTER(0x45F9, float, SHADER_CONSTANT_382_Y) -XE_GPU_REGISTER(0x45FA, float, SHADER_CONSTANT_382_Z) -XE_GPU_REGISTER(0x45FB, float, SHADER_CONSTANT_382_W) -XE_GPU_REGISTER(0x45FC, float, SHADER_CONSTANT_383_X) -XE_GPU_REGISTER(0x45FD, float, SHADER_CONSTANT_383_Y) -XE_GPU_REGISTER(0x45FE, float, SHADER_CONSTANT_383_Z) -XE_GPU_REGISTER(0x45FF, float, SHADER_CONSTANT_383_W) -XE_GPU_REGISTER(0x4600, float, SHADER_CONSTANT_384_X) -XE_GPU_REGISTER(0x4601, float, SHADER_CONSTANT_384_Y) -XE_GPU_REGISTER(0x4602, float, SHADER_CONSTANT_384_Z) -XE_GPU_REGISTER(0x4603, float, SHADER_CONSTANT_384_W) -XE_GPU_REGISTER(0x4604, float, SHADER_CONSTANT_385_X) -XE_GPU_REGISTER(0x4605, float, SHADER_CONSTANT_385_Y) -XE_GPU_REGISTER(0x4606, float, SHADER_CONSTANT_385_Z) -XE_GPU_REGISTER(0x4607, float, SHADER_CONSTANT_385_W) -XE_GPU_REGISTER(0x4608, float, SHADER_CONSTANT_386_X) -XE_GPU_REGISTER(0x4609, float, SHADER_CONSTANT_386_Y) -XE_GPU_REGISTER(0x460A, float, SHADER_CONSTANT_386_Z) -XE_GPU_REGISTER(0x460B, float, SHADER_CONSTANT_386_W) -XE_GPU_REGISTER(0x460C, float, SHADER_CONSTANT_387_X) -XE_GPU_REGISTER(0x460D, float, SHADER_CONSTANT_387_Y) -XE_GPU_REGISTER(0x460E, float, SHADER_CONSTANT_387_Z) -XE_GPU_REGISTER(0x460F, float, SHADER_CONSTANT_387_W) -XE_GPU_REGISTER(0x4610, float, SHADER_CONSTANT_388_X) -XE_GPU_REGISTER(0x4611, float, SHADER_CONSTANT_388_Y) -XE_GPU_REGISTER(0x4612, float, SHADER_CONSTANT_388_Z) -XE_GPU_REGISTER(0x4613, float, SHADER_CONSTANT_388_W) -XE_GPU_REGISTER(0x4614, float, SHADER_CONSTANT_389_X) -XE_GPU_REGISTER(0x4615, float, SHADER_CONSTANT_389_Y) -XE_GPU_REGISTER(0x4616, float, SHADER_CONSTANT_389_Z) -XE_GPU_REGISTER(0x4617, float, SHADER_CONSTANT_389_W) -XE_GPU_REGISTER(0x4618, float, SHADER_CONSTANT_390_X) -XE_GPU_REGISTER(0x4619, float, SHADER_CONSTANT_390_Y) -XE_GPU_REGISTER(0x461A, float, SHADER_CONSTANT_390_Z) -XE_GPU_REGISTER(0x461B, float, SHADER_CONSTANT_390_W) -XE_GPU_REGISTER(0x461C, float, SHADER_CONSTANT_391_X) -XE_GPU_REGISTER(0x461D, float, SHADER_CONSTANT_391_Y) -XE_GPU_REGISTER(0x461E, float, SHADER_CONSTANT_391_Z) -XE_GPU_REGISTER(0x461F, float, SHADER_CONSTANT_391_W) -XE_GPU_REGISTER(0x4620, float, SHADER_CONSTANT_392_X) -XE_GPU_REGISTER(0x4621, float, SHADER_CONSTANT_392_Y) -XE_GPU_REGISTER(0x4622, float, SHADER_CONSTANT_392_Z) -XE_GPU_REGISTER(0x4623, float, SHADER_CONSTANT_392_W) -XE_GPU_REGISTER(0x4624, float, SHADER_CONSTANT_393_X) -XE_GPU_REGISTER(0x4625, float, SHADER_CONSTANT_393_Y) -XE_GPU_REGISTER(0x4626, float, SHADER_CONSTANT_393_Z) -XE_GPU_REGISTER(0x4627, float, SHADER_CONSTANT_393_W) -XE_GPU_REGISTER(0x4628, float, SHADER_CONSTANT_394_X) -XE_GPU_REGISTER(0x4629, float, SHADER_CONSTANT_394_Y) -XE_GPU_REGISTER(0x462A, float, SHADER_CONSTANT_394_Z) -XE_GPU_REGISTER(0x462B, float, SHADER_CONSTANT_394_W) -XE_GPU_REGISTER(0x462C, float, SHADER_CONSTANT_395_X) -XE_GPU_REGISTER(0x462D, float, SHADER_CONSTANT_395_Y) -XE_GPU_REGISTER(0x462E, float, SHADER_CONSTANT_395_Z) -XE_GPU_REGISTER(0x462F, float, SHADER_CONSTANT_395_W) -XE_GPU_REGISTER(0x4630, float, SHADER_CONSTANT_396_X) -XE_GPU_REGISTER(0x4631, float, SHADER_CONSTANT_396_Y) -XE_GPU_REGISTER(0x4632, float, SHADER_CONSTANT_396_Z) -XE_GPU_REGISTER(0x4633, float, SHADER_CONSTANT_396_W) -XE_GPU_REGISTER(0x4634, float, SHADER_CONSTANT_397_X) -XE_GPU_REGISTER(0x4635, float, SHADER_CONSTANT_397_Y) -XE_GPU_REGISTER(0x4636, float, SHADER_CONSTANT_397_Z) -XE_GPU_REGISTER(0x4637, float, SHADER_CONSTANT_397_W) -XE_GPU_REGISTER(0x4638, float, SHADER_CONSTANT_398_X) -XE_GPU_REGISTER(0x4639, float, SHADER_CONSTANT_398_Y) -XE_GPU_REGISTER(0x463A, float, SHADER_CONSTANT_398_Z) -XE_GPU_REGISTER(0x463B, float, SHADER_CONSTANT_398_W) -XE_GPU_REGISTER(0x463C, float, SHADER_CONSTANT_399_X) -XE_GPU_REGISTER(0x463D, float, SHADER_CONSTANT_399_Y) -XE_GPU_REGISTER(0x463E, float, SHADER_CONSTANT_399_Z) -XE_GPU_REGISTER(0x463F, float, SHADER_CONSTANT_399_W) -XE_GPU_REGISTER(0x4640, float, SHADER_CONSTANT_400_X) -XE_GPU_REGISTER(0x4641, float, SHADER_CONSTANT_400_Y) -XE_GPU_REGISTER(0x4642, float, SHADER_CONSTANT_400_Z) -XE_GPU_REGISTER(0x4643, float, SHADER_CONSTANT_400_W) -XE_GPU_REGISTER(0x4644, float, SHADER_CONSTANT_401_X) -XE_GPU_REGISTER(0x4645, float, SHADER_CONSTANT_401_Y) -XE_GPU_REGISTER(0x4646, float, SHADER_CONSTANT_401_Z) -XE_GPU_REGISTER(0x4647, float, SHADER_CONSTANT_401_W) -XE_GPU_REGISTER(0x4648, float, SHADER_CONSTANT_402_X) -XE_GPU_REGISTER(0x4649, float, SHADER_CONSTANT_402_Y) -XE_GPU_REGISTER(0x464A, float, SHADER_CONSTANT_402_Z) -XE_GPU_REGISTER(0x464B, float, SHADER_CONSTANT_402_W) -XE_GPU_REGISTER(0x464C, float, SHADER_CONSTANT_403_X) -XE_GPU_REGISTER(0x464D, float, SHADER_CONSTANT_403_Y) -XE_GPU_REGISTER(0x464E, float, SHADER_CONSTANT_403_Z) -XE_GPU_REGISTER(0x464F, float, SHADER_CONSTANT_403_W) -XE_GPU_REGISTER(0x4650, float, SHADER_CONSTANT_404_X) -XE_GPU_REGISTER(0x4651, float, SHADER_CONSTANT_404_Y) -XE_GPU_REGISTER(0x4652, float, SHADER_CONSTANT_404_Z) -XE_GPU_REGISTER(0x4653, float, SHADER_CONSTANT_404_W) -XE_GPU_REGISTER(0x4654, float, SHADER_CONSTANT_405_X) -XE_GPU_REGISTER(0x4655, float, SHADER_CONSTANT_405_Y) -XE_GPU_REGISTER(0x4656, float, SHADER_CONSTANT_405_Z) -XE_GPU_REGISTER(0x4657, float, SHADER_CONSTANT_405_W) -XE_GPU_REGISTER(0x4658, float, SHADER_CONSTANT_406_X) -XE_GPU_REGISTER(0x4659, float, SHADER_CONSTANT_406_Y) -XE_GPU_REGISTER(0x465A, float, SHADER_CONSTANT_406_Z) -XE_GPU_REGISTER(0x465B, float, SHADER_CONSTANT_406_W) -XE_GPU_REGISTER(0x465C, float, SHADER_CONSTANT_407_X) -XE_GPU_REGISTER(0x465D, float, SHADER_CONSTANT_407_Y) -XE_GPU_REGISTER(0x465E, float, SHADER_CONSTANT_407_Z) -XE_GPU_REGISTER(0x465F, float, SHADER_CONSTANT_407_W) -XE_GPU_REGISTER(0x4660, float, SHADER_CONSTANT_408_X) -XE_GPU_REGISTER(0x4661, float, SHADER_CONSTANT_408_Y) -XE_GPU_REGISTER(0x4662, float, SHADER_CONSTANT_408_Z) -XE_GPU_REGISTER(0x4663, float, SHADER_CONSTANT_408_W) -XE_GPU_REGISTER(0x4664, float, SHADER_CONSTANT_409_X) -XE_GPU_REGISTER(0x4665, float, SHADER_CONSTANT_409_Y) -XE_GPU_REGISTER(0x4666, float, SHADER_CONSTANT_409_Z) -XE_GPU_REGISTER(0x4667, float, SHADER_CONSTANT_409_W) -XE_GPU_REGISTER(0x4668, float, SHADER_CONSTANT_410_X) -XE_GPU_REGISTER(0x4669, float, SHADER_CONSTANT_410_Y) -XE_GPU_REGISTER(0x466A, float, SHADER_CONSTANT_410_Z) -XE_GPU_REGISTER(0x466B, float, SHADER_CONSTANT_410_W) -XE_GPU_REGISTER(0x466C, float, SHADER_CONSTANT_411_X) -XE_GPU_REGISTER(0x466D, float, SHADER_CONSTANT_411_Y) -XE_GPU_REGISTER(0x466E, float, SHADER_CONSTANT_411_Z) -XE_GPU_REGISTER(0x466F, float, SHADER_CONSTANT_411_W) -XE_GPU_REGISTER(0x4670, float, SHADER_CONSTANT_412_X) -XE_GPU_REGISTER(0x4671, float, SHADER_CONSTANT_412_Y) -XE_GPU_REGISTER(0x4672, float, SHADER_CONSTANT_412_Z) -XE_GPU_REGISTER(0x4673, float, SHADER_CONSTANT_412_W) -XE_GPU_REGISTER(0x4674, float, SHADER_CONSTANT_413_X) -XE_GPU_REGISTER(0x4675, float, SHADER_CONSTANT_413_Y) -XE_GPU_REGISTER(0x4676, float, SHADER_CONSTANT_413_Z) -XE_GPU_REGISTER(0x4677, float, SHADER_CONSTANT_413_W) -XE_GPU_REGISTER(0x4678, float, SHADER_CONSTANT_414_X) -XE_GPU_REGISTER(0x4679, float, SHADER_CONSTANT_414_Y) -XE_GPU_REGISTER(0x467A, float, SHADER_CONSTANT_414_Z) -XE_GPU_REGISTER(0x467B, float, SHADER_CONSTANT_414_W) -XE_GPU_REGISTER(0x467C, float, SHADER_CONSTANT_415_X) -XE_GPU_REGISTER(0x467D, float, SHADER_CONSTANT_415_Y) -XE_GPU_REGISTER(0x467E, float, SHADER_CONSTANT_415_Z) -XE_GPU_REGISTER(0x467F, float, SHADER_CONSTANT_415_W) -XE_GPU_REGISTER(0x4680, float, SHADER_CONSTANT_416_X) -XE_GPU_REGISTER(0x4681, float, SHADER_CONSTANT_416_Y) -XE_GPU_REGISTER(0x4682, float, SHADER_CONSTANT_416_Z) -XE_GPU_REGISTER(0x4683, float, SHADER_CONSTANT_416_W) -XE_GPU_REGISTER(0x4684, float, SHADER_CONSTANT_417_X) -XE_GPU_REGISTER(0x4685, float, SHADER_CONSTANT_417_Y) -XE_GPU_REGISTER(0x4686, float, SHADER_CONSTANT_417_Z) -XE_GPU_REGISTER(0x4687, float, SHADER_CONSTANT_417_W) -XE_GPU_REGISTER(0x4688, float, SHADER_CONSTANT_418_X) -XE_GPU_REGISTER(0x4689, float, SHADER_CONSTANT_418_Y) -XE_GPU_REGISTER(0x468A, float, SHADER_CONSTANT_418_Z) -XE_GPU_REGISTER(0x468B, float, SHADER_CONSTANT_418_W) -XE_GPU_REGISTER(0x468C, float, SHADER_CONSTANT_419_X) -XE_GPU_REGISTER(0x468D, float, SHADER_CONSTANT_419_Y) -XE_GPU_REGISTER(0x468E, float, SHADER_CONSTANT_419_Z) -XE_GPU_REGISTER(0x468F, float, SHADER_CONSTANT_419_W) -XE_GPU_REGISTER(0x4690, float, SHADER_CONSTANT_420_X) -XE_GPU_REGISTER(0x4691, float, SHADER_CONSTANT_420_Y) -XE_GPU_REGISTER(0x4692, float, SHADER_CONSTANT_420_Z) -XE_GPU_REGISTER(0x4693, float, SHADER_CONSTANT_420_W) -XE_GPU_REGISTER(0x4694, float, SHADER_CONSTANT_421_X) -XE_GPU_REGISTER(0x4695, float, SHADER_CONSTANT_421_Y) -XE_GPU_REGISTER(0x4696, float, SHADER_CONSTANT_421_Z) -XE_GPU_REGISTER(0x4697, float, SHADER_CONSTANT_421_W) -XE_GPU_REGISTER(0x4698, float, SHADER_CONSTANT_422_X) -XE_GPU_REGISTER(0x4699, float, SHADER_CONSTANT_422_Y) -XE_GPU_REGISTER(0x469A, float, SHADER_CONSTANT_422_Z) -XE_GPU_REGISTER(0x469B, float, SHADER_CONSTANT_422_W) -XE_GPU_REGISTER(0x469C, float, SHADER_CONSTANT_423_X) -XE_GPU_REGISTER(0x469D, float, SHADER_CONSTANT_423_Y) -XE_GPU_REGISTER(0x469E, float, SHADER_CONSTANT_423_Z) -XE_GPU_REGISTER(0x469F, float, SHADER_CONSTANT_423_W) -XE_GPU_REGISTER(0x46A0, float, SHADER_CONSTANT_424_X) -XE_GPU_REGISTER(0x46A1, float, SHADER_CONSTANT_424_Y) -XE_GPU_REGISTER(0x46A2, float, SHADER_CONSTANT_424_Z) -XE_GPU_REGISTER(0x46A3, float, SHADER_CONSTANT_424_W) -XE_GPU_REGISTER(0x46A4, float, SHADER_CONSTANT_425_X) -XE_GPU_REGISTER(0x46A5, float, SHADER_CONSTANT_425_Y) -XE_GPU_REGISTER(0x46A6, float, SHADER_CONSTANT_425_Z) -XE_GPU_REGISTER(0x46A7, float, SHADER_CONSTANT_425_W) -XE_GPU_REGISTER(0x46A8, float, SHADER_CONSTANT_426_X) -XE_GPU_REGISTER(0x46A9, float, SHADER_CONSTANT_426_Y) -XE_GPU_REGISTER(0x46AA, float, SHADER_CONSTANT_426_Z) -XE_GPU_REGISTER(0x46AB, float, SHADER_CONSTANT_426_W) -XE_GPU_REGISTER(0x46AC, float, SHADER_CONSTANT_427_X) -XE_GPU_REGISTER(0x46AD, float, SHADER_CONSTANT_427_Y) -XE_GPU_REGISTER(0x46AE, float, SHADER_CONSTANT_427_Z) -XE_GPU_REGISTER(0x46AF, float, SHADER_CONSTANT_427_W) -XE_GPU_REGISTER(0x46B0, float, SHADER_CONSTANT_428_X) -XE_GPU_REGISTER(0x46B1, float, SHADER_CONSTANT_428_Y) -XE_GPU_REGISTER(0x46B2, float, SHADER_CONSTANT_428_Z) -XE_GPU_REGISTER(0x46B3, float, SHADER_CONSTANT_428_W) -XE_GPU_REGISTER(0x46B4, float, SHADER_CONSTANT_429_X) -XE_GPU_REGISTER(0x46B5, float, SHADER_CONSTANT_429_Y) -XE_GPU_REGISTER(0x46B6, float, SHADER_CONSTANT_429_Z) -XE_GPU_REGISTER(0x46B7, float, SHADER_CONSTANT_429_W) -XE_GPU_REGISTER(0x46B8, float, SHADER_CONSTANT_430_X) -XE_GPU_REGISTER(0x46B9, float, SHADER_CONSTANT_430_Y) -XE_GPU_REGISTER(0x46BA, float, SHADER_CONSTANT_430_Z) -XE_GPU_REGISTER(0x46BB, float, SHADER_CONSTANT_430_W) -XE_GPU_REGISTER(0x46BC, float, SHADER_CONSTANT_431_X) -XE_GPU_REGISTER(0x46BD, float, SHADER_CONSTANT_431_Y) -XE_GPU_REGISTER(0x46BE, float, SHADER_CONSTANT_431_Z) -XE_GPU_REGISTER(0x46BF, float, SHADER_CONSTANT_431_W) -XE_GPU_REGISTER(0x46C0, float, SHADER_CONSTANT_432_X) -XE_GPU_REGISTER(0x46C1, float, SHADER_CONSTANT_432_Y) -XE_GPU_REGISTER(0x46C2, float, SHADER_CONSTANT_432_Z) -XE_GPU_REGISTER(0x46C3, float, SHADER_CONSTANT_432_W) -XE_GPU_REGISTER(0x46C4, float, SHADER_CONSTANT_433_X) -XE_GPU_REGISTER(0x46C5, float, SHADER_CONSTANT_433_Y) -XE_GPU_REGISTER(0x46C6, float, SHADER_CONSTANT_433_Z) -XE_GPU_REGISTER(0x46C7, float, SHADER_CONSTANT_433_W) -XE_GPU_REGISTER(0x46C8, float, SHADER_CONSTANT_434_X) -XE_GPU_REGISTER(0x46C9, float, SHADER_CONSTANT_434_Y) -XE_GPU_REGISTER(0x46CA, float, SHADER_CONSTANT_434_Z) -XE_GPU_REGISTER(0x46CB, float, SHADER_CONSTANT_434_W) -XE_GPU_REGISTER(0x46CC, float, SHADER_CONSTANT_435_X) -XE_GPU_REGISTER(0x46CD, float, SHADER_CONSTANT_435_Y) -XE_GPU_REGISTER(0x46CE, float, SHADER_CONSTANT_435_Z) -XE_GPU_REGISTER(0x46CF, float, SHADER_CONSTANT_435_W) -XE_GPU_REGISTER(0x46D0, float, SHADER_CONSTANT_436_X) -XE_GPU_REGISTER(0x46D1, float, SHADER_CONSTANT_436_Y) -XE_GPU_REGISTER(0x46D2, float, SHADER_CONSTANT_436_Z) -XE_GPU_REGISTER(0x46D3, float, SHADER_CONSTANT_436_W) -XE_GPU_REGISTER(0x46D4, float, SHADER_CONSTANT_437_X) -XE_GPU_REGISTER(0x46D5, float, SHADER_CONSTANT_437_Y) -XE_GPU_REGISTER(0x46D6, float, SHADER_CONSTANT_437_Z) -XE_GPU_REGISTER(0x46D7, float, SHADER_CONSTANT_437_W) -XE_GPU_REGISTER(0x46D8, float, SHADER_CONSTANT_438_X) -XE_GPU_REGISTER(0x46D9, float, SHADER_CONSTANT_438_Y) -XE_GPU_REGISTER(0x46DA, float, SHADER_CONSTANT_438_Z) -XE_GPU_REGISTER(0x46DB, float, SHADER_CONSTANT_438_W) -XE_GPU_REGISTER(0x46DC, float, SHADER_CONSTANT_439_X) -XE_GPU_REGISTER(0x46DD, float, SHADER_CONSTANT_439_Y) -XE_GPU_REGISTER(0x46DE, float, SHADER_CONSTANT_439_Z) -XE_GPU_REGISTER(0x46DF, float, SHADER_CONSTANT_439_W) -XE_GPU_REGISTER(0x46E0, float, SHADER_CONSTANT_440_X) -XE_GPU_REGISTER(0x46E1, float, SHADER_CONSTANT_440_Y) -XE_GPU_REGISTER(0x46E2, float, SHADER_CONSTANT_440_Z) -XE_GPU_REGISTER(0x46E3, float, SHADER_CONSTANT_440_W) -XE_GPU_REGISTER(0x46E4, float, SHADER_CONSTANT_441_X) -XE_GPU_REGISTER(0x46E5, float, SHADER_CONSTANT_441_Y) -XE_GPU_REGISTER(0x46E6, float, SHADER_CONSTANT_441_Z) -XE_GPU_REGISTER(0x46E7, float, SHADER_CONSTANT_441_W) -XE_GPU_REGISTER(0x46E8, float, SHADER_CONSTANT_442_X) -XE_GPU_REGISTER(0x46E9, float, SHADER_CONSTANT_442_Y) -XE_GPU_REGISTER(0x46EA, float, SHADER_CONSTANT_442_Z) -XE_GPU_REGISTER(0x46EB, float, SHADER_CONSTANT_442_W) -XE_GPU_REGISTER(0x46EC, float, SHADER_CONSTANT_443_X) -XE_GPU_REGISTER(0x46ED, float, SHADER_CONSTANT_443_Y) -XE_GPU_REGISTER(0x46EE, float, SHADER_CONSTANT_443_Z) -XE_GPU_REGISTER(0x46EF, float, SHADER_CONSTANT_443_W) -XE_GPU_REGISTER(0x46F0, float, SHADER_CONSTANT_444_X) -XE_GPU_REGISTER(0x46F1, float, SHADER_CONSTANT_444_Y) -XE_GPU_REGISTER(0x46F2, float, SHADER_CONSTANT_444_Z) -XE_GPU_REGISTER(0x46F3, float, SHADER_CONSTANT_444_W) -XE_GPU_REGISTER(0x46F4, float, SHADER_CONSTANT_445_X) -XE_GPU_REGISTER(0x46F5, float, SHADER_CONSTANT_445_Y) -XE_GPU_REGISTER(0x46F6, float, SHADER_CONSTANT_445_Z) -XE_GPU_REGISTER(0x46F7, float, SHADER_CONSTANT_445_W) -XE_GPU_REGISTER(0x46F8, float, SHADER_CONSTANT_446_X) -XE_GPU_REGISTER(0x46F9, float, SHADER_CONSTANT_446_Y) -XE_GPU_REGISTER(0x46FA, float, SHADER_CONSTANT_446_Z) -XE_GPU_REGISTER(0x46FB, float, SHADER_CONSTANT_446_W) -XE_GPU_REGISTER(0x46FC, float, SHADER_CONSTANT_447_X) -XE_GPU_REGISTER(0x46FD, float, SHADER_CONSTANT_447_Y) -XE_GPU_REGISTER(0x46FE, float, SHADER_CONSTANT_447_Z) -XE_GPU_REGISTER(0x46FF, float, SHADER_CONSTANT_447_W) -XE_GPU_REGISTER(0x4700, float, SHADER_CONSTANT_448_X) -XE_GPU_REGISTER(0x4701, float, SHADER_CONSTANT_448_Y) -XE_GPU_REGISTER(0x4702, float, SHADER_CONSTANT_448_Z) -XE_GPU_REGISTER(0x4703, float, SHADER_CONSTANT_448_W) -XE_GPU_REGISTER(0x4704, float, SHADER_CONSTANT_449_X) -XE_GPU_REGISTER(0x4705, float, SHADER_CONSTANT_449_Y) -XE_GPU_REGISTER(0x4706, float, SHADER_CONSTANT_449_Z) -XE_GPU_REGISTER(0x4707, float, SHADER_CONSTANT_449_W) -XE_GPU_REGISTER(0x4708, float, SHADER_CONSTANT_450_X) -XE_GPU_REGISTER(0x4709, float, SHADER_CONSTANT_450_Y) -XE_GPU_REGISTER(0x470A, float, SHADER_CONSTANT_450_Z) -XE_GPU_REGISTER(0x470B, float, SHADER_CONSTANT_450_W) -XE_GPU_REGISTER(0x470C, float, SHADER_CONSTANT_451_X) -XE_GPU_REGISTER(0x470D, float, SHADER_CONSTANT_451_Y) -XE_GPU_REGISTER(0x470E, float, SHADER_CONSTANT_451_Z) -XE_GPU_REGISTER(0x470F, float, SHADER_CONSTANT_451_W) -XE_GPU_REGISTER(0x4710, float, SHADER_CONSTANT_452_X) -XE_GPU_REGISTER(0x4711, float, SHADER_CONSTANT_452_Y) -XE_GPU_REGISTER(0x4712, float, SHADER_CONSTANT_452_Z) -XE_GPU_REGISTER(0x4713, float, SHADER_CONSTANT_452_W) -XE_GPU_REGISTER(0x4714, float, SHADER_CONSTANT_453_X) -XE_GPU_REGISTER(0x4715, float, SHADER_CONSTANT_453_Y) -XE_GPU_REGISTER(0x4716, float, SHADER_CONSTANT_453_Z) -XE_GPU_REGISTER(0x4717, float, SHADER_CONSTANT_453_W) -XE_GPU_REGISTER(0x4718, float, SHADER_CONSTANT_454_X) -XE_GPU_REGISTER(0x4719, float, SHADER_CONSTANT_454_Y) -XE_GPU_REGISTER(0x471A, float, SHADER_CONSTANT_454_Z) -XE_GPU_REGISTER(0x471B, float, SHADER_CONSTANT_454_W) -XE_GPU_REGISTER(0x471C, float, SHADER_CONSTANT_455_X) -XE_GPU_REGISTER(0x471D, float, SHADER_CONSTANT_455_Y) -XE_GPU_REGISTER(0x471E, float, SHADER_CONSTANT_455_Z) -XE_GPU_REGISTER(0x471F, float, SHADER_CONSTANT_455_W) -XE_GPU_REGISTER(0x4720, float, SHADER_CONSTANT_456_X) -XE_GPU_REGISTER(0x4721, float, SHADER_CONSTANT_456_Y) -XE_GPU_REGISTER(0x4722, float, SHADER_CONSTANT_456_Z) -XE_GPU_REGISTER(0x4723, float, SHADER_CONSTANT_456_W) -XE_GPU_REGISTER(0x4724, float, SHADER_CONSTANT_457_X) -XE_GPU_REGISTER(0x4725, float, SHADER_CONSTANT_457_Y) -XE_GPU_REGISTER(0x4726, float, SHADER_CONSTANT_457_Z) -XE_GPU_REGISTER(0x4727, float, SHADER_CONSTANT_457_W) -XE_GPU_REGISTER(0x4728, float, SHADER_CONSTANT_458_X) -XE_GPU_REGISTER(0x4729, float, SHADER_CONSTANT_458_Y) -XE_GPU_REGISTER(0x472A, float, SHADER_CONSTANT_458_Z) -XE_GPU_REGISTER(0x472B, float, SHADER_CONSTANT_458_W) -XE_GPU_REGISTER(0x472C, float, SHADER_CONSTANT_459_X) -XE_GPU_REGISTER(0x472D, float, SHADER_CONSTANT_459_Y) -XE_GPU_REGISTER(0x472E, float, SHADER_CONSTANT_459_Z) -XE_GPU_REGISTER(0x472F, float, SHADER_CONSTANT_459_W) -XE_GPU_REGISTER(0x4730, float, SHADER_CONSTANT_460_X) -XE_GPU_REGISTER(0x4731, float, SHADER_CONSTANT_460_Y) -XE_GPU_REGISTER(0x4732, float, SHADER_CONSTANT_460_Z) -XE_GPU_REGISTER(0x4733, float, SHADER_CONSTANT_460_W) -XE_GPU_REGISTER(0x4734, float, SHADER_CONSTANT_461_X) -XE_GPU_REGISTER(0x4735, float, SHADER_CONSTANT_461_Y) -XE_GPU_REGISTER(0x4736, float, SHADER_CONSTANT_461_Z) -XE_GPU_REGISTER(0x4737, float, SHADER_CONSTANT_461_W) -XE_GPU_REGISTER(0x4738, float, SHADER_CONSTANT_462_X) -XE_GPU_REGISTER(0x4739, float, SHADER_CONSTANT_462_Y) -XE_GPU_REGISTER(0x473A, float, SHADER_CONSTANT_462_Z) -XE_GPU_REGISTER(0x473B, float, SHADER_CONSTANT_462_W) -XE_GPU_REGISTER(0x473C, float, SHADER_CONSTANT_463_X) -XE_GPU_REGISTER(0x473D, float, SHADER_CONSTANT_463_Y) -XE_GPU_REGISTER(0x473E, float, SHADER_CONSTANT_463_Z) -XE_GPU_REGISTER(0x473F, float, SHADER_CONSTANT_463_W) -XE_GPU_REGISTER(0x4740, float, SHADER_CONSTANT_464_X) -XE_GPU_REGISTER(0x4741, float, SHADER_CONSTANT_464_Y) -XE_GPU_REGISTER(0x4742, float, SHADER_CONSTANT_464_Z) -XE_GPU_REGISTER(0x4743, float, SHADER_CONSTANT_464_W) -XE_GPU_REGISTER(0x4744, float, SHADER_CONSTANT_465_X) -XE_GPU_REGISTER(0x4745, float, SHADER_CONSTANT_465_Y) -XE_GPU_REGISTER(0x4746, float, SHADER_CONSTANT_465_Z) -XE_GPU_REGISTER(0x4747, float, SHADER_CONSTANT_465_W) -XE_GPU_REGISTER(0x4748, float, SHADER_CONSTANT_466_X) -XE_GPU_REGISTER(0x4749, float, SHADER_CONSTANT_466_Y) -XE_GPU_REGISTER(0x474A, float, SHADER_CONSTANT_466_Z) -XE_GPU_REGISTER(0x474B, float, SHADER_CONSTANT_466_W) -XE_GPU_REGISTER(0x474C, float, SHADER_CONSTANT_467_X) -XE_GPU_REGISTER(0x474D, float, SHADER_CONSTANT_467_Y) -XE_GPU_REGISTER(0x474E, float, SHADER_CONSTANT_467_Z) -XE_GPU_REGISTER(0x474F, float, SHADER_CONSTANT_467_W) -XE_GPU_REGISTER(0x4750, float, SHADER_CONSTANT_468_X) -XE_GPU_REGISTER(0x4751, float, SHADER_CONSTANT_468_Y) -XE_GPU_REGISTER(0x4752, float, SHADER_CONSTANT_468_Z) -XE_GPU_REGISTER(0x4753, float, SHADER_CONSTANT_468_W) -XE_GPU_REGISTER(0x4754, float, SHADER_CONSTANT_469_X) -XE_GPU_REGISTER(0x4755, float, SHADER_CONSTANT_469_Y) -XE_GPU_REGISTER(0x4756, float, SHADER_CONSTANT_469_Z) -XE_GPU_REGISTER(0x4757, float, SHADER_CONSTANT_469_W) -XE_GPU_REGISTER(0x4758, float, SHADER_CONSTANT_470_X) -XE_GPU_REGISTER(0x4759, float, SHADER_CONSTANT_470_Y) -XE_GPU_REGISTER(0x475A, float, SHADER_CONSTANT_470_Z) -XE_GPU_REGISTER(0x475B, float, SHADER_CONSTANT_470_W) -XE_GPU_REGISTER(0x475C, float, SHADER_CONSTANT_471_X) -XE_GPU_REGISTER(0x475D, float, SHADER_CONSTANT_471_Y) -XE_GPU_REGISTER(0x475E, float, SHADER_CONSTANT_471_Z) -XE_GPU_REGISTER(0x475F, float, SHADER_CONSTANT_471_W) -XE_GPU_REGISTER(0x4760, float, SHADER_CONSTANT_472_X) -XE_GPU_REGISTER(0x4761, float, SHADER_CONSTANT_472_Y) -XE_GPU_REGISTER(0x4762, float, SHADER_CONSTANT_472_Z) -XE_GPU_REGISTER(0x4763, float, SHADER_CONSTANT_472_W) -XE_GPU_REGISTER(0x4764, float, SHADER_CONSTANT_473_X) -XE_GPU_REGISTER(0x4765, float, SHADER_CONSTANT_473_Y) -XE_GPU_REGISTER(0x4766, float, SHADER_CONSTANT_473_Z) -XE_GPU_REGISTER(0x4767, float, SHADER_CONSTANT_473_W) -XE_GPU_REGISTER(0x4768, float, SHADER_CONSTANT_474_X) -XE_GPU_REGISTER(0x4769, float, SHADER_CONSTANT_474_Y) -XE_GPU_REGISTER(0x476A, float, SHADER_CONSTANT_474_Z) -XE_GPU_REGISTER(0x476B, float, SHADER_CONSTANT_474_W) -XE_GPU_REGISTER(0x476C, float, SHADER_CONSTANT_475_X) -XE_GPU_REGISTER(0x476D, float, SHADER_CONSTANT_475_Y) -XE_GPU_REGISTER(0x476E, float, SHADER_CONSTANT_475_Z) -XE_GPU_REGISTER(0x476F, float, SHADER_CONSTANT_475_W) -XE_GPU_REGISTER(0x4770, float, SHADER_CONSTANT_476_X) -XE_GPU_REGISTER(0x4771, float, SHADER_CONSTANT_476_Y) -XE_GPU_REGISTER(0x4772, float, SHADER_CONSTANT_476_Z) -XE_GPU_REGISTER(0x4773, float, SHADER_CONSTANT_476_W) -XE_GPU_REGISTER(0x4774, float, SHADER_CONSTANT_477_X) -XE_GPU_REGISTER(0x4775, float, SHADER_CONSTANT_477_Y) -XE_GPU_REGISTER(0x4776, float, SHADER_CONSTANT_477_Z) -XE_GPU_REGISTER(0x4777, float, SHADER_CONSTANT_477_W) -XE_GPU_REGISTER(0x4778, float, SHADER_CONSTANT_478_X) -XE_GPU_REGISTER(0x4779, float, SHADER_CONSTANT_478_Y) -XE_GPU_REGISTER(0x477A, float, SHADER_CONSTANT_478_Z) -XE_GPU_REGISTER(0x477B, float, SHADER_CONSTANT_478_W) -XE_GPU_REGISTER(0x477C, float, SHADER_CONSTANT_479_X) -XE_GPU_REGISTER(0x477D, float, SHADER_CONSTANT_479_Y) -XE_GPU_REGISTER(0x477E, float, SHADER_CONSTANT_479_Z) -XE_GPU_REGISTER(0x477F, float, SHADER_CONSTANT_479_W) -XE_GPU_REGISTER(0x4780, float, SHADER_CONSTANT_480_X) -XE_GPU_REGISTER(0x4781, float, SHADER_CONSTANT_480_Y) -XE_GPU_REGISTER(0x4782, float, SHADER_CONSTANT_480_Z) -XE_GPU_REGISTER(0x4783, float, SHADER_CONSTANT_480_W) -XE_GPU_REGISTER(0x4784, float, SHADER_CONSTANT_481_X) -XE_GPU_REGISTER(0x4785, float, SHADER_CONSTANT_481_Y) -XE_GPU_REGISTER(0x4786, float, SHADER_CONSTANT_481_Z) -XE_GPU_REGISTER(0x4787, float, SHADER_CONSTANT_481_W) -XE_GPU_REGISTER(0x4788, float, SHADER_CONSTANT_482_X) -XE_GPU_REGISTER(0x4789, float, SHADER_CONSTANT_482_Y) -XE_GPU_REGISTER(0x478A, float, SHADER_CONSTANT_482_Z) -XE_GPU_REGISTER(0x478B, float, SHADER_CONSTANT_482_W) -XE_GPU_REGISTER(0x478C, float, SHADER_CONSTANT_483_X) -XE_GPU_REGISTER(0x478D, float, SHADER_CONSTANT_483_Y) -XE_GPU_REGISTER(0x478E, float, SHADER_CONSTANT_483_Z) -XE_GPU_REGISTER(0x478F, float, SHADER_CONSTANT_483_W) -XE_GPU_REGISTER(0x4790, float, SHADER_CONSTANT_484_X) -XE_GPU_REGISTER(0x4791, float, SHADER_CONSTANT_484_Y) -XE_GPU_REGISTER(0x4792, float, SHADER_CONSTANT_484_Z) -XE_GPU_REGISTER(0x4793, float, SHADER_CONSTANT_484_W) -XE_GPU_REGISTER(0x4794, float, SHADER_CONSTANT_485_X) -XE_GPU_REGISTER(0x4795, float, SHADER_CONSTANT_485_Y) -XE_GPU_REGISTER(0x4796, float, SHADER_CONSTANT_485_Z) -XE_GPU_REGISTER(0x4797, float, SHADER_CONSTANT_485_W) -XE_GPU_REGISTER(0x4798, float, SHADER_CONSTANT_486_X) -XE_GPU_REGISTER(0x4799, float, SHADER_CONSTANT_486_Y) -XE_GPU_REGISTER(0x479A, float, SHADER_CONSTANT_486_Z) -XE_GPU_REGISTER(0x479B, float, SHADER_CONSTANT_486_W) -XE_GPU_REGISTER(0x479C, float, SHADER_CONSTANT_487_X) -XE_GPU_REGISTER(0x479D, float, SHADER_CONSTANT_487_Y) -XE_GPU_REGISTER(0x479E, float, SHADER_CONSTANT_487_Z) -XE_GPU_REGISTER(0x479F, float, SHADER_CONSTANT_487_W) -XE_GPU_REGISTER(0x47A0, float, SHADER_CONSTANT_488_X) -XE_GPU_REGISTER(0x47A1, float, SHADER_CONSTANT_488_Y) -XE_GPU_REGISTER(0x47A2, float, SHADER_CONSTANT_488_Z) -XE_GPU_REGISTER(0x47A3, float, SHADER_CONSTANT_488_W) -XE_GPU_REGISTER(0x47A4, float, SHADER_CONSTANT_489_X) -XE_GPU_REGISTER(0x47A5, float, SHADER_CONSTANT_489_Y) -XE_GPU_REGISTER(0x47A6, float, SHADER_CONSTANT_489_Z) -XE_GPU_REGISTER(0x47A7, float, SHADER_CONSTANT_489_W) -XE_GPU_REGISTER(0x47A8, float, SHADER_CONSTANT_490_X) -XE_GPU_REGISTER(0x47A9, float, SHADER_CONSTANT_490_Y) -XE_GPU_REGISTER(0x47AA, float, SHADER_CONSTANT_490_Z) -XE_GPU_REGISTER(0x47AB, float, SHADER_CONSTANT_490_W) -XE_GPU_REGISTER(0x47AC, float, SHADER_CONSTANT_491_X) -XE_GPU_REGISTER(0x47AD, float, SHADER_CONSTANT_491_Y) -XE_GPU_REGISTER(0x47AE, float, SHADER_CONSTANT_491_Z) -XE_GPU_REGISTER(0x47AF, float, SHADER_CONSTANT_491_W) -XE_GPU_REGISTER(0x47B0, float, SHADER_CONSTANT_492_X) -XE_GPU_REGISTER(0x47B1, float, SHADER_CONSTANT_492_Y) -XE_GPU_REGISTER(0x47B2, float, SHADER_CONSTANT_492_Z) -XE_GPU_REGISTER(0x47B3, float, SHADER_CONSTANT_492_W) -XE_GPU_REGISTER(0x47B4, float, SHADER_CONSTANT_493_X) -XE_GPU_REGISTER(0x47B5, float, SHADER_CONSTANT_493_Y) -XE_GPU_REGISTER(0x47B6, float, SHADER_CONSTANT_493_Z) -XE_GPU_REGISTER(0x47B7, float, SHADER_CONSTANT_493_W) -XE_GPU_REGISTER(0x47B8, float, SHADER_CONSTANT_494_X) -XE_GPU_REGISTER(0x47B9, float, SHADER_CONSTANT_494_Y) -XE_GPU_REGISTER(0x47BA, float, SHADER_CONSTANT_494_Z) -XE_GPU_REGISTER(0x47BB, float, SHADER_CONSTANT_494_W) -XE_GPU_REGISTER(0x47BC, float, SHADER_CONSTANT_495_X) -XE_GPU_REGISTER(0x47BD, float, SHADER_CONSTANT_495_Y) -XE_GPU_REGISTER(0x47BE, float, SHADER_CONSTANT_495_Z) -XE_GPU_REGISTER(0x47BF, float, SHADER_CONSTANT_495_W) -XE_GPU_REGISTER(0x47C0, float, SHADER_CONSTANT_496_X) -XE_GPU_REGISTER(0x47C1, float, SHADER_CONSTANT_496_Y) -XE_GPU_REGISTER(0x47C2, float, SHADER_CONSTANT_496_Z) -XE_GPU_REGISTER(0x47C3, float, SHADER_CONSTANT_496_W) -XE_GPU_REGISTER(0x47C4, float, SHADER_CONSTANT_497_X) -XE_GPU_REGISTER(0x47C5, float, SHADER_CONSTANT_497_Y) -XE_GPU_REGISTER(0x47C6, float, SHADER_CONSTANT_497_Z) -XE_GPU_REGISTER(0x47C7, float, SHADER_CONSTANT_497_W) -XE_GPU_REGISTER(0x47C8, float, SHADER_CONSTANT_498_X) -XE_GPU_REGISTER(0x47C9, float, SHADER_CONSTANT_498_Y) -XE_GPU_REGISTER(0x47CA, float, SHADER_CONSTANT_498_Z) -XE_GPU_REGISTER(0x47CB, float, SHADER_CONSTANT_498_W) -XE_GPU_REGISTER(0x47CC, float, SHADER_CONSTANT_499_X) -XE_GPU_REGISTER(0x47CD, float, SHADER_CONSTANT_499_Y) -XE_GPU_REGISTER(0x47CE, float, SHADER_CONSTANT_499_Z) -XE_GPU_REGISTER(0x47CF, float, SHADER_CONSTANT_499_W) -XE_GPU_REGISTER(0x47D0, float, SHADER_CONSTANT_500_X) -XE_GPU_REGISTER(0x47D1, float, SHADER_CONSTANT_500_Y) -XE_GPU_REGISTER(0x47D2, float, SHADER_CONSTANT_500_Z) -XE_GPU_REGISTER(0x47D3, float, SHADER_CONSTANT_500_W) -XE_GPU_REGISTER(0x47D4, float, SHADER_CONSTANT_501_X) -XE_GPU_REGISTER(0x47D5, float, SHADER_CONSTANT_501_Y) -XE_GPU_REGISTER(0x47D6, float, SHADER_CONSTANT_501_Z) -XE_GPU_REGISTER(0x47D7, float, SHADER_CONSTANT_501_W) -XE_GPU_REGISTER(0x47D8, float, SHADER_CONSTANT_502_X) -XE_GPU_REGISTER(0x47D9, float, SHADER_CONSTANT_502_Y) -XE_GPU_REGISTER(0x47DA, float, SHADER_CONSTANT_502_Z) -XE_GPU_REGISTER(0x47DB, float, SHADER_CONSTANT_502_W) -XE_GPU_REGISTER(0x47DC, float, SHADER_CONSTANT_503_X) -XE_GPU_REGISTER(0x47DD, float, SHADER_CONSTANT_503_Y) -XE_GPU_REGISTER(0x47DE, float, SHADER_CONSTANT_503_Z) -XE_GPU_REGISTER(0x47DF, float, SHADER_CONSTANT_503_W) -XE_GPU_REGISTER(0x47E0, float, SHADER_CONSTANT_504_X) -XE_GPU_REGISTER(0x47E1, float, SHADER_CONSTANT_504_Y) -XE_GPU_REGISTER(0x47E2, float, SHADER_CONSTANT_504_Z) -XE_GPU_REGISTER(0x47E3, float, SHADER_CONSTANT_504_W) -XE_GPU_REGISTER(0x47E4, float, SHADER_CONSTANT_505_X) -XE_GPU_REGISTER(0x47E5, float, SHADER_CONSTANT_505_Y) -XE_GPU_REGISTER(0x47E6, float, SHADER_CONSTANT_505_Z) -XE_GPU_REGISTER(0x47E7, float, SHADER_CONSTANT_505_W) -XE_GPU_REGISTER(0x47E8, float, SHADER_CONSTANT_506_X) -XE_GPU_REGISTER(0x47E9, float, SHADER_CONSTANT_506_Y) -XE_GPU_REGISTER(0x47EA, float, SHADER_CONSTANT_506_Z) -XE_GPU_REGISTER(0x47EB, float, SHADER_CONSTANT_506_W) -XE_GPU_REGISTER(0x47EC, float, SHADER_CONSTANT_507_X) -XE_GPU_REGISTER(0x47ED, float, SHADER_CONSTANT_507_Y) -XE_GPU_REGISTER(0x47EE, float, SHADER_CONSTANT_507_Z) -XE_GPU_REGISTER(0x47EF, float, SHADER_CONSTANT_507_W) -XE_GPU_REGISTER(0x47F0, float, SHADER_CONSTANT_508_X) -XE_GPU_REGISTER(0x47F1, float, SHADER_CONSTANT_508_Y) -XE_GPU_REGISTER(0x47F2, float, SHADER_CONSTANT_508_Z) -XE_GPU_REGISTER(0x47F3, float, SHADER_CONSTANT_508_W) -XE_GPU_REGISTER(0x47F4, float, SHADER_CONSTANT_509_X) -XE_GPU_REGISTER(0x47F5, float, SHADER_CONSTANT_509_Y) -XE_GPU_REGISTER(0x47F6, float, SHADER_CONSTANT_509_Z) -XE_GPU_REGISTER(0x47F7, float, SHADER_CONSTANT_509_W) -XE_GPU_REGISTER(0x47F8, float, SHADER_CONSTANT_510_X) -XE_GPU_REGISTER(0x47F9, float, SHADER_CONSTANT_510_Y) -XE_GPU_REGISTER(0x47FA, float, SHADER_CONSTANT_510_Z) -XE_GPU_REGISTER(0x47FB, float, SHADER_CONSTANT_510_W) -XE_GPU_REGISTER(0x47FC, float, SHADER_CONSTANT_511_X) -XE_GPU_REGISTER(0x47FD, float, SHADER_CONSTANT_511_Y) -XE_GPU_REGISTER(0x47FE, float, SHADER_CONSTANT_511_Z) -XE_GPU_REGISTER(0x47FF, float, SHADER_CONSTANT_511_W) - -XE_GPU_REGISTER(0x4800, dword, SHADER_CONSTANT_FETCH_00_0) -XE_GPU_REGISTER(0x4801, dword, SHADER_CONSTANT_FETCH_00_1) -XE_GPU_REGISTER(0x4802, dword, SHADER_CONSTANT_FETCH_00_2) -XE_GPU_REGISTER(0x4803, dword, SHADER_CONSTANT_FETCH_00_3) -XE_GPU_REGISTER(0x4804, dword, SHADER_CONSTANT_FETCH_00_4) -XE_GPU_REGISTER(0x4805, dword, SHADER_CONSTANT_FETCH_00_5) -XE_GPU_REGISTER(0x4806, dword, SHADER_CONSTANT_FETCH_01_0) -XE_GPU_REGISTER(0x4807, dword, SHADER_CONSTANT_FETCH_01_1) -XE_GPU_REGISTER(0x4808, dword, SHADER_CONSTANT_FETCH_01_2) -XE_GPU_REGISTER(0x4809, dword, SHADER_CONSTANT_FETCH_01_3) -XE_GPU_REGISTER(0x480A, dword, SHADER_CONSTANT_FETCH_01_4) -XE_GPU_REGISTER(0x480B, dword, SHADER_CONSTANT_FETCH_01_5) -XE_GPU_REGISTER(0x480C, dword, SHADER_CONSTANT_FETCH_02_0) -XE_GPU_REGISTER(0x480D, dword, SHADER_CONSTANT_FETCH_02_1) -XE_GPU_REGISTER(0x480E, dword, SHADER_CONSTANT_FETCH_02_2) -XE_GPU_REGISTER(0x480F, dword, SHADER_CONSTANT_FETCH_02_3) -XE_GPU_REGISTER(0x4810, dword, SHADER_CONSTANT_FETCH_02_4) -XE_GPU_REGISTER(0x4811, dword, SHADER_CONSTANT_FETCH_02_5) -XE_GPU_REGISTER(0x4812, dword, SHADER_CONSTANT_FETCH_03_0) -XE_GPU_REGISTER(0x4813, dword, SHADER_CONSTANT_FETCH_03_1) -XE_GPU_REGISTER(0x4814, dword, SHADER_CONSTANT_FETCH_03_2) -XE_GPU_REGISTER(0x4815, dword, SHADER_CONSTANT_FETCH_03_3) -XE_GPU_REGISTER(0x4816, dword, SHADER_CONSTANT_FETCH_03_4) -XE_GPU_REGISTER(0x4817, dword, SHADER_CONSTANT_FETCH_03_5) -XE_GPU_REGISTER(0x4818, dword, SHADER_CONSTANT_FETCH_04_0) -XE_GPU_REGISTER(0x4819, dword, SHADER_CONSTANT_FETCH_04_1) -XE_GPU_REGISTER(0x481A, dword, SHADER_CONSTANT_FETCH_04_2) -XE_GPU_REGISTER(0x481B, dword, SHADER_CONSTANT_FETCH_04_3) -XE_GPU_REGISTER(0x481C, dword, SHADER_CONSTANT_FETCH_04_4) -XE_GPU_REGISTER(0x481D, dword, SHADER_CONSTANT_FETCH_04_5) -XE_GPU_REGISTER(0x481E, dword, SHADER_CONSTANT_FETCH_05_0) -XE_GPU_REGISTER(0x481F, dword, SHADER_CONSTANT_FETCH_05_1) -XE_GPU_REGISTER(0x4820, dword, SHADER_CONSTANT_FETCH_05_2) -XE_GPU_REGISTER(0x4821, dword, SHADER_CONSTANT_FETCH_05_3) -XE_GPU_REGISTER(0x4822, dword, SHADER_CONSTANT_FETCH_05_4) -XE_GPU_REGISTER(0x4823, dword, SHADER_CONSTANT_FETCH_05_5) -XE_GPU_REGISTER(0x4824, dword, SHADER_CONSTANT_FETCH_06_0) -XE_GPU_REGISTER(0x4825, dword, SHADER_CONSTANT_FETCH_06_1) -XE_GPU_REGISTER(0x4826, dword, SHADER_CONSTANT_FETCH_06_2) -XE_GPU_REGISTER(0x4827, dword, SHADER_CONSTANT_FETCH_06_3) -XE_GPU_REGISTER(0x4828, dword, SHADER_CONSTANT_FETCH_06_4) -XE_GPU_REGISTER(0x4829, dword, SHADER_CONSTANT_FETCH_06_5) -XE_GPU_REGISTER(0x482A, dword, SHADER_CONSTANT_FETCH_07_0) -XE_GPU_REGISTER(0x482B, dword, SHADER_CONSTANT_FETCH_07_1) -XE_GPU_REGISTER(0x482C, dword, SHADER_CONSTANT_FETCH_07_2) -XE_GPU_REGISTER(0x482D, dword, SHADER_CONSTANT_FETCH_07_3) -XE_GPU_REGISTER(0x482E, dword, SHADER_CONSTANT_FETCH_07_4) -XE_GPU_REGISTER(0x482F, dword, SHADER_CONSTANT_FETCH_07_5) -XE_GPU_REGISTER(0x4830, dword, SHADER_CONSTANT_FETCH_08_0) -XE_GPU_REGISTER(0x4831, dword, SHADER_CONSTANT_FETCH_08_1) -XE_GPU_REGISTER(0x4832, dword, SHADER_CONSTANT_FETCH_08_2) -XE_GPU_REGISTER(0x4833, dword, SHADER_CONSTANT_FETCH_08_3) -XE_GPU_REGISTER(0x4834, dword, SHADER_CONSTANT_FETCH_08_4) -XE_GPU_REGISTER(0x4835, dword, SHADER_CONSTANT_FETCH_08_5) -XE_GPU_REGISTER(0x4836, dword, SHADER_CONSTANT_FETCH_09_0) -XE_GPU_REGISTER(0x4837, dword, SHADER_CONSTANT_FETCH_09_1) -XE_GPU_REGISTER(0x4838, dword, SHADER_CONSTANT_FETCH_09_2) -XE_GPU_REGISTER(0x4839, dword, SHADER_CONSTANT_FETCH_09_3) -XE_GPU_REGISTER(0x483A, dword, SHADER_CONSTANT_FETCH_09_4) -XE_GPU_REGISTER(0x483B, dword, SHADER_CONSTANT_FETCH_09_5) -XE_GPU_REGISTER(0x483C, dword, SHADER_CONSTANT_FETCH_10_0) -XE_GPU_REGISTER(0x483D, dword, SHADER_CONSTANT_FETCH_10_1) -XE_GPU_REGISTER(0x483E, dword, SHADER_CONSTANT_FETCH_10_2) -XE_GPU_REGISTER(0x483F, dword, SHADER_CONSTANT_FETCH_10_3) -XE_GPU_REGISTER(0x4840, dword, SHADER_CONSTANT_FETCH_10_4) -XE_GPU_REGISTER(0x4841, dword, SHADER_CONSTANT_FETCH_10_5) -XE_GPU_REGISTER(0x4842, dword, SHADER_CONSTANT_FETCH_11_0) -XE_GPU_REGISTER(0x4843, dword, SHADER_CONSTANT_FETCH_11_1) -XE_GPU_REGISTER(0x4844, dword, SHADER_CONSTANT_FETCH_11_2) -XE_GPU_REGISTER(0x4845, dword, SHADER_CONSTANT_FETCH_11_3) -XE_GPU_REGISTER(0x4846, dword, SHADER_CONSTANT_FETCH_11_4) -XE_GPU_REGISTER(0x4847, dword, SHADER_CONSTANT_FETCH_11_5) -XE_GPU_REGISTER(0x4848, dword, SHADER_CONSTANT_FETCH_12_0) -XE_GPU_REGISTER(0x4849, dword, SHADER_CONSTANT_FETCH_12_1) -XE_GPU_REGISTER(0x484A, dword, SHADER_CONSTANT_FETCH_12_2) -XE_GPU_REGISTER(0x484B, dword, SHADER_CONSTANT_FETCH_12_3) -XE_GPU_REGISTER(0x484C, dword, SHADER_CONSTANT_FETCH_12_4) -XE_GPU_REGISTER(0x484D, dword, SHADER_CONSTANT_FETCH_12_5) -XE_GPU_REGISTER(0x484E, dword, SHADER_CONSTANT_FETCH_13_0) -XE_GPU_REGISTER(0x484F, dword, SHADER_CONSTANT_FETCH_13_1) -XE_GPU_REGISTER(0x4850, dword, SHADER_CONSTANT_FETCH_13_2) -XE_GPU_REGISTER(0x4851, dword, SHADER_CONSTANT_FETCH_13_3) -XE_GPU_REGISTER(0x4852, dword, SHADER_CONSTANT_FETCH_13_4) -XE_GPU_REGISTER(0x4853, dword, SHADER_CONSTANT_FETCH_13_5) -XE_GPU_REGISTER(0x4854, dword, SHADER_CONSTANT_FETCH_14_0) -XE_GPU_REGISTER(0x4855, dword, SHADER_CONSTANT_FETCH_14_1) -XE_GPU_REGISTER(0x4856, dword, SHADER_CONSTANT_FETCH_14_2) -XE_GPU_REGISTER(0x4857, dword, SHADER_CONSTANT_FETCH_14_3) -XE_GPU_REGISTER(0x4858, dword, SHADER_CONSTANT_FETCH_14_4) -XE_GPU_REGISTER(0x4859, dword, SHADER_CONSTANT_FETCH_14_5) -XE_GPU_REGISTER(0x485A, dword, SHADER_CONSTANT_FETCH_15_0) -XE_GPU_REGISTER(0x485B, dword, SHADER_CONSTANT_FETCH_15_1) -XE_GPU_REGISTER(0x485C, dword, SHADER_CONSTANT_FETCH_15_2) -XE_GPU_REGISTER(0x485D, dword, SHADER_CONSTANT_FETCH_15_3) -XE_GPU_REGISTER(0x485E, dword, SHADER_CONSTANT_FETCH_15_4) -XE_GPU_REGISTER(0x485F, dword, SHADER_CONSTANT_FETCH_15_5) -XE_GPU_REGISTER(0x4860, dword, SHADER_CONSTANT_FETCH_16_0) -XE_GPU_REGISTER(0x4861, dword, SHADER_CONSTANT_FETCH_16_1) -XE_GPU_REGISTER(0x4862, dword, SHADER_CONSTANT_FETCH_16_2) -XE_GPU_REGISTER(0x4863, dword, SHADER_CONSTANT_FETCH_16_3) -XE_GPU_REGISTER(0x4864, dword, SHADER_CONSTANT_FETCH_16_4) -XE_GPU_REGISTER(0x4865, dword, SHADER_CONSTANT_FETCH_16_5) -XE_GPU_REGISTER(0x4866, dword, SHADER_CONSTANT_FETCH_17_0) -XE_GPU_REGISTER(0x4867, dword, SHADER_CONSTANT_FETCH_17_1) -XE_GPU_REGISTER(0x4868, dword, SHADER_CONSTANT_FETCH_17_2) -XE_GPU_REGISTER(0x4869, dword, SHADER_CONSTANT_FETCH_17_3) -XE_GPU_REGISTER(0x486A, dword, SHADER_CONSTANT_FETCH_17_4) -XE_GPU_REGISTER(0x486B, dword, SHADER_CONSTANT_FETCH_17_5) -XE_GPU_REGISTER(0x486C, dword, SHADER_CONSTANT_FETCH_18_0) -XE_GPU_REGISTER(0x486D, dword, SHADER_CONSTANT_FETCH_18_1) -XE_GPU_REGISTER(0x486E, dword, SHADER_CONSTANT_FETCH_18_2) -XE_GPU_REGISTER(0x486F, dword, SHADER_CONSTANT_FETCH_18_3) -XE_GPU_REGISTER(0x4870, dword, SHADER_CONSTANT_FETCH_18_4) -XE_GPU_REGISTER(0x4871, dword, SHADER_CONSTANT_FETCH_18_5) -XE_GPU_REGISTER(0x4872, dword, SHADER_CONSTANT_FETCH_19_0) -XE_GPU_REGISTER(0x4873, dword, SHADER_CONSTANT_FETCH_19_1) -XE_GPU_REGISTER(0x4874, dword, SHADER_CONSTANT_FETCH_19_2) -XE_GPU_REGISTER(0x4875, dword, SHADER_CONSTANT_FETCH_19_3) -XE_GPU_REGISTER(0x4876, dword, SHADER_CONSTANT_FETCH_19_4) -XE_GPU_REGISTER(0x4877, dword, SHADER_CONSTANT_FETCH_19_5) -XE_GPU_REGISTER(0x4878, dword, SHADER_CONSTANT_FETCH_20_0) -XE_GPU_REGISTER(0x4879, dword, SHADER_CONSTANT_FETCH_20_1) -XE_GPU_REGISTER(0x487A, dword, SHADER_CONSTANT_FETCH_20_2) -XE_GPU_REGISTER(0x487B, dword, SHADER_CONSTANT_FETCH_20_3) -XE_GPU_REGISTER(0x487C, dword, SHADER_CONSTANT_FETCH_20_4) -XE_GPU_REGISTER(0x487D, dword, SHADER_CONSTANT_FETCH_20_5) -XE_GPU_REGISTER(0x487E, dword, SHADER_CONSTANT_FETCH_21_0) -XE_GPU_REGISTER(0x487F, dword, SHADER_CONSTANT_FETCH_21_1) -XE_GPU_REGISTER(0x4880, dword, SHADER_CONSTANT_FETCH_21_2) -XE_GPU_REGISTER(0x4881, dword, SHADER_CONSTANT_FETCH_21_3) -XE_GPU_REGISTER(0x4882, dword, SHADER_CONSTANT_FETCH_21_4) -XE_GPU_REGISTER(0x4883, dword, SHADER_CONSTANT_FETCH_21_5) -XE_GPU_REGISTER(0x4884, dword, SHADER_CONSTANT_FETCH_22_0) -XE_GPU_REGISTER(0x4885, dword, SHADER_CONSTANT_FETCH_22_1) -XE_GPU_REGISTER(0x4886, dword, SHADER_CONSTANT_FETCH_22_2) -XE_GPU_REGISTER(0x4887, dword, SHADER_CONSTANT_FETCH_22_3) -XE_GPU_REGISTER(0x4888, dword, SHADER_CONSTANT_FETCH_22_4) -XE_GPU_REGISTER(0x4889, dword, SHADER_CONSTANT_FETCH_22_5) -XE_GPU_REGISTER(0x488A, dword, SHADER_CONSTANT_FETCH_23_0) -XE_GPU_REGISTER(0x488B, dword, SHADER_CONSTANT_FETCH_23_1) -XE_GPU_REGISTER(0x488C, dword, SHADER_CONSTANT_FETCH_23_2) -XE_GPU_REGISTER(0x488D, dword, SHADER_CONSTANT_FETCH_23_3) -XE_GPU_REGISTER(0x488E, dword, SHADER_CONSTANT_FETCH_23_4) -XE_GPU_REGISTER(0x488F, dword, SHADER_CONSTANT_FETCH_23_5) -XE_GPU_REGISTER(0x4890, dword, SHADER_CONSTANT_FETCH_24_0) -XE_GPU_REGISTER(0x4891, dword, SHADER_CONSTANT_FETCH_24_1) -XE_GPU_REGISTER(0x4892, dword, SHADER_CONSTANT_FETCH_24_2) -XE_GPU_REGISTER(0x4893, dword, SHADER_CONSTANT_FETCH_24_3) -XE_GPU_REGISTER(0x4894, dword, SHADER_CONSTANT_FETCH_24_4) -XE_GPU_REGISTER(0x4895, dword, SHADER_CONSTANT_FETCH_24_5) -XE_GPU_REGISTER(0x4896, dword, SHADER_CONSTANT_FETCH_25_0) -XE_GPU_REGISTER(0x4897, dword, SHADER_CONSTANT_FETCH_25_1) -XE_GPU_REGISTER(0x4898, dword, SHADER_CONSTANT_FETCH_25_2) -XE_GPU_REGISTER(0x4899, dword, SHADER_CONSTANT_FETCH_25_3) -XE_GPU_REGISTER(0x489A, dword, SHADER_CONSTANT_FETCH_25_4) -XE_GPU_REGISTER(0x489B, dword, SHADER_CONSTANT_FETCH_25_5) -XE_GPU_REGISTER(0x489C, dword, SHADER_CONSTANT_FETCH_26_0) -XE_GPU_REGISTER(0x489D, dword, SHADER_CONSTANT_FETCH_26_1) -XE_GPU_REGISTER(0x489E, dword, SHADER_CONSTANT_FETCH_26_2) -XE_GPU_REGISTER(0x489F, dword, SHADER_CONSTANT_FETCH_26_3) -XE_GPU_REGISTER(0x48A0, dword, SHADER_CONSTANT_FETCH_26_4) -XE_GPU_REGISTER(0x48A1, dword, SHADER_CONSTANT_FETCH_26_5) -XE_GPU_REGISTER(0x48A2, dword, SHADER_CONSTANT_FETCH_27_0) -XE_GPU_REGISTER(0x48A3, dword, SHADER_CONSTANT_FETCH_27_1) -XE_GPU_REGISTER(0x48A4, dword, SHADER_CONSTANT_FETCH_27_2) -XE_GPU_REGISTER(0x48A5, dword, SHADER_CONSTANT_FETCH_27_3) -XE_GPU_REGISTER(0x48A6, dword, SHADER_CONSTANT_FETCH_27_4) -XE_GPU_REGISTER(0x48A7, dword, SHADER_CONSTANT_FETCH_27_5) -XE_GPU_REGISTER(0x48A8, dword, SHADER_CONSTANT_FETCH_28_0) -XE_GPU_REGISTER(0x48A9, dword, SHADER_CONSTANT_FETCH_28_1) -XE_GPU_REGISTER(0x48AA, dword, SHADER_CONSTANT_FETCH_28_2) -XE_GPU_REGISTER(0x48AB, dword, SHADER_CONSTANT_FETCH_28_3) -XE_GPU_REGISTER(0x48AC, dword, SHADER_CONSTANT_FETCH_28_4) -XE_GPU_REGISTER(0x48AD, dword, SHADER_CONSTANT_FETCH_28_5) -XE_GPU_REGISTER(0x48AE, dword, SHADER_CONSTANT_FETCH_29_0) -XE_GPU_REGISTER(0x48AF, dword, SHADER_CONSTANT_FETCH_29_1) -XE_GPU_REGISTER(0x48B0, dword, SHADER_CONSTANT_FETCH_29_2) -XE_GPU_REGISTER(0x48B1, dword, SHADER_CONSTANT_FETCH_29_3) -XE_GPU_REGISTER(0x48B2, dword, SHADER_CONSTANT_FETCH_29_4) -XE_GPU_REGISTER(0x48B3, dword, SHADER_CONSTANT_FETCH_29_5) -XE_GPU_REGISTER(0x48B4, dword, SHADER_CONSTANT_FETCH_30_0) -XE_GPU_REGISTER(0x48B5, dword, SHADER_CONSTANT_FETCH_30_1) -XE_GPU_REGISTER(0x48B6, dword, SHADER_CONSTANT_FETCH_30_2) -XE_GPU_REGISTER(0x48B7, dword, SHADER_CONSTANT_FETCH_30_3) -XE_GPU_REGISTER(0x48B8, dword, SHADER_CONSTANT_FETCH_30_4) -XE_GPU_REGISTER(0x48B9, dword, SHADER_CONSTANT_FETCH_30_5) -XE_GPU_REGISTER(0x48BA, dword, SHADER_CONSTANT_FETCH_31_0) -XE_GPU_REGISTER(0x48BB, dword, SHADER_CONSTANT_FETCH_31_1) -XE_GPU_REGISTER(0x48BC, dword, SHADER_CONSTANT_FETCH_31_2) -XE_GPU_REGISTER(0x48BD, dword, SHADER_CONSTANT_FETCH_31_3) -XE_GPU_REGISTER(0x48BE, dword, SHADER_CONSTANT_FETCH_31_4) -XE_GPU_REGISTER(0x48BF, dword, SHADER_CONSTANT_FETCH_31_5) - -XE_GPU_REGISTER(0x4900, dword, SHADER_CONSTANT_BOOL_000_031) -XE_GPU_REGISTER(0x4901, dword, SHADER_CONSTANT_BOOL_032_063) -XE_GPU_REGISTER(0x4902, dword, SHADER_CONSTANT_BOOL_064_095) -XE_GPU_REGISTER(0x4903, dword, SHADER_CONSTANT_BOOL_096_127) -XE_GPU_REGISTER(0x4904, dword, SHADER_CONSTANT_BOOL_128_159) -XE_GPU_REGISTER(0x4905, dword, SHADER_CONSTANT_BOOL_160_191) -XE_GPU_REGISTER(0x4906, dword, SHADER_CONSTANT_BOOL_192_223) -XE_GPU_REGISTER(0x4907, dword, SHADER_CONSTANT_BOOL_224_255) - -XE_GPU_REGISTER(0x4908, dword, SHADER_CONSTANT_LOOP_00) -XE_GPU_REGISTER(0x4909, dword, SHADER_CONSTANT_LOOP_01) -XE_GPU_REGISTER(0x490A, dword, SHADER_CONSTANT_LOOP_02) -XE_GPU_REGISTER(0x490B, dword, SHADER_CONSTANT_LOOP_03) -XE_GPU_REGISTER(0x490C, dword, SHADER_CONSTANT_LOOP_04) -XE_GPU_REGISTER(0x490D, dword, SHADER_CONSTANT_LOOP_05) -XE_GPU_REGISTER(0x490E, dword, SHADER_CONSTANT_LOOP_06) -XE_GPU_REGISTER(0x490F, dword, SHADER_CONSTANT_LOOP_07) -XE_GPU_REGISTER(0x4910, dword, SHADER_CONSTANT_LOOP_08) -XE_GPU_REGISTER(0x4911, dword, SHADER_CONSTANT_LOOP_09) -XE_GPU_REGISTER(0x4912, dword, SHADER_CONSTANT_LOOP_10) -XE_GPU_REGISTER(0x4913, dword, SHADER_CONSTANT_LOOP_11) -XE_GPU_REGISTER(0x4914, dword, SHADER_CONSTANT_LOOP_12) -XE_GPU_REGISTER(0x4915, dword, SHADER_CONSTANT_LOOP_13) -XE_GPU_REGISTER(0x4916, dword, SHADER_CONSTANT_LOOP_14) -XE_GPU_REGISTER(0x4917, dword, SHADER_CONSTANT_LOOP_15) -XE_GPU_REGISTER(0x4918, dword, SHADER_CONSTANT_LOOP_16) -XE_GPU_REGISTER(0x4919, dword, SHADER_CONSTANT_LOOP_17) -XE_GPU_REGISTER(0x491A, dword, SHADER_CONSTANT_LOOP_18) -XE_GPU_REGISTER(0x491B, dword, SHADER_CONSTANT_LOOP_19) -XE_GPU_REGISTER(0x491C, dword, SHADER_CONSTANT_LOOP_20) -XE_GPU_REGISTER(0x491D, dword, SHADER_CONSTANT_LOOP_21) -XE_GPU_REGISTER(0x491E, dword, SHADER_CONSTANT_LOOP_22) -XE_GPU_REGISTER(0x491F, dword, SHADER_CONSTANT_LOOP_23) -XE_GPU_REGISTER(0x4920, dword, SHADER_CONSTANT_LOOP_24) -XE_GPU_REGISTER(0x4921, dword, SHADER_CONSTANT_LOOP_25) -XE_GPU_REGISTER(0x4922, dword, SHADER_CONSTANT_LOOP_26) -XE_GPU_REGISTER(0x4923, dword, SHADER_CONSTANT_LOOP_27) -XE_GPU_REGISTER(0x4924, dword, SHADER_CONSTANT_LOOP_28) -XE_GPU_REGISTER(0x4925, dword, SHADER_CONSTANT_LOOP_29) -XE_GPU_REGISTER(0x4926, dword, SHADER_CONSTANT_LOOP_30) -XE_GPU_REGISTER(0x4927, dword, SHADER_CONSTANT_LOOP_31) - -// Ignored because I have no clue what these are. -// XE_GPU_REGISTER(0x8D00, dword, UNKNOWN_8D00) -// XE_GPU_REGISTER(0x8D01, dword, UNKNOWN_8D01) -// XE_GPU_REGISTER(0x8D02, dword, UNKNOWN_8D02) -// XE_GPU_REGISTER(0x8D03, dword, UNKNOWN_8D03) -// XE_GPU_REGISTER(0x8D04, dword, UNKNOWN_8D04) -// XE_GPU_REGISTER(0x8D05, dword, UNKNOWN_8D05) -// XE_GPU_REGISTER(0x8D06, dword, UNKNOWN_8D06) -// XE_GPU_REGISTER(0x8D07, dword, UNKNOWN_8D07) +/** + ****************************************************************************** + * Xenia : Xbox 360 Emulator Research Project * + ****************************************************************************** + * Copyright 2013 Ben Vanik. All rights reserved. * + * Released under the BSD license - see LICENSE in the root for more details. * + ****************************************************************************** + */ + +// This is a partial file designed to be included by other files when +// constructing various tables. + +// Almost all of these values are taken directly from: +// https://github.com/freedreno/amd-gpu/blob/master/include/reg/yamato/22/yamato_offset.h + +//#define XE_GPU_REGISTER(index, type, name) + +XE_GPU_REGISTER(0x01DD, dword, SCRATCH_ADDR) +XE_GPU_REGISTER(0x01DC, dword, SCRATCH_UMSK) + +XE_GPU_REGISTER(0x0578, dword, SCRATCH_REG0) // interrupt sync +XE_GPU_REGISTER(0x0579, dword, SCRATCH_REG1) // present interval +XE_GPU_REGISTER(0x057A, dword, SCRATCH_REG2) +XE_GPU_REGISTER(0x057B, dword, SCRATCH_REG3) +XE_GPU_REGISTER(0x057C, dword, CALLBACK_ADDRESS) +XE_GPU_REGISTER(0x057D, dword, CALLBACK_CONTEXT) +XE_GPU_REGISTER(0x057E, dword, SCRATCH_REG6) +XE_GPU_REGISTER(0x057F, dword, SCRATCH_REG7) + +XE_GPU_REGISTER(0x05C8, dword, WAIT_UNTIL) + +XE_GPU_REGISTER(0x0A02, dword, UNKNOWN_0A02) +XE_GPU_REGISTER(0x0A03, dword, UNKNOWN_0A03) +XE_GPU_REGISTER(0x0A04, dword, UNKNOWN_0A04) +XE_GPU_REGISTER(0x0A05, dword, UNKNOWN_0A05) + +XE_GPU_REGISTER(0x0A2F, dword, COHER_SIZE_HOST) +XE_GPU_REGISTER(0x0A30, dword, COHER_BASE_HOST) +XE_GPU_REGISTER(0x0A31, dword, COHER_STATUS_HOST) + +XE_GPU_REGISTER(0x0D00, dword, SQ_GPR_MANAGEMENT) +XE_GPU_REGISTER(0x0D01, dword, SQ_FLOW_CONTROL) +XE_GPU_REGISTER(0x0D02, dword, SQ_INST_STORE_MANAGMENT) +XE_GPU_REGISTER(0x0D04, dword, SQ_EO_RT) + +XE_GPU_REGISTER(0x0C85, dword, PA_CL_ENHANCE) + +XE_GPU_REGISTER(0x0E42, dword, UNKNOWN_0E42) + +XE_GPU_REGISTER(0x0F01, dword, RB_BC_CONTROL) + +XE_GPU_REGISTER(0x2000, dword, RB_SURFACE_INFO) +XE_GPU_REGISTER(0x2001, dword, RB_COLOR_INFO) +XE_GPU_REGISTER(0x2002, dword, RB_DEPTH_INFO) +XE_GPU_REGISTER(0x2003, dword, RB_COLOR1_INFO) +XE_GPU_REGISTER(0x2004, dword, RB_COLOR2_INFO) +XE_GPU_REGISTER(0x2005, dword, RB_COLOR3_INFO) +XE_GPU_REGISTER(0x2006, dword, COHER_DEST_BASE_0) +XE_GPU_REGISTER(0x2007, dword, COHER_DEST_BASE_1) +XE_GPU_REGISTER(0x2008, dword, COHER_DEST_BASE_2) +XE_GPU_REGISTER(0x2009, dword, COHER_DEST_BASE_3) +XE_GPU_REGISTER(0x200A, dword, COHER_DEST_BASE_4) +XE_GPU_REGISTER(0x200B, dword, COHER_DEST_BASE_5) +XE_GPU_REGISTER(0x200C, dword, COHER_DEST_BASE_6) +XE_GPU_REGISTER(0x200D, dword, COHER_DEST_BASE_7) +XE_GPU_REGISTER(0x200E, dword, PA_SC_SCREEN_SCISSOR_TL) +XE_GPU_REGISTER(0x200F, dword, PA_SC_SCREEN_SCISSOR_BR) + +XE_GPU_REGISTER(0x2080, dword, PA_SC_WINDOW_OFFSET) +XE_GPU_REGISTER(0x2081, dword, PA_SC_WINDOW_SCISSOR_TL) +XE_GPU_REGISTER(0x2082, dword, PA_SC_WINDOW_SCISSOR_BR) + +XE_GPU_REGISTER(0x2100, dword, VGT_MAX_VTX_INDX) +XE_GPU_REGISTER(0x2101, dword, VGT_MIN_VTX_INDX) +XE_GPU_REGISTER(0x2102, dword, VGT_INDX_OFFSET) +XE_GPU_REGISTER(0x2103, dword, VGT_MULTI_PRIM_IB_RESET_INDX) +XE_GPU_REGISTER(0x2104, dword, RB_COLOR_MASK) +XE_GPU_REGISTER(0x2105, float, RB_BLEND_RED) +XE_GPU_REGISTER(0x2106, float, RB_BLEND_GREEN) +XE_GPU_REGISTER(0x2107, float, RB_BLEND_BLUE) +XE_GPU_REGISTER(0x2108, float, RB_BLEND_ALPHA) +XE_GPU_REGISTER(0x2109, float, RB_FOG_COLOR_RED) +XE_GPU_REGISTER(0x210A, float, RB_FOG_COLOR_GREEN) +XE_GPU_REGISTER(0x210B, float, RB_FOG_COLOR_BLUE) +XE_GPU_REGISTER(0x210C, dword, RB_STENCILREFMASK_BF) +XE_GPU_REGISTER(0x210D, dword, RB_STENCILREFMASK) +XE_GPU_REGISTER(0x210E, float, RB_ALPHA_REF) +XE_GPU_REGISTER(0x210F, float, PA_CL_VPORT_XSCALE) +XE_GPU_REGISTER(0x2110, float, PA_CL_VPORT_XOFFSET) +XE_GPU_REGISTER(0x2111, float, PA_CL_VPORT_YSCALE) +XE_GPU_REGISTER(0x2112, float, PA_CL_VPORT_YOFFSET) +XE_GPU_REGISTER(0x2113, float, PA_CL_VPORT_ZSCALE) +XE_GPU_REGISTER(0x2114, float, PA_CL_VPORT_ZOFFSET) + +XE_GPU_REGISTER(0x2180, dword, SQ_PROGRAM_CNTL) +XE_GPU_REGISTER(0x2181, dword, SQ_CONTEXT_MISC) +XE_GPU_REGISTER(0x2182, dword, SQ_INTERPOLATOR_CNTL) +XE_GPU_REGISTER(0x2183, dword, SQ_WRAPPING_0) +XE_GPU_REGISTER(0x2184, dword, SQ_WRAPPING_1) + +XE_GPU_REGISTER(0x21F9, dword, VGT_EVENT_INITIATOR) + +XE_GPU_REGISTER(0x2200, dword, RB_DEPTHCONTROL) +XE_GPU_REGISTER(0x2201, dword, RB_BLENDCONTROL_0) +XE_GPU_REGISTER(0x2202, dword, RB_COLORCONTROL) +XE_GPU_REGISTER(0x2203, dword, RB_TILECONTROL) +XE_GPU_REGISTER(0x2204, dword, PA_CL_CLIP_CNTL) +XE_GPU_REGISTER(0x2205, dword, PA_SU_SC_MODE_CNTL) +XE_GPU_REGISTER(0x2206, dword, PA_CL_VTE_CNTL) +XE_GPU_REGISTER(0x2207, dword, VGT_CURRENT_BIN_ID_MIN) +XE_GPU_REGISTER(0x2208, dword, RB_MODECONTROL) +XE_GPU_REGISTER(0x2209, dword, RB_BLENDCONTROL_1) +XE_GPU_REGISTER(0x220A, dword, RB_BLENDCONTROL_2) +XE_GPU_REGISTER(0x220B, dword, RB_BLENDCONTROL_3) + +XE_GPU_REGISTER(0x2280, dword, PA_SU_POINT_SIZE) +XE_GPU_REGISTER(0x2281, dword, PA_SU_POINT_MINMAX) +XE_GPU_REGISTER(0x2282, dword, PA_SU_LINE_CNTL) +XE_GPU_REGISTER(0x2283, dword, PA_SC_LINE_STIPPLE) +XE_GPU_REGISTER(0x2284, dword, VGT_OUTPUT_PATH_CNTL) +XE_GPU_REGISTER(0x2285, dword, VGT_HOS_CNTL) +XE_GPU_REGISTER(0x2286, float, VGT_HOS_MAX_TESS_LEVEL) +XE_GPU_REGISTER(0x2287, float, VGT_HOS_MIN_TESS_LEVEL) +XE_GPU_REGISTER(0x2288, dword, VGT_HOS_REUSE_DEPTH) +XE_GPU_REGISTER(0x2289, dword, VGT_GROUP_PRIM_TYPE) +XE_GPU_REGISTER(0x228A, dword, VGT_GROUP_FIRST_DECR) +XE_GPU_REGISTER(0x228B, dword, VGT_GROUP_DECR) +XE_GPU_REGISTER(0x228C, dword, VGT_GROUP_VECT_0_CNTL) +XE_GPU_REGISTER(0x228D, dword, VGT_GROUP_VECT_1_CNTL) +XE_GPU_REGISTER(0x228E, dword, VGT_GROUP_VECT_0_FMT_CNTL) +XE_GPU_REGISTER(0x228F, dword, VGT_GROUP_VECT_1_FMT_CNTL) +XE_GPU_REGISTER(0x2290, dword, UNKNOWN_2290) +XE_GPU_REGISTER(0x2291, dword, UNKNOWN_2291) +XE_GPU_REGISTER(0x2292, dword, PA_SC_MPASS_PS_CNTL) +XE_GPU_REGISTER(0x2293, dword, PA_SC_VIZ_QUERY) +XE_GPU_REGISTER(0x2294, dword, VGT_ENHANCE) + +XE_GPU_REGISTER(0x2300, dword, PA_SC_LINE_CNTL) +XE_GPU_REGISTER(0x2301, dword, PA_SC_AA_CONFIG) +XE_GPU_REGISTER(0x2302, dword, PA_SU_VTX_CNTL) +XE_GPU_REGISTER(0x2303, float, PA_CL_GB_VERT_CLIP_ADJ) +XE_GPU_REGISTER(0x2304, float, PA_CL_GB_VERT_DISC_ADJ) +XE_GPU_REGISTER(0x2305, float, PA_CL_GB_HORZ_CLIP_ADJ) +XE_GPU_REGISTER(0x2306, float, PA_CL_GB_HORZ_DISC_ADJ) +XE_GPU_REGISTER(0x2307, dword, SQ_VS_CONST) +XE_GPU_REGISTER(0x2308, dword, SQ_PS_CONST) +XE_GPU_REGISTER(0x2309, dword, SQ_DEBUG_MISC_0) +XE_GPU_REGISTER(0x230A, dword, SQ_DEBUG_MISC_1) +XE_GPU_REGISTER(0x230B, dword, UNKNOWN_230B) +XE_GPU_REGISTER(0x230C, dword, UNKNOWN_230C) +XE_GPU_REGISTER(0x230D, dword, UNKNOWN_230D) +XE_GPU_REGISTER(0x230E, dword, UNKNOWN_230E) +XE_GPU_REGISTER(0x230F, dword, UNKNOWN_230F) +XE_GPU_REGISTER(0x2310, dword, UNKNOWN_2310) +XE_GPU_REGISTER(0x2311, dword, UNKNOWN_2311) +XE_GPU_REGISTER(0x2312, dword, PA_SC_AA_MASK) +XE_GPU_REGISTER(0x2313, dword, UNKNOWN_2313) +XE_GPU_REGISTER(0x2314, dword, UNKNOWN_2314) +XE_GPU_REGISTER(0x2315, dword, SQ_CF_PROGRAM_SIZE) +XE_GPU_REGISTER(0x2316, dword, VGT_VERTEX_REUSE_BLOCK_CNTL) +XE_GPU_REGISTER(0x2317, dword, VGT_OUT_DEALLOC_CNTL) +XE_GPU_REGISTER(0x2318, dword, RB_COPY_CONTROL) +XE_GPU_REGISTER(0x2319, dword, RB_COPY_DEST_BASE) +XE_GPU_REGISTER(0x231A, dword, RB_COPY_DEST_PITCH) +XE_GPU_REGISTER(0x231B, dword, RB_COPY_DEST_INFO) +XE_GPU_REGISTER(0x231C, dword, RB_TILE_CLEAR) +XE_GPU_REGISTER(0x231D, dword, RB_DEPTH_CLEAR) +XE_GPU_REGISTER(0x231E, dword, RB_COLOR_CLEAR) +XE_GPU_REGISTER(0x231F, dword, RB_COLOR_CLEAR_LOW) +XE_GPU_REGISTER(0x2320, dword, RB_COPY_FUNC) +XE_GPU_REGISTER(0x2321, dword, RB_COPY_REF) +XE_GPU_REGISTER(0x2322, dword, RB_COPY_MASK) +XE_GPU_REGISTER(0x2323, dword, RB_COPY_SURFACE_SLICE) +XE_GPU_REGISTER(0x2324, dword, RB_SAMPLE_COUNT_CTL) +XE_GPU_REGISTER(0x2325, dword, RB_SAMPLE_COUNT_ADDR) + +XE_GPU_REGISTER(0x2380, float, PA_SU_POLY_OFFSET_FRONT_SCALE) +XE_GPU_REGISTER(0x2381, float, PA_SU_POLY_OFFSET_FRONT_OFFSET) +XE_GPU_REGISTER(0x2382, float, PA_SU_POLY_OFFSET_BACK_SCALE) +XE_GPU_REGISTER(0x2383, float, PA_SU_POLY_OFFSET_BACK_OFFSET) +XE_GPU_REGISTER(0x2384, float, PA_CL_POINT_X_RAD) +XE_GPU_REGISTER(0x2385, float, PA_CL_POINT_Y_RAD) +XE_GPU_REGISTER(0x2386, float, PA_CL_POINT_SIZE) +XE_GPU_REGISTER(0x2387, float, PA_CL_POINT_CULL_RAD) + +XE_GPU_REGISTER(0x4000, float, SHADER_CONSTANT_000_X) +XE_GPU_REGISTER(0x4001, float, SHADER_CONSTANT_000_Y) +XE_GPU_REGISTER(0x4002, float, SHADER_CONSTANT_000_Z) +XE_GPU_REGISTER(0x4003, float, SHADER_CONSTANT_000_W) +XE_GPU_REGISTER(0x4004, float, SHADER_CONSTANT_001_X) +XE_GPU_REGISTER(0x4005, float, SHADER_CONSTANT_001_Y) +XE_GPU_REGISTER(0x4006, float, SHADER_CONSTANT_001_Z) +XE_GPU_REGISTER(0x4007, float, SHADER_CONSTANT_001_W) +XE_GPU_REGISTER(0x4008, float, SHADER_CONSTANT_002_X) +XE_GPU_REGISTER(0x4009, float, SHADER_CONSTANT_002_Y) +XE_GPU_REGISTER(0x400A, float, SHADER_CONSTANT_002_Z) +XE_GPU_REGISTER(0x400B, float, SHADER_CONSTANT_002_W) +XE_GPU_REGISTER(0x400C, float, SHADER_CONSTANT_003_X) +XE_GPU_REGISTER(0x400D, float, SHADER_CONSTANT_003_Y) +XE_GPU_REGISTER(0x400E, float, SHADER_CONSTANT_003_Z) +XE_GPU_REGISTER(0x400F, float, SHADER_CONSTANT_003_W) +XE_GPU_REGISTER(0x4010, float, SHADER_CONSTANT_004_X) +XE_GPU_REGISTER(0x4011, float, SHADER_CONSTANT_004_Y) +XE_GPU_REGISTER(0x4012, float, SHADER_CONSTANT_004_Z) +XE_GPU_REGISTER(0x4013, float, SHADER_CONSTANT_004_W) +XE_GPU_REGISTER(0x4014, float, SHADER_CONSTANT_005_X) +XE_GPU_REGISTER(0x4015, float, SHADER_CONSTANT_005_Y) +XE_GPU_REGISTER(0x4016, float, SHADER_CONSTANT_005_Z) +XE_GPU_REGISTER(0x4017, float, SHADER_CONSTANT_005_W) +XE_GPU_REGISTER(0x4018, float, SHADER_CONSTANT_006_X) +XE_GPU_REGISTER(0x4019, float, SHADER_CONSTANT_006_Y) +XE_GPU_REGISTER(0x401A, float, SHADER_CONSTANT_006_Z) +XE_GPU_REGISTER(0x401B, float, SHADER_CONSTANT_006_W) +XE_GPU_REGISTER(0x401C, float, SHADER_CONSTANT_007_X) +XE_GPU_REGISTER(0x401D, float, SHADER_CONSTANT_007_Y) +XE_GPU_REGISTER(0x401E, float, SHADER_CONSTANT_007_Z) +XE_GPU_REGISTER(0x401F, float, SHADER_CONSTANT_007_W) +XE_GPU_REGISTER(0x4020, float, SHADER_CONSTANT_008_X) +XE_GPU_REGISTER(0x4021, float, SHADER_CONSTANT_008_Y) +XE_GPU_REGISTER(0x4022, float, SHADER_CONSTANT_008_Z) +XE_GPU_REGISTER(0x4023, float, SHADER_CONSTANT_008_W) +XE_GPU_REGISTER(0x4024, float, SHADER_CONSTANT_009_X) +XE_GPU_REGISTER(0x4025, float, SHADER_CONSTANT_009_Y) +XE_GPU_REGISTER(0x4026, float, SHADER_CONSTANT_009_Z) +XE_GPU_REGISTER(0x4027, float, SHADER_CONSTANT_009_W) +XE_GPU_REGISTER(0x4028, float, SHADER_CONSTANT_010_X) +XE_GPU_REGISTER(0x4029, float, SHADER_CONSTANT_010_Y) +XE_GPU_REGISTER(0x402A, float, SHADER_CONSTANT_010_Z) +XE_GPU_REGISTER(0x402B, float, SHADER_CONSTANT_010_W) +XE_GPU_REGISTER(0x402C, float, SHADER_CONSTANT_011_X) +XE_GPU_REGISTER(0x402D, float, SHADER_CONSTANT_011_Y) +XE_GPU_REGISTER(0x402E, float, SHADER_CONSTANT_011_Z) +XE_GPU_REGISTER(0x402F, float, SHADER_CONSTANT_011_W) +XE_GPU_REGISTER(0x4030, float, SHADER_CONSTANT_012_X) +XE_GPU_REGISTER(0x4031, float, SHADER_CONSTANT_012_Y) +XE_GPU_REGISTER(0x4032, float, SHADER_CONSTANT_012_Z) +XE_GPU_REGISTER(0x4033, float, SHADER_CONSTANT_012_W) +XE_GPU_REGISTER(0x4034, float, SHADER_CONSTANT_013_X) +XE_GPU_REGISTER(0x4035, float, SHADER_CONSTANT_013_Y) +XE_GPU_REGISTER(0x4036, float, SHADER_CONSTANT_013_Z) +XE_GPU_REGISTER(0x4037, float, SHADER_CONSTANT_013_W) +XE_GPU_REGISTER(0x4038, float, SHADER_CONSTANT_014_X) +XE_GPU_REGISTER(0x4039, float, SHADER_CONSTANT_014_Y) +XE_GPU_REGISTER(0x403A, float, SHADER_CONSTANT_014_Z) +XE_GPU_REGISTER(0x403B, float, SHADER_CONSTANT_014_W) +XE_GPU_REGISTER(0x403C, float, SHADER_CONSTANT_015_X) +XE_GPU_REGISTER(0x403D, float, SHADER_CONSTANT_015_Y) +XE_GPU_REGISTER(0x403E, float, SHADER_CONSTANT_015_Z) +XE_GPU_REGISTER(0x403F, float, SHADER_CONSTANT_015_W) +XE_GPU_REGISTER(0x4040, float, SHADER_CONSTANT_016_X) +XE_GPU_REGISTER(0x4041, float, SHADER_CONSTANT_016_Y) +XE_GPU_REGISTER(0x4042, float, SHADER_CONSTANT_016_Z) +XE_GPU_REGISTER(0x4043, float, SHADER_CONSTANT_016_W) +XE_GPU_REGISTER(0x4044, float, SHADER_CONSTANT_017_X) +XE_GPU_REGISTER(0x4045, float, SHADER_CONSTANT_017_Y) +XE_GPU_REGISTER(0x4046, float, SHADER_CONSTANT_017_Z) +XE_GPU_REGISTER(0x4047, float, SHADER_CONSTANT_017_W) +XE_GPU_REGISTER(0x4048, float, SHADER_CONSTANT_018_X) +XE_GPU_REGISTER(0x4049, float, SHADER_CONSTANT_018_Y) +XE_GPU_REGISTER(0x404A, float, SHADER_CONSTANT_018_Z) +XE_GPU_REGISTER(0x404B, float, SHADER_CONSTANT_018_W) +XE_GPU_REGISTER(0x404C, float, SHADER_CONSTANT_019_X) +XE_GPU_REGISTER(0x404D, float, SHADER_CONSTANT_019_Y) +XE_GPU_REGISTER(0x404E, float, SHADER_CONSTANT_019_Z) +XE_GPU_REGISTER(0x404F, float, SHADER_CONSTANT_019_W) +XE_GPU_REGISTER(0x4050, float, SHADER_CONSTANT_020_X) +XE_GPU_REGISTER(0x4051, float, SHADER_CONSTANT_020_Y) +XE_GPU_REGISTER(0x4052, float, SHADER_CONSTANT_020_Z) +XE_GPU_REGISTER(0x4053, float, SHADER_CONSTANT_020_W) +XE_GPU_REGISTER(0x4054, float, SHADER_CONSTANT_021_X) +XE_GPU_REGISTER(0x4055, float, SHADER_CONSTANT_021_Y) +XE_GPU_REGISTER(0x4056, float, SHADER_CONSTANT_021_Z) +XE_GPU_REGISTER(0x4057, float, SHADER_CONSTANT_021_W) +XE_GPU_REGISTER(0x4058, float, SHADER_CONSTANT_022_X) +XE_GPU_REGISTER(0x4059, float, SHADER_CONSTANT_022_Y) +XE_GPU_REGISTER(0x405A, float, SHADER_CONSTANT_022_Z) +XE_GPU_REGISTER(0x405B, float, SHADER_CONSTANT_022_W) +XE_GPU_REGISTER(0x405C, float, SHADER_CONSTANT_023_X) +XE_GPU_REGISTER(0x405D, float, SHADER_CONSTANT_023_Y) +XE_GPU_REGISTER(0x405E, float, SHADER_CONSTANT_023_Z) +XE_GPU_REGISTER(0x405F, float, SHADER_CONSTANT_023_W) +XE_GPU_REGISTER(0x4060, float, SHADER_CONSTANT_024_X) +XE_GPU_REGISTER(0x4061, float, SHADER_CONSTANT_024_Y) +XE_GPU_REGISTER(0x4062, float, SHADER_CONSTANT_024_Z) +XE_GPU_REGISTER(0x4063, float, SHADER_CONSTANT_024_W) +XE_GPU_REGISTER(0x4064, float, SHADER_CONSTANT_025_X) +XE_GPU_REGISTER(0x4065, float, SHADER_CONSTANT_025_Y) +XE_GPU_REGISTER(0x4066, float, SHADER_CONSTANT_025_Z) +XE_GPU_REGISTER(0x4067, float, SHADER_CONSTANT_025_W) +XE_GPU_REGISTER(0x4068, float, SHADER_CONSTANT_026_X) +XE_GPU_REGISTER(0x4069, float, SHADER_CONSTANT_026_Y) +XE_GPU_REGISTER(0x406A, float, SHADER_CONSTANT_026_Z) +XE_GPU_REGISTER(0x406B, float, SHADER_CONSTANT_026_W) +XE_GPU_REGISTER(0x406C, float, SHADER_CONSTANT_027_X) +XE_GPU_REGISTER(0x406D, float, SHADER_CONSTANT_027_Y) +XE_GPU_REGISTER(0x406E, float, SHADER_CONSTANT_027_Z) +XE_GPU_REGISTER(0x406F, float, SHADER_CONSTANT_027_W) +XE_GPU_REGISTER(0x4070, float, SHADER_CONSTANT_028_X) +XE_GPU_REGISTER(0x4071, float, SHADER_CONSTANT_028_Y) +XE_GPU_REGISTER(0x4072, float, SHADER_CONSTANT_028_Z) +XE_GPU_REGISTER(0x4073, float, SHADER_CONSTANT_028_W) +XE_GPU_REGISTER(0x4074, float, SHADER_CONSTANT_029_X) +XE_GPU_REGISTER(0x4075, float, SHADER_CONSTANT_029_Y) +XE_GPU_REGISTER(0x4076, float, SHADER_CONSTANT_029_Z) +XE_GPU_REGISTER(0x4077, float, SHADER_CONSTANT_029_W) +XE_GPU_REGISTER(0x4078, float, SHADER_CONSTANT_030_X) +XE_GPU_REGISTER(0x4079, float, SHADER_CONSTANT_030_Y) +XE_GPU_REGISTER(0x407A, float, SHADER_CONSTANT_030_Z) +XE_GPU_REGISTER(0x407B, float, SHADER_CONSTANT_030_W) +XE_GPU_REGISTER(0x407C, float, SHADER_CONSTANT_031_X) +XE_GPU_REGISTER(0x407D, float, SHADER_CONSTANT_031_Y) +XE_GPU_REGISTER(0x407E, float, SHADER_CONSTANT_031_Z) +XE_GPU_REGISTER(0x407F, float, SHADER_CONSTANT_031_W) +XE_GPU_REGISTER(0x4080, float, SHADER_CONSTANT_032_X) +XE_GPU_REGISTER(0x4081, float, SHADER_CONSTANT_032_Y) +XE_GPU_REGISTER(0x4082, float, SHADER_CONSTANT_032_Z) +XE_GPU_REGISTER(0x4083, float, SHADER_CONSTANT_032_W) +XE_GPU_REGISTER(0x4084, float, SHADER_CONSTANT_033_X) +XE_GPU_REGISTER(0x4085, float, SHADER_CONSTANT_033_Y) +XE_GPU_REGISTER(0x4086, float, SHADER_CONSTANT_033_Z) +XE_GPU_REGISTER(0x4087, float, SHADER_CONSTANT_033_W) +XE_GPU_REGISTER(0x4088, float, SHADER_CONSTANT_034_X) +XE_GPU_REGISTER(0x4089, float, SHADER_CONSTANT_034_Y) +XE_GPU_REGISTER(0x408A, float, SHADER_CONSTANT_034_Z) +XE_GPU_REGISTER(0x408B, float, SHADER_CONSTANT_034_W) +XE_GPU_REGISTER(0x408C, float, SHADER_CONSTANT_035_X) +XE_GPU_REGISTER(0x408D, float, SHADER_CONSTANT_035_Y) +XE_GPU_REGISTER(0x408E, float, SHADER_CONSTANT_035_Z) +XE_GPU_REGISTER(0x408F, float, SHADER_CONSTANT_035_W) +XE_GPU_REGISTER(0x4090, float, SHADER_CONSTANT_036_X) +XE_GPU_REGISTER(0x4091, float, SHADER_CONSTANT_036_Y) +XE_GPU_REGISTER(0x4092, float, SHADER_CONSTANT_036_Z) +XE_GPU_REGISTER(0x4093, float, SHADER_CONSTANT_036_W) +XE_GPU_REGISTER(0x4094, float, SHADER_CONSTANT_037_X) +XE_GPU_REGISTER(0x4095, float, SHADER_CONSTANT_037_Y) +XE_GPU_REGISTER(0x4096, float, SHADER_CONSTANT_037_Z) +XE_GPU_REGISTER(0x4097, float, SHADER_CONSTANT_037_W) +XE_GPU_REGISTER(0x4098, float, SHADER_CONSTANT_038_X) +XE_GPU_REGISTER(0x4099, float, SHADER_CONSTANT_038_Y) +XE_GPU_REGISTER(0x409A, float, SHADER_CONSTANT_038_Z) +XE_GPU_REGISTER(0x409B, float, SHADER_CONSTANT_038_W) +XE_GPU_REGISTER(0x409C, float, SHADER_CONSTANT_039_X) +XE_GPU_REGISTER(0x409D, float, SHADER_CONSTANT_039_Y) +XE_GPU_REGISTER(0x409E, float, SHADER_CONSTANT_039_Z) +XE_GPU_REGISTER(0x409F, float, SHADER_CONSTANT_039_W) +XE_GPU_REGISTER(0x40A0, float, SHADER_CONSTANT_040_X) +XE_GPU_REGISTER(0x40A1, float, SHADER_CONSTANT_040_Y) +XE_GPU_REGISTER(0x40A2, float, SHADER_CONSTANT_040_Z) +XE_GPU_REGISTER(0x40A3, float, SHADER_CONSTANT_040_W) +XE_GPU_REGISTER(0x40A4, float, SHADER_CONSTANT_041_X) +XE_GPU_REGISTER(0x40A5, float, SHADER_CONSTANT_041_Y) +XE_GPU_REGISTER(0x40A6, float, SHADER_CONSTANT_041_Z) +XE_GPU_REGISTER(0x40A7, float, SHADER_CONSTANT_041_W) +XE_GPU_REGISTER(0x40A8, float, SHADER_CONSTANT_042_X) +XE_GPU_REGISTER(0x40A9, float, SHADER_CONSTANT_042_Y) +XE_GPU_REGISTER(0x40AA, float, SHADER_CONSTANT_042_Z) +XE_GPU_REGISTER(0x40AB, float, SHADER_CONSTANT_042_W) +XE_GPU_REGISTER(0x40AC, float, SHADER_CONSTANT_043_X) +XE_GPU_REGISTER(0x40AD, float, SHADER_CONSTANT_043_Y) +XE_GPU_REGISTER(0x40AE, float, SHADER_CONSTANT_043_Z) +XE_GPU_REGISTER(0x40AF, float, SHADER_CONSTANT_043_W) +XE_GPU_REGISTER(0x40B0, float, SHADER_CONSTANT_044_X) +XE_GPU_REGISTER(0x40B1, float, SHADER_CONSTANT_044_Y) +XE_GPU_REGISTER(0x40B2, float, SHADER_CONSTANT_044_Z) +XE_GPU_REGISTER(0x40B3, float, SHADER_CONSTANT_044_W) +XE_GPU_REGISTER(0x40B4, float, SHADER_CONSTANT_045_X) +XE_GPU_REGISTER(0x40B5, float, SHADER_CONSTANT_045_Y) +XE_GPU_REGISTER(0x40B6, float, SHADER_CONSTANT_045_Z) +XE_GPU_REGISTER(0x40B7, float, SHADER_CONSTANT_045_W) +XE_GPU_REGISTER(0x40B8, float, SHADER_CONSTANT_046_X) +XE_GPU_REGISTER(0x40B9, float, SHADER_CONSTANT_046_Y) +XE_GPU_REGISTER(0x40BA, float, SHADER_CONSTANT_046_Z) +XE_GPU_REGISTER(0x40BB, float, SHADER_CONSTANT_046_W) +XE_GPU_REGISTER(0x40BC, float, SHADER_CONSTANT_047_X) +XE_GPU_REGISTER(0x40BD, float, SHADER_CONSTANT_047_Y) +XE_GPU_REGISTER(0x40BE, float, SHADER_CONSTANT_047_Z) +XE_GPU_REGISTER(0x40BF, float, SHADER_CONSTANT_047_W) +XE_GPU_REGISTER(0x40C0, float, SHADER_CONSTANT_048_X) +XE_GPU_REGISTER(0x40C1, float, SHADER_CONSTANT_048_Y) +XE_GPU_REGISTER(0x40C2, float, SHADER_CONSTANT_048_Z) +XE_GPU_REGISTER(0x40C3, float, SHADER_CONSTANT_048_W) +XE_GPU_REGISTER(0x40C4, float, SHADER_CONSTANT_049_X) +XE_GPU_REGISTER(0x40C5, float, SHADER_CONSTANT_049_Y) +XE_GPU_REGISTER(0x40C6, float, SHADER_CONSTANT_049_Z) +XE_GPU_REGISTER(0x40C7, float, SHADER_CONSTANT_049_W) +XE_GPU_REGISTER(0x40C8, float, SHADER_CONSTANT_050_X) +XE_GPU_REGISTER(0x40C9, float, SHADER_CONSTANT_050_Y) +XE_GPU_REGISTER(0x40CA, float, SHADER_CONSTANT_050_Z) +XE_GPU_REGISTER(0x40CB, float, SHADER_CONSTANT_050_W) +XE_GPU_REGISTER(0x40CC, float, SHADER_CONSTANT_051_X) +XE_GPU_REGISTER(0x40CD, float, SHADER_CONSTANT_051_Y) +XE_GPU_REGISTER(0x40CE, float, SHADER_CONSTANT_051_Z) +XE_GPU_REGISTER(0x40CF, float, SHADER_CONSTANT_051_W) +XE_GPU_REGISTER(0x40D0, float, SHADER_CONSTANT_052_X) +XE_GPU_REGISTER(0x40D1, float, SHADER_CONSTANT_052_Y) +XE_GPU_REGISTER(0x40D2, float, SHADER_CONSTANT_052_Z) +XE_GPU_REGISTER(0x40D3, float, SHADER_CONSTANT_052_W) +XE_GPU_REGISTER(0x40D4, float, SHADER_CONSTANT_053_X) +XE_GPU_REGISTER(0x40D5, float, SHADER_CONSTANT_053_Y) +XE_GPU_REGISTER(0x40D6, float, SHADER_CONSTANT_053_Z) +XE_GPU_REGISTER(0x40D7, float, SHADER_CONSTANT_053_W) +XE_GPU_REGISTER(0x40D8, float, SHADER_CONSTANT_054_X) +XE_GPU_REGISTER(0x40D9, float, SHADER_CONSTANT_054_Y) +XE_GPU_REGISTER(0x40DA, float, SHADER_CONSTANT_054_Z) +XE_GPU_REGISTER(0x40DB, float, SHADER_CONSTANT_054_W) +XE_GPU_REGISTER(0x40DC, float, SHADER_CONSTANT_055_X) +XE_GPU_REGISTER(0x40DD, float, SHADER_CONSTANT_055_Y) +XE_GPU_REGISTER(0x40DE, float, SHADER_CONSTANT_055_Z) +XE_GPU_REGISTER(0x40DF, float, SHADER_CONSTANT_055_W) +XE_GPU_REGISTER(0x40E0, float, SHADER_CONSTANT_056_X) +XE_GPU_REGISTER(0x40E1, float, SHADER_CONSTANT_056_Y) +XE_GPU_REGISTER(0x40E2, float, SHADER_CONSTANT_056_Z) +XE_GPU_REGISTER(0x40E3, float, SHADER_CONSTANT_056_W) +XE_GPU_REGISTER(0x40E4, float, SHADER_CONSTANT_057_X) +XE_GPU_REGISTER(0x40E5, float, SHADER_CONSTANT_057_Y) +XE_GPU_REGISTER(0x40E6, float, SHADER_CONSTANT_057_Z) +XE_GPU_REGISTER(0x40E7, float, SHADER_CONSTANT_057_W) +XE_GPU_REGISTER(0x40E8, float, SHADER_CONSTANT_058_X) +XE_GPU_REGISTER(0x40E9, float, SHADER_CONSTANT_058_Y) +XE_GPU_REGISTER(0x40EA, float, SHADER_CONSTANT_058_Z) +XE_GPU_REGISTER(0x40EB, float, SHADER_CONSTANT_058_W) +XE_GPU_REGISTER(0x40EC, float, SHADER_CONSTANT_059_X) +XE_GPU_REGISTER(0x40ED, float, SHADER_CONSTANT_059_Y) +XE_GPU_REGISTER(0x40EE, float, SHADER_CONSTANT_059_Z) +XE_GPU_REGISTER(0x40EF, float, SHADER_CONSTANT_059_W) +XE_GPU_REGISTER(0x40F0, float, SHADER_CONSTANT_060_X) +XE_GPU_REGISTER(0x40F1, float, SHADER_CONSTANT_060_Y) +XE_GPU_REGISTER(0x40F2, float, SHADER_CONSTANT_060_Z) +XE_GPU_REGISTER(0x40F3, float, SHADER_CONSTANT_060_W) +XE_GPU_REGISTER(0x40F4, float, SHADER_CONSTANT_061_X) +XE_GPU_REGISTER(0x40F5, float, SHADER_CONSTANT_061_Y) +XE_GPU_REGISTER(0x40F6, float, SHADER_CONSTANT_061_Z) +XE_GPU_REGISTER(0x40F7, float, SHADER_CONSTANT_061_W) +XE_GPU_REGISTER(0x40F8, float, SHADER_CONSTANT_062_X) +XE_GPU_REGISTER(0x40F9, float, SHADER_CONSTANT_062_Y) +XE_GPU_REGISTER(0x40FA, float, SHADER_CONSTANT_062_Z) +XE_GPU_REGISTER(0x40FB, float, SHADER_CONSTANT_062_W) +XE_GPU_REGISTER(0x40FC, float, SHADER_CONSTANT_063_X) +XE_GPU_REGISTER(0x40FD, float, SHADER_CONSTANT_063_Y) +XE_GPU_REGISTER(0x40FE, float, SHADER_CONSTANT_063_Z) +XE_GPU_REGISTER(0x40FF, float, SHADER_CONSTANT_063_W) +XE_GPU_REGISTER(0x4100, float, SHADER_CONSTANT_064_X) +XE_GPU_REGISTER(0x4101, float, SHADER_CONSTANT_064_Y) +XE_GPU_REGISTER(0x4102, float, SHADER_CONSTANT_064_Z) +XE_GPU_REGISTER(0x4103, float, SHADER_CONSTANT_064_W) +XE_GPU_REGISTER(0x4104, float, SHADER_CONSTANT_065_X) +XE_GPU_REGISTER(0x4105, float, SHADER_CONSTANT_065_Y) +XE_GPU_REGISTER(0x4106, float, SHADER_CONSTANT_065_Z) +XE_GPU_REGISTER(0x4107, float, SHADER_CONSTANT_065_W) +XE_GPU_REGISTER(0x4108, float, SHADER_CONSTANT_066_X) +XE_GPU_REGISTER(0x4109, float, SHADER_CONSTANT_066_Y) +XE_GPU_REGISTER(0x410A, float, SHADER_CONSTANT_066_Z) +XE_GPU_REGISTER(0x410B, float, SHADER_CONSTANT_066_W) +XE_GPU_REGISTER(0x410C, float, SHADER_CONSTANT_067_X) +XE_GPU_REGISTER(0x410D, float, SHADER_CONSTANT_067_Y) +XE_GPU_REGISTER(0x410E, float, SHADER_CONSTANT_067_Z) +XE_GPU_REGISTER(0x410F, float, SHADER_CONSTANT_067_W) +XE_GPU_REGISTER(0x4110, float, SHADER_CONSTANT_068_X) +XE_GPU_REGISTER(0x4111, float, SHADER_CONSTANT_068_Y) +XE_GPU_REGISTER(0x4112, float, SHADER_CONSTANT_068_Z) +XE_GPU_REGISTER(0x4113, float, SHADER_CONSTANT_068_W) +XE_GPU_REGISTER(0x4114, float, SHADER_CONSTANT_069_X) +XE_GPU_REGISTER(0x4115, float, SHADER_CONSTANT_069_Y) +XE_GPU_REGISTER(0x4116, float, SHADER_CONSTANT_069_Z) +XE_GPU_REGISTER(0x4117, float, SHADER_CONSTANT_069_W) +XE_GPU_REGISTER(0x4118, float, SHADER_CONSTANT_070_X) +XE_GPU_REGISTER(0x4119, float, SHADER_CONSTANT_070_Y) +XE_GPU_REGISTER(0x411A, float, SHADER_CONSTANT_070_Z) +XE_GPU_REGISTER(0x411B, float, SHADER_CONSTANT_070_W) +XE_GPU_REGISTER(0x411C, float, SHADER_CONSTANT_071_X) +XE_GPU_REGISTER(0x411D, float, SHADER_CONSTANT_071_Y) +XE_GPU_REGISTER(0x411E, float, SHADER_CONSTANT_071_Z) +XE_GPU_REGISTER(0x411F, float, SHADER_CONSTANT_071_W) +XE_GPU_REGISTER(0x4120, float, SHADER_CONSTANT_072_X) +XE_GPU_REGISTER(0x4121, float, SHADER_CONSTANT_072_Y) +XE_GPU_REGISTER(0x4122, float, SHADER_CONSTANT_072_Z) +XE_GPU_REGISTER(0x4123, float, SHADER_CONSTANT_072_W) +XE_GPU_REGISTER(0x4124, float, SHADER_CONSTANT_073_X) +XE_GPU_REGISTER(0x4125, float, SHADER_CONSTANT_073_Y) +XE_GPU_REGISTER(0x4126, float, SHADER_CONSTANT_073_Z) +XE_GPU_REGISTER(0x4127, float, SHADER_CONSTANT_073_W) +XE_GPU_REGISTER(0x4128, float, SHADER_CONSTANT_074_X) +XE_GPU_REGISTER(0x4129, float, SHADER_CONSTANT_074_Y) +XE_GPU_REGISTER(0x412A, float, SHADER_CONSTANT_074_Z) +XE_GPU_REGISTER(0x412B, float, SHADER_CONSTANT_074_W) +XE_GPU_REGISTER(0x412C, float, SHADER_CONSTANT_075_X) +XE_GPU_REGISTER(0x412D, float, SHADER_CONSTANT_075_Y) +XE_GPU_REGISTER(0x412E, float, SHADER_CONSTANT_075_Z) +XE_GPU_REGISTER(0x412F, float, SHADER_CONSTANT_075_W) +XE_GPU_REGISTER(0x4130, float, SHADER_CONSTANT_076_X) +XE_GPU_REGISTER(0x4131, float, SHADER_CONSTANT_076_Y) +XE_GPU_REGISTER(0x4132, float, SHADER_CONSTANT_076_Z) +XE_GPU_REGISTER(0x4133, float, SHADER_CONSTANT_076_W) +XE_GPU_REGISTER(0x4134, float, SHADER_CONSTANT_077_X) +XE_GPU_REGISTER(0x4135, float, SHADER_CONSTANT_077_Y) +XE_GPU_REGISTER(0x4136, float, SHADER_CONSTANT_077_Z) +XE_GPU_REGISTER(0x4137, float, SHADER_CONSTANT_077_W) +XE_GPU_REGISTER(0x4138, float, SHADER_CONSTANT_078_X) +XE_GPU_REGISTER(0x4139, float, SHADER_CONSTANT_078_Y) +XE_GPU_REGISTER(0x413A, float, SHADER_CONSTANT_078_Z) +XE_GPU_REGISTER(0x413B, float, SHADER_CONSTANT_078_W) +XE_GPU_REGISTER(0x413C, float, SHADER_CONSTANT_079_X) +XE_GPU_REGISTER(0x413D, float, SHADER_CONSTANT_079_Y) +XE_GPU_REGISTER(0x413E, float, SHADER_CONSTANT_079_Z) +XE_GPU_REGISTER(0x413F, float, SHADER_CONSTANT_079_W) +XE_GPU_REGISTER(0x4140, float, SHADER_CONSTANT_080_X) +XE_GPU_REGISTER(0x4141, float, SHADER_CONSTANT_080_Y) +XE_GPU_REGISTER(0x4142, float, SHADER_CONSTANT_080_Z) +XE_GPU_REGISTER(0x4143, float, SHADER_CONSTANT_080_W) +XE_GPU_REGISTER(0x4144, float, SHADER_CONSTANT_081_X) +XE_GPU_REGISTER(0x4145, float, SHADER_CONSTANT_081_Y) +XE_GPU_REGISTER(0x4146, float, SHADER_CONSTANT_081_Z) +XE_GPU_REGISTER(0x4147, float, SHADER_CONSTANT_081_W) +XE_GPU_REGISTER(0x4148, float, SHADER_CONSTANT_082_X) +XE_GPU_REGISTER(0x4149, float, SHADER_CONSTANT_082_Y) +XE_GPU_REGISTER(0x414A, float, SHADER_CONSTANT_082_Z) +XE_GPU_REGISTER(0x414B, float, SHADER_CONSTANT_082_W) +XE_GPU_REGISTER(0x414C, float, SHADER_CONSTANT_083_X) +XE_GPU_REGISTER(0x414D, float, SHADER_CONSTANT_083_Y) +XE_GPU_REGISTER(0x414E, float, SHADER_CONSTANT_083_Z) +XE_GPU_REGISTER(0x414F, float, SHADER_CONSTANT_083_W) +XE_GPU_REGISTER(0x4150, float, SHADER_CONSTANT_084_X) +XE_GPU_REGISTER(0x4151, float, SHADER_CONSTANT_084_Y) +XE_GPU_REGISTER(0x4152, float, SHADER_CONSTANT_084_Z) +XE_GPU_REGISTER(0x4153, float, SHADER_CONSTANT_084_W) +XE_GPU_REGISTER(0x4154, float, SHADER_CONSTANT_085_X) +XE_GPU_REGISTER(0x4155, float, SHADER_CONSTANT_085_Y) +XE_GPU_REGISTER(0x4156, float, SHADER_CONSTANT_085_Z) +XE_GPU_REGISTER(0x4157, float, SHADER_CONSTANT_085_W) +XE_GPU_REGISTER(0x4158, float, SHADER_CONSTANT_086_X) +XE_GPU_REGISTER(0x4159, float, SHADER_CONSTANT_086_Y) +XE_GPU_REGISTER(0x415A, float, SHADER_CONSTANT_086_Z) +XE_GPU_REGISTER(0x415B, float, SHADER_CONSTANT_086_W) +XE_GPU_REGISTER(0x415C, float, SHADER_CONSTANT_087_X) +XE_GPU_REGISTER(0x415D, float, SHADER_CONSTANT_087_Y) +XE_GPU_REGISTER(0x415E, float, SHADER_CONSTANT_087_Z) +XE_GPU_REGISTER(0x415F, float, SHADER_CONSTANT_087_W) +XE_GPU_REGISTER(0x4160, float, SHADER_CONSTANT_088_X) +XE_GPU_REGISTER(0x4161, float, SHADER_CONSTANT_088_Y) +XE_GPU_REGISTER(0x4162, float, SHADER_CONSTANT_088_Z) +XE_GPU_REGISTER(0x4163, float, SHADER_CONSTANT_088_W) +XE_GPU_REGISTER(0x4164, float, SHADER_CONSTANT_089_X) +XE_GPU_REGISTER(0x4165, float, SHADER_CONSTANT_089_Y) +XE_GPU_REGISTER(0x4166, float, SHADER_CONSTANT_089_Z) +XE_GPU_REGISTER(0x4167, float, SHADER_CONSTANT_089_W) +XE_GPU_REGISTER(0x4168, float, SHADER_CONSTANT_090_X) +XE_GPU_REGISTER(0x4169, float, SHADER_CONSTANT_090_Y) +XE_GPU_REGISTER(0x416A, float, SHADER_CONSTANT_090_Z) +XE_GPU_REGISTER(0x416B, float, SHADER_CONSTANT_090_W) +XE_GPU_REGISTER(0x416C, float, SHADER_CONSTANT_091_X) +XE_GPU_REGISTER(0x416D, float, SHADER_CONSTANT_091_Y) +XE_GPU_REGISTER(0x416E, float, SHADER_CONSTANT_091_Z) +XE_GPU_REGISTER(0x416F, float, SHADER_CONSTANT_091_W) +XE_GPU_REGISTER(0x4170, float, SHADER_CONSTANT_092_X) +XE_GPU_REGISTER(0x4171, float, SHADER_CONSTANT_092_Y) +XE_GPU_REGISTER(0x4172, float, SHADER_CONSTANT_092_Z) +XE_GPU_REGISTER(0x4173, float, SHADER_CONSTANT_092_W) +XE_GPU_REGISTER(0x4174, float, SHADER_CONSTANT_093_X) +XE_GPU_REGISTER(0x4175, float, SHADER_CONSTANT_093_Y) +XE_GPU_REGISTER(0x4176, float, SHADER_CONSTANT_093_Z) +XE_GPU_REGISTER(0x4177, float, SHADER_CONSTANT_093_W) +XE_GPU_REGISTER(0x4178, float, SHADER_CONSTANT_094_X) +XE_GPU_REGISTER(0x4179, float, SHADER_CONSTANT_094_Y) +XE_GPU_REGISTER(0x417A, float, SHADER_CONSTANT_094_Z) +XE_GPU_REGISTER(0x417B, float, SHADER_CONSTANT_094_W) +XE_GPU_REGISTER(0x417C, float, SHADER_CONSTANT_095_X) +XE_GPU_REGISTER(0x417D, float, SHADER_CONSTANT_095_Y) +XE_GPU_REGISTER(0x417E, float, SHADER_CONSTANT_095_Z) +XE_GPU_REGISTER(0x417F, float, SHADER_CONSTANT_095_W) +XE_GPU_REGISTER(0x4180, float, SHADER_CONSTANT_096_X) +XE_GPU_REGISTER(0x4181, float, SHADER_CONSTANT_096_Y) +XE_GPU_REGISTER(0x4182, float, SHADER_CONSTANT_096_Z) +XE_GPU_REGISTER(0x4183, float, SHADER_CONSTANT_096_W) +XE_GPU_REGISTER(0x4184, float, SHADER_CONSTANT_097_X) +XE_GPU_REGISTER(0x4185, float, SHADER_CONSTANT_097_Y) +XE_GPU_REGISTER(0x4186, float, SHADER_CONSTANT_097_Z) +XE_GPU_REGISTER(0x4187, float, SHADER_CONSTANT_097_W) +XE_GPU_REGISTER(0x4188, float, SHADER_CONSTANT_098_X) +XE_GPU_REGISTER(0x4189, float, SHADER_CONSTANT_098_Y) +XE_GPU_REGISTER(0x418A, float, SHADER_CONSTANT_098_Z) +XE_GPU_REGISTER(0x418B, float, SHADER_CONSTANT_098_W) +XE_GPU_REGISTER(0x418C, float, SHADER_CONSTANT_099_X) +XE_GPU_REGISTER(0x418D, float, SHADER_CONSTANT_099_Y) +XE_GPU_REGISTER(0x418E, float, SHADER_CONSTANT_099_Z) +XE_GPU_REGISTER(0x418F, float, SHADER_CONSTANT_099_W) +XE_GPU_REGISTER(0x4190, float, SHADER_CONSTANT_100_X) +XE_GPU_REGISTER(0x4191, float, SHADER_CONSTANT_100_Y) +XE_GPU_REGISTER(0x4192, float, SHADER_CONSTANT_100_Z) +XE_GPU_REGISTER(0x4193, float, SHADER_CONSTANT_100_W) +XE_GPU_REGISTER(0x4194, float, SHADER_CONSTANT_101_X) +XE_GPU_REGISTER(0x4195, float, SHADER_CONSTANT_101_Y) +XE_GPU_REGISTER(0x4196, float, SHADER_CONSTANT_101_Z) +XE_GPU_REGISTER(0x4197, float, SHADER_CONSTANT_101_W) +XE_GPU_REGISTER(0x4198, float, SHADER_CONSTANT_102_X) +XE_GPU_REGISTER(0x4199, float, SHADER_CONSTANT_102_Y) +XE_GPU_REGISTER(0x419A, float, SHADER_CONSTANT_102_Z) +XE_GPU_REGISTER(0x419B, float, SHADER_CONSTANT_102_W) +XE_GPU_REGISTER(0x419C, float, SHADER_CONSTANT_103_X) +XE_GPU_REGISTER(0x419D, float, SHADER_CONSTANT_103_Y) +XE_GPU_REGISTER(0x419E, float, SHADER_CONSTANT_103_Z) +XE_GPU_REGISTER(0x419F, float, SHADER_CONSTANT_103_W) +XE_GPU_REGISTER(0x41A0, float, SHADER_CONSTANT_104_X) +XE_GPU_REGISTER(0x41A1, float, SHADER_CONSTANT_104_Y) +XE_GPU_REGISTER(0x41A2, float, SHADER_CONSTANT_104_Z) +XE_GPU_REGISTER(0x41A3, float, SHADER_CONSTANT_104_W) +XE_GPU_REGISTER(0x41A4, float, SHADER_CONSTANT_105_X) +XE_GPU_REGISTER(0x41A5, float, SHADER_CONSTANT_105_Y) +XE_GPU_REGISTER(0x41A6, float, SHADER_CONSTANT_105_Z) +XE_GPU_REGISTER(0x41A7, float, SHADER_CONSTANT_105_W) +XE_GPU_REGISTER(0x41A8, float, SHADER_CONSTANT_106_X) +XE_GPU_REGISTER(0x41A9, float, SHADER_CONSTANT_106_Y) +XE_GPU_REGISTER(0x41AA, float, SHADER_CONSTANT_106_Z) +XE_GPU_REGISTER(0x41AB, float, SHADER_CONSTANT_106_W) +XE_GPU_REGISTER(0x41AC, float, SHADER_CONSTANT_107_X) +XE_GPU_REGISTER(0x41AD, float, SHADER_CONSTANT_107_Y) +XE_GPU_REGISTER(0x41AE, float, SHADER_CONSTANT_107_Z) +XE_GPU_REGISTER(0x41AF, float, SHADER_CONSTANT_107_W) +XE_GPU_REGISTER(0x41B0, float, SHADER_CONSTANT_108_X) +XE_GPU_REGISTER(0x41B1, float, SHADER_CONSTANT_108_Y) +XE_GPU_REGISTER(0x41B2, float, SHADER_CONSTANT_108_Z) +XE_GPU_REGISTER(0x41B3, float, SHADER_CONSTANT_108_W) +XE_GPU_REGISTER(0x41B4, float, SHADER_CONSTANT_109_X) +XE_GPU_REGISTER(0x41B5, float, SHADER_CONSTANT_109_Y) +XE_GPU_REGISTER(0x41B6, float, SHADER_CONSTANT_109_Z) +XE_GPU_REGISTER(0x41B7, float, SHADER_CONSTANT_109_W) +XE_GPU_REGISTER(0x41B8, float, SHADER_CONSTANT_110_X) +XE_GPU_REGISTER(0x41B9, float, SHADER_CONSTANT_110_Y) +XE_GPU_REGISTER(0x41BA, float, SHADER_CONSTANT_110_Z) +XE_GPU_REGISTER(0x41BB, float, SHADER_CONSTANT_110_W) +XE_GPU_REGISTER(0x41BC, float, SHADER_CONSTANT_111_X) +XE_GPU_REGISTER(0x41BD, float, SHADER_CONSTANT_111_Y) +XE_GPU_REGISTER(0x41BE, float, SHADER_CONSTANT_111_Z) +XE_GPU_REGISTER(0x41BF, float, SHADER_CONSTANT_111_W) +XE_GPU_REGISTER(0x41C0, float, SHADER_CONSTANT_112_X) +XE_GPU_REGISTER(0x41C1, float, SHADER_CONSTANT_112_Y) +XE_GPU_REGISTER(0x41C2, float, SHADER_CONSTANT_112_Z) +XE_GPU_REGISTER(0x41C3, float, SHADER_CONSTANT_112_W) +XE_GPU_REGISTER(0x41C4, float, SHADER_CONSTANT_113_X) +XE_GPU_REGISTER(0x41C5, float, SHADER_CONSTANT_113_Y) +XE_GPU_REGISTER(0x41C6, float, SHADER_CONSTANT_113_Z) +XE_GPU_REGISTER(0x41C7, float, SHADER_CONSTANT_113_W) +XE_GPU_REGISTER(0x41C8, float, SHADER_CONSTANT_114_X) +XE_GPU_REGISTER(0x41C9, float, SHADER_CONSTANT_114_Y) +XE_GPU_REGISTER(0x41CA, float, SHADER_CONSTANT_114_Z) +XE_GPU_REGISTER(0x41CB, float, SHADER_CONSTANT_114_W) +XE_GPU_REGISTER(0x41CC, float, SHADER_CONSTANT_115_X) +XE_GPU_REGISTER(0x41CD, float, SHADER_CONSTANT_115_Y) +XE_GPU_REGISTER(0x41CE, float, SHADER_CONSTANT_115_Z) +XE_GPU_REGISTER(0x41CF, float, SHADER_CONSTANT_115_W) +XE_GPU_REGISTER(0x41D0, float, SHADER_CONSTANT_116_X) +XE_GPU_REGISTER(0x41D1, float, SHADER_CONSTANT_116_Y) +XE_GPU_REGISTER(0x41D2, float, SHADER_CONSTANT_116_Z) +XE_GPU_REGISTER(0x41D3, float, SHADER_CONSTANT_116_W) +XE_GPU_REGISTER(0x41D4, float, SHADER_CONSTANT_117_X) +XE_GPU_REGISTER(0x41D5, float, SHADER_CONSTANT_117_Y) +XE_GPU_REGISTER(0x41D6, float, SHADER_CONSTANT_117_Z) +XE_GPU_REGISTER(0x41D7, float, SHADER_CONSTANT_117_W) +XE_GPU_REGISTER(0x41D8, float, SHADER_CONSTANT_118_X) +XE_GPU_REGISTER(0x41D9, float, SHADER_CONSTANT_118_Y) +XE_GPU_REGISTER(0x41DA, float, SHADER_CONSTANT_118_Z) +XE_GPU_REGISTER(0x41DB, float, SHADER_CONSTANT_118_W) +XE_GPU_REGISTER(0x41DC, float, SHADER_CONSTANT_119_X) +XE_GPU_REGISTER(0x41DD, float, SHADER_CONSTANT_119_Y) +XE_GPU_REGISTER(0x41DE, float, SHADER_CONSTANT_119_Z) +XE_GPU_REGISTER(0x41DF, float, SHADER_CONSTANT_119_W) +XE_GPU_REGISTER(0x41E0, float, SHADER_CONSTANT_120_X) +XE_GPU_REGISTER(0x41E1, float, SHADER_CONSTANT_120_Y) +XE_GPU_REGISTER(0x41E2, float, SHADER_CONSTANT_120_Z) +XE_GPU_REGISTER(0x41E3, float, SHADER_CONSTANT_120_W) +XE_GPU_REGISTER(0x41E4, float, SHADER_CONSTANT_121_X) +XE_GPU_REGISTER(0x41E5, float, SHADER_CONSTANT_121_Y) +XE_GPU_REGISTER(0x41E6, float, SHADER_CONSTANT_121_Z) +XE_GPU_REGISTER(0x41E7, float, SHADER_CONSTANT_121_W) +XE_GPU_REGISTER(0x41E8, float, SHADER_CONSTANT_122_X) +XE_GPU_REGISTER(0x41E9, float, SHADER_CONSTANT_122_Y) +XE_GPU_REGISTER(0x41EA, float, SHADER_CONSTANT_122_Z) +XE_GPU_REGISTER(0x41EB, float, SHADER_CONSTANT_122_W) +XE_GPU_REGISTER(0x41EC, float, SHADER_CONSTANT_123_X) +XE_GPU_REGISTER(0x41ED, float, SHADER_CONSTANT_123_Y) +XE_GPU_REGISTER(0x41EE, float, SHADER_CONSTANT_123_Z) +XE_GPU_REGISTER(0x41EF, float, SHADER_CONSTANT_123_W) +XE_GPU_REGISTER(0x41F0, float, SHADER_CONSTANT_124_X) +XE_GPU_REGISTER(0x41F1, float, SHADER_CONSTANT_124_Y) +XE_GPU_REGISTER(0x41F2, float, SHADER_CONSTANT_124_Z) +XE_GPU_REGISTER(0x41F3, float, SHADER_CONSTANT_124_W) +XE_GPU_REGISTER(0x41F4, float, SHADER_CONSTANT_125_X) +XE_GPU_REGISTER(0x41F5, float, SHADER_CONSTANT_125_Y) +XE_GPU_REGISTER(0x41F6, float, SHADER_CONSTANT_125_Z) +XE_GPU_REGISTER(0x41F7, float, SHADER_CONSTANT_125_W) +XE_GPU_REGISTER(0x41F8, float, SHADER_CONSTANT_126_X) +XE_GPU_REGISTER(0x41F9, float, SHADER_CONSTANT_126_Y) +XE_GPU_REGISTER(0x41FA, float, SHADER_CONSTANT_126_Z) +XE_GPU_REGISTER(0x41FB, float, SHADER_CONSTANT_126_W) +XE_GPU_REGISTER(0x41FC, float, SHADER_CONSTANT_127_X) +XE_GPU_REGISTER(0x41FD, float, SHADER_CONSTANT_127_Y) +XE_GPU_REGISTER(0x41FE, float, SHADER_CONSTANT_127_Z) +XE_GPU_REGISTER(0x41FF, float, SHADER_CONSTANT_127_W) +XE_GPU_REGISTER(0x4200, float, SHADER_CONSTANT_128_X) +XE_GPU_REGISTER(0x4201, float, SHADER_CONSTANT_128_Y) +XE_GPU_REGISTER(0x4202, float, SHADER_CONSTANT_128_Z) +XE_GPU_REGISTER(0x4203, float, SHADER_CONSTANT_128_W) +XE_GPU_REGISTER(0x4204, float, SHADER_CONSTANT_129_X) +XE_GPU_REGISTER(0x4205, float, SHADER_CONSTANT_129_Y) +XE_GPU_REGISTER(0x4206, float, SHADER_CONSTANT_129_Z) +XE_GPU_REGISTER(0x4207, float, SHADER_CONSTANT_129_W) +XE_GPU_REGISTER(0x4208, float, SHADER_CONSTANT_130_X) +XE_GPU_REGISTER(0x4209, float, SHADER_CONSTANT_130_Y) +XE_GPU_REGISTER(0x420A, float, SHADER_CONSTANT_130_Z) +XE_GPU_REGISTER(0x420B, float, SHADER_CONSTANT_130_W) +XE_GPU_REGISTER(0x420C, float, SHADER_CONSTANT_131_X) +XE_GPU_REGISTER(0x420D, float, SHADER_CONSTANT_131_Y) +XE_GPU_REGISTER(0x420E, float, SHADER_CONSTANT_131_Z) +XE_GPU_REGISTER(0x420F, float, SHADER_CONSTANT_131_W) +XE_GPU_REGISTER(0x4210, float, SHADER_CONSTANT_132_X) +XE_GPU_REGISTER(0x4211, float, SHADER_CONSTANT_132_Y) +XE_GPU_REGISTER(0x4212, float, SHADER_CONSTANT_132_Z) +XE_GPU_REGISTER(0x4213, float, SHADER_CONSTANT_132_W) +XE_GPU_REGISTER(0x4214, float, SHADER_CONSTANT_133_X) +XE_GPU_REGISTER(0x4215, float, SHADER_CONSTANT_133_Y) +XE_GPU_REGISTER(0x4216, float, SHADER_CONSTANT_133_Z) +XE_GPU_REGISTER(0x4217, float, SHADER_CONSTANT_133_W) +XE_GPU_REGISTER(0x4218, float, SHADER_CONSTANT_134_X) +XE_GPU_REGISTER(0x4219, float, SHADER_CONSTANT_134_Y) +XE_GPU_REGISTER(0x421A, float, SHADER_CONSTANT_134_Z) +XE_GPU_REGISTER(0x421B, float, SHADER_CONSTANT_134_W) +XE_GPU_REGISTER(0x421C, float, SHADER_CONSTANT_135_X) +XE_GPU_REGISTER(0x421D, float, SHADER_CONSTANT_135_Y) +XE_GPU_REGISTER(0x421E, float, SHADER_CONSTANT_135_Z) +XE_GPU_REGISTER(0x421F, float, SHADER_CONSTANT_135_W) +XE_GPU_REGISTER(0x4220, float, SHADER_CONSTANT_136_X) +XE_GPU_REGISTER(0x4221, float, SHADER_CONSTANT_136_Y) +XE_GPU_REGISTER(0x4222, float, SHADER_CONSTANT_136_Z) +XE_GPU_REGISTER(0x4223, float, SHADER_CONSTANT_136_W) +XE_GPU_REGISTER(0x4224, float, SHADER_CONSTANT_137_X) +XE_GPU_REGISTER(0x4225, float, SHADER_CONSTANT_137_Y) +XE_GPU_REGISTER(0x4226, float, SHADER_CONSTANT_137_Z) +XE_GPU_REGISTER(0x4227, float, SHADER_CONSTANT_137_W) +XE_GPU_REGISTER(0x4228, float, SHADER_CONSTANT_138_X) +XE_GPU_REGISTER(0x4229, float, SHADER_CONSTANT_138_Y) +XE_GPU_REGISTER(0x422A, float, SHADER_CONSTANT_138_Z) +XE_GPU_REGISTER(0x422B, float, SHADER_CONSTANT_138_W) +XE_GPU_REGISTER(0x422C, float, SHADER_CONSTANT_139_X) +XE_GPU_REGISTER(0x422D, float, SHADER_CONSTANT_139_Y) +XE_GPU_REGISTER(0x422E, float, SHADER_CONSTANT_139_Z) +XE_GPU_REGISTER(0x422F, float, SHADER_CONSTANT_139_W) +XE_GPU_REGISTER(0x4230, float, SHADER_CONSTANT_140_X) +XE_GPU_REGISTER(0x4231, float, SHADER_CONSTANT_140_Y) +XE_GPU_REGISTER(0x4232, float, SHADER_CONSTANT_140_Z) +XE_GPU_REGISTER(0x4233, float, SHADER_CONSTANT_140_W) +XE_GPU_REGISTER(0x4234, float, SHADER_CONSTANT_141_X) +XE_GPU_REGISTER(0x4235, float, SHADER_CONSTANT_141_Y) +XE_GPU_REGISTER(0x4236, float, SHADER_CONSTANT_141_Z) +XE_GPU_REGISTER(0x4237, float, SHADER_CONSTANT_141_W) +XE_GPU_REGISTER(0x4238, float, SHADER_CONSTANT_142_X) +XE_GPU_REGISTER(0x4239, float, SHADER_CONSTANT_142_Y) +XE_GPU_REGISTER(0x423A, float, SHADER_CONSTANT_142_Z) +XE_GPU_REGISTER(0x423B, float, SHADER_CONSTANT_142_W) +XE_GPU_REGISTER(0x423C, float, SHADER_CONSTANT_143_X) +XE_GPU_REGISTER(0x423D, float, SHADER_CONSTANT_143_Y) +XE_GPU_REGISTER(0x423E, float, SHADER_CONSTANT_143_Z) +XE_GPU_REGISTER(0x423F, float, SHADER_CONSTANT_143_W) +XE_GPU_REGISTER(0x4240, float, SHADER_CONSTANT_144_X) +XE_GPU_REGISTER(0x4241, float, SHADER_CONSTANT_144_Y) +XE_GPU_REGISTER(0x4242, float, SHADER_CONSTANT_144_Z) +XE_GPU_REGISTER(0x4243, float, SHADER_CONSTANT_144_W) +XE_GPU_REGISTER(0x4244, float, SHADER_CONSTANT_145_X) +XE_GPU_REGISTER(0x4245, float, SHADER_CONSTANT_145_Y) +XE_GPU_REGISTER(0x4246, float, SHADER_CONSTANT_145_Z) +XE_GPU_REGISTER(0x4247, float, SHADER_CONSTANT_145_W) +XE_GPU_REGISTER(0x4248, float, SHADER_CONSTANT_146_X) +XE_GPU_REGISTER(0x4249, float, SHADER_CONSTANT_146_Y) +XE_GPU_REGISTER(0x424A, float, SHADER_CONSTANT_146_Z) +XE_GPU_REGISTER(0x424B, float, SHADER_CONSTANT_146_W) +XE_GPU_REGISTER(0x424C, float, SHADER_CONSTANT_147_X) +XE_GPU_REGISTER(0x424D, float, SHADER_CONSTANT_147_Y) +XE_GPU_REGISTER(0x424E, float, SHADER_CONSTANT_147_Z) +XE_GPU_REGISTER(0x424F, float, SHADER_CONSTANT_147_W) +XE_GPU_REGISTER(0x4250, float, SHADER_CONSTANT_148_X) +XE_GPU_REGISTER(0x4251, float, SHADER_CONSTANT_148_Y) +XE_GPU_REGISTER(0x4252, float, SHADER_CONSTANT_148_Z) +XE_GPU_REGISTER(0x4253, float, SHADER_CONSTANT_148_W) +XE_GPU_REGISTER(0x4254, float, SHADER_CONSTANT_149_X) +XE_GPU_REGISTER(0x4255, float, SHADER_CONSTANT_149_Y) +XE_GPU_REGISTER(0x4256, float, SHADER_CONSTANT_149_Z) +XE_GPU_REGISTER(0x4257, float, SHADER_CONSTANT_149_W) +XE_GPU_REGISTER(0x4258, float, SHADER_CONSTANT_150_X) +XE_GPU_REGISTER(0x4259, float, SHADER_CONSTANT_150_Y) +XE_GPU_REGISTER(0x425A, float, SHADER_CONSTANT_150_Z) +XE_GPU_REGISTER(0x425B, float, SHADER_CONSTANT_150_W) +XE_GPU_REGISTER(0x425C, float, SHADER_CONSTANT_151_X) +XE_GPU_REGISTER(0x425D, float, SHADER_CONSTANT_151_Y) +XE_GPU_REGISTER(0x425E, float, SHADER_CONSTANT_151_Z) +XE_GPU_REGISTER(0x425F, float, SHADER_CONSTANT_151_W) +XE_GPU_REGISTER(0x4260, float, SHADER_CONSTANT_152_X) +XE_GPU_REGISTER(0x4261, float, SHADER_CONSTANT_152_Y) +XE_GPU_REGISTER(0x4262, float, SHADER_CONSTANT_152_Z) +XE_GPU_REGISTER(0x4263, float, SHADER_CONSTANT_152_W) +XE_GPU_REGISTER(0x4264, float, SHADER_CONSTANT_153_X) +XE_GPU_REGISTER(0x4265, float, SHADER_CONSTANT_153_Y) +XE_GPU_REGISTER(0x4266, float, SHADER_CONSTANT_153_Z) +XE_GPU_REGISTER(0x4267, float, SHADER_CONSTANT_153_W) +XE_GPU_REGISTER(0x4268, float, SHADER_CONSTANT_154_X) +XE_GPU_REGISTER(0x4269, float, SHADER_CONSTANT_154_Y) +XE_GPU_REGISTER(0x426A, float, SHADER_CONSTANT_154_Z) +XE_GPU_REGISTER(0x426B, float, SHADER_CONSTANT_154_W) +XE_GPU_REGISTER(0x426C, float, SHADER_CONSTANT_155_X) +XE_GPU_REGISTER(0x426D, float, SHADER_CONSTANT_155_Y) +XE_GPU_REGISTER(0x426E, float, SHADER_CONSTANT_155_Z) +XE_GPU_REGISTER(0x426F, float, SHADER_CONSTANT_155_W) +XE_GPU_REGISTER(0x4270, float, SHADER_CONSTANT_156_X) +XE_GPU_REGISTER(0x4271, float, SHADER_CONSTANT_156_Y) +XE_GPU_REGISTER(0x4272, float, SHADER_CONSTANT_156_Z) +XE_GPU_REGISTER(0x4273, float, SHADER_CONSTANT_156_W) +XE_GPU_REGISTER(0x4274, float, SHADER_CONSTANT_157_X) +XE_GPU_REGISTER(0x4275, float, SHADER_CONSTANT_157_Y) +XE_GPU_REGISTER(0x4276, float, SHADER_CONSTANT_157_Z) +XE_GPU_REGISTER(0x4277, float, SHADER_CONSTANT_157_W) +XE_GPU_REGISTER(0x4278, float, SHADER_CONSTANT_158_X) +XE_GPU_REGISTER(0x4279, float, SHADER_CONSTANT_158_Y) +XE_GPU_REGISTER(0x427A, float, SHADER_CONSTANT_158_Z) +XE_GPU_REGISTER(0x427B, float, SHADER_CONSTANT_158_W) +XE_GPU_REGISTER(0x427C, float, SHADER_CONSTANT_159_X) +XE_GPU_REGISTER(0x427D, float, SHADER_CONSTANT_159_Y) +XE_GPU_REGISTER(0x427E, float, SHADER_CONSTANT_159_Z) +XE_GPU_REGISTER(0x427F, float, SHADER_CONSTANT_159_W) +XE_GPU_REGISTER(0x4280, float, SHADER_CONSTANT_160_X) +XE_GPU_REGISTER(0x4281, float, SHADER_CONSTANT_160_Y) +XE_GPU_REGISTER(0x4282, float, SHADER_CONSTANT_160_Z) +XE_GPU_REGISTER(0x4283, float, SHADER_CONSTANT_160_W) +XE_GPU_REGISTER(0x4284, float, SHADER_CONSTANT_161_X) +XE_GPU_REGISTER(0x4285, float, SHADER_CONSTANT_161_Y) +XE_GPU_REGISTER(0x4286, float, SHADER_CONSTANT_161_Z) +XE_GPU_REGISTER(0x4287, float, SHADER_CONSTANT_161_W) +XE_GPU_REGISTER(0x4288, float, SHADER_CONSTANT_162_X) +XE_GPU_REGISTER(0x4289, float, SHADER_CONSTANT_162_Y) +XE_GPU_REGISTER(0x428A, float, SHADER_CONSTANT_162_Z) +XE_GPU_REGISTER(0x428B, float, SHADER_CONSTANT_162_W) +XE_GPU_REGISTER(0x428C, float, SHADER_CONSTANT_163_X) +XE_GPU_REGISTER(0x428D, float, SHADER_CONSTANT_163_Y) +XE_GPU_REGISTER(0x428E, float, SHADER_CONSTANT_163_Z) +XE_GPU_REGISTER(0x428F, float, SHADER_CONSTANT_163_W) +XE_GPU_REGISTER(0x4290, float, SHADER_CONSTANT_164_X) +XE_GPU_REGISTER(0x4291, float, SHADER_CONSTANT_164_Y) +XE_GPU_REGISTER(0x4292, float, SHADER_CONSTANT_164_Z) +XE_GPU_REGISTER(0x4293, float, SHADER_CONSTANT_164_W) +XE_GPU_REGISTER(0x4294, float, SHADER_CONSTANT_165_X) +XE_GPU_REGISTER(0x4295, float, SHADER_CONSTANT_165_Y) +XE_GPU_REGISTER(0x4296, float, SHADER_CONSTANT_165_Z) +XE_GPU_REGISTER(0x4297, float, SHADER_CONSTANT_165_W) +XE_GPU_REGISTER(0x4298, float, SHADER_CONSTANT_166_X) +XE_GPU_REGISTER(0x4299, float, SHADER_CONSTANT_166_Y) +XE_GPU_REGISTER(0x429A, float, SHADER_CONSTANT_166_Z) +XE_GPU_REGISTER(0x429B, float, SHADER_CONSTANT_166_W) +XE_GPU_REGISTER(0x429C, float, SHADER_CONSTANT_167_X) +XE_GPU_REGISTER(0x429D, float, SHADER_CONSTANT_167_Y) +XE_GPU_REGISTER(0x429E, float, SHADER_CONSTANT_167_Z) +XE_GPU_REGISTER(0x429F, float, SHADER_CONSTANT_167_W) +XE_GPU_REGISTER(0x42A0, float, SHADER_CONSTANT_168_X) +XE_GPU_REGISTER(0x42A1, float, SHADER_CONSTANT_168_Y) +XE_GPU_REGISTER(0x42A2, float, SHADER_CONSTANT_168_Z) +XE_GPU_REGISTER(0x42A3, float, SHADER_CONSTANT_168_W) +XE_GPU_REGISTER(0x42A4, float, SHADER_CONSTANT_169_X) +XE_GPU_REGISTER(0x42A5, float, SHADER_CONSTANT_169_Y) +XE_GPU_REGISTER(0x42A6, float, SHADER_CONSTANT_169_Z) +XE_GPU_REGISTER(0x42A7, float, SHADER_CONSTANT_169_W) +XE_GPU_REGISTER(0x42A8, float, SHADER_CONSTANT_170_X) +XE_GPU_REGISTER(0x42A9, float, SHADER_CONSTANT_170_Y) +XE_GPU_REGISTER(0x42AA, float, SHADER_CONSTANT_170_Z) +XE_GPU_REGISTER(0x42AB, float, SHADER_CONSTANT_170_W) +XE_GPU_REGISTER(0x42AC, float, SHADER_CONSTANT_171_X) +XE_GPU_REGISTER(0x42AD, float, SHADER_CONSTANT_171_Y) +XE_GPU_REGISTER(0x42AE, float, SHADER_CONSTANT_171_Z) +XE_GPU_REGISTER(0x42AF, float, SHADER_CONSTANT_171_W) +XE_GPU_REGISTER(0x42B0, float, SHADER_CONSTANT_172_X) +XE_GPU_REGISTER(0x42B1, float, SHADER_CONSTANT_172_Y) +XE_GPU_REGISTER(0x42B2, float, SHADER_CONSTANT_172_Z) +XE_GPU_REGISTER(0x42B3, float, SHADER_CONSTANT_172_W) +XE_GPU_REGISTER(0x42B4, float, SHADER_CONSTANT_173_X) +XE_GPU_REGISTER(0x42B5, float, SHADER_CONSTANT_173_Y) +XE_GPU_REGISTER(0x42B6, float, SHADER_CONSTANT_173_Z) +XE_GPU_REGISTER(0x42B7, float, SHADER_CONSTANT_173_W) +XE_GPU_REGISTER(0x42B8, float, SHADER_CONSTANT_174_X) +XE_GPU_REGISTER(0x42B9, float, SHADER_CONSTANT_174_Y) +XE_GPU_REGISTER(0x42BA, float, SHADER_CONSTANT_174_Z) +XE_GPU_REGISTER(0x42BB, float, SHADER_CONSTANT_174_W) +XE_GPU_REGISTER(0x42BC, float, SHADER_CONSTANT_175_X) +XE_GPU_REGISTER(0x42BD, float, SHADER_CONSTANT_175_Y) +XE_GPU_REGISTER(0x42BE, float, SHADER_CONSTANT_175_Z) +XE_GPU_REGISTER(0x42BF, float, SHADER_CONSTANT_175_W) +XE_GPU_REGISTER(0x42C0, float, SHADER_CONSTANT_176_X) +XE_GPU_REGISTER(0x42C1, float, SHADER_CONSTANT_176_Y) +XE_GPU_REGISTER(0x42C2, float, SHADER_CONSTANT_176_Z) +XE_GPU_REGISTER(0x42C3, float, SHADER_CONSTANT_176_W) +XE_GPU_REGISTER(0x42C4, float, SHADER_CONSTANT_177_X) +XE_GPU_REGISTER(0x42C5, float, SHADER_CONSTANT_177_Y) +XE_GPU_REGISTER(0x42C6, float, SHADER_CONSTANT_177_Z) +XE_GPU_REGISTER(0x42C7, float, SHADER_CONSTANT_177_W) +XE_GPU_REGISTER(0x42C8, float, SHADER_CONSTANT_178_X) +XE_GPU_REGISTER(0x42C9, float, SHADER_CONSTANT_178_Y) +XE_GPU_REGISTER(0x42CA, float, SHADER_CONSTANT_178_Z) +XE_GPU_REGISTER(0x42CB, float, SHADER_CONSTANT_178_W) +XE_GPU_REGISTER(0x42CC, float, SHADER_CONSTANT_179_X) +XE_GPU_REGISTER(0x42CD, float, SHADER_CONSTANT_179_Y) +XE_GPU_REGISTER(0x42CE, float, SHADER_CONSTANT_179_Z) +XE_GPU_REGISTER(0x42CF, float, SHADER_CONSTANT_179_W) +XE_GPU_REGISTER(0x42D0, float, SHADER_CONSTANT_180_X) +XE_GPU_REGISTER(0x42D1, float, SHADER_CONSTANT_180_Y) +XE_GPU_REGISTER(0x42D2, float, SHADER_CONSTANT_180_Z) +XE_GPU_REGISTER(0x42D3, float, SHADER_CONSTANT_180_W) +XE_GPU_REGISTER(0x42D4, float, SHADER_CONSTANT_181_X) +XE_GPU_REGISTER(0x42D5, float, SHADER_CONSTANT_181_Y) +XE_GPU_REGISTER(0x42D6, float, SHADER_CONSTANT_181_Z) +XE_GPU_REGISTER(0x42D7, float, SHADER_CONSTANT_181_W) +XE_GPU_REGISTER(0x42D8, float, SHADER_CONSTANT_182_X) +XE_GPU_REGISTER(0x42D9, float, SHADER_CONSTANT_182_Y) +XE_GPU_REGISTER(0x42DA, float, SHADER_CONSTANT_182_Z) +XE_GPU_REGISTER(0x42DB, float, SHADER_CONSTANT_182_W) +XE_GPU_REGISTER(0x42DC, float, SHADER_CONSTANT_183_X) +XE_GPU_REGISTER(0x42DD, float, SHADER_CONSTANT_183_Y) +XE_GPU_REGISTER(0x42DE, float, SHADER_CONSTANT_183_Z) +XE_GPU_REGISTER(0x42DF, float, SHADER_CONSTANT_183_W) +XE_GPU_REGISTER(0x42E0, float, SHADER_CONSTANT_184_X) +XE_GPU_REGISTER(0x42E1, float, SHADER_CONSTANT_184_Y) +XE_GPU_REGISTER(0x42E2, float, SHADER_CONSTANT_184_Z) +XE_GPU_REGISTER(0x42E3, float, SHADER_CONSTANT_184_W) +XE_GPU_REGISTER(0x42E4, float, SHADER_CONSTANT_185_X) +XE_GPU_REGISTER(0x42E5, float, SHADER_CONSTANT_185_Y) +XE_GPU_REGISTER(0x42E6, float, SHADER_CONSTANT_185_Z) +XE_GPU_REGISTER(0x42E7, float, SHADER_CONSTANT_185_W) +XE_GPU_REGISTER(0x42E8, float, SHADER_CONSTANT_186_X) +XE_GPU_REGISTER(0x42E9, float, SHADER_CONSTANT_186_Y) +XE_GPU_REGISTER(0x42EA, float, SHADER_CONSTANT_186_Z) +XE_GPU_REGISTER(0x42EB, float, SHADER_CONSTANT_186_W) +XE_GPU_REGISTER(0x42EC, float, SHADER_CONSTANT_187_X) +XE_GPU_REGISTER(0x42ED, float, SHADER_CONSTANT_187_Y) +XE_GPU_REGISTER(0x42EE, float, SHADER_CONSTANT_187_Z) +XE_GPU_REGISTER(0x42EF, float, SHADER_CONSTANT_187_W) +XE_GPU_REGISTER(0x42F0, float, SHADER_CONSTANT_188_X) +XE_GPU_REGISTER(0x42F1, float, SHADER_CONSTANT_188_Y) +XE_GPU_REGISTER(0x42F2, float, SHADER_CONSTANT_188_Z) +XE_GPU_REGISTER(0x42F3, float, SHADER_CONSTANT_188_W) +XE_GPU_REGISTER(0x42F4, float, SHADER_CONSTANT_189_X) +XE_GPU_REGISTER(0x42F5, float, SHADER_CONSTANT_189_Y) +XE_GPU_REGISTER(0x42F6, float, SHADER_CONSTANT_189_Z) +XE_GPU_REGISTER(0x42F7, float, SHADER_CONSTANT_189_W) +XE_GPU_REGISTER(0x42F8, float, SHADER_CONSTANT_190_X) +XE_GPU_REGISTER(0x42F9, float, SHADER_CONSTANT_190_Y) +XE_GPU_REGISTER(0x42FA, float, SHADER_CONSTANT_190_Z) +XE_GPU_REGISTER(0x42FB, float, SHADER_CONSTANT_190_W) +XE_GPU_REGISTER(0x42FC, float, SHADER_CONSTANT_191_X) +XE_GPU_REGISTER(0x42FD, float, SHADER_CONSTANT_191_Y) +XE_GPU_REGISTER(0x42FE, float, SHADER_CONSTANT_191_Z) +XE_GPU_REGISTER(0x42FF, float, SHADER_CONSTANT_191_W) +XE_GPU_REGISTER(0x4300, float, SHADER_CONSTANT_192_X) +XE_GPU_REGISTER(0x4301, float, SHADER_CONSTANT_192_Y) +XE_GPU_REGISTER(0x4302, float, SHADER_CONSTANT_192_Z) +XE_GPU_REGISTER(0x4303, float, SHADER_CONSTANT_192_W) +XE_GPU_REGISTER(0x4304, float, SHADER_CONSTANT_193_X) +XE_GPU_REGISTER(0x4305, float, SHADER_CONSTANT_193_Y) +XE_GPU_REGISTER(0x4306, float, SHADER_CONSTANT_193_Z) +XE_GPU_REGISTER(0x4307, float, SHADER_CONSTANT_193_W) +XE_GPU_REGISTER(0x4308, float, SHADER_CONSTANT_194_X) +XE_GPU_REGISTER(0x4309, float, SHADER_CONSTANT_194_Y) +XE_GPU_REGISTER(0x430A, float, SHADER_CONSTANT_194_Z) +XE_GPU_REGISTER(0x430B, float, SHADER_CONSTANT_194_W) +XE_GPU_REGISTER(0x430C, float, SHADER_CONSTANT_195_X) +XE_GPU_REGISTER(0x430D, float, SHADER_CONSTANT_195_Y) +XE_GPU_REGISTER(0x430E, float, SHADER_CONSTANT_195_Z) +XE_GPU_REGISTER(0x430F, float, SHADER_CONSTANT_195_W) +XE_GPU_REGISTER(0x4310, float, SHADER_CONSTANT_196_X) +XE_GPU_REGISTER(0x4311, float, SHADER_CONSTANT_196_Y) +XE_GPU_REGISTER(0x4312, float, SHADER_CONSTANT_196_Z) +XE_GPU_REGISTER(0x4313, float, SHADER_CONSTANT_196_W) +XE_GPU_REGISTER(0x4314, float, SHADER_CONSTANT_197_X) +XE_GPU_REGISTER(0x4315, float, SHADER_CONSTANT_197_Y) +XE_GPU_REGISTER(0x4316, float, SHADER_CONSTANT_197_Z) +XE_GPU_REGISTER(0x4317, float, SHADER_CONSTANT_197_W) +XE_GPU_REGISTER(0x4318, float, SHADER_CONSTANT_198_X) +XE_GPU_REGISTER(0x4319, float, SHADER_CONSTANT_198_Y) +XE_GPU_REGISTER(0x431A, float, SHADER_CONSTANT_198_Z) +XE_GPU_REGISTER(0x431B, float, SHADER_CONSTANT_198_W) +XE_GPU_REGISTER(0x431C, float, SHADER_CONSTANT_199_X) +XE_GPU_REGISTER(0x431D, float, SHADER_CONSTANT_199_Y) +XE_GPU_REGISTER(0x431E, float, SHADER_CONSTANT_199_Z) +XE_GPU_REGISTER(0x431F, float, SHADER_CONSTANT_199_W) +XE_GPU_REGISTER(0x4320, float, SHADER_CONSTANT_200_X) +XE_GPU_REGISTER(0x4321, float, SHADER_CONSTANT_200_Y) +XE_GPU_REGISTER(0x4322, float, SHADER_CONSTANT_200_Z) +XE_GPU_REGISTER(0x4323, float, SHADER_CONSTANT_200_W) +XE_GPU_REGISTER(0x4324, float, SHADER_CONSTANT_201_X) +XE_GPU_REGISTER(0x4325, float, SHADER_CONSTANT_201_Y) +XE_GPU_REGISTER(0x4326, float, SHADER_CONSTANT_201_Z) +XE_GPU_REGISTER(0x4327, float, SHADER_CONSTANT_201_W) +XE_GPU_REGISTER(0x4328, float, SHADER_CONSTANT_202_X) +XE_GPU_REGISTER(0x4329, float, SHADER_CONSTANT_202_Y) +XE_GPU_REGISTER(0x432A, float, SHADER_CONSTANT_202_Z) +XE_GPU_REGISTER(0x432B, float, SHADER_CONSTANT_202_W) +XE_GPU_REGISTER(0x432C, float, SHADER_CONSTANT_203_X) +XE_GPU_REGISTER(0x432D, float, SHADER_CONSTANT_203_Y) +XE_GPU_REGISTER(0x432E, float, SHADER_CONSTANT_203_Z) +XE_GPU_REGISTER(0x432F, float, SHADER_CONSTANT_203_W) +XE_GPU_REGISTER(0x4330, float, SHADER_CONSTANT_204_X) +XE_GPU_REGISTER(0x4331, float, SHADER_CONSTANT_204_Y) +XE_GPU_REGISTER(0x4332, float, SHADER_CONSTANT_204_Z) +XE_GPU_REGISTER(0x4333, float, SHADER_CONSTANT_204_W) +XE_GPU_REGISTER(0x4334, float, SHADER_CONSTANT_205_X) +XE_GPU_REGISTER(0x4335, float, SHADER_CONSTANT_205_Y) +XE_GPU_REGISTER(0x4336, float, SHADER_CONSTANT_205_Z) +XE_GPU_REGISTER(0x4337, float, SHADER_CONSTANT_205_W) +XE_GPU_REGISTER(0x4338, float, SHADER_CONSTANT_206_X) +XE_GPU_REGISTER(0x4339, float, SHADER_CONSTANT_206_Y) +XE_GPU_REGISTER(0x433A, float, SHADER_CONSTANT_206_Z) +XE_GPU_REGISTER(0x433B, float, SHADER_CONSTANT_206_W) +XE_GPU_REGISTER(0x433C, float, SHADER_CONSTANT_207_X) +XE_GPU_REGISTER(0x433D, float, SHADER_CONSTANT_207_Y) +XE_GPU_REGISTER(0x433E, float, SHADER_CONSTANT_207_Z) +XE_GPU_REGISTER(0x433F, float, SHADER_CONSTANT_207_W) +XE_GPU_REGISTER(0x4340, float, SHADER_CONSTANT_208_X) +XE_GPU_REGISTER(0x4341, float, SHADER_CONSTANT_208_Y) +XE_GPU_REGISTER(0x4342, float, SHADER_CONSTANT_208_Z) +XE_GPU_REGISTER(0x4343, float, SHADER_CONSTANT_208_W) +XE_GPU_REGISTER(0x4344, float, SHADER_CONSTANT_209_X) +XE_GPU_REGISTER(0x4345, float, SHADER_CONSTANT_209_Y) +XE_GPU_REGISTER(0x4346, float, SHADER_CONSTANT_209_Z) +XE_GPU_REGISTER(0x4347, float, SHADER_CONSTANT_209_W) +XE_GPU_REGISTER(0x4348, float, SHADER_CONSTANT_210_X) +XE_GPU_REGISTER(0x4349, float, SHADER_CONSTANT_210_Y) +XE_GPU_REGISTER(0x434A, float, SHADER_CONSTANT_210_Z) +XE_GPU_REGISTER(0x434B, float, SHADER_CONSTANT_210_W) +XE_GPU_REGISTER(0x434C, float, SHADER_CONSTANT_211_X) +XE_GPU_REGISTER(0x434D, float, SHADER_CONSTANT_211_Y) +XE_GPU_REGISTER(0x434E, float, SHADER_CONSTANT_211_Z) +XE_GPU_REGISTER(0x434F, float, SHADER_CONSTANT_211_W) +XE_GPU_REGISTER(0x4350, float, SHADER_CONSTANT_212_X) +XE_GPU_REGISTER(0x4351, float, SHADER_CONSTANT_212_Y) +XE_GPU_REGISTER(0x4352, float, SHADER_CONSTANT_212_Z) +XE_GPU_REGISTER(0x4353, float, SHADER_CONSTANT_212_W) +XE_GPU_REGISTER(0x4354, float, SHADER_CONSTANT_213_X) +XE_GPU_REGISTER(0x4355, float, SHADER_CONSTANT_213_Y) +XE_GPU_REGISTER(0x4356, float, SHADER_CONSTANT_213_Z) +XE_GPU_REGISTER(0x4357, float, SHADER_CONSTANT_213_W) +XE_GPU_REGISTER(0x4358, float, SHADER_CONSTANT_214_X) +XE_GPU_REGISTER(0x4359, float, SHADER_CONSTANT_214_Y) +XE_GPU_REGISTER(0x435A, float, SHADER_CONSTANT_214_Z) +XE_GPU_REGISTER(0x435B, float, SHADER_CONSTANT_214_W) +XE_GPU_REGISTER(0x435C, float, SHADER_CONSTANT_215_X) +XE_GPU_REGISTER(0x435D, float, SHADER_CONSTANT_215_Y) +XE_GPU_REGISTER(0x435E, float, SHADER_CONSTANT_215_Z) +XE_GPU_REGISTER(0x435F, float, SHADER_CONSTANT_215_W) +XE_GPU_REGISTER(0x4360, float, SHADER_CONSTANT_216_X) +XE_GPU_REGISTER(0x4361, float, SHADER_CONSTANT_216_Y) +XE_GPU_REGISTER(0x4362, float, SHADER_CONSTANT_216_Z) +XE_GPU_REGISTER(0x4363, float, SHADER_CONSTANT_216_W) +XE_GPU_REGISTER(0x4364, float, SHADER_CONSTANT_217_X) +XE_GPU_REGISTER(0x4365, float, SHADER_CONSTANT_217_Y) +XE_GPU_REGISTER(0x4366, float, SHADER_CONSTANT_217_Z) +XE_GPU_REGISTER(0x4367, float, SHADER_CONSTANT_217_W) +XE_GPU_REGISTER(0x4368, float, SHADER_CONSTANT_218_X) +XE_GPU_REGISTER(0x4369, float, SHADER_CONSTANT_218_Y) +XE_GPU_REGISTER(0x436A, float, SHADER_CONSTANT_218_Z) +XE_GPU_REGISTER(0x436B, float, SHADER_CONSTANT_218_W) +XE_GPU_REGISTER(0x436C, float, SHADER_CONSTANT_219_X) +XE_GPU_REGISTER(0x436D, float, SHADER_CONSTANT_219_Y) +XE_GPU_REGISTER(0x436E, float, SHADER_CONSTANT_219_Z) +XE_GPU_REGISTER(0x436F, float, SHADER_CONSTANT_219_W) +XE_GPU_REGISTER(0x4370, float, SHADER_CONSTANT_220_X) +XE_GPU_REGISTER(0x4371, float, SHADER_CONSTANT_220_Y) +XE_GPU_REGISTER(0x4372, float, SHADER_CONSTANT_220_Z) +XE_GPU_REGISTER(0x4373, float, SHADER_CONSTANT_220_W) +XE_GPU_REGISTER(0x4374, float, SHADER_CONSTANT_221_X) +XE_GPU_REGISTER(0x4375, float, SHADER_CONSTANT_221_Y) +XE_GPU_REGISTER(0x4376, float, SHADER_CONSTANT_221_Z) +XE_GPU_REGISTER(0x4377, float, SHADER_CONSTANT_221_W) +XE_GPU_REGISTER(0x4378, float, SHADER_CONSTANT_222_X) +XE_GPU_REGISTER(0x4379, float, SHADER_CONSTANT_222_Y) +XE_GPU_REGISTER(0x437A, float, SHADER_CONSTANT_222_Z) +XE_GPU_REGISTER(0x437B, float, SHADER_CONSTANT_222_W) +XE_GPU_REGISTER(0x437C, float, SHADER_CONSTANT_223_X) +XE_GPU_REGISTER(0x437D, float, SHADER_CONSTANT_223_Y) +XE_GPU_REGISTER(0x437E, float, SHADER_CONSTANT_223_Z) +XE_GPU_REGISTER(0x437F, float, SHADER_CONSTANT_223_W) +XE_GPU_REGISTER(0x4380, float, SHADER_CONSTANT_224_X) +XE_GPU_REGISTER(0x4381, float, SHADER_CONSTANT_224_Y) +XE_GPU_REGISTER(0x4382, float, SHADER_CONSTANT_224_Z) +XE_GPU_REGISTER(0x4383, float, SHADER_CONSTANT_224_W) +XE_GPU_REGISTER(0x4384, float, SHADER_CONSTANT_225_X) +XE_GPU_REGISTER(0x4385, float, SHADER_CONSTANT_225_Y) +XE_GPU_REGISTER(0x4386, float, SHADER_CONSTANT_225_Z) +XE_GPU_REGISTER(0x4387, float, SHADER_CONSTANT_225_W) +XE_GPU_REGISTER(0x4388, float, SHADER_CONSTANT_226_X) +XE_GPU_REGISTER(0x4389, float, SHADER_CONSTANT_226_Y) +XE_GPU_REGISTER(0x438A, float, SHADER_CONSTANT_226_Z) +XE_GPU_REGISTER(0x438B, float, SHADER_CONSTANT_226_W) +XE_GPU_REGISTER(0x438C, float, SHADER_CONSTANT_227_X) +XE_GPU_REGISTER(0x438D, float, SHADER_CONSTANT_227_Y) +XE_GPU_REGISTER(0x438E, float, SHADER_CONSTANT_227_Z) +XE_GPU_REGISTER(0x438F, float, SHADER_CONSTANT_227_W) +XE_GPU_REGISTER(0x4390, float, SHADER_CONSTANT_228_X) +XE_GPU_REGISTER(0x4391, float, SHADER_CONSTANT_228_Y) +XE_GPU_REGISTER(0x4392, float, SHADER_CONSTANT_228_Z) +XE_GPU_REGISTER(0x4393, float, SHADER_CONSTANT_228_W) +XE_GPU_REGISTER(0x4394, float, SHADER_CONSTANT_229_X) +XE_GPU_REGISTER(0x4395, float, SHADER_CONSTANT_229_Y) +XE_GPU_REGISTER(0x4396, float, SHADER_CONSTANT_229_Z) +XE_GPU_REGISTER(0x4397, float, SHADER_CONSTANT_229_W) +XE_GPU_REGISTER(0x4398, float, SHADER_CONSTANT_230_X) +XE_GPU_REGISTER(0x4399, float, SHADER_CONSTANT_230_Y) +XE_GPU_REGISTER(0x439A, float, SHADER_CONSTANT_230_Z) +XE_GPU_REGISTER(0x439B, float, SHADER_CONSTANT_230_W) +XE_GPU_REGISTER(0x439C, float, SHADER_CONSTANT_231_X) +XE_GPU_REGISTER(0x439D, float, SHADER_CONSTANT_231_Y) +XE_GPU_REGISTER(0x439E, float, SHADER_CONSTANT_231_Z) +XE_GPU_REGISTER(0x439F, float, SHADER_CONSTANT_231_W) +XE_GPU_REGISTER(0x43A0, float, SHADER_CONSTANT_232_X) +XE_GPU_REGISTER(0x43A1, float, SHADER_CONSTANT_232_Y) +XE_GPU_REGISTER(0x43A2, float, SHADER_CONSTANT_232_Z) +XE_GPU_REGISTER(0x43A3, float, SHADER_CONSTANT_232_W) +XE_GPU_REGISTER(0x43A4, float, SHADER_CONSTANT_233_X) +XE_GPU_REGISTER(0x43A5, float, SHADER_CONSTANT_233_Y) +XE_GPU_REGISTER(0x43A6, float, SHADER_CONSTANT_233_Z) +XE_GPU_REGISTER(0x43A7, float, SHADER_CONSTANT_233_W) +XE_GPU_REGISTER(0x43A8, float, SHADER_CONSTANT_234_X) +XE_GPU_REGISTER(0x43A9, float, SHADER_CONSTANT_234_Y) +XE_GPU_REGISTER(0x43AA, float, SHADER_CONSTANT_234_Z) +XE_GPU_REGISTER(0x43AB, float, SHADER_CONSTANT_234_W) +XE_GPU_REGISTER(0x43AC, float, SHADER_CONSTANT_235_X) +XE_GPU_REGISTER(0x43AD, float, SHADER_CONSTANT_235_Y) +XE_GPU_REGISTER(0x43AE, float, SHADER_CONSTANT_235_Z) +XE_GPU_REGISTER(0x43AF, float, SHADER_CONSTANT_235_W) +XE_GPU_REGISTER(0x43B0, float, SHADER_CONSTANT_236_X) +XE_GPU_REGISTER(0x43B1, float, SHADER_CONSTANT_236_Y) +XE_GPU_REGISTER(0x43B2, float, SHADER_CONSTANT_236_Z) +XE_GPU_REGISTER(0x43B3, float, SHADER_CONSTANT_236_W) +XE_GPU_REGISTER(0x43B4, float, SHADER_CONSTANT_237_X) +XE_GPU_REGISTER(0x43B5, float, SHADER_CONSTANT_237_Y) +XE_GPU_REGISTER(0x43B6, float, SHADER_CONSTANT_237_Z) +XE_GPU_REGISTER(0x43B7, float, SHADER_CONSTANT_237_W) +XE_GPU_REGISTER(0x43B8, float, SHADER_CONSTANT_238_X) +XE_GPU_REGISTER(0x43B9, float, SHADER_CONSTANT_238_Y) +XE_GPU_REGISTER(0x43BA, float, SHADER_CONSTANT_238_Z) +XE_GPU_REGISTER(0x43BB, float, SHADER_CONSTANT_238_W) +XE_GPU_REGISTER(0x43BC, float, SHADER_CONSTANT_239_X) +XE_GPU_REGISTER(0x43BD, float, SHADER_CONSTANT_239_Y) +XE_GPU_REGISTER(0x43BE, float, SHADER_CONSTANT_239_Z) +XE_GPU_REGISTER(0x43BF, float, SHADER_CONSTANT_239_W) +XE_GPU_REGISTER(0x43C0, float, SHADER_CONSTANT_240_X) +XE_GPU_REGISTER(0x43C1, float, SHADER_CONSTANT_240_Y) +XE_GPU_REGISTER(0x43C2, float, SHADER_CONSTANT_240_Z) +XE_GPU_REGISTER(0x43C3, float, SHADER_CONSTANT_240_W) +XE_GPU_REGISTER(0x43C4, float, SHADER_CONSTANT_241_X) +XE_GPU_REGISTER(0x43C5, float, SHADER_CONSTANT_241_Y) +XE_GPU_REGISTER(0x43C6, float, SHADER_CONSTANT_241_Z) +XE_GPU_REGISTER(0x43C7, float, SHADER_CONSTANT_241_W) +XE_GPU_REGISTER(0x43C8, float, SHADER_CONSTANT_242_X) +XE_GPU_REGISTER(0x43C9, float, SHADER_CONSTANT_242_Y) +XE_GPU_REGISTER(0x43CA, float, SHADER_CONSTANT_242_Z) +XE_GPU_REGISTER(0x43CB, float, SHADER_CONSTANT_242_W) +XE_GPU_REGISTER(0x43CC, float, SHADER_CONSTANT_243_X) +XE_GPU_REGISTER(0x43CD, float, SHADER_CONSTANT_243_Y) +XE_GPU_REGISTER(0x43CE, float, SHADER_CONSTANT_243_Z) +XE_GPU_REGISTER(0x43CF, float, SHADER_CONSTANT_243_W) +XE_GPU_REGISTER(0x43D0, float, SHADER_CONSTANT_244_X) +XE_GPU_REGISTER(0x43D1, float, SHADER_CONSTANT_244_Y) +XE_GPU_REGISTER(0x43D2, float, SHADER_CONSTANT_244_Z) +XE_GPU_REGISTER(0x43D3, float, SHADER_CONSTANT_244_W) +XE_GPU_REGISTER(0x43D4, float, SHADER_CONSTANT_245_X) +XE_GPU_REGISTER(0x43D5, float, SHADER_CONSTANT_245_Y) +XE_GPU_REGISTER(0x43D6, float, SHADER_CONSTANT_245_Z) +XE_GPU_REGISTER(0x43D7, float, SHADER_CONSTANT_245_W) +XE_GPU_REGISTER(0x43D8, float, SHADER_CONSTANT_246_X) +XE_GPU_REGISTER(0x43D9, float, SHADER_CONSTANT_246_Y) +XE_GPU_REGISTER(0x43DA, float, SHADER_CONSTANT_246_Z) +XE_GPU_REGISTER(0x43DB, float, SHADER_CONSTANT_246_W) +XE_GPU_REGISTER(0x43DC, float, SHADER_CONSTANT_247_X) +XE_GPU_REGISTER(0x43DD, float, SHADER_CONSTANT_247_Y) +XE_GPU_REGISTER(0x43DE, float, SHADER_CONSTANT_247_Z) +XE_GPU_REGISTER(0x43DF, float, SHADER_CONSTANT_247_W) +XE_GPU_REGISTER(0x43E0, float, SHADER_CONSTANT_248_X) +XE_GPU_REGISTER(0x43E1, float, SHADER_CONSTANT_248_Y) +XE_GPU_REGISTER(0x43E2, float, SHADER_CONSTANT_248_Z) +XE_GPU_REGISTER(0x43E3, float, SHADER_CONSTANT_248_W) +XE_GPU_REGISTER(0x43E4, float, SHADER_CONSTANT_249_X) +XE_GPU_REGISTER(0x43E5, float, SHADER_CONSTANT_249_Y) +XE_GPU_REGISTER(0x43E6, float, SHADER_CONSTANT_249_Z) +XE_GPU_REGISTER(0x43E7, float, SHADER_CONSTANT_249_W) +XE_GPU_REGISTER(0x43E8, float, SHADER_CONSTANT_250_X) +XE_GPU_REGISTER(0x43E9, float, SHADER_CONSTANT_250_Y) +XE_GPU_REGISTER(0x43EA, float, SHADER_CONSTANT_250_Z) +XE_GPU_REGISTER(0x43EB, float, SHADER_CONSTANT_250_W) +XE_GPU_REGISTER(0x43EC, float, SHADER_CONSTANT_251_X) +XE_GPU_REGISTER(0x43ED, float, SHADER_CONSTANT_251_Y) +XE_GPU_REGISTER(0x43EE, float, SHADER_CONSTANT_251_Z) +XE_GPU_REGISTER(0x43EF, float, SHADER_CONSTANT_251_W) +XE_GPU_REGISTER(0x43F0, float, SHADER_CONSTANT_252_X) +XE_GPU_REGISTER(0x43F1, float, SHADER_CONSTANT_252_Y) +XE_GPU_REGISTER(0x43F2, float, SHADER_CONSTANT_252_Z) +XE_GPU_REGISTER(0x43F3, float, SHADER_CONSTANT_252_W) +XE_GPU_REGISTER(0x43F4, float, SHADER_CONSTANT_253_X) +XE_GPU_REGISTER(0x43F5, float, SHADER_CONSTANT_253_Y) +XE_GPU_REGISTER(0x43F6, float, SHADER_CONSTANT_253_Z) +XE_GPU_REGISTER(0x43F7, float, SHADER_CONSTANT_253_W) +XE_GPU_REGISTER(0x43F8, float, SHADER_CONSTANT_254_X) +XE_GPU_REGISTER(0x43F9, float, SHADER_CONSTANT_254_Y) +XE_GPU_REGISTER(0x43FA, float, SHADER_CONSTANT_254_Z) +XE_GPU_REGISTER(0x43FB, float, SHADER_CONSTANT_254_W) +XE_GPU_REGISTER(0x43FC, float, SHADER_CONSTANT_255_X) +XE_GPU_REGISTER(0x43FD, float, SHADER_CONSTANT_255_Y) +XE_GPU_REGISTER(0x43FE, float, SHADER_CONSTANT_255_Z) +XE_GPU_REGISTER(0x43FF, float, SHADER_CONSTANT_255_W) +XE_GPU_REGISTER(0x4400, float, SHADER_CONSTANT_256_X) +XE_GPU_REGISTER(0x4401, float, SHADER_CONSTANT_256_Y) +XE_GPU_REGISTER(0x4402, float, SHADER_CONSTANT_256_Z) +XE_GPU_REGISTER(0x4403, float, SHADER_CONSTANT_256_W) +XE_GPU_REGISTER(0x4404, float, SHADER_CONSTANT_257_X) +XE_GPU_REGISTER(0x4405, float, SHADER_CONSTANT_257_Y) +XE_GPU_REGISTER(0x4406, float, SHADER_CONSTANT_257_Z) +XE_GPU_REGISTER(0x4407, float, SHADER_CONSTANT_257_W) +XE_GPU_REGISTER(0x4408, float, SHADER_CONSTANT_258_X) +XE_GPU_REGISTER(0x4409, float, SHADER_CONSTANT_258_Y) +XE_GPU_REGISTER(0x440A, float, SHADER_CONSTANT_258_Z) +XE_GPU_REGISTER(0x440B, float, SHADER_CONSTANT_258_W) +XE_GPU_REGISTER(0x440C, float, SHADER_CONSTANT_259_X) +XE_GPU_REGISTER(0x440D, float, SHADER_CONSTANT_259_Y) +XE_GPU_REGISTER(0x440E, float, SHADER_CONSTANT_259_Z) +XE_GPU_REGISTER(0x440F, float, SHADER_CONSTANT_259_W) +XE_GPU_REGISTER(0x4410, float, SHADER_CONSTANT_260_X) +XE_GPU_REGISTER(0x4411, float, SHADER_CONSTANT_260_Y) +XE_GPU_REGISTER(0x4412, float, SHADER_CONSTANT_260_Z) +XE_GPU_REGISTER(0x4413, float, SHADER_CONSTANT_260_W) +XE_GPU_REGISTER(0x4414, float, SHADER_CONSTANT_261_X) +XE_GPU_REGISTER(0x4415, float, SHADER_CONSTANT_261_Y) +XE_GPU_REGISTER(0x4416, float, SHADER_CONSTANT_261_Z) +XE_GPU_REGISTER(0x4417, float, SHADER_CONSTANT_261_W) +XE_GPU_REGISTER(0x4418, float, SHADER_CONSTANT_262_X) +XE_GPU_REGISTER(0x4419, float, SHADER_CONSTANT_262_Y) +XE_GPU_REGISTER(0x441A, float, SHADER_CONSTANT_262_Z) +XE_GPU_REGISTER(0x441B, float, SHADER_CONSTANT_262_W) +XE_GPU_REGISTER(0x441C, float, SHADER_CONSTANT_263_X) +XE_GPU_REGISTER(0x441D, float, SHADER_CONSTANT_263_Y) +XE_GPU_REGISTER(0x441E, float, SHADER_CONSTANT_263_Z) +XE_GPU_REGISTER(0x441F, float, SHADER_CONSTANT_263_W) +XE_GPU_REGISTER(0x4420, float, SHADER_CONSTANT_264_X) +XE_GPU_REGISTER(0x4421, float, SHADER_CONSTANT_264_Y) +XE_GPU_REGISTER(0x4422, float, SHADER_CONSTANT_264_Z) +XE_GPU_REGISTER(0x4423, float, SHADER_CONSTANT_264_W) +XE_GPU_REGISTER(0x4424, float, SHADER_CONSTANT_265_X) +XE_GPU_REGISTER(0x4425, float, SHADER_CONSTANT_265_Y) +XE_GPU_REGISTER(0x4426, float, SHADER_CONSTANT_265_Z) +XE_GPU_REGISTER(0x4427, float, SHADER_CONSTANT_265_W) +XE_GPU_REGISTER(0x4428, float, SHADER_CONSTANT_266_X) +XE_GPU_REGISTER(0x4429, float, SHADER_CONSTANT_266_Y) +XE_GPU_REGISTER(0x442A, float, SHADER_CONSTANT_266_Z) +XE_GPU_REGISTER(0x442B, float, SHADER_CONSTANT_266_W) +XE_GPU_REGISTER(0x442C, float, SHADER_CONSTANT_267_X) +XE_GPU_REGISTER(0x442D, float, SHADER_CONSTANT_267_Y) +XE_GPU_REGISTER(0x442E, float, SHADER_CONSTANT_267_Z) +XE_GPU_REGISTER(0x442F, float, SHADER_CONSTANT_267_W) +XE_GPU_REGISTER(0x4430, float, SHADER_CONSTANT_268_X) +XE_GPU_REGISTER(0x4431, float, SHADER_CONSTANT_268_Y) +XE_GPU_REGISTER(0x4432, float, SHADER_CONSTANT_268_Z) +XE_GPU_REGISTER(0x4433, float, SHADER_CONSTANT_268_W) +XE_GPU_REGISTER(0x4434, float, SHADER_CONSTANT_269_X) +XE_GPU_REGISTER(0x4435, float, SHADER_CONSTANT_269_Y) +XE_GPU_REGISTER(0x4436, float, SHADER_CONSTANT_269_Z) +XE_GPU_REGISTER(0x4437, float, SHADER_CONSTANT_269_W) +XE_GPU_REGISTER(0x4438, float, SHADER_CONSTANT_270_X) +XE_GPU_REGISTER(0x4439, float, SHADER_CONSTANT_270_Y) +XE_GPU_REGISTER(0x443A, float, SHADER_CONSTANT_270_Z) +XE_GPU_REGISTER(0x443B, float, SHADER_CONSTANT_270_W) +XE_GPU_REGISTER(0x443C, float, SHADER_CONSTANT_271_X) +XE_GPU_REGISTER(0x443D, float, SHADER_CONSTANT_271_Y) +XE_GPU_REGISTER(0x443E, float, SHADER_CONSTANT_271_Z) +XE_GPU_REGISTER(0x443F, float, SHADER_CONSTANT_271_W) +XE_GPU_REGISTER(0x4440, float, SHADER_CONSTANT_272_X) +XE_GPU_REGISTER(0x4441, float, SHADER_CONSTANT_272_Y) +XE_GPU_REGISTER(0x4442, float, SHADER_CONSTANT_272_Z) +XE_GPU_REGISTER(0x4443, float, SHADER_CONSTANT_272_W) +XE_GPU_REGISTER(0x4444, float, SHADER_CONSTANT_273_X) +XE_GPU_REGISTER(0x4445, float, SHADER_CONSTANT_273_Y) +XE_GPU_REGISTER(0x4446, float, SHADER_CONSTANT_273_Z) +XE_GPU_REGISTER(0x4447, float, SHADER_CONSTANT_273_W) +XE_GPU_REGISTER(0x4448, float, SHADER_CONSTANT_274_X) +XE_GPU_REGISTER(0x4449, float, SHADER_CONSTANT_274_Y) +XE_GPU_REGISTER(0x444A, float, SHADER_CONSTANT_274_Z) +XE_GPU_REGISTER(0x444B, float, SHADER_CONSTANT_274_W) +XE_GPU_REGISTER(0x444C, float, SHADER_CONSTANT_275_X) +XE_GPU_REGISTER(0x444D, float, SHADER_CONSTANT_275_Y) +XE_GPU_REGISTER(0x444E, float, SHADER_CONSTANT_275_Z) +XE_GPU_REGISTER(0x444F, float, SHADER_CONSTANT_275_W) +XE_GPU_REGISTER(0x4450, float, SHADER_CONSTANT_276_X) +XE_GPU_REGISTER(0x4451, float, SHADER_CONSTANT_276_Y) +XE_GPU_REGISTER(0x4452, float, SHADER_CONSTANT_276_Z) +XE_GPU_REGISTER(0x4453, float, SHADER_CONSTANT_276_W) +XE_GPU_REGISTER(0x4454, float, SHADER_CONSTANT_277_X) +XE_GPU_REGISTER(0x4455, float, SHADER_CONSTANT_277_Y) +XE_GPU_REGISTER(0x4456, float, SHADER_CONSTANT_277_Z) +XE_GPU_REGISTER(0x4457, float, SHADER_CONSTANT_277_W) +XE_GPU_REGISTER(0x4458, float, SHADER_CONSTANT_278_X) +XE_GPU_REGISTER(0x4459, float, SHADER_CONSTANT_278_Y) +XE_GPU_REGISTER(0x445A, float, SHADER_CONSTANT_278_Z) +XE_GPU_REGISTER(0x445B, float, SHADER_CONSTANT_278_W) +XE_GPU_REGISTER(0x445C, float, SHADER_CONSTANT_279_X) +XE_GPU_REGISTER(0x445D, float, SHADER_CONSTANT_279_Y) +XE_GPU_REGISTER(0x445E, float, SHADER_CONSTANT_279_Z) +XE_GPU_REGISTER(0x445F, float, SHADER_CONSTANT_279_W) +XE_GPU_REGISTER(0x4460, float, SHADER_CONSTANT_280_X) +XE_GPU_REGISTER(0x4461, float, SHADER_CONSTANT_280_Y) +XE_GPU_REGISTER(0x4462, float, SHADER_CONSTANT_280_Z) +XE_GPU_REGISTER(0x4463, float, SHADER_CONSTANT_280_W) +XE_GPU_REGISTER(0x4464, float, SHADER_CONSTANT_281_X) +XE_GPU_REGISTER(0x4465, float, SHADER_CONSTANT_281_Y) +XE_GPU_REGISTER(0x4466, float, SHADER_CONSTANT_281_Z) +XE_GPU_REGISTER(0x4467, float, SHADER_CONSTANT_281_W) +XE_GPU_REGISTER(0x4468, float, SHADER_CONSTANT_282_X) +XE_GPU_REGISTER(0x4469, float, SHADER_CONSTANT_282_Y) +XE_GPU_REGISTER(0x446A, float, SHADER_CONSTANT_282_Z) +XE_GPU_REGISTER(0x446B, float, SHADER_CONSTANT_282_W) +XE_GPU_REGISTER(0x446C, float, SHADER_CONSTANT_283_X) +XE_GPU_REGISTER(0x446D, float, SHADER_CONSTANT_283_Y) +XE_GPU_REGISTER(0x446E, float, SHADER_CONSTANT_283_Z) +XE_GPU_REGISTER(0x446F, float, SHADER_CONSTANT_283_W) +XE_GPU_REGISTER(0x4470, float, SHADER_CONSTANT_284_X) +XE_GPU_REGISTER(0x4471, float, SHADER_CONSTANT_284_Y) +XE_GPU_REGISTER(0x4472, float, SHADER_CONSTANT_284_Z) +XE_GPU_REGISTER(0x4473, float, SHADER_CONSTANT_284_W) +XE_GPU_REGISTER(0x4474, float, SHADER_CONSTANT_285_X) +XE_GPU_REGISTER(0x4475, float, SHADER_CONSTANT_285_Y) +XE_GPU_REGISTER(0x4476, float, SHADER_CONSTANT_285_Z) +XE_GPU_REGISTER(0x4477, float, SHADER_CONSTANT_285_W) +XE_GPU_REGISTER(0x4478, float, SHADER_CONSTANT_286_X) +XE_GPU_REGISTER(0x4479, float, SHADER_CONSTANT_286_Y) +XE_GPU_REGISTER(0x447A, float, SHADER_CONSTANT_286_Z) +XE_GPU_REGISTER(0x447B, float, SHADER_CONSTANT_286_W) +XE_GPU_REGISTER(0x447C, float, SHADER_CONSTANT_287_X) +XE_GPU_REGISTER(0x447D, float, SHADER_CONSTANT_287_Y) +XE_GPU_REGISTER(0x447E, float, SHADER_CONSTANT_287_Z) +XE_GPU_REGISTER(0x447F, float, SHADER_CONSTANT_287_W) +XE_GPU_REGISTER(0x4480, float, SHADER_CONSTANT_288_X) +XE_GPU_REGISTER(0x4481, float, SHADER_CONSTANT_288_Y) +XE_GPU_REGISTER(0x4482, float, SHADER_CONSTANT_288_Z) +XE_GPU_REGISTER(0x4483, float, SHADER_CONSTANT_288_W) +XE_GPU_REGISTER(0x4484, float, SHADER_CONSTANT_289_X) +XE_GPU_REGISTER(0x4485, float, SHADER_CONSTANT_289_Y) +XE_GPU_REGISTER(0x4486, float, SHADER_CONSTANT_289_Z) +XE_GPU_REGISTER(0x4487, float, SHADER_CONSTANT_289_W) +XE_GPU_REGISTER(0x4488, float, SHADER_CONSTANT_290_X) +XE_GPU_REGISTER(0x4489, float, SHADER_CONSTANT_290_Y) +XE_GPU_REGISTER(0x448A, float, SHADER_CONSTANT_290_Z) +XE_GPU_REGISTER(0x448B, float, SHADER_CONSTANT_290_W) +XE_GPU_REGISTER(0x448C, float, SHADER_CONSTANT_291_X) +XE_GPU_REGISTER(0x448D, float, SHADER_CONSTANT_291_Y) +XE_GPU_REGISTER(0x448E, float, SHADER_CONSTANT_291_Z) +XE_GPU_REGISTER(0x448F, float, SHADER_CONSTANT_291_W) +XE_GPU_REGISTER(0x4490, float, SHADER_CONSTANT_292_X) +XE_GPU_REGISTER(0x4491, float, SHADER_CONSTANT_292_Y) +XE_GPU_REGISTER(0x4492, float, SHADER_CONSTANT_292_Z) +XE_GPU_REGISTER(0x4493, float, SHADER_CONSTANT_292_W) +XE_GPU_REGISTER(0x4494, float, SHADER_CONSTANT_293_X) +XE_GPU_REGISTER(0x4495, float, SHADER_CONSTANT_293_Y) +XE_GPU_REGISTER(0x4496, float, SHADER_CONSTANT_293_Z) +XE_GPU_REGISTER(0x4497, float, SHADER_CONSTANT_293_W) +XE_GPU_REGISTER(0x4498, float, SHADER_CONSTANT_294_X) +XE_GPU_REGISTER(0x4499, float, SHADER_CONSTANT_294_Y) +XE_GPU_REGISTER(0x449A, float, SHADER_CONSTANT_294_Z) +XE_GPU_REGISTER(0x449B, float, SHADER_CONSTANT_294_W) +XE_GPU_REGISTER(0x449C, float, SHADER_CONSTANT_295_X) +XE_GPU_REGISTER(0x449D, float, SHADER_CONSTANT_295_Y) +XE_GPU_REGISTER(0x449E, float, SHADER_CONSTANT_295_Z) +XE_GPU_REGISTER(0x449F, float, SHADER_CONSTANT_295_W) +XE_GPU_REGISTER(0x44A0, float, SHADER_CONSTANT_296_X) +XE_GPU_REGISTER(0x44A1, float, SHADER_CONSTANT_296_Y) +XE_GPU_REGISTER(0x44A2, float, SHADER_CONSTANT_296_Z) +XE_GPU_REGISTER(0x44A3, float, SHADER_CONSTANT_296_W) +XE_GPU_REGISTER(0x44A4, float, SHADER_CONSTANT_297_X) +XE_GPU_REGISTER(0x44A5, float, SHADER_CONSTANT_297_Y) +XE_GPU_REGISTER(0x44A6, float, SHADER_CONSTANT_297_Z) +XE_GPU_REGISTER(0x44A7, float, SHADER_CONSTANT_297_W) +XE_GPU_REGISTER(0x44A8, float, SHADER_CONSTANT_298_X) +XE_GPU_REGISTER(0x44A9, float, SHADER_CONSTANT_298_Y) +XE_GPU_REGISTER(0x44AA, float, SHADER_CONSTANT_298_Z) +XE_GPU_REGISTER(0x44AB, float, SHADER_CONSTANT_298_W) +XE_GPU_REGISTER(0x44AC, float, SHADER_CONSTANT_299_X) +XE_GPU_REGISTER(0x44AD, float, SHADER_CONSTANT_299_Y) +XE_GPU_REGISTER(0x44AE, float, SHADER_CONSTANT_299_Z) +XE_GPU_REGISTER(0x44AF, float, SHADER_CONSTANT_299_W) +XE_GPU_REGISTER(0x44B0, float, SHADER_CONSTANT_300_X) +XE_GPU_REGISTER(0x44B1, float, SHADER_CONSTANT_300_Y) +XE_GPU_REGISTER(0x44B2, float, SHADER_CONSTANT_300_Z) +XE_GPU_REGISTER(0x44B3, float, SHADER_CONSTANT_300_W) +XE_GPU_REGISTER(0x44B4, float, SHADER_CONSTANT_301_X) +XE_GPU_REGISTER(0x44B5, float, SHADER_CONSTANT_301_Y) +XE_GPU_REGISTER(0x44B6, float, SHADER_CONSTANT_301_Z) +XE_GPU_REGISTER(0x44B7, float, SHADER_CONSTANT_301_W) +XE_GPU_REGISTER(0x44B8, float, SHADER_CONSTANT_302_X) +XE_GPU_REGISTER(0x44B9, float, SHADER_CONSTANT_302_Y) +XE_GPU_REGISTER(0x44BA, float, SHADER_CONSTANT_302_Z) +XE_GPU_REGISTER(0x44BB, float, SHADER_CONSTANT_302_W) +XE_GPU_REGISTER(0x44BC, float, SHADER_CONSTANT_303_X) +XE_GPU_REGISTER(0x44BD, float, SHADER_CONSTANT_303_Y) +XE_GPU_REGISTER(0x44BE, float, SHADER_CONSTANT_303_Z) +XE_GPU_REGISTER(0x44BF, float, SHADER_CONSTANT_303_W) +XE_GPU_REGISTER(0x44C0, float, SHADER_CONSTANT_304_X) +XE_GPU_REGISTER(0x44C1, float, SHADER_CONSTANT_304_Y) +XE_GPU_REGISTER(0x44C2, float, SHADER_CONSTANT_304_Z) +XE_GPU_REGISTER(0x44C3, float, SHADER_CONSTANT_304_W) +XE_GPU_REGISTER(0x44C4, float, SHADER_CONSTANT_305_X) +XE_GPU_REGISTER(0x44C5, float, SHADER_CONSTANT_305_Y) +XE_GPU_REGISTER(0x44C6, float, SHADER_CONSTANT_305_Z) +XE_GPU_REGISTER(0x44C7, float, SHADER_CONSTANT_305_W) +XE_GPU_REGISTER(0x44C8, float, SHADER_CONSTANT_306_X) +XE_GPU_REGISTER(0x44C9, float, SHADER_CONSTANT_306_Y) +XE_GPU_REGISTER(0x44CA, float, SHADER_CONSTANT_306_Z) +XE_GPU_REGISTER(0x44CB, float, SHADER_CONSTANT_306_W) +XE_GPU_REGISTER(0x44CC, float, SHADER_CONSTANT_307_X) +XE_GPU_REGISTER(0x44CD, float, SHADER_CONSTANT_307_Y) +XE_GPU_REGISTER(0x44CE, float, SHADER_CONSTANT_307_Z) +XE_GPU_REGISTER(0x44CF, float, SHADER_CONSTANT_307_W) +XE_GPU_REGISTER(0x44D0, float, SHADER_CONSTANT_308_X) +XE_GPU_REGISTER(0x44D1, float, SHADER_CONSTANT_308_Y) +XE_GPU_REGISTER(0x44D2, float, SHADER_CONSTANT_308_Z) +XE_GPU_REGISTER(0x44D3, float, SHADER_CONSTANT_308_W) +XE_GPU_REGISTER(0x44D4, float, SHADER_CONSTANT_309_X) +XE_GPU_REGISTER(0x44D5, float, SHADER_CONSTANT_309_Y) +XE_GPU_REGISTER(0x44D6, float, SHADER_CONSTANT_309_Z) +XE_GPU_REGISTER(0x44D7, float, SHADER_CONSTANT_309_W) +XE_GPU_REGISTER(0x44D8, float, SHADER_CONSTANT_310_X) +XE_GPU_REGISTER(0x44D9, float, SHADER_CONSTANT_310_Y) +XE_GPU_REGISTER(0x44DA, float, SHADER_CONSTANT_310_Z) +XE_GPU_REGISTER(0x44DB, float, SHADER_CONSTANT_310_W) +XE_GPU_REGISTER(0x44DC, float, SHADER_CONSTANT_311_X) +XE_GPU_REGISTER(0x44DD, float, SHADER_CONSTANT_311_Y) +XE_GPU_REGISTER(0x44DE, float, SHADER_CONSTANT_311_Z) +XE_GPU_REGISTER(0x44DF, float, SHADER_CONSTANT_311_W) +XE_GPU_REGISTER(0x44E0, float, SHADER_CONSTANT_312_X) +XE_GPU_REGISTER(0x44E1, float, SHADER_CONSTANT_312_Y) +XE_GPU_REGISTER(0x44E2, float, SHADER_CONSTANT_312_Z) +XE_GPU_REGISTER(0x44E3, float, SHADER_CONSTANT_312_W) +XE_GPU_REGISTER(0x44E4, float, SHADER_CONSTANT_313_X) +XE_GPU_REGISTER(0x44E5, float, SHADER_CONSTANT_313_Y) +XE_GPU_REGISTER(0x44E6, float, SHADER_CONSTANT_313_Z) +XE_GPU_REGISTER(0x44E7, float, SHADER_CONSTANT_313_W) +XE_GPU_REGISTER(0x44E8, float, SHADER_CONSTANT_314_X) +XE_GPU_REGISTER(0x44E9, float, SHADER_CONSTANT_314_Y) +XE_GPU_REGISTER(0x44EA, float, SHADER_CONSTANT_314_Z) +XE_GPU_REGISTER(0x44EB, float, SHADER_CONSTANT_314_W) +XE_GPU_REGISTER(0x44EC, float, SHADER_CONSTANT_315_X) +XE_GPU_REGISTER(0x44ED, float, SHADER_CONSTANT_315_Y) +XE_GPU_REGISTER(0x44EE, float, SHADER_CONSTANT_315_Z) +XE_GPU_REGISTER(0x44EF, float, SHADER_CONSTANT_315_W) +XE_GPU_REGISTER(0x44F0, float, SHADER_CONSTANT_316_X) +XE_GPU_REGISTER(0x44F1, float, SHADER_CONSTANT_316_Y) +XE_GPU_REGISTER(0x44F2, float, SHADER_CONSTANT_316_Z) +XE_GPU_REGISTER(0x44F3, float, SHADER_CONSTANT_316_W) +XE_GPU_REGISTER(0x44F4, float, SHADER_CONSTANT_317_X) +XE_GPU_REGISTER(0x44F5, float, SHADER_CONSTANT_317_Y) +XE_GPU_REGISTER(0x44F6, float, SHADER_CONSTANT_317_Z) +XE_GPU_REGISTER(0x44F7, float, SHADER_CONSTANT_317_W) +XE_GPU_REGISTER(0x44F8, float, SHADER_CONSTANT_318_X) +XE_GPU_REGISTER(0x44F9, float, SHADER_CONSTANT_318_Y) +XE_GPU_REGISTER(0x44FA, float, SHADER_CONSTANT_318_Z) +XE_GPU_REGISTER(0x44FB, float, SHADER_CONSTANT_318_W) +XE_GPU_REGISTER(0x44FC, float, SHADER_CONSTANT_319_X) +XE_GPU_REGISTER(0x44FD, float, SHADER_CONSTANT_319_Y) +XE_GPU_REGISTER(0x44FE, float, SHADER_CONSTANT_319_Z) +XE_GPU_REGISTER(0x44FF, float, SHADER_CONSTANT_319_W) +XE_GPU_REGISTER(0x4500, float, SHADER_CONSTANT_320_X) +XE_GPU_REGISTER(0x4501, float, SHADER_CONSTANT_320_Y) +XE_GPU_REGISTER(0x4502, float, SHADER_CONSTANT_320_Z) +XE_GPU_REGISTER(0x4503, float, SHADER_CONSTANT_320_W) +XE_GPU_REGISTER(0x4504, float, SHADER_CONSTANT_321_X) +XE_GPU_REGISTER(0x4505, float, SHADER_CONSTANT_321_Y) +XE_GPU_REGISTER(0x4506, float, SHADER_CONSTANT_321_Z) +XE_GPU_REGISTER(0x4507, float, SHADER_CONSTANT_321_W) +XE_GPU_REGISTER(0x4508, float, SHADER_CONSTANT_322_X) +XE_GPU_REGISTER(0x4509, float, SHADER_CONSTANT_322_Y) +XE_GPU_REGISTER(0x450A, float, SHADER_CONSTANT_322_Z) +XE_GPU_REGISTER(0x450B, float, SHADER_CONSTANT_322_W) +XE_GPU_REGISTER(0x450C, float, SHADER_CONSTANT_323_X) +XE_GPU_REGISTER(0x450D, float, SHADER_CONSTANT_323_Y) +XE_GPU_REGISTER(0x450E, float, SHADER_CONSTANT_323_Z) +XE_GPU_REGISTER(0x450F, float, SHADER_CONSTANT_323_W) +XE_GPU_REGISTER(0x4510, float, SHADER_CONSTANT_324_X) +XE_GPU_REGISTER(0x4511, float, SHADER_CONSTANT_324_Y) +XE_GPU_REGISTER(0x4512, float, SHADER_CONSTANT_324_Z) +XE_GPU_REGISTER(0x4513, float, SHADER_CONSTANT_324_W) +XE_GPU_REGISTER(0x4514, float, SHADER_CONSTANT_325_X) +XE_GPU_REGISTER(0x4515, float, SHADER_CONSTANT_325_Y) +XE_GPU_REGISTER(0x4516, float, SHADER_CONSTANT_325_Z) +XE_GPU_REGISTER(0x4517, float, SHADER_CONSTANT_325_W) +XE_GPU_REGISTER(0x4518, float, SHADER_CONSTANT_326_X) +XE_GPU_REGISTER(0x4519, float, SHADER_CONSTANT_326_Y) +XE_GPU_REGISTER(0x451A, float, SHADER_CONSTANT_326_Z) +XE_GPU_REGISTER(0x451B, float, SHADER_CONSTANT_326_W) +XE_GPU_REGISTER(0x451C, float, SHADER_CONSTANT_327_X) +XE_GPU_REGISTER(0x451D, float, SHADER_CONSTANT_327_Y) +XE_GPU_REGISTER(0x451E, float, SHADER_CONSTANT_327_Z) +XE_GPU_REGISTER(0x451F, float, SHADER_CONSTANT_327_W) +XE_GPU_REGISTER(0x4520, float, SHADER_CONSTANT_328_X) +XE_GPU_REGISTER(0x4521, float, SHADER_CONSTANT_328_Y) +XE_GPU_REGISTER(0x4522, float, SHADER_CONSTANT_328_Z) +XE_GPU_REGISTER(0x4523, float, SHADER_CONSTANT_328_W) +XE_GPU_REGISTER(0x4524, float, SHADER_CONSTANT_329_X) +XE_GPU_REGISTER(0x4525, float, SHADER_CONSTANT_329_Y) +XE_GPU_REGISTER(0x4526, float, SHADER_CONSTANT_329_Z) +XE_GPU_REGISTER(0x4527, float, SHADER_CONSTANT_329_W) +XE_GPU_REGISTER(0x4528, float, SHADER_CONSTANT_330_X) +XE_GPU_REGISTER(0x4529, float, SHADER_CONSTANT_330_Y) +XE_GPU_REGISTER(0x452A, float, SHADER_CONSTANT_330_Z) +XE_GPU_REGISTER(0x452B, float, SHADER_CONSTANT_330_W) +XE_GPU_REGISTER(0x452C, float, SHADER_CONSTANT_331_X) +XE_GPU_REGISTER(0x452D, float, SHADER_CONSTANT_331_Y) +XE_GPU_REGISTER(0x452E, float, SHADER_CONSTANT_331_Z) +XE_GPU_REGISTER(0x452F, float, SHADER_CONSTANT_331_W) +XE_GPU_REGISTER(0x4530, float, SHADER_CONSTANT_332_X) +XE_GPU_REGISTER(0x4531, float, SHADER_CONSTANT_332_Y) +XE_GPU_REGISTER(0x4532, float, SHADER_CONSTANT_332_Z) +XE_GPU_REGISTER(0x4533, float, SHADER_CONSTANT_332_W) +XE_GPU_REGISTER(0x4534, float, SHADER_CONSTANT_333_X) +XE_GPU_REGISTER(0x4535, float, SHADER_CONSTANT_333_Y) +XE_GPU_REGISTER(0x4536, float, SHADER_CONSTANT_333_Z) +XE_GPU_REGISTER(0x4537, float, SHADER_CONSTANT_333_W) +XE_GPU_REGISTER(0x4538, float, SHADER_CONSTANT_334_X) +XE_GPU_REGISTER(0x4539, float, SHADER_CONSTANT_334_Y) +XE_GPU_REGISTER(0x453A, float, SHADER_CONSTANT_334_Z) +XE_GPU_REGISTER(0x453B, float, SHADER_CONSTANT_334_W) +XE_GPU_REGISTER(0x453C, float, SHADER_CONSTANT_335_X) +XE_GPU_REGISTER(0x453D, float, SHADER_CONSTANT_335_Y) +XE_GPU_REGISTER(0x453E, float, SHADER_CONSTANT_335_Z) +XE_GPU_REGISTER(0x453F, float, SHADER_CONSTANT_335_W) +XE_GPU_REGISTER(0x4540, float, SHADER_CONSTANT_336_X) +XE_GPU_REGISTER(0x4541, float, SHADER_CONSTANT_336_Y) +XE_GPU_REGISTER(0x4542, float, SHADER_CONSTANT_336_Z) +XE_GPU_REGISTER(0x4543, float, SHADER_CONSTANT_336_W) +XE_GPU_REGISTER(0x4544, float, SHADER_CONSTANT_337_X) +XE_GPU_REGISTER(0x4545, float, SHADER_CONSTANT_337_Y) +XE_GPU_REGISTER(0x4546, float, SHADER_CONSTANT_337_Z) +XE_GPU_REGISTER(0x4547, float, SHADER_CONSTANT_337_W) +XE_GPU_REGISTER(0x4548, float, SHADER_CONSTANT_338_X) +XE_GPU_REGISTER(0x4549, float, SHADER_CONSTANT_338_Y) +XE_GPU_REGISTER(0x454A, float, SHADER_CONSTANT_338_Z) +XE_GPU_REGISTER(0x454B, float, SHADER_CONSTANT_338_W) +XE_GPU_REGISTER(0x454C, float, SHADER_CONSTANT_339_X) +XE_GPU_REGISTER(0x454D, float, SHADER_CONSTANT_339_Y) +XE_GPU_REGISTER(0x454E, float, SHADER_CONSTANT_339_Z) +XE_GPU_REGISTER(0x454F, float, SHADER_CONSTANT_339_W) +XE_GPU_REGISTER(0x4550, float, SHADER_CONSTANT_340_X) +XE_GPU_REGISTER(0x4551, float, SHADER_CONSTANT_340_Y) +XE_GPU_REGISTER(0x4552, float, SHADER_CONSTANT_340_Z) +XE_GPU_REGISTER(0x4553, float, SHADER_CONSTANT_340_W) +XE_GPU_REGISTER(0x4554, float, SHADER_CONSTANT_341_X) +XE_GPU_REGISTER(0x4555, float, SHADER_CONSTANT_341_Y) +XE_GPU_REGISTER(0x4556, float, SHADER_CONSTANT_341_Z) +XE_GPU_REGISTER(0x4557, float, SHADER_CONSTANT_341_W) +XE_GPU_REGISTER(0x4558, float, SHADER_CONSTANT_342_X) +XE_GPU_REGISTER(0x4559, float, SHADER_CONSTANT_342_Y) +XE_GPU_REGISTER(0x455A, float, SHADER_CONSTANT_342_Z) +XE_GPU_REGISTER(0x455B, float, SHADER_CONSTANT_342_W) +XE_GPU_REGISTER(0x455C, float, SHADER_CONSTANT_343_X) +XE_GPU_REGISTER(0x455D, float, SHADER_CONSTANT_343_Y) +XE_GPU_REGISTER(0x455E, float, SHADER_CONSTANT_343_Z) +XE_GPU_REGISTER(0x455F, float, SHADER_CONSTANT_343_W) +XE_GPU_REGISTER(0x4560, float, SHADER_CONSTANT_344_X) +XE_GPU_REGISTER(0x4561, float, SHADER_CONSTANT_344_Y) +XE_GPU_REGISTER(0x4562, float, SHADER_CONSTANT_344_Z) +XE_GPU_REGISTER(0x4563, float, SHADER_CONSTANT_344_W) +XE_GPU_REGISTER(0x4564, float, SHADER_CONSTANT_345_X) +XE_GPU_REGISTER(0x4565, float, SHADER_CONSTANT_345_Y) +XE_GPU_REGISTER(0x4566, float, SHADER_CONSTANT_345_Z) +XE_GPU_REGISTER(0x4567, float, SHADER_CONSTANT_345_W) +XE_GPU_REGISTER(0x4568, float, SHADER_CONSTANT_346_X) +XE_GPU_REGISTER(0x4569, float, SHADER_CONSTANT_346_Y) +XE_GPU_REGISTER(0x456A, float, SHADER_CONSTANT_346_Z) +XE_GPU_REGISTER(0x456B, float, SHADER_CONSTANT_346_W) +XE_GPU_REGISTER(0x456C, float, SHADER_CONSTANT_347_X) +XE_GPU_REGISTER(0x456D, float, SHADER_CONSTANT_347_Y) +XE_GPU_REGISTER(0x456E, float, SHADER_CONSTANT_347_Z) +XE_GPU_REGISTER(0x456F, float, SHADER_CONSTANT_347_W) +XE_GPU_REGISTER(0x4570, float, SHADER_CONSTANT_348_X) +XE_GPU_REGISTER(0x4571, float, SHADER_CONSTANT_348_Y) +XE_GPU_REGISTER(0x4572, float, SHADER_CONSTANT_348_Z) +XE_GPU_REGISTER(0x4573, float, SHADER_CONSTANT_348_W) +XE_GPU_REGISTER(0x4574, float, SHADER_CONSTANT_349_X) +XE_GPU_REGISTER(0x4575, float, SHADER_CONSTANT_349_Y) +XE_GPU_REGISTER(0x4576, float, SHADER_CONSTANT_349_Z) +XE_GPU_REGISTER(0x4577, float, SHADER_CONSTANT_349_W) +XE_GPU_REGISTER(0x4578, float, SHADER_CONSTANT_350_X) +XE_GPU_REGISTER(0x4579, float, SHADER_CONSTANT_350_Y) +XE_GPU_REGISTER(0x457A, float, SHADER_CONSTANT_350_Z) +XE_GPU_REGISTER(0x457B, float, SHADER_CONSTANT_350_W) +XE_GPU_REGISTER(0x457C, float, SHADER_CONSTANT_351_X) +XE_GPU_REGISTER(0x457D, float, SHADER_CONSTANT_351_Y) +XE_GPU_REGISTER(0x457E, float, SHADER_CONSTANT_351_Z) +XE_GPU_REGISTER(0x457F, float, SHADER_CONSTANT_351_W) +XE_GPU_REGISTER(0x4580, float, SHADER_CONSTANT_352_X) +XE_GPU_REGISTER(0x4581, float, SHADER_CONSTANT_352_Y) +XE_GPU_REGISTER(0x4582, float, SHADER_CONSTANT_352_Z) +XE_GPU_REGISTER(0x4583, float, SHADER_CONSTANT_352_W) +XE_GPU_REGISTER(0x4584, float, SHADER_CONSTANT_353_X) +XE_GPU_REGISTER(0x4585, float, SHADER_CONSTANT_353_Y) +XE_GPU_REGISTER(0x4586, float, SHADER_CONSTANT_353_Z) +XE_GPU_REGISTER(0x4587, float, SHADER_CONSTANT_353_W) +XE_GPU_REGISTER(0x4588, float, SHADER_CONSTANT_354_X) +XE_GPU_REGISTER(0x4589, float, SHADER_CONSTANT_354_Y) +XE_GPU_REGISTER(0x458A, float, SHADER_CONSTANT_354_Z) +XE_GPU_REGISTER(0x458B, float, SHADER_CONSTANT_354_W) +XE_GPU_REGISTER(0x458C, float, SHADER_CONSTANT_355_X) +XE_GPU_REGISTER(0x458D, float, SHADER_CONSTANT_355_Y) +XE_GPU_REGISTER(0x458E, float, SHADER_CONSTANT_355_Z) +XE_GPU_REGISTER(0x458F, float, SHADER_CONSTANT_355_W) +XE_GPU_REGISTER(0x4590, float, SHADER_CONSTANT_356_X) +XE_GPU_REGISTER(0x4591, float, SHADER_CONSTANT_356_Y) +XE_GPU_REGISTER(0x4592, float, SHADER_CONSTANT_356_Z) +XE_GPU_REGISTER(0x4593, float, SHADER_CONSTANT_356_W) +XE_GPU_REGISTER(0x4594, float, SHADER_CONSTANT_357_X) +XE_GPU_REGISTER(0x4595, float, SHADER_CONSTANT_357_Y) +XE_GPU_REGISTER(0x4596, float, SHADER_CONSTANT_357_Z) +XE_GPU_REGISTER(0x4597, float, SHADER_CONSTANT_357_W) +XE_GPU_REGISTER(0x4598, float, SHADER_CONSTANT_358_X) +XE_GPU_REGISTER(0x4599, float, SHADER_CONSTANT_358_Y) +XE_GPU_REGISTER(0x459A, float, SHADER_CONSTANT_358_Z) +XE_GPU_REGISTER(0x459B, float, SHADER_CONSTANT_358_W) +XE_GPU_REGISTER(0x459C, float, SHADER_CONSTANT_359_X) +XE_GPU_REGISTER(0x459D, float, SHADER_CONSTANT_359_Y) +XE_GPU_REGISTER(0x459E, float, SHADER_CONSTANT_359_Z) +XE_GPU_REGISTER(0x459F, float, SHADER_CONSTANT_359_W) +XE_GPU_REGISTER(0x45A0, float, SHADER_CONSTANT_360_X) +XE_GPU_REGISTER(0x45A1, float, SHADER_CONSTANT_360_Y) +XE_GPU_REGISTER(0x45A2, float, SHADER_CONSTANT_360_Z) +XE_GPU_REGISTER(0x45A3, float, SHADER_CONSTANT_360_W) +XE_GPU_REGISTER(0x45A4, float, SHADER_CONSTANT_361_X) +XE_GPU_REGISTER(0x45A5, float, SHADER_CONSTANT_361_Y) +XE_GPU_REGISTER(0x45A6, float, SHADER_CONSTANT_361_Z) +XE_GPU_REGISTER(0x45A7, float, SHADER_CONSTANT_361_W) +XE_GPU_REGISTER(0x45A8, float, SHADER_CONSTANT_362_X) +XE_GPU_REGISTER(0x45A9, float, SHADER_CONSTANT_362_Y) +XE_GPU_REGISTER(0x45AA, float, SHADER_CONSTANT_362_Z) +XE_GPU_REGISTER(0x45AB, float, SHADER_CONSTANT_362_W) +XE_GPU_REGISTER(0x45AC, float, SHADER_CONSTANT_363_X) +XE_GPU_REGISTER(0x45AD, float, SHADER_CONSTANT_363_Y) +XE_GPU_REGISTER(0x45AE, float, SHADER_CONSTANT_363_Z) +XE_GPU_REGISTER(0x45AF, float, SHADER_CONSTANT_363_W) +XE_GPU_REGISTER(0x45B0, float, SHADER_CONSTANT_364_X) +XE_GPU_REGISTER(0x45B1, float, SHADER_CONSTANT_364_Y) +XE_GPU_REGISTER(0x45B2, float, SHADER_CONSTANT_364_Z) +XE_GPU_REGISTER(0x45B3, float, SHADER_CONSTANT_364_W) +XE_GPU_REGISTER(0x45B4, float, SHADER_CONSTANT_365_X) +XE_GPU_REGISTER(0x45B5, float, SHADER_CONSTANT_365_Y) +XE_GPU_REGISTER(0x45B6, float, SHADER_CONSTANT_365_Z) +XE_GPU_REGISTER(0x45B7, float, SHADER_CONSTANT_365_W) +XE_GPU_REGISTER(0x45B8, float, SHADER_CONSTANT_366_X) +XE_GPU_REGISTER(0x45B9, float, SHADER_CONSTANT_366_Y) +XE_GPU_REGISTER(0x45BA, float, SHADER_CONSTANT_366_Z) +XE_GPU_REGISTER(0x45BB, float, SHADER_CONSTANT_366_W) +XE_GPU_REGISTER(0x45BC, float, SHADER_CONSTANT_367_X) +XE_GPU_REGISTER(0x45BD, float, SHADER_CONSTANT_367_Y) +XE_GPU_REGISTER(0x45BE, float, SHADER_CONSTANT_367_Z) +XE_GPU_REGISTER(0x45BF, float, SHADER_CONSTANT_367_W) +XE_GPU_REGISTER(0x45C0, float, SHADER_CONSTANT_368_X) +XE_GPU_REGISTER(0x45C1, float, SHADER_CONSTANT_368_Y) +XE_GPU_REGISTER(0x45C2, float, SHADER_CONSTANT_368_Z) +XE_GPU_REGISTER(0x45C3, float, SHADER_CONSTANT_368_W) +XE_GPU_REGISTER(0x45C4, float, SHADER_CONSTANT_369_X) +XE_GPU_REGISTER(0x45C5, float, SHADER_CONSTANT_369_Y) +XE_GPU_REGISTER(0x45C6, float, SHADER_CONSTANT_369_Z) +XE_GPU_REGISTER(0x45C7, float, SHADER_CONSTANT_369_W) +XE_GPU_REGISTER(0x45C8, float, SHADER_CONSTANT_370_X) +XE_GPU_REGISTER(0x45C9, float, SHADER_CONSTANT_370_Y) +XE_GPU_REGISTER(0x45CA, float, SHADER_CONSTANT_370_Z) +XE_GPU_REGISTER(0x45CB, float, SHADER_CONSTANT_370_W) +XE_GPU_REGISTER(0x45CC, float, SHADER_CONSTANT_371_X) +XE_GPU_REGISTER(0x45CD, float, SHADER_CONSTANT_371_Y) +XE_GPU_REGISTER(0x45CE, float, SHADER_CONSTANT_371_Z) +XE_GPU_REGISTER(0x45CF, float, SHADER_CONSTANT_371_W) +XE_GPU_REGISTER(0x45D0, float, SHADER_CONSTANT_372_X) +XE_GPU_REGISTER(0x45D1, float, SHADER_CONSTANT_372_Y) +XE_GPU_REGISTER(0x45D2, float, SHADER_CONSTANT_372_Z) +XE_GPU_REGISTER(0x45D3, float, SHADER_CONSTANT_372_W) +XE_GPU_REGISTER(0x45D4, float, SHADER_CONSTANT_373_X) +XE_GPU_REGISTER(0x45D5, float, SHADER_CONSTANT_373_Y) +XE_GPU_REGISTER(0x45D6, float, SHADER_CONSTANT_373_Z) +XE_GPU_REGISTER(0x45D7, float, SHADER_CONSTANT_373_W) +XE_GPU_REGISTER(0x45D8, float, SHADER_CONSTANT_374_X) +XE_GPU_REGISTER(0x45D9, float, SHADER_CONSTANT_374_Y) +XE_GPU_REGISTER(0x45DA, float, SHADER_CONSTANT_374_Z) +XE_GPU_REGISTER(0x45DB, float, SHADER_CONSTANT_374_W) +XE_GPU_REGISTER(0x45DC, float, SHADER_CONSTANT_375_X) +XE_GPU_REGISTER(0x45DD, float, SHADER_CONSTANT_375_Y) +XE_GPU_REGISTER(0x45DE, float, SHADER_CONSTANT_375_Z) +XE_GPU_REGISTER(0x45DF, float, SHADER_CONSTANT_375_W) +XE_GPU_REGISTER(0x45E0, float, SHADER_CONSTANT_376_X) +XE_GPU_REGISTER(0x45E1, float, SHADER_CONSTANT_376_Y) +XE_GPU_REGISTER(0x45E2, float, SHADER_CONSTANT_376_Z) +XE_GPU_REGISTER(0x45E3, float, SHADER_CONSTANT_376_W) +XE_GPU_REGISTER(0x45E4, float, SHADER_CONSTANT_377_X) +XE_GPU_REGISTER(0x45E5, float, SHADER_CONSTANT_377_Y) +XE_GPU_REGISTER(0x45E6, float, SHADER_CONSTANT_377_Z) +XE_GPU_REGISTER(0x45E7, float, SHADER_CONSTANT_377_W) +XE_GPU_REGISTER(0x45E8, float, SHADER_CONSTANT_378_X) +XE_GPU_REGISTER(0x45E9, float, SHADER_CONSTANT_378_Y) +XE_GPU_REGISTER(0x45EA, float, SHADER_CONSTANT_378_Z) +XE_GPU_REGISTER(0x45EB, float, SHADER_CONSTANT_378_W) +XE_GPU_REGISTER(0x45EC, float, SHADER_CONSTANT_379_X) +XE_GPU_REGISTER(0x45ED, float, SHADER_CONSTANT_379_Y) +XE_GPU_REGISTER(0x45EE, float, SHADER_CONSTANT_379_Z) +XE_GPU_REGISTER(0x45EF, float, SHADER_CONSTANT_379_W) +XE_GPU_REGISTER(0x45F0, float, SHADER_CONSTANT_380_X) +XE_GPU_REGISTER(0x45F1, float, SHADER_CONSTANT_380_Y) +XE_GPU_REGISTER(0x45F2, float, SHADER_CONSTANT_380_Z) +XE_GPU_REGISTER(0x45F3, float, SHADER_CONSTANT_380_W) +XE_GPU_REGISTER(0x45F4, float, SHADER_CONSTANT_381_X) +XE_GPU_REGISTER(0x45F5, float, SHADER_CONSTANT_381_Y) +XE_GPU_REGISTER(0x45F6, float, SHADER_CONSTANT_381_Z) +XE_GPU_REGISTER(0x45F7, float, SHADER_CONSTANT_381_W) +XE_GPU_REGISTER(0x45F8, float, SHADER_CONSTANT_382_X) +XE_GPU_REGISTER(0x45F9, float, SHADER_CONSTANT_382_Y) +XE_GPU_REGISTER(0x45FA, float, SHADER_CONSTANT_382_Z) +XE_GPU_REGISTER(0x45FB, float, SHADER_CONSTANT_382_W) +XE_GPU_REGISTER(0x45FC, float, SHADER_CONSTANT_383_X) +XE_GPU_REGISTER(0x45FD, float, SHADER_CONSTANT_383_Y) +XE_GPU_REGISTER(0x45FE, float, SHADER_CONSTANT_383_Z) +XE_GPU_REGISTER(0x45FF, float, SHADER_CONSTANT_383_W) +XE_GPU_REGISTER(0x4600, float, SHADER_CONSTANT_384_X) +XE_GPU_REGISTER(0x4601, float, SHADER_CONSTANT_384_Y) +XE_GPU_REGISTER(0x4602, float, SHADER_CONSTANT_384_Z) +XE_GPU_REGISTER(0x4603, float, SHADER_CONSTANT_384_W) +XE_GPU_REGISTER(0x4604, float, SHADER_CONSTANT_385_X) +XE_GPU_REGISTER(0x4605, float, SHADER_CONSTANT_385_Y) +XE_GPU_REGISTER(0x4606, float, SHADER_CONSTANT_385_Z) +XE_GPU_REGISTER(0x4607, float, SHADER_CONSTANT_385_W) +XE_GPU_REGISTER(0x4608, float, SHADER_CONSTANT_386_X) +XE_GPU_REGISTER(0x4609, float, SHADER_CONSTANT_386_Y) +XE_GPU_REGISTER(0x460A, float, SHADER_CONSTANT_386_Z) +XE_GPU_REGISTER(0x460B, float, SHADER_CONSTANT_386_W) +XE_GPU_REGISTER(0x460C, float, SHADER_CONSTANT_387_X) +XE_GPU_REGISTER(0x460D, float, SHADER_CONSTANT_387_Y) +XE_GPU_REGISTER(0x460E, float, SHADER_CONSTANT_387_Z) +XE_GPU_REGISTER(0x460F, float, SHADER_CONSTANT_387_W) +XE_GPU_REGISTER(0x4610, float, SHADER_CONSTANT_388_X) +XE_GPU_REGISTER(0x4611, float, SHADER_CONSTANT_388_Y) +XE_GPU_REGISTER(0x4612, float, SHADER_CONSTANT_388_Z) +XE_GPU_REGISTER(0x4613, float, SHADER_CONSTANT_388_W) +XE_GPU_REGISTER(0x4614, float, SHADER_CONSTANT_389_X) +XE_GPU_REGISTER(0x4615, float, SHADER_CONSTANT_389_Y) +XE_GPU_REGISTER(0x4616, float, SHADER_CONSTANT_389_Z) +XE_GPU_REGISTER(0x4617, float, SHADER_CONSTANT_389_W) +XE_GPU_REGISTER(0x4618, float, SHADER_CONSTANT_390_X) +XE_GPU_REGISTER(0x4619, float, SHADER_CONSTANT_390_Y) +XE_GPU_REGISTER(0x461A, float, SHADER_CONSTANT_390_Z) +XE_GPU_REGISTER(0x461B, float, SHADER_CONSTANT_390_W) +XE_GPU_REGISTER(0x461C, float, SHADER_CONSTANT_391_X) +XE_GPU_REGISTER(0x461D, float, SHADER_CONSTANT_391_Y) +XE_GPU_REGISTER(0x461E, float, SHADER_CONSTANT_391_Z) +XE_GPU_REGISTER(0x461F, float, SHADER_CONSTANT_391_W) +XE_GPU_REGISTER(0x4620, float, SHADER_CONSTANT_392_X) +XE_GPU_REGISTER(0x4621, float, SHADER_CONSTANT_392_Y) +XE_GPU_REGISTER(0x4622, float, SHADER_CONSTANT_392_Z) +XE_GPU_REGISTER(0x4623, float, SHADER_CONSTANT_392_W) +XE_GPU_REGISTER(0x4624, float, SHADER_CONSTANT_393_X) +XE_GPU_REGISTER(0x4625, float, SHADER_CONSTANT_393_Y) +XE_GPU_REGISTER(0x4626, float, SHADER_CONSTANT_393_Z) +XE_GPU_REGISTER(0x4627, float, SHADER_CONSTANT_393_W) +XE_GPU_REGISTER(0x4628, float, SHADER_CONSTANT_394_X) +XE_GPU_REGISTER(0x4629, float, SHADER_CONSTANT_394_Y) +XE_GPU_REGISTER(0x462A, float, SHADER_CONSTANT_394_Z) +XE_GPU_REGISTER(0x462B, float, SHADER_CONSTANT_394_W) +XE_GPU_REGISTER(0x462C, float, SHADER_CONSTANT_395_X) +XE_GPU_REGISTER(0x462D, float, SHADER_CONSTANT_395_Y) +XE_GPU_REGISTER(0x462E, float, SHADER_CONSTANT_395_Z) +XE_GPU_REGISTER(0x462F, float, SHADER_CONSTANT_395_W) +XE_GPU_REGISTER(0x4630, float, SHADER_CONSTANT_396_X) +XE_GPU_REGISTER(0x4631, float, SHADER_CONSTANT_396_Y) +XE_GPU_REGISTER(0x4632, float, SHADER_CONSTANT_396_Z) +XE_GPU_REGISTER(0x4633, float, SHADER_CONSTANT_396_W) +XE_GPU_REGISTER(0x4634, float, SHADER_CONSTANT_397_X) +XE_GPU_REGISTER(0x4635, float, SHADER_CONSTANT_397_Y) +XE_GPU_REGISTER(0x4636, float, SHADER_CONSTANT_397_Z) +XE_GPU_REGISTER(0x4637, float, SHADER_CONSTANT_397_W) +XE_GPU_REGISTER(0x4638, float, SHADER_CONSTANT_398_X) +XE_GPU_REGISTER(0x4639, float, SHADER_CONSTANT_398_Y) +XE_GPU_REGISTER(0x463A, float, SHADER_CONSTANT_398_Z) +XE_GPU_REGISTER(0x463B, float, SHADER_CONSTANT_398_W) +XE_GPU_REGISTER(0x463C, float, SHADER_CONSTANT_399_X) +XE_GPU_REGISTER(0x463D, float, SHADER_CONSTANT_399_Y) +XE_GPU_REGISTER(0x463E, float, SHADER_CONSTANT_399_Z) +XE_GPU_REGISTER(0x463F, float, SHADER_CONSTANT_399_W) +XE_GPU_REGISTER(0x4640, float, SHADER_CONSTANT_400_X) +XE_GPU_REGISTER(0x4641, float, SHADER_CONSTANT_400_Y) +XE_GPU_REGISTER(0x4642, float, SHADER_CONSTANT_400_Z) +XE_GPU_REGISTER(0x4643, float, SHADER_CONSTANT_400_W) +XE_GPU_REGISTER(0x4644, float, SHADER_CONSTANT_401_X) +XE_GPU_REGISTER(0x4645, float, SHADER_CONSTANT_401_Y) +XE_GPU_REGISTER(0x4646, float, SHADER_CONSTANT_401_Z) +XE_GPU_REGISTER(0x4647, float, SHADER_CONSTANT_401_W) +XE_GPU_REGISTER(0x4648, float, SHADER_CONSTANT_402_X) +XE_GPU_REGISTER(0x4649, float, SHADER_CONSTANT_402_Y) +XE_GPU_REGISTER(0x464A, float, SHADER_CONSTANT_402_Z) +XE_GPU_REGISTER(0x464B, float, SHADER_CONSTANT_402_W) +XE_GPU_REGISTER(0x464C, float, SHADER_CONSTANT_403_X) +XE_GPU_REGISTER(0x464D, float, SHADER_CONSTANT_403_Y) +XE_GPU_REGISTER(0x464E, float, SHADER_CONSTANT_403_Z) +XE_GPU_REGISTER(0x464F, float, SHADER_CONSTANT_403_W) +XE_GPU_REGISTER(0x4650, float, SHADER_CONSTANT_404_X) +XE_GPU_REGISTER(0x4651, float, SHADER_CONSTANT_404_Y) +XE_GPU_REGISTER(0x4652, float, SHADER_CONSTANT_404_Z) +XE_GPU_REGISTER(0x4653, float, SHADER_CONSTANT_404_W) +XE_GPU_REGISTER(0x4654, float, SHADER_CONSTANT_405_X) +XE_GPU_REGISTER(0x4655, float, SHADER_CONSTANT_405_Y) +XE_GPU_REGISTER(0x4656, float, SHADER_CONSTANT_405_Z) +XE_GPU_REGISTER(0x4657, float, SHADER_CONSTANT_405_W) +XE_GPU_REGISTER(0x4658, float, SHADER_CONSTANT_406_X) +XE_GPU_REGISTER(0x4659, float, SHADER_CONSTANT_406_Y) +XE_GPU_REGISTER(0x465A, float, SHADER_CONSTANT_406_Z) +XE_GPU_REGISTER(0x465B, float, SHADER_CONSTANT_406_W) +XE_GPU_REGISTER(0x465C, float, SHADER_CONSTANT_407_X) +XE_GPU_REGISTER(0x465D, float, SHADER_CONSTANT_407_Y) +XE_GPU_REGISTER(0x465E, float, SHADER_CONSTANT_407_Z) +XE_GPU_REGISTER(0x465F, float, SHADER_CONSTANT_407_W) +XE_GPU_REGISTER(0x4660, float, SHADER_CONSTANT_408_X) +XE_GPU_REGISTER(0x4661, float, SHADER_CONSTANT_408_Y) +XE_GPU_REGISTER(0x4662, float, SHADER_CONSTANT_408_Z) +XE_GPU_REGISTER(0x4663, float, SHADER_CONSTANT_408_W) +XE_GPU_REGISTER(0x4664, float, SHADER_CONSTANT_409_X) +XE_GPU_REGISTER(0x4665, float, SHADER_CONSTANT_409_Y) +XE_GPU_REGISTER(0x4666, float, SHADER_CONSTANT_409_Z) +XE_GPU_REGISTER(0x4667, float, SHADER_CONSTANT_409_W) +XE_GPU_REGISTER(0x4668, float, SHADER_CONSTANT_410_X) +XE_GPU_REGISTER(0x4669, float, SHADER_CONSTANT_410_Y) +XE_GPU_REGISTER(0x466A, float, SHADER_CONSTANT_410_Z) +XE_GPU_REGISTER(0x466B, float, SHADER_CONSTANT_410_W) +XE_GPU_REGISTER(0x466C, float, SHADER_CONSTANT_411_X) +XE_GPU_REGISTER(0x466D, float, SHADER_CONSTANT_411_Y) +XE_GPU_REGISTER(0x466E, float, SHADER_CONSTANT_411_Z) +XE_GPU_REGISTER(0x466F, float, SHADER_CONSTANT_411_W) +XE_GPU_REGISTER(0x4670, float, SHADER_CONSTANT_412_X) +XE_GPU_REGISTER(0x4671, float, SHADER_CONSTANT_412_Y) +XE_GPU_REGISTER(0x4672, float, SHADER_CONSTANT_412_Z) +XE_GPU_REGISTER(0x4673, float, SHADER_CONSTANT_412_W) +XE_GPU_REGISTER(0x4674, float, SHADER_CONSTANT_413_X) +XE_GPU_REGISTER(0x4675, float, SHADER_CONSTANT_413_Y) +XE_GPU_REGISTER(0x4676, float, SHADER_CONSTANT_413_Z) +XE_GPU_REGISTER(0x4677, float, SHADER_CONSTANT_413_W) +XE_GPU_REGISTER(0x4678, float, SHADER_CONSTANT_414_X) +XE_GPU_REGISTER(0x4679, float, SHADER_CONSTANT_414_Y) +XE_GPU_REGISTER(0x467A, float, SHADER_CONSTANT_414_Z) +XE_GPU_REGISTER(0x467B, float, SHADER_CONSTANT_414_W) +XE_GPU_REGISTER(0x467C, float, SHADER_CONSTANT_415_X) +XE_GPU_REGISTER(0x467D, float, SHADER_CONSTANT_415_Y) +XE_GPU_REGISTER(0x467E, float, SHADER_CONSTANT_415_Z) +XE_GPU_REGISTER(0x467F, float, SHADER_CONSTANT_415_W) +XE_GPU_REGISTER(0x4680, float, SHADER_CONSTANT_416_X) +XE_GPU_REGISTER(0x4681, float, SHADER_CONSTANT_416_Y) +XE_GPU_REGISTER(0x4682, float, SHADER_CONSTANT_416_Z) +XE_GPU_REGISTER(0x4683, float, SHADER_CONSTANT_416_W) +XE_GPU_REGISTER(0x4684, float, SHADER_CONSTANT_417_X) +XE_GPU_REGISTER(0x4685, float, SHADER_CONSTANT_417_Y) +XE_GPU_REGISTER(0x4686, float, SHADER_CONSTANT_417_Z) +XE_GPU_REGISTER(0x4687, float, SHADER_CONSTANT_417_W) +XE_GPU_REGISTER(0x4688, float, SHADER_CONSTANT_418_X) +XE_GPU_REGISTER(0x4689, float, SHADER_CONSTANT_418_Y) +XE_GPU_REGISTER(0x468A, float, SHADER_CONSTANT_418_Z) +XE_GPU_REGISTER(0x468B, float, SHADER_CONSTANT_418_W) +XE_GPU_REGISTER(0x468C, float, SHADER_CONSTANT_419_X) +XE_GPU_REGISTER(0x468D, float, SHADER_CONSTANT_419_Y) +XE_GPU_REGISTER(0x468E, float, SHADER_CONSTANT_419_Z) +XE_GPU_REGISTER(0x468F, float, SHADER_CONSTANT_419_W) +XE_GPU_REGISTER(0x4690, float, SHADER_CONSTANT_420_X) +XE_GPU_REGISTER(0x4691, float, SHADER_CONSTANT_420_Y) +XE_GPU_REGISTER(0x4692, float, SHADER_CONSTANT_420_Z) +XE_GPU_REGISTER(0x4693, float, SHADER_CONSTANT_420_W) +XE_GPU_REGISTER(0x4694, float, SHADER_CONSTANT_421_X) +XE_GPU_REGISTER(0x4695, float, SHADER_CONSTANT_421_Y) +XE_GPU_REGISTER(0x4696, float, SHADER_CONSTANT_421_Z) +XE_GPU_REGISTER(0x4697, float, SHADER_CONSTANT_421_W) +XE_GPU_REGISTER(0x4698, float, SHADER_CONSTANT_422_X) +XE_GPU_REGISTER(0x4699, float, SHADER_CONSTANT_422_Y) +XE_GPU_REGISTER(0x469A, float, SHADER_CONSTANT_422_Z) +XE_GPU_REGISTER(0x469B, float, SHADER_CONSTANT_422_W) +XE_GPU_REGISTER(0x469C, float, SHADER_CONSTANT_423_X) +XE_GPU_REGISTER(0x469D, float, SHADER_CONSTANT_423_Y) +XE_GPU_REGISTER(0x469E, float, SHADER_CONSTANT_423_Z) +XE_GPU_REGISTER(0x469F, float, SHADER_CONSTANT_423_W) +XE_GPU_REGISTER(0x46A0, float, SHADER_CONSTANT_424_X) +XE_GPU_REGISTER(0x46A1, float, SHADER_CONSTANT_424_Y) +XE_GPU_REGISTER(0x46A2, float, SHADER_CONSTANT_424_Z) +XE_GPU_REGISTER(0x46A3, float, SHADER_CONSTANT_424_W) +XE_GPU_REGISTER(0x46A4, float, SHADER_CONSTANT_425_X) +XE_GPU_REGISTER(0x46A5, float, SHADER_CONSTANT_425_Y) +XE_GPU_REGISTER(0x46A6, float, SHADER_CONSTANT_425_Z) +XE_GPU_REGISTER(0x46A7, float, SHADER_CONSTANT_425_W) +XE_GPU_REGISTER(0x46A8, float, SHADER_CONSTANT_426_X) +XE_GPU_REGISTER(0x46A9, float, SHADER_CONSTANT_426_Y) +XE_GPU_REGISTER(0x46AA, float, SHADER_CONSTANT_426_Z) +XE_GPU_REGISTER(0x46AB, float, SHADER_CONSTANT_426_W) +XE_GPU_REGISTER(0x46AC, float, SHADER_CONSTANT_427_X) +XE_GPU_REGISTER(0x46AD, float, SHADER_CONSTANT_427_Y) +XE_GPU_REGISTER(0x46AE, float, SHADER_CONSTANT_427_Z) +XE_GPU_REGISTER(0x46AF, float, SHADER_CONSTANT_427_W) +XE_GPU_REGISTER(0x46B0, float, SHADER_CONSTANT_428_X) +XE_GPU_REGISTER(0x46B1, float, SHADER_CONSTANT_428_Y) +XE_GPU_REGISTER(0x46B2, float, SHADER_CONSTANT_428_Z) +XE_GPU_REGISTER(0x46B3, float, SHADER_CONSTANT_428_W) +XE_GPU_REGISTER(0x46B4, float, SHADER_CONSTANT_429_X) +XE_GPU_REGISTER(0x46B5, float, SHADER_CONSTANT_429_Y) +XE_GPU_REGISTER(0x46B6, float, SHADER_CONSTANT_429_Z) +XE_GPU_REGISTER(0x46B7, float, SHADER_CONSTANT_429_W) +XE_GPU_REGISTER(0x46B8, float, SHADER_CONSTANT_430_X) +XE_GPU_REGISTER(0x46B9, float, SHADER_CONSTANT_430_Y) +XE_GPU_REGISTER(0x46BA, float, SHADER_CONSTANT_430_Z) +XE_GPU_REGISTER(0x46BB, float, SHADER_CONSTANT_430_W) +XE_GPU_REGISTER(0x46BC, float, SHADER_CONSTANT_431_X) +XE_GPU_REGISTER(0x46BD, float, SHADER_CONSTANT_431_Y) +XE_GPU_REGISTER(0x46BE, float, SHADER_CONSTANT_431_Z) +XE_GPU_REGISTER(0x46BF, float, SHADER_CONSTANT_431_W) +XE_GPU_REGISTER(0x46C0, float, SHADER_CONSTANT_432_X) +XE_GPU_REGISTER(0x46C1, float, SHADER_CONSTANT_432_Y) +XE_GPU_REGISTER(0x46C2, float, SHADER_CONSTANT_432_Z) +XE_GPU_REGISTER(0x46C3, float, SHADER_CONSTANT_432_W) +XE_GPU_REGISTER(0x46C4, float, SHADER_CONSTANT_433_X) +XE_GPU_REGISTER(0x46C5, float, SHADER_CONSTANT_433_Y) +XE_GPU_REGISTER(0x46C6, float, SHADER_CONSTANT_433_Z) +XE_GPU_REGISTER(0x46C7, float, SHADER_CONSTANT_433_W) +XE_GPU_REGISTER(0x46C8, float, SHADER_CONSTANT_434_X) +XE_GPU_REGISTER(0x46C9, float, SHADER_CONSTANT_434_Y) +XE_GPU_REGISTER(0x46CA, float, SHADER_CONSTANT_434_Z) +XE_GPU_REGISTER(0x46CB, float, SHADER_CONSTANT_434_W) +XE_GPU_REGISTER(0x46CC, float, SHADER_CONSTANT_435_X) +XE_GPU_REGISTER(0x46CD, float, SHADER_CONSTANT_435_Y) +XE_GPU_REGISTER(0x46CE, float, SHADER_CONSTANT_435_Z) +XE_GPU_REGISTER(0x46CF, float, SHADER_CONSTANT_435_W) +XE_GPU_REGISTER(0x46D0, float, SHADER_CONSTANT_436_X) +XE_GPU_REGISTER(0x46D1, float, SHADER_CONSTANT_436_Y) +XE_GPU_REGISTER(0x46D2, float, SHADER_CONSTANT_436_Z) +XE_GPU_REGISTER(0x46D3, float, SHADER_CONSTANT_436_W) +XE_GPU_REGISTER(0x46D4, float, SHADER_CONSTANT_437_X) +XE_GPU_REGISTER(0x46D5, float, SHADER_CONSTANT_437_Y) +XE_GPU_REGISTER(0x46D6, float, SHADER_CONSTANT_437_Z) +XE_GPU_REGISTER(0x46D7, float, SHADER_CONSTANT_437_W) +XE_GPU_REGISTER(0x46D8, float, SHADER_CONSTANT_438_X) +XE_GPU_REGISTER(0x46D9, float, SHADER_CONSTANT_438_Y) +XE_GPU_REGISTER(0x46DA, float, SHADER_CONSTANT_438_Z) +XE_GPU_REGISTER(0x46DB, float, SHADER_CONSTANT_438_W) +XE_GPU_REGISTER(0x46DC, float, SHADER_CONSTANT_439_X) +XE_GPU_REGISTER(0x46DD, float, SHADER_CONSTANT_439_Y) +XE_GPU_REGISTER(0x46DE, float, SHADER_CONSTANT_439_Z) +XE_GPU_REGISTER(0x46DF, float, SHADER_CONSTANT_439_W) +XE_GPU_REGISTER(0x46E0, float, SHADER_CONSTANT_440_X) +XE_GPU_REGISTER(0x46E1, float, SHADER_CONSTANT_440_Y) +XE_GPU_REGISTER(0x46E2, float, SHADER_CONSTANT_440_Z) +XE_GPU_REGISTER(0x46E3, float, SHADER_CONSTANT_440_W) +XE_GPU_REGISTER(0x46E4, float, SHADER_CONSTANT_441_X) +XE_GPU_REGISTER(0x46E5, float, SHADER_CONSTANT_441_Y) +XE_GPU_REGISTER(0x46E6, float, SHADER_CONSTANT_441_Z) +XE_GPU_REGISTER(0x46E7, float, SHADER_CONSTANT_441_W) +XE_GPU_REGISTER(0x46E8, float, SHADER_CONSTANT_442_X) +XE_GPU_REGISTER(0x46E9, float, SHADER_CONSTANT_442_Y) +XE_GPU_REGISTER(0x46EA, float, SHADER_CONSTANT_442_Z) +XE_GPU_REGISTER(0x46EB, float, SHADER_CONSTANT_442_W) +XE_GPU_REGISTER(0x46EC, float, SHADER_CONSTANT_443_X) +XE_GPU_REGISTER(0x46ED, float, SHADER_CONSTANT_443_Y) +XE_GPU_REGISTER(0x46EE, float, SHADER_CONSTANT_443_Z) +XE_GPU_REGISTER(0x46EF, float, SHADER_CONSTANT_443_W) +XE_GPU_REGISTER(0x46F0, float, SHADER_CONSTANT_444_X) +XE_GPU_REGISTER(0x46F1, float, SHADER_CONSTANT_444_Y) +XE_GPU_REGISTER(0x46F2, float, SHADER_CONSTANT_444_Z) +XE_GPU_REGISTER(0x46F3, float, SHADER_CONSTANT_444_W) +XE_GPU_REGISTER(0x46F4, float, SHADER_CONSTANT_445_X) +XE_GPU_REGISTER(0x46F5, float, SHADER_CONSTANT_445_Y) +XE_GPU_REGISTER(0x46F6, float, SHADER_CONSTANT_445_Z) +XE_GPU_REGISTER(0x46F7, float, SHADER_CONSTANT_445_W) +XE_GPU_REGISTER(0x46F8, float, SHADER_CONSTANT_446_X) +XE_GPU_REGISTER(0x46F9, float, SHADER_CONSTANT_446_Y) +XE_GPU_REGISTER(0x46FA, float, SHADER_CONSTANT_446_Z) +XE_GPU_REGISTER(0x46FB, float, SHADER_CONSTANT_446_W) +XE_GPU_REGISTER(0x46FC, float, SHADER_CONSTANT_447_X) +XE_GPU_REGISTER(0x46FD, float, SHADER_CONSTANT_447_Y) +XE_GPU_REGISTER(0x46FE, float, SHADER_CONSTANT_447_Z) +XE_GPU_REGISTER(0x46FF, float, SHADER_CONSTANT_447_W) +XE_GPU_REGISTER(0x4700, float, SHADER_CONSTANT_448_X) +XE_GPU_REGISTER(0x4701, float, SHADER_CONSTANT_448_Y) +XE_GPU_REGISTER(0x4702, float, SHADER_CONSTANT_448_Z) +XE_GPU_REGISTER(0x4703, float, SHADER_CONSTANT_448_W) +XE_GPU_REGISTER(0x4704, float, SHADER_CONSTANT_449_X) +XE_GPU_REGISTER(0x4705, float, SHADER_CONSTANT_449_Y) +XE_GPU_REGISTER(0x4706, float, SHADER_CONSTANT_449_Z) +XE_GPU_REGISTER(0x4707, float, SHADER_CONSTANT_449_W) +XE_GPU_REGISTER(0x4708, float, SHADER_CONSTANT_450_X) +XE_GPU_REGISTER(0x4709, float, SHADER_CONSTANT_450_Y) +XE_GPU_REGISTER(0x470A, float, SHADER_CONSTANT_450_Z) +XE_GPU_REGISTER(0x470B, float, SHADER_CONSTANT_450_W) +XE_GPU_REGISTER(0x470C, float, SHADER_CONSTANT_451_X) +XE_GPU_REGISTER(0x470D, float, SHADER_CONSTANT_451_Y) +XE_GPU_REGISTER(0x470E, float, SHADER_CONSTANT_451_Z) +XE_GPU_REGISTER(0x470F, float, SHADER_CONSTANT_451_W) +XE_GPU_REGISTER(0x4710, float, SHADER_CONSTANT_452_X) +XE_GPU_REGISTER(0x4711, float, SHADER_CONSTANT_452_Y) +XE_GPU_REGISTER(0x4712, float, SHADER_CONSTANT_452_Z) +XE_GPU_REGISTER(0x4713, float, SHADER_CONSTANT_452_W) +XE_GPU_REGISTER(0x4714, float, SHADER_CONSTANT_453_X) +XE_GPU_REGISTER(0x4715, float, SHADER_CONSTANT_453_Y) +XE_GPU_REGISTER(0x4716, float, SHADER_CONSTANT_453_Z) +XE_GPU_REGISTER(0x4717, float, SHADER_CONSTANT_453_W) +XE_GPU_REGISTER(0x4718, float, SHADER_CONSTANT_454_X) +XE_GPU_REGISTER(0x4719, float, SHADER_CONSTANT_454_Y) +XE_GPU_REGISTER(0x471A, float, SHADER_CONSTANT_454_Z) +XE_GPU_REGISTER(0x471B, float, SHADER_CONSTANT_454_W) +XE_GPU_REGISTER(0x471C, float, SHADER_CONSTANT_455_X) +XE_GPU_REGISTER(0x471D, float, SHADER_CONSTANT_455_Y) +XE_GPU_REGISTER(0x471E, float, SHADER_CONSTANT_455_Z) +XE_GPU_REGISTER(0x471F, float, SHADER_CONSTANT_455_W) +XE_GPU_REGISTER(0x4720, float, SHADER_CONSTANT_456_X) +XE_GPU_REGISTER(0x4721, float, SHADER_CONSTANT_456_Y) +XE_GPU_REGISTER(0x4722, float, SHADER_CONSTANT_456_Z) +XE_GPU_REGISTER(0x4723, float, SHADER_CONSTANT_456_W) +XE_GPU_REGISTER(0x4724, float, SHADER_CONSTANT_457_X) +XE_GPU_REGISTER(0x4725, float, SHADER_CONSTANT_457_Y) +XE_GPU_REGISTER(0x4726, float, SHADER_CONSTANT_457_Z) +XE_GPU_REGISTER(0x4727, float, SHADER_CONSTANT_457_W) +XE_GPU_REGISTER(0x4728, float, SHADER_CONSTANT_458_X) +XE_GPU_REGISTER(0x4729, float, SHADER_CONSTANT_458_Y) +XE_GPU_REGISTER(0x472A, float, SHADER_CONSTANT_458_Z) +XE_GPU_REGISTER(0x472B, float, SHADER_CONSTANT_458_W) +XE_GPU_REGISTER(0x472C, float, SHADER_CONSTANT_459_X) +XE_GPU_REGISTER(0x472D, float, SHADER_CONSTANT_459_Y) +XE_GPU_REGISTER(0x472E, float, SHADER_CONSTANT_459_Z) +XE_GPU_REGISTER(0x472F, float, SHADER_CONSTANT_459_W) +XE_GPU_REGISTER(0x4730, float, SHADER_CONSTANT_460_X) +XE_GPU_REGISTER(0x4731, float, SHADER_CONSTANT_460_Y) +XE_GPU_REGISTER(0x4732, float, SHADER_CONSTANT_460_Z) +XE_GPU_REGISTER(0x4733, float, SHADER_CONSTANT_460_W) +XE_GPU_REGISTER(0x4734, float, SHADER_CONSTANT_461_X) +XE_GPU_REGISTER(0x4735, float, SHADER_CONSTANT_461_Y) +XE_GPU_REGISTER(0x4736, float, SHADER_CONSTANT_461_Z) +XE_GPU_REGISTER(0x4737, float, SHADER_CONSTANT_461_W) +XE_GPU_REGISTER(0x4738, float, SHADER_CONSTANT_462_X) +XE_GPU_REGISTER(0x4739, float, SHADER_CONSTANT_462_Y) +XE_GPU_REGISTER(0x473A, float, SHADER_CONSTANT_462_Z) +XE_GPU_REGISTER(0x473B, float, SHADER_CONSTANT_462_W) +XE_GPU_REGISTER(0x473C, float, SHADER_CONSTANT_463_X) +XE_GPU_REGISTER(0x473D, float, SHADER_CONSTANT_463_Y) +XE_GPU_REGISTER(0x473E, float, SHADER_CONSTANT_463_Z) +XE_GPU_REGISTER(0x473F, float, SHADER_CONSTANT_463_W) +XE_GPU_REGISTER(0x4740, float, SHADER_CONSTANT_464_X) +XE_GPU_REGISTER(0x4741, float, SHADER_CONSTANT_464_Y) +XE_GPU_REGISTER(0x4742, float, SHADER_CONSTANT_464_Z) +XE_GPU_REGISTER(0x4743, float, SHADER_CONSTANT_464_W) +XE_GPU_REGISTER(0x4744, float, SHADER_CONSTANT_465_X) +XE_GPU_REGISTER(0x4745, float, SHADER_CONSTANT_465_Y) +XE_GPU_REGISTER(0x4746, float, SHADER_CONSTANT_465_Z) +XE_GPU_REGISTER(0x4747, float, SHADER_CONSTANT_465_W) +XE_GPU_REGISTER(0x4748, float, SHADER_CONSTANT_466_X) +XE_GPU_REGISTER(0x4749, float, SHADER_CONSTANT_466_Y) +XE_GPU_REGISTER(0x474A, float, SHADER_CONSTANT_466_Z) +XE_GPU_REGISTER(0x474B, float, SHADER_CONSTANT_466_W) +XE_GPU_REGISTER(0x474C, float, SHADER_CONSTANT_467_X) +XE_GPU_REGISTER(0x474D, float, SHADER_CONSTANT_467_Y) +XE_GPU_REGISTER(0x474E, float, SHADER_CONSTANT_467_Z) +XE_GPU_REGISTER(0x474F, float, SHADER_CONSTANT_467_W) +XE_GPU_REGISTER(0x4750, float, SHADER_CONSTANT_468_X) +XE_GPU_REGISTER(0x4751, float, SHADER_CONSTANT_468_Y) +XE_GPU_REGISTER(0x4752, float, SHADER_CONSTANT_468_Z) +XE_GPU_REGISTER(0x4753, float, SHADER_CONSTANT_468_W) +XE_GPU_REGISTER(0x4754, float, SHADER_CONSTANT_469_X) +XE_GPU_REGISTER(0x4755, float, SHADER_CONSTANT_469_Y) +XE_GPU_REGISTER(0x4756, float, SHADER_CONSTANT_469_Z) +XE_GPU_REGISTER(0x4757, float, SHADER_CONSTANT_469_W) +XE_GPU_REGISTER(0x4758, float, SHADER_CONSTANT_470_X) +XE_GPU_REGISTER(0x4759, float, SHADER_CONSTANT_470_Y) +XE_GPU_REGISTER(0x475A, float, SHADER_CONSTANT_470_Z) +XE_GPU_REGISTER(0x475B, float, SHADER_CONSTANT_470_W) +XE_GPU_REGISTER(0x475C, float, SHADER_CONSTANT_471_X) +XE_GPU_REGISTER(0x475D, float, SHADER_CONSTANT_471_Y) +XE_GPU_REGISTER(0x475E, float, SHADER_CONSTANT_471_Z) +XE_GPU_REGISTER(0x475F, float, SHADER_CONSTANT_471_W) +XE_GPU_REGISTER(0x4760, float, SHADER_CONSTANT_472_X) +XE_GPU_REGISTER(0x4761, float, SHADER_CONSTANT_472_Y) +XE_GPU_REGISTER(0x4762, float, SHADER_CONSTANT_472_Z) +XE_GPU_REGISTER(0x4763, float, SHADER_CONSTANT_472_W) +XE_GPU_REGISTER(0x4764, float, SHADER_CONSTANT_473_X) +XE_GPU_REGISTER(0x4765, float, SHADER_CONSTANT_473_Y) +XE_GPU_REGISTER(0x4766, float, SHADER_CONSTANT_473_Z) +XE_GPU_REGISTER(0x4767, float, SHADER_CONSTANT_473_W) +XE_GPU_REGISTER(0x4768, float, SHADER_CONSTANT_474_X) +XE_GPU_REGISTER(0x4769, float, SHADER_CONSTANT_474_Y) +XE_GPU_REGISTER(0x476A, float, SHADER_CONSTANT_474_Z) +XE_GPU_REGISTER(0x476B, float, SHADER_CONSTANT_474_W) +XE_GPU_REGISTER(0x476C, float, SHADER_CONSTANT_475_X) +XE_GPU_REGISTER(0x476D, float, SHADER_CONSTANT_475_Y) +XE_GPU_REGISTER(0x476E, float, SHADER_CONSTANT_475_Z) +XE_GPU_REGISTER(0x476F, float, SHADER_CONSTANT_475_W) +XE_GPU_REGISTER(0x4770, float, SHADER_CONSTANT_476_X) +XE_GPU_REGISTER(0x4771, float, SHADER_CONSTANT_476_Y) +XE_GPU_REGISTER(0x4772, float, SHADER_CONSTANT_476_Z) +XE_GPU_REGISTER(0x4773, float, SHADER_CONSTANT_476_W) +XE_GPU_REGISTER(0x4774, float, SHADER_CONSTANT_477_X) +XE_GPU_REGISTER(0x4775, float, SHADER_CONSTANT_477_Y) +XE_GPU_REGISTER(0x4776, float, SHADER_CONSTANT_477_Z) +XE_GPU_REGISTER(0x4777, float, SHADER_CONSTANT_477_W) +XE_GPU_REGISTER(0x4778, float, SHADER_CONSTANT_478_X) +XE_GPU_REGISTER(0x4779, float, SHADER_CONSTANT_478_Y) +XE_GPU_REGISTER(0x477A, float, SHADER_CONSTANT_478_Z) +XE_GPU_REGISTER(0x477B, float, SHADER_CONSTANT_478_W) +XE_GPU_REGISTER(0x477C, float, SHADER_CONSTANT_479_X) +XE_GPU_REGISTER(0x477D, float, SHADER_CONSTANT_479_Y) +XE_GPU_REGISTER(0x477E, float, SHADER_CONSTANT_479_Z) +XE_GPU_REGISTER(0x477F, float, SHADER_CONSTANT_479_W) +XE_GPU_REGISTER(0x4780, float, SHADER_CONSTANT_480_X) +XE_GPU_REGISTER(0x4781, float, SHADER_CONSTANT_480_Y) +XE_GPU_REGISTER(0x4782, float, SHADER_CONSTANT_480_Z) +XE_GPU_REGISTER(0x4783, float, SHADER_CONSTANT_480_W) +XE_GPU_REGISTER(0x4784, float, SHADER_CONSTANT_481_X) +XE_GPU_REGISTER(0x4785, float, SHADER_CONSTANT_481_Y) +XE_GPU_REGISTER(0x4786, float, SHADER_CONSTANT_481_Z) +XE_GPU_REGISTER(0x4787, float, SHADER_CONSTANT_481_W) +XE_GPU_REGISTER(0x4788, float, SHADER_CONSTANT_482_X) +XE_GPU_REGISTER(0x4789, float, SHADER_CONSTANT_482_Y) +XE_GPU_REGISTER(0x478A, float, SHADER_CONSTANT_482_Z) +XE_GPU_REGISTER(0x478B, float, SHADER_CONSTANT_482_W) +XE_GPU_REGISTER(0x478C, float, SHADER_CONSTANT_483_X) +XE_GPU_REGISTER(0x478D, float, SHADER_CONSTANT_483_Y) +XE_GPU_REGISTER(0x478E, float, SHADER_CONSTANT_483_Z) +XE_GPU_REGISTER(0x478F, float, SHADER_CONSTANT_483_W) +XE_GPU_REGISTER(0x4790, float, SHADER_CONSTANT_484_X) +XE_GPU_REGISTER(0x4791, float, SHADER_CONSTANT_484_Y) +XE_GPU_REGISTER(0x4792, float, SHADER_CONSTANT_484_Z) +XE_GPU_REGISTER(0x4793, float, SHADER_CONSTANT_484_W) +XE_GPU_REGISTER(0x4794, float, SHADER_CONSTANT_485_X) +XE_GPU_REGISTER(0x4795, float, SHADER_CONSTANT_485_Y) +XE_GPU_REGISTER(0x4796, float, SHADER_CONSTANT_485_Z) +XE_GPU_REGISTER(0x4797, float, SHADER_CONSTANT_485_W) +XE_GPU_REGISTER(0x4798, float, SHADER_CONSTANT_486_X) +XE_GPU_REGISTER(0x4799, float, SHADER_CONSTANT_486_Y) +XE_GPU_REGISTER(0x479A, float, SHADER_CONSTANT_486_Z) +XE_GPU_REGISTER(0x479B, float, SHADER_CONSTANT_486_W) +XE_GPU_REGISTER(0x479C, float, SHADER_CONSTANT_487_X) +XE_GPU_REGISTER(0x479D, float, SHADER_CONSTANT_487_Y) +XE_GPU_REGISTER(0x479E, float, SHADER_CONSTANT_487_Z) +XE_GPU_REGISTER(0x479F, float, SHADER_CONSTANT_487_W) +XE_GPU_REGISTER(0x47A0, float, SHADER_CONSTANT_488_X) +XE_GPU_REGISTER(0x47A1, float, SHADER_CONSTANT_488_Y) +XE_GPU_REGISTER(0x47A2, float, SHADER_CONSTANT_488_Z) +XE_GPU_REGISTER(0x47A3, float, SHADER_CONSTANT_488_W) +XE_GPU_REGISTER(0x47A4, float, SHADER_CONSTANT_489_X) +XE_GPU_REGISTER(0x47A5, float, SHADER_CONSTANT_489_Y) +XE_GPU_REGISTER(0x47A6, float, SHADER_CONSTANT_489_Z) +XE_GPU_REGISTER(0x47A7, float, SHADER_CONSTANT_489_W) +XE_GPU_REGISTER(0x47A8, float, SHADER_CONSTANT_490_X) +XE_GPU_REGISTER(0x47A9, float, SHADER_CONSTANT_490_Y) +XE_GPU_REGISTER(0x47AA, float, SHADER_CONSTANT_490_Z) +XE_GPU_REGISTER(0x47AB, float, SHADER_CONSTANT_490_W) +XE_GPU_REGISTER(0x47AC, float, SHADER_CONSTANT_491_X) +XE_GPU_REGISTER(0x47AD, float, SHADER_CONSTANT_491_Y) +XE_GPU_REGISTER(0x47AE, float, SHADER_CONSTANT_491_Z) +XE_GPU_REGISTER(0x47AF, float, SHADER_CONSTANT_491_W) +XE_GPU_REGISTER(0x47B0, float, SHADER_CONSTANT_492_X) +XE_GPU_REGISTER(0x47B1, float, SHADER_CONSTANT_492_Y) +XE_GPU_REGISTER(0x47B2, float, SHADER_CONSTANT_492_Z) +XE_GPU_REGISTER(0x47B3, float, SHADER_CONSTANT_492_W) +XE_GPU_REGISTER(0x47B4, float, SHADER_CONSTANT_493_X) +XE_GPU_REGISTER(0x47B5, float, SHADER_CONSTANT_493_Y) +XE_GPU_REGISTER(0x47B6, float, SHADER_CONSTANT_493_Z) +XE_GPU_REGISTER(0x47B7, float, SHADER_CONSTANT_493_W) +XE_GPU_REGISTER(0x47B8, float, SHADER_CONSTANT_494_X) +XE_GPU_REGISTER(0x47B9, float, SHADER_CONSTANT_494_Y) +XE_GPU_REGISTER(0x47BA, float, SHADER_CONSTANT_494_Z) +XE_GPU_REGISTER(0x47BB, float, SHADER_CONSTANT_494_W) +XE_GPU_REGISTER(0x47BC, float, SHADER_CONSTANT_495_X) +XE_GPU_REGISTER(0x47BD, float, SHADER_CONSTANT_495_Y) +XE_GPU_REGISTER(0x47BE, float, SHADER_CONSTANT_495_Z) +XE_GPU_REGISTER(0x47BF, float, SHADER_CONSTANT_495_W) +XE_GPU_REGISTER(0x47C0, float, SHADER_CONSTANT_496_X) +XE_GPU_REGISTER(0x47C1, float, SHADER_CONSTANT_496_Y) +XE_GPU_REGISTER(0x47C2, float, SHADER_CONSTANT_496_Z) +XE_GPU_REGISTER(0x47C3, float, SHADER_CONSTANT_496_W) +XE_GPU_REGISTER(0x47C4, float, SHADER_CONSTANT_497_X) +XE_GPU_REGISTER(0x47C5, float, SHADER_CONSTANT_497_Y) +XE_GPU_REGISTER(0x47C6, float, SHADER_CONSTANT_497_Z) +XE_GPU_REGISTER(0x47C7, float, SHADER_CONSTANT_497_W) +XE_GPU_REGISTER(0x47C8, float, SHADER_CONSTANT_498_X) +XE_GPU_REGISTER(0x47C9, float, SHADER_CONSTANT_498_Y) +XE_GPU_REGISTER(0x47CA, float, SHADER_CONSTANT_498_Z) +XE_GPU_REGISTER(0x47CB, float, SHADER_CONSTANT_498_W) +XE_GPU_REGISTER(0x47CC, float, SHADER_CONSTANT_499_X) +XE_GPU_REGISTER(0x47CD, float, SHADER_CONSTANT_499_Y) +XE_GPU_REGISTER(0x47CE, float, SHADER_CONSTANT_499_Z) +XE_GPU_REGISTER(0x47CF, float, SHADER_CONSTANT_499_W) +XE_GPU_REGISTER(0x47D0, float, SHADER_CONSTANT_500_X) +XE_GPU_REGISTER(0x47D1, float, SHADER_CONSTANT_500_Y) +XE_GPU_REGISTER(0x47D2, float, SHADER_CONSTANT_500_Z) +XE_GPU_REGISTER(0x47D3, float, SHADER_CONSTANT_500_W) +XE_GPU_REGISTER(0x47D4, float, SHADER_CONSTANT_501_X) +XE_GPU_REGISTER(0x47D5, float, SHADER_CONSTANT_501_Y) +XE_GPU_REGISTER(0x47D6, float, SHADER_CONSTANT_501_Z) +XE_GPU_REGISTER(0x47D7, float, SHADER_CONSTANT_501_W) +XE_GPU_REGISTER(0x47D8, float, SHADER_CONSTANT_502_X) +XE_GPU_REGISTER(0x47D9, float, SHADER_CONSTANT_502_Y) +XE_GPU_REGISTER(0x47DA, float, SHADER_CONSTANT_502_Z) +XE_GPU_REGISTER(0x47DB, float, SHADER_CONSTANT_502_W) +XE_GPU_REGISTER(0x47DC, float, SHADER_CONSTANT_503_X) +XE_GPU_REGISTER(0x47DD, float, SHADER_CONSTANT_503_Y) +XE_GPU_REGISTER(0x47DE, float, SHADER_CONSTANT_503_Z) +XE_GPU_REGISTER(0x47DF, float, SHADER_CONSTANT_503_W) +XE_GPU_REGISTER(0x47E0, float, SHADER_CONSTANT_504_X) +XE_GPU_REGISTER(0x47E1, float, SHADER_CONSTANT_504_Y) +XE_GPU_REGISTER(0x47E2, float, SHADER_CONSTANT_504_Z) +XE_GPU_REGISTER(0x47E3, float, SHADER_CONSTANT_504_W) +XE_GPU_REGISTER(0x47E4, float, SHADER_CONSTANT_505_X) +XE_GPU_REGISTER(0x47E5, float, SHADER_CONSTANT_505_Y) +XE_GPU_REGISTER(0x47E6, float, SHADER_CONSTANT_505_Z) +XE_GPU_REGISTER(0x47E7, float, SHADER_CONSTANT_505_W) +XE_GPU_REGISTER(0x47E8, float, SHADER_CONSTANT_506_X) +XE_GPU_REGISTER(0x47E9, float, SHADER_CONSTANT_506_Y) +XE_GPU_REGISTER(0x47EA, float, SHADER_CONSTANT_506_Z) +XE_GPU_REGISTER(0x47EB, float, SHADER_CONSTANT_506_W) +XE_GPU_REGISTER(0x47EC, float, SHADER_CONSTANT_507_X) +XE_GPU_REGISTER(0x47ED, float, SHADER_CONSTANT_507_Y) +XE_GPU_REGISTER(0x47EE, float, SHADER_CONSTANT_507_Z) +XE_GPU_REGISTER(0x47EF, float, SHADER_CONSTANT_507_W) +XE_GPU_REGISTER(0x47F0, float, SHADER_CONSTANT_508_X) +XE_GPU_REGISTER(0x47F1, float, SHADER_CONSTANT_508_Y) +XE_GPU_REGISTER(0x47F2, float, SHADER_CONSTANT_508_Z) +XE_GPU_REGISTER(0x47F3, float, SHADER_CONSTANT_508_W) +XE_GPU_REGISTER(0x47F4, float, SHADER_CONSTANT_509_X) +XE_GPU_REGISTER(0x47F5, float, SHADER_CONSTANT_509_Y) +XE_GPU_REGISTER(0x47F6, float, SHADER_CONSTANT_509_Z) +XE_GPU_REGISTER(0x47F7, float, SHADER_CONSTANT_509_W) +XE_GPU_REGISTER(0x47F8, float, SHADER_CONSTANT_510_X) +XE_GPU_REGISTER(0x47F9, float, SHADER_CONSTANT_510_Y) +XE_GPU_REGISTER(0x47FA, float, SHADER_CONSTANT_510_Z) +XE_GPU_REGISTER(0x47FB, float, SHADER_CONSTANT_510_W) +XE_GPU_REGISTER(0x47FC, float, SHADER_CONSTANT_511_X) +XE_GPU_REGISTER(0x47FD, float, SHADER_CONSTANT_511_Y) +XE_GPU_REGISTER(0x47FE, float, SHADER_CONSTANT_511_Z) +XE_GPU_REGISTER(0x47FF, float, SHADER_CONSTANT_511_W) + +XE_GPU_REGISTER(0x4800, dword, SHADER_CONSTANT_FETCH_00_0) +XE_GPU_REGISTER(0x4801, dword, SHADER_CONSTANT_FETCH_00_1) +XE_GPU_REGISTER(0x4802, dword, SHADER_CONSTANT_FETCH_00_2) +XE_GPU_REGISTER(0x4803, dword, SHADER_CONSTANT_FETCH_00_3) +XE_GPU_REGISTER(0x4804, dword, SHADER_CONSTANT_FETCH_00_4) +XE_GPU_REGISTER(0x4805, dword, SHADER_CONSTANT_FETCH_00_5) +XE_GPU_REGISTER(0x4806, dword, SHADER_CONSTANT_FETCH_01_0) +XE_GPU_REGISTER(0x4807, dword, SHADER_CONSTANT_FETCH_01_1) +XE_GPU_REGISTER(0x4808, dword, SHADER_CONSTANT_FETCH_01_2) +XE_GPU_REGISTER(0x4809, dword, SHADER_CONSTANT_FETCH_01_3) +XE_GPU_REGISTER(0x480A, dword, SHADER_CONSTANT_FETCH_01_4) +XE_GPU_REGISTER(0x480B, dword, SHADER_CONSTANT_FETCH_01_5) +XE_GPU_REGISTER(0x480C, dword, SHADER_CONSTANT_FETCH_02_0) +XE_GPU_REGISTER(0x480D, dword, SHADER_CONSTANT_FETCH_02_1) +XE_GPU_REGISTER(0x480E, dword, SHADER_CONSTANT_FETCH_02_2) +XE_GPU_REGISTER(0x480F, dword, SHADER_CONSTANT_FETCH_02_3) +XE_GPU_REGISTER(0x4810, dword, SHADER_CONSTANT_FETCH_02_4) +XE_GPU_REGISTER(0x4811, dword, SHADER_CONSTANT_FETCH_02_5) +XE_GPU_REGISTER(0x4812, dword, SHADER_CONSTANT_FETCH_03_0) +XE_GPU_REGISTER(0x4813, dword, SHADER_CONSTANT_FETCH_03_1) +XE_GPU_REGISTER(0x4814, dword, SHADER_CONSTANT_FETCH_03_2) +XE_GPU_REGISTER(0x4815, dword, SHADER_CONSTANT_FETCH_03_3) +XE_GPU_REGISTER(0x4816, dword, SHADER_CONSTANT_FETCH_03_4) +XE_GPU_REGISTER(0x4817, dword, SHADER_CONSTANT_FETCH_03_5) +XE_GPU_REGISTER(0x4818, dword, SHADER_CONSTANT_FETCH_04_0) +XE_GPU_REGISTER(0x4819, dword, SHADER_CONSTANT_FETCH_04_1) +XE_GPU_REGISTER(0x481A, dword, SHADER_CONSTANT_FETCH_04_2) +XE_GPU_REGISTER(0x481B, dword, SHADER_CONSTANT_FETCH_04_3) +XE_GPU_REGISTER(0x481C, dword, SHADER_CONSTANT_FETCH_04_4) +XE_GPU_REGISTER(0x481D, dword, SHADER_CONSTANT_FETCH_04_5) +XE_GPU_REGISTER(0x481E, dword, SHADER_CONSTANT_FETCH_05_0) +XE_GPU_REGISTER(0x481F, dword, SHADER_CONSTANT_FETCH_05_1) +XE_GPU_REGISTER(0x4820, dword, SHADER_CONSTANT_FETCH_05_2) +XE_GPU_REGISTER(0x4821, dword, SHADER_CONSTANT_FETCH_05_3) +XE_GPU_REGISTER(0x4822, dword, SHADER_CONSTANT_FETCH_05_4) +XE_GPU_REGISTER(0x4823, dword, SHADER_CONSTANT_FETCH_05_5) +XE_GPU_REGISTER(0x4824, dword, SHADER_CONSTANT_FETCH_06_0) +XE_GPU_REGISTER(0x4825, dword, SHADER_CONSTANT_FETCH_06_1) +XE_GPU_REGISTER(0x4826, dword, SHADER_CONSTANT_FETCH_06_2) +XE_GPU_REGISTER(0x4827, dword, SHADER_CONSTANT_FETCH_06_3) +XE_GPU_REGISTER(0x4828, dword, SHADER_CONSTANT_FETCH_06_4) +XE_GPU_REGISTER(0x4829, dword, SHADER_CONSTANT_FETCH_06_5) +XE_GPU_REGISTER(0x482A, dword, SHADER_CONSTANT_FETCH_07_0) +XE_GPU_REGISTER(0x482B, dword, SHADER_CONSTANT_FETCH_07_1) +XE_GPU_REGISTER(0x482C, dword, SHADER_CONSTANT_FETCH_07_2) +XE_GPU_REGISTER(0x482D, dword, SHADER_CONSTANT_FETCH_07_3) +XE_GPU_REGISTER(0x482E, dword, SHADER_CONSTANT_FETCH_07_4) +XE_GPU_REGISTER(0x482F, dword, SHADER_CONSTANT_FETCH_07_5) +XE_GPU_REGISTER(0x4830, dword, SHADER_CONSTANT_FETCH_08_0) +XE_GPU_REGISTER(0x4831, dword, SHADER_CONSTANT_FETCH_08_1) +XE_GPU_REGISTER(0x4832, dword, SHADER_CONSTANT_FETCH_08_2) +XE_GPU_REGISTER(0x4833, dword, SHADER_CONSTANT_FETCH_08_3) +XE_GPU_REGISTER(0x4834, dword, SHADER_CONSTANT_FETCH_08_4) +XE_GPU_REGISTER(0x4835, dword, SHADER_CONSTANT_FETCH_08_5) +XE_GPU_REGISTER(0x4836, dword, SHADER_CONSTANT_FETCH_09_0) +XE_GPU_REGISTER(0x4837, dword, SHADER_CONSTANT_FETCH_09_1) +XE_GPU_REGISTER(0x4838, dword, SHADER_CONSTANT_FETCH_09_2) +XE_GPU_REGISTER(0x4839, dword, SHADER_CONSTANT_FETCH_09_3) +XE_GPU_REGISTER(0x483A, dword, SHADER_CONSTANT_FETCH_09_4) +XE_GPU_REGISTER(0x483B, dword, SHADER_CONSTANT_FETCH_09_5) +XE_GPU_REGISTER(0x483C, dword, SHADER_CONSTANT_FETCH_10_0) +XE_GPU_REGISTER(0x483D, dword, SHADER_CONSTANT_FETCH_10_1) +XE_GPU_REGISTER(0x483E, dword, SHADER_CONSTANT_FETCH_10_2) +XE_GPU_REGISTER(0x483F, dword, SHADER_CONSTANT_FETCH_10_3) +XE_GPU_REGISTER(0x4840, dword, SHADER_CONSTANT_FETCH_10_4) +XE_GPU_REGISTER(0x4841, dword, SHADER_CONSTANT_FETCH_10_5) +XE_GPU_REGISTER(0x4842, dword, SHADER_CONSTANT_FETCH_11_0) +XE_GPU_REGISTER(0x4843, dword, SHADER_CONSTANT_FETCH_11_1) +XE_GPU_REGISTER(0x4844, dword, SHADER_CONSTANT_FETCH_11_2) +XE_GPU_REGISTER(0x4845, dword, SHADER_CONSTANT_FETCH_11_3) +XE_GPU_REGISTER(0x4846, dword, SHADER_CONSTANT_FETCH_11_4) +XE_GPU_REGISTER(0x4847, dword, SHADER_CONSTANT_FETCH_11_5) +XE_GPU_REGISTER(0x4848, dword, SHADER_CONSTANT_FETCH_12_0) +XE_GPU_REGISTER(0x4849, dword, SHADER_CONSTANT_FETCH_12_1) +XE_GPU_REGISTER(0x484A, dword, SHADER_CONSTANT_FETCH_12_2) +XE_GPU_REGISTER(0x484B, dword, SHADER_CONSTANT_FETCH_12_3) +XE_GPU_REGISTER(0x484C, dword, SHADER_CONSTANT_FETCH_12_4) +XE_GPU_REGISTER(0x484D, dword, SHADER_CONSTANT_FETCH_12_5) +XE_GPU_REGISTER(0x484E, dword, SHADER_CONSTANT_FETCH_13_0) +XE_GPU_REGISTER(0x484F, dword, SHADER_CONSTANT_FETCH_13_1) +XE_GPU_REGISTER(0x4850, dword, SHADER_CONSTANT_FETCH_13_2) +XE_GPU_REGISTER(0x4851, dword, SHADER_CONSTANT_FETCH_13_3) +XE_GPU_REGISTER(0x4852, dword, SHADER_CONSTANT_FETCH_13_4) +XE_GPU_REGISTER(0x4853, dword, SHADER_CONSTANT_FETCH_13_5) +XE_GPU_REGISTER(0x4854, dword, SHADER_CONSTANT_FETCH_14_0) +XE_GPU_REGISTER(0x4855, dword, SHADER_CONSTANT_FETCH_14_1) +XE_GPU_REGISTER(0x4856, dword, SHADER_CONSTANT_FETCH_14_2) +XE_GPU_REGISTER(0x4857, dword, SHADER_CONSTANT_FETCH_14_3) +XE_GPU_REGISTER(0x4858, dword, SHADER_CONSTANT_FETCH_14_4) +XE_GPU_REGISTER(0x4859, dword, SHADER_CONSTANT_FETCH_14_5) +XE_GPU_REGISTER(0x485A, dword, SHADER_CONSTANT_FETCH_15_0) +XE_GPU_REGISTER(0x485B, dword, SHADER_CONSTANT_FETCH_15_1) +XE_GPU_REGISTER(0x485C, dword, SHADER_CONSTANT_FETCH_15_2) +XE_GPU_REGISTER(0x485D, dword, SHADER_CONSTANT_FETCH_15_3) +XE_GPU_REGISTER(0x485E, dword, SHADER_CONSTANT_FETCH_15_4) +XE_GPU_REGISTER(0x485F, dword, SHADER_CONSTANT_FETCH_15_5) +XE_GPU_REGISTER(0x4860, dword, SHADER_CONSTANT_FETCH_16_0) +XE_GPU_REGISTER(0x4861, dword, SHADER_CONSTANT_FETCH_16_1) +XE_GPU_REGISTER(0x4862, dword, SHADER_CONSTANT_FETCH_16_2) +XE_GPU_REGISTER(0x4863, dword, SHADER_CONSTANT_FETCH_16_3) +XE_GPU_REGISTER(0x4864, dword, SHADER_CONSTANT_FETCH_16_4) +XE_GPU_REGISTER(0x4865, dword, SHADER_CONSTANT_FETCH_16_5) +XE_GPU_REGISTER(0x4866, dword, SHADER_CONSTANT_FETCH_17_0) +XE_GPU_REGISTER(0x4867, dword, SHADER_CONSTANT_FETCH_17_1) +XE_GPU_REGISTER(0x4868, dword, SHADER_CONSTANT_FETCH_17_2) +XE_GPU_REGISTER(0x4869, dword, SHADER_CONSTANT_FETCH_17_3) +XE_GPU_REGISTER(0x486A, dword, SHADER_CONSTANT_FETCH_17_4) +XE_GPU_REGISTER(0x486B, dword, SHADER_CONSTANT_FETCH_17_5) +XE_GPU_REGISTER(0x486C, dword, SHADER_CONSTANT_FETCH_18_0) +XE_GPU_REGISTER(0x486D, dword, SHADER_CONSTANT_FETCH_18_1) +XE_GPU_REGISTER(0x486E, dword, SHADER_CONSTANT_FETCH_18_2) +XE_GPU_REGISTER(0x486F, dword, SHADER_CONSTANT_FETCH_18_3) +XE_GPU_REGISTER(0x4870, dword, SHADER_CONSTANT_FETCH_18_4) +XE_GPU_REGISTER(0x4871, dword, SHADER_CONSTANT_FETCH_18_5) +XE_GPU_REGISTER(0x4872, dword, SHADER_CONSTANT_FETCH_19_0) +XE_GPU_REGISTER(0x4873, dword, SHADER_CONSTANT_FETCH_19_1) +XE_GPU_REGISTER(0x4874, dword, SHADER_CONSTANT_FETCH_19_2) +XE_GPU_REGISTER(0x4875, dword, SHADER_CONSTANT_FETCH_19_3) +XE_GPU_REGISTER(0x4876, dword, SHADER_CONSTANT_FETCH_19_4) +XE_GPU_REGISTER(0x4877, dword, SHADER_CONSTANT_FETCH_19_5) +XE_GPU_REGISTER(0x4878, dword, SHADER_CONSTANT_FETCH_20_0) +XE_GPU_REGISTER(0x4879, dword, SHADER_CONSTANT_FETCH_20_1) +XE_GPU_REGISTER(0x487A, dword, SHADER_CONSTANT_FETCH_20_2) +XE_GPU_REGISTER(0x487B, dword, SHADER_CONSTANT_FETCH_20_3) +XE_GPU_REGISTER(0x487C, dword, SHADER_CONSTANT_FETCH_20_4) +XE_GPU_REGISTER(0x487D, dword, SHADER_CONSTANT_FETCH_20_5) +XE_GPU_REGISTER(0x487E, dword, SHADER_CONSTANT_FETCH_21_0) +XE_GPU_REGISTER(0x487F, dword, SHADER_CONSTANT_FETCH_21_1) +XE_GPU_REGISTER(0x4880, dword, SHADER_CONSTANT_FETCH_21_2) +XE_GPU_REGISTER(0x4881, dword, SHADER_CONSTANT_FETCH_21_3) +XE_GPU_REGISTER(0x4882, dword, SHADER_CONSTANT_FETCH_21_4) +XE_GPU_REGISTER(0x4883, dword, SHADER_CONSTANT_FETCH_21_5) +XE_GPU_REGISTER(0x4884, dword, SHADER_CONSTANT_FETCH_22_0) +XE_GPU_REGISTER(0x4885, dword, SHADER_CONSTANT_FETCH_22_1) +XE_GPU_REGISTER(0x4886, dword, SHADER_CONSTANT_FETCH_22_2) +XE_GPU_REGISTER(0x4887, dword, SHADER_CONSTANT_FETCH_22_3) +XE_GPU_REGISTER(0x4888, dword, SHADER_CONSTANT_FETCH_22_4) +XE_GPU_REGISTER(0x4889, dword, SHADER_CONSTANT_FETCH_22_5) +XE_GPU_REGISTER(0x488A, dword, SHADER_CONSTANT_FETCH_23_0) +XE_GPU_REGISTER(0x488B, dword, SHADER_CONSTANT_FETCH_23_1) +XE_GPU_REGISTER(0x488C, dword, SHADER_CONSTANT_FETCH_23_2) +XE_GPU_REGISTER(0x488D, dword, SHADER_CONSTANT_FETCH_23_3) +XE_GPU_REGISTER(0x488E, dword, SHADER_CONSTANT_FETCH_23_4) +XE_GPU_REGISTER(0x488F, dword, SHADER_CONSTANT_FETCH_23_5) +XE_GPU_REGISTER(0x4890, dword, SHADER_CONSTANT_FETCH_24_0) +XE_GPU_REGISTER(0x4891, dword, SHADER_CONSTANT_FETCH_24_1) +XE_GPU_REGISTER(0x4892, dword, SHADER_CONSTANT_FETCH_24_2) +XE_GPU_REGISTER(0x4893, dword, SHADER_CONSTANT_FETCH_24_3) +XE_GPU_REGISTER(0x4894, dword, SHADER_CONSTANT_FETCH_24_4) +XE_GPU_REGISTER(0x4895, dword, SHADER_CONSTANT_FETCH_24_5) +XE_GPU_REGISTER(0x4896, dword, SHADER_CONSTANT_FETCH_25_0) +XE_GPU_REGISTER(0x4897, dword, SHADER_CONSTANT_FETCH_25_1) +XE_GPU_REGISTER(0x4898, dword, SHADER_CONSTANT_FETCH_25_2) +XE_GPU_REGISTER(0x4899, dword, SHADER_CONSTANT_FETCH_25_3) +XE_GPU_REGISTER(0x489A, dword, SHADER_CONSTANT_FETCH_25_4) +XE_GPU_REGISTER(0x489B, dword, SHADER_CONSTANT_FETCH_25_5) +XE_GPU_REGISTER(0x489C, dword, SHADER_CONSTANT_FETCH_26_0) +XE_GPU_REGISTER(0x489D, dword, SHADER_CONSTANT_FETCH_26_1) +XE_GPU_REGISTER(0x489E, dword, SHADER_CONSTANT_FETCH_26_2) +XE_GPU_REGISTER(0x489F, dword, SHADER_CONSTANT_FETCH_26_3) +XE_GPU_REGISTER(0x48A0, dword, SHADER_CONSTANT_FETCH_26_4) +XE_GPU_REGISTER(0x48A1, dword, SHADER_CONSTANT_FETCH_26_5) +XE_GPU_REGISTER(0x48A2, dword, SHADER_CONSTANT_FETCH_27_0) +XE_GPU_REGISTER(0x48A3, dword, SHADER_CONSTANT_FETCH_27_1) +XE_GPU_REGISTER(0x48A4, dword, SHADER_CONSTANT_FETCH_27_2) +XE_GPU_REGISTER(0x48A5, dword, SHADER_CONSTANT_FETCH_27_3) +XE_GPU_REGISTER(0x48A6, dword, SHADER_CONSTANT_FETCH_27_4) +XE_GPU_REGISTER(0x48A7, dword, SHADER_CONSTANT_FETCH_27_5) +XE_GPU_REGISTER(0x48A8, dword, SHADER_CONSTANT_FETCH_28_0) +XE_GPU_REGISTER(0x48A9, dword, SHADER_CONSTANT_FETCH_28_1) +XE_GPU_REGISTER(0x48AA, dword, SHADER_CONSTANT_FETCH_28_2) +XE_GPU_REGISTER(0x48AB, dword, SHADER_CONSTANT_FETCH_28_3) +XE_GPU_REGISTER(0x48AC, dword, SHADER_CONSTANT_FETCH_28_4) +XE_GPU_REGISTER(0x48AD, dword, SHADER_CONSTANT_FETCH_28_5) +XE_GPU_REGISTER(0x48AE, dword, SHADER_CONSTANT_FETCH_29_0) +XE_GPU_REGISTER(0x48AF, dword, SHADER_CONSTANT_FETCH_29_1) +XE_GPU_REGISTER(0x48B0, dword, SHADER_CONSTANT_FETCH_29_2) +XE_GPU_REGISTER(0x48B1, dword, SHADER_CONSTANT_FETCH_29_3) +XE_GPU_REGISTER(0x48B2, dword, SHADER_CONSTANT_FETCH_29_4) +XE_GPU_REGISTER(0x48B3, dword, SHADER_CONSTANT_FETCH_29_5) +XE_GPU_REGISTER(0x48B4, dword, SHADER_CONSTANT_FETCH_30_0) +XE_GPU_REGISTER(0x48B5, dword, SHADER_CONSTANT_FETCH_30_1) +XE_GPU_REGISTER(0x48B6, dword, SHADER_CONSTANT_FETCH_30_2) +XE_GPU_REGISTER(0x48B7, dword, SHADER_CONSTANT_FETCH_30_3) +XE_GPU_REGISTER(0x48B8, dword, SHADER_CONSTANT_FETCH_30_4) +XE_GPU_REGISTER(0x48B9, dword, SHADER_CONSTANT_FETCH_30_5) +XE_GPU_REGISTER(0x48BA, dword, SHADER_CONSTANT_FETCH_31_0) +XE_GPU_REGISTER(0x48BB, dword, SHADER_CONSTANT_FETCH_31_1) +XE_GPU_REGISTER(0x48BC, dword, SHADER_CONSTANT_FETCH_31_2) +XE_GPU_REGISTER(0x48BD, dword, SHADER_CONSTANT_FETCH_31_3) +XE_GPU_REGISTER(0x48BE, dword, SHADER_CONSTANT_FETCH_31_4) +XE_GPU_REGISTER(0x48BF, dword, SHADER_CONSTANT_FETCH_31_5) + +XE_GPU_REGISTER(0x4900, dword, SHADER_CONSTANT_BOOL_000_031) +XE_GPU_REGISTER(0x4901, dword, SHADER_CONSTANT_BOOL_032_063) +XE_GPU_REGISTER(0x4902, dword, SHADER_CONSTANT_BOOL_064_095) +XE_GPU_REGISTER(0x4903, dword, SHADER_CONSTANT_BOOL_096_127) +XE_GPU_REGISTER(0x4904, dword, SHADER_CONSTANT_BOOL_128_159) +XE_GPU_REGISTER(0x4905, dword, SHADER_CONSTANT_BOOL_160_191) +XE_GPU_REGISTER(0x4906, dword, SHADER_CONSTANT_BOOL_192_223) +XE_GPU_REGISTER(0x4907, dword, SHADER_CONSTANT_BOOL_224_255) + +XE_GPU_REGISTER(0x4908, dword, SHADER_CONSTANT_LOOP_00) +XE_GPU_REGISTER(0x4909, dword, SHADER_CONSTANT_LOOP_01) +XE_GPU_REGISTER(0x490A, dword, SHADER_CONSTANT_LOOP_02) +XE_GPU_REGISTER(0x490B, dword, SHADER_CONSTANT_LOOP_03) +XE_GPU_REGISTER(0x490C, dword, SHADER_CONSTANT_LOOP_04) +XE_GPU_REGISTER(0x490D, dword, SHADER_CONSTANT_LOOP_05) +XE_GPU_REGISTER(0x490E, dword, SHADER_CONSTANT_LOOP_06) +XE_GPU_REGISTER(0x490F, dword, SHADER_CONSTANT_LOOP_07) +XE_GPU_REGISTER(0x4910, dword, SHADER_CONSTANT_LOOP_08) +XE_GPU_REGISTER(0x4911, dword, SHADER_CONSTANT_LOOP_09) +XE_GPU_REGISTER(0x4912, dword, SHADER_CONSTANT_LOOP_10) +XE_GPU_REGISTER(0x4913, dword, SHADER_CONSTANT_LOOP_11) +XE_GPU_REGISTER(0x4914, dword, SHADER_CONSTANT_LOOP_12) +XE_GPU_REGISTER(0x4915, dword, SHADER_CONSTANT_LOOP_13) +XE_GPU_REGISTER(0x4916, dword, SHADER_CONSTANT_LOOP_14) +XE_GPU_REGISTER(0x4917, dword, SHADER_CONSTANT_LOOP_15) +XE_GPU_REGISTER(0x4918, dword, SHADER_CONSTANT_LOOP_16) +XE_GPU_REGISTER(0x4919, dword, SHADER_CONSTANT_LOOP_17) +XE_GPU_REGISTER(0x491A, dword, SHADER_CONSTANT_LOOP_18) +XE_GPU_REGISTER(0x491B, dword, SHADER_CONSTANT_LOOP_19) +XE_GPU_REGISTER(0x491C, dword, SHADER_CONSTANT_LOOP_20) +XE_GPU_REGISTER(0x491D, dword, SHADER_CONSTANT_LOOP_21) +XE_GPU_REGISTER(0x491E, dword, SHADER_CONSTANT_LOOP_22) +XE_GPU_REGISTER(0x491F, dword, SHADER_CONSTANT_LOOP_23) +XE_GPU_REGISTER(0x4920, dword, SHADER_CONSTANT_LOOP_24) +XE_GPU_REGISTER(0x4921, dword, SHADER_CONSTANT_LOOP_25) +XE_GPU_REGISTER(0x4922, dword, SHADER_CONSTANT_LOOP_26) +XE_GPU_REGISTER(0x4923, dword, SHADER_CONSTANT_LOOP_27) +XE_GPU_REGISTER(0x4924, dword, SHADER_CONSTANT_LOOP_28) +XE_GPU_REGISTER(0x4925, dword, SHADER_CONSTANT_LOOP_29) +XE_GPU_REGISTER(0x4926, dword, SHADER_CONSTANT_LOOP_30) +XE_GPU_REGISTER(0x4927, dword, SHADER_CONSTANT_LOOP_31) + +// Ignored because I have no clue what these are. +// XE_GPU_REGISTER(0x8D00, dword, UNKNOWN_8D00) +// XE_GPU_REGISTER(0x8D01, dword, UNKNOWN_8D01) +// XE_GPU_REGISTER(0x8D02, dword, UNKNOWN_8D02) +// XE_GPU_REGISTER(0x8D03, dword, UNKNOWN_8D03) +// XE_GPU_REGISTER(0x8D04, dword, UNKNOWN_8D04) +// XE_GPU_REGISTER(0x8D05, dword, UNKNOWN_8D05) +// XE_GPU_REGISTER(0x8D06, dword, UNKNOWN_8D06) +// XE_GPU_REGISTER(0x8D07, dword, UNKNOWN_8D07) diff --git a/src/xenia/gpu/resource.cc b/src/xenia/gpu/resource.cc deleted file mode 100644 index 35ef82bb6..000000000 --- a/src/xenia/gpu/resource.cc +++ /dev/null @@ -1,37 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#include - - -using namespace std; -using namespace xe; -using namespace xe::gpu; -using namespace xe::gpu::xenos; - - -HashedResource::HashedResource(const MemoryRange& memory_range) - : memory_range_(memory_range) { -} - -HashedResource::~HashedResource() = default; - -PagedResource::PagedResource(const MemoryRange& memory_range) - : memory_range_(memory_range), dirtied_(true) { -} - -PagedResource::~PagedResource() = default; - -void PagedResource::MarkDirty(uint32_t lo_address, uint32_t hi_address) { - dirtied_ = true; -} - -StaticResource::StaticResource() = default; - -StaticResource::~StaticResource() = default; diff --git a/src/xenia/gpu/resource.h b/src/xenia/gpu/resource.h deleted file mode 100644 index 21a6fba84..000000000 --- a/src/xenia/gpu/resource.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef XENIA_GPU_RESOURCE_H_ -#define XENIA_GPU_RESOURCE_H_ - -#include -#include - -namespace xe { -namespace gpu { - -struct MemoryRange { - uint8_t* host_base; - uint32_t guest_base; - uint32_t length; - - MemoryRange() : host_base(nullptr), guest_base(0), length(0) {} - MemoryRange(const MemoryRange& other) - : host_base(other.host_base), guest_base(other.guest_base), - length(other.length) {} - MemoryRange(uint8_t* _host_base, uint32_t _guest_base, uint32_t _length) - : host_base(_host_base), guest_base(_guest_base), length(_length) {} -}; - - -class Resource { -public: - virtual ~Resource() = default; - - virtual void* handle() const = 0; - - template - T* handle_as() { - return reinterpret_cast(handle()); - } - -protected: - Resource() = default; - - // last use/LRU stuff -}; - - -class HashedResource : public Resource { -public: - ~HashedResource() override; - - const MemoryRange& memory_range() const { return memory_range_; } - -protected: - HashedResource(const MemoryRange& memory_range); - - MemoryRange memory_range_; - // key -}; - - -class PagedResource : public Resource { -public: - ~PagedResource() override; - - const MemoryRange& memory_range() const { return memory_range_; } - - template - bool Equals(const T& info) { - return Equals(&info, sizeof(info)); - } - virtual bool Equals(const void* info_ptr, size_t info_length) = 0; - - bool is_dirty() const { return true; } - void MarkDirty(uint32_t lo_address, uint32_t hi_address); - -protected: - PagedResource(const MemoryRange& memory_range); - - MemoryRange memory_range_; - bool dirtied_; - // dirtied pages list -}; - - -class StaticResource : public Resource { -public: - ~StaticResource() override; - -protected: - StaticResource(); -}; - -} // namespace gpu -} // namespace xe - -#endif // XENIA_GPU_RESOURCE_H_ diff --git a/src/xenia/gpu/resource_cache.cc b/src/xenia/gpu/resource_cache.cc deleted file mode 100644 index 10d6203d4..000000000 --- a/src/xenia/gpu/resource_cache.cc +++ /dev/null @@ -1,120 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#include - -#include - -#include - -using namespace std; -using namespace xe; -using namespace xe::gpu; -using namespace xe::gpu::xenos; - - -ResourceCache::ResourceCache(Memory* memory) - : memory_(memory) { -} - -ResourceCache::~ResourceCache() { - for (auto it = resources_.begin(); it != resources_.end(); ++it) { - Resource* resource = *it; - delete resource; - } - resources_.clear(); -} - -VertexShaderResource* ResourceCache::FetchVertexShader( - const MemoryRange& memory_range, - const VertexShaderResource::Info& info) { - return FetchHashedResource( - memory_range, info, &ResourceCache::CreateVertexShader); -} - -PixelShaderResource* ResourceCache::FetchPixelShader( - const MemoryRange& memory_range, - const PixelShaderResource::Info& info) { - return FetchHashedResource( - memory_range, info, &ResourceCache::CreatePixelShader); -} - -TextureResource* ResourceCache::FetchTexture( - const MemoryRange& memory_range, - const TextureResource::Info& info) { - auto resource = FetchPagedResource( - memory_range, info, &ResourceCache::CreateTexture); - if (!resource) { - return nullptr; - } - if (resource->Prepare()) { - XELOGE("Unable to prepare texture"); - return nullptr; - } - return resource; -} - -SamplerStateResource* ResourceCache::FetchSamplerState( - const SamplerStateResource::Info& info) { - auto key = info.hash(); - auto it = static_resources_.find(key); - if (it != static_resources_.end()) { - return static_cast(it->second); - } - auto resource = CreateSamplerState(info); - if (resource->Prepare()) { - XELOGE("Unable to prepare sampler state"); - return nullptr; - } - static_resources_.insert({ key, resource }); - resources_.push_back(resource); - return resource; -} - -IndexBufferResource* ResourceCache::FetchIndexBuffer( - const MemoryRange& memory_range, - const IndexBufferResource::Info& info) { - auto resource = FetchPagedResource( - memory_range, info, &ResourceCache::CreateIndexBuffer); - if (!resource) { - return nullptr; - } - if (resource->Prepare()) { - XELOGE("Unable to prepare index buffer"); - return nullptr; - } - return resource; -} - -VertexBufferResource* ResourceCache::FetchVertexBuffer( - const MemoryRange& memory_range, - const VertexBufferResource::Info& info) { - auto resource = FetchPagedResource( - memory_range, info, &ResourceCache::CreateVertexBuffer); - if (!resource) { - return nullptr; - } - if (resource->Prepare()) { - XELOGE("Unable to prepare vertex buffer"); - return nullptr; - } - return resource; -} - -uint64_t ResourceCache::HashRange(const MemoryRange& memory_range) { - // We could do something smarter here to potentially early exit. - return hash64(memory_range.host_base, memory_range.length); -} - -void ResourceCache::SyncRange(uint32_t address, int length) { - SCOPE_profile_cpu_f("gpu"); - // TODO(benvanik): something interesting? - //uint32_t lo_address = address % 0x20000000; - //uint32_t hi_address = lo_address + length; -} diff --git a/src/xenia/gpu/resource_cache.h b/src/xenia/gpu/resource_cache.h deleted file mode 100644 index 870a6c495..000000000 --- a/src/xenia/gpu/resource_cache.h +++ /dev/null @@ -1,124 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef XENIA_GPU_RESOURCE_CACHE_H_ -#define XENIA_GPU_RESOURCE_CACHE_H_ - -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -namespace xe { -namespace gpu { - -class ResourceCache { -public: - virtual ~ResourceCache(); - - VertexShaderResource* FetchVertexShader( - const MemoryRange& memory_range, - const VertexShaderResource::Info& info); - PixelShaderResource* FetchPixelShader( - const MemoryRange& memory_range, - const PixelShaderResource::Info& info); - - TextureResource* FetchTexture( - const MemoryRange& memory_range, - const TextureResource::Info& info); - SamplerStateResource* FetchSamplerState( - const SamplerStateResource::Info& info); - - IndexBufferResource* FetchIndexBuffer( - const MemoryRange& memory_range, - const IndexBufferResource::Info& info); - VertexBufferResource* FetchVertexBuffer( - const MemoryRange& memory_range, - const VertexBufferResource::Info& info); - - uint64_t HashRange(const MemoryRange& memory_range); - - void SyncRange(uint32_t address, int length); - -protected: - ResourceCache(Memory* memory); - - template - T* FetchHashedResource(const MemoryRange& memory_range, - const typename T::Info& info, - const V& factory) { - // TODO(benvanik): if there's no way it's changed and it's been checked, - // just lookup. This way we don't rehash 100x a frame. - auto key = HashRange(memory_range); - auto it = hashed_resources_.find(key); - if (it != hashed_resources_.end()) { - return static_cast(it->second); - } - auto resource = (this->*factory)(memory_range, info); - hashed_resources_.insert({ key, resource }); - resources_.push_back(resource); - return resource; - } - - template - T* FetchPagedResource(const MemoryRange& memory_range, - const typename T::Info& info, - const V& factory) { - uint32_t lo_address = memory_range.guest_base % 0x20000000; - auto key = uint64_t(lo_address); - auto range = paged_resources_.equal_range(key); - for (auto it = range.first; it != range.second; ++it) { - if (it->second->memory_range().length == memory_range.length && - it->second->Equals(info)) { - return static_cast(it->second); - } - } - auto resource = (this->*factory)(memory_range, info); - paged_resources_.insert({ key, resource }); - resources_.push_back(resource); - return resource; - } - - virtual VertexShaderResource* CreateVertexShader( - const MemoryRange& memory_range, - const VertexShaderResource::Info& info) = 0; - virtual PixelShaderResource* CreatePixelShader( - const MemoryRange& memory_range, - const PixelShaderResource::Info& info) = 0; - virtual TextureResource* CreateTexture( - const MemoryRange& memory_range, - const TextureResource::Info& info) = 0; - virtual SamplerStateResource* CreateSamplerState( - const SamplerStateResource::Info& info) = 0; - virtual IndexBufferResource* CreateIndexBuffer( - const MemoryRange& memory_range, - const IndexBufferResource::Info& info) = 0; - virtual VertexBufferResource* CreateVertexBuffer( - const MemoryRange& memory_range, - const VertexBufferResource::Info& info) = 0; - -private: - Memory* memory_; - - std::vector resources_; - std::unordered_map hashed_resources_; - std::unordered_map static_resources_; - std::multimap paged_resources_; -}; - -} // namespace gpu -} // namespace xe - -#endif // XENIA_GPU_RESOURCE_CACHE_H_ diff --git a/src/xenia/gpu/sampler_state_resource.cc b/src/xenia/gpu/sampler_state_resource.cc deleted file mode 100644 index 5865a6920..000000000 --- a/src/xenia/gpu/sampler_state_resource.cc +++ /dev/null @@ -1,32 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#include - - -using namespace std; -using namespace xe; -using namespace xe::gpu; -using namespace xe::gpu::xenos; - - -bool SamplerStateResource::Info::Prepare( - const xe_gpu_texture_fetch_t& fetch, const instr_fetch_tex_t& fetch_instr, - Info& out_info) { - out_info.min_filter = static_cast( - fetch_instr.min_filter == 3 ? fetch.min_filter : fetch_instr.min_filter); - out_info.mag_filter = static_cast( - fetch_instr.mag_filter == 3 ? fetch.mag_filter : fetch_instr.mag_filter); - out_info.mip_filter = static_cast( - fetch_instr.mip_filter == 3 ? fetch.mip_filter : fetch_instr.mip_filter); - out_info.clamp_u = fetch.clamp_x; - out_info.clamp_v = fetch.clamp_y; - out_info.clamp_w = fetch.clamp_z; - return true; -} diff --git a/src/xenia/gpu/sampler_state_resource.h b/src/xenia/gpu/sampler_state_resource.h deleted file mode 100644 index 1a14cef4d..000000000 --- a/src/xenia/gpu/sampler_state_resource.h +++ /dev/null @@ -1,68 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef XENIA_GPU_SAMPLER_STATE_RESOURCE_H_ -#define XENIA_GPU_SAMPLER_STATE_RESOURCE_H_ - -#include -#include -#include -#include - - -namespace xe { -namespace gpu { - - -class SamplerStateResource : public StaticResource { -public: - struct Info { - xenos::instr_tex_filter_t min_filter; - xenos::instr_tex_filter_t mag_filter; - xenos::instr_tex_filter_t mip_filter; - uint32_t clamp_u; - uint32_t clamp_v; - uint32_t clamp_w; - - uint64_t hash() const { - return hash_combine(0, - min_filter, mag_filter, mip_filter, - clamp_u, clamp_v, clamp_w); - } - bool Equals(const Info& other) const { - return min_filter == other.min_filter && - mag_filter == other.mag_filter && - mip_filter == other.mip_filter && - clamp_u == other.clamp_u && - clamp_v == other.clamp_v && - clamp_w == other.clamp_w; - } - - static bool Prepare(const xenos::xe_gpu_texture_fetch_t& fetch, - const xenos::instr_fetch_tex_t& fetch_instr, - Info& out_info); - }; - - SamplerStateResource(const Info& info) : info_(info) {} - virtual ~SamplerStateResource() = default; - - const Info& info() const { return info_; } - - virtual int Prepare() = 0; - -protected: - Info info_; -}; - - -} // namespace gpu -} // namespace xe - - -#endif // XENIA_GPU_SAMPLER_STATE_RESOURCE_H_ diff --git a/src/xenia/gpu/shader_resource.cc b/src/xenia/gpu/shader_resource.cc deleted file mode 100644 index 595e5522c..000000000 --- a/src/xenia/gpu/shader_resource.cc +++ /dev/null @@ -1,280 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#include - -#include -#include - -const bool kAssertOnZeroShaders = false; - -using namespace std; -using namespace xe; -using namespace xe::gpu; -using namespace xe::gpu::xenos; - -ShaderResource::ShaderResource(const MemoryRange& memory_range, - const Info& info, xenos::XE_GPU_SHADER_TYPE type) - : HashedResource(memory_range), - info_(info), - type_(type), - is_prepared_(false), - disasm_src_(nullptr) { - memset(&alloc_counts_, 0, sizeof(alloc_counts_)); - memset(&buffer_inputs_, 0, sizeof(buffer_inputs_)); - memset(&sampler_inputs_, 0, sizeof(sampler_inputs_)); - - // Verify. - dword_count_ = memory_range.length / 4; - assert_true(dword_count_ <= 512); - - // Copy bytes and swap. - size_t byte_size = dword_count_ * sizeof(uint32_t); - dwords_ = (uint32_t*)malloc(byte_size); - bool any_nonzero = false; - for (uint32_t n = 0; n < dword_count_; n++) { - dwords_[n] = poly::load_and_swap(memory_range.host_base + n * 4); - any_nonzero = any_nonzero || dwords_[n] != 0; - } - if (kAssertOnZeroShaders) { - assert_true(any_nonzero); - } - - // Disassemble, for debugging. - disasm_src_ = DisassembleShader(type_, dwords_, dword_count_); - - // Gather input/output registers/etc. - GatherIO(); -} - -ShaderResource::~ShaderResource() { - free(disasm_src_); - free(dwords_); -} - -void ShaderResource::GatherIO() { - // Process all execution blocks. - instr_cf_t cfa; - instr_cf_t cfb; - for (int idx = 0; idx < dword_count_; idx += 3) { - uint32_t dword_0 = dwords_[idx + 0]; - uint32_t dword_1 = dwords_[idx + 1]; - uint32_t dword_2 = dwords_[idx + 2]; - cfa.dword_0 = dword_0; - cfa.dword_1 = dword_1 & 0xFFFF; - cfb.dword_0 = (dword_1 >> 16) | (dword_2 << 16); - cfb.dword_1 = dword_2 >> 16; - if (cfa.opc == ALLOC) { - GatherAlloc(&cfa.alloc); - } else if (cfa.is_exec()) { - GatherExec(&cfa.exec); - } - if (cfb.opc == ALLOC) { - GatherAlloc(&cfb.alloc); - } else if (cfb.is_exec()) { - GatherExec(&cfb.exec); - } - if (cfa.opc == EXEC_END || cfb.opc == EXEC_END) { - break; - } - } -} - -void ShaderResource::GatherAlloc(const instr_cf_alloc_t* cf) { - allocs_.push_back(*cf); - - switch (cf->buffer_select) { - case SQ_POSITION: - // Position (SV_POSITION). - alloc_counts_.positions += cf->size + 1; - break; - case SQ_PARAMETER_PIXEL: - // Output to PS (if VS), or frag output (if PS). - alloc_counts_.params += cf->size + 1; - break; - case SQ_MEMORY: - // MEMEXPORT? - alloc_counts_.memories += cf->size + 1; - break; - } -} - -void ShaderResource::GatherExec(const instr_cf_exec_t* cf) { - execs_.push_back(*cf); - - uint32_t sequence = cf->serialize; - for (uint32_t i = 0; i < cf->count; i++) { - uint32_t alu_off = (cf->address + i); - int sync = sequence & 0x2; - if (sequence & 0x1) { - const instr_fetch_t* fetch = - (const instr_fetch_t*)(dwords_ + alu_off * 3); - switch (fetch->opc) { - case VTX_FETCH: - GatherVertexFetch(&fetch->vtx); - break; - case TEX_FETCH: - GatherTextureFetch(&fetch->tex); - break; - case TEX_GET_BORDER_COLOR_FRAC: - case TEX_GET_COMP_TEX_LOD: - case TEX_GET_GRADIENTS: - case TEX_GET_WEIGHTS: - case TEX_SET_TEX_LOD: - case TEX_SET_GRADIENTS_H: - case TEX_SET_GRADIENTS_V: - default: - assert_always(); - break; - } - } else { - // TODO(benvanik): gather registers used, predicate bits used, etc. - const instr_alu_t* alu = (const instr_alu_t*)(dwords_ + alu_off * 3); - if (alu->vector_write_mask) { - if (alu->export_data && alu->vector_dest == 63) { - alloc_counts_.point_size = true; - } - } - if (alu->scalar_write_mask || !alu->vector_write_mask) { - if (alu->export_data && alu->scalar_dest == 63) { - alloc_counts_.point_size = true; - } - } - } - sequence >>= 2; - } -} - -void ShaderResource::GatherVertexFetch(const instr_fetch_vtx_t* vtx) { - assert_true(type_ == XE_GPU_SHADER_TYPE_VERTEX); - - // dst_reg/dst_swiz - // src_reg/src_swiz - // format = a2xx_sq_surfaceformat - // format_comp_all ? signed : unsigned - // num_format_all ? normalized - // stride - // offset - // const_index/const_index_sel -- fetch constant register - // num_format_all ? integer : fraction - // exp_adjust_all - [-32,31] - (2^exp_adjust_all)*fetch - 0 = default - - // Sometimes games have fetches that just produce constants. We can - // ignore those. - uint32_t dst_swiz = vtx->dst_swiz; - bool fetches_any_data = false; - for (int i = 0; i < 4; i++) { - if ((dst_swiz & 0x7) == 4) { - // 0.0 - } else if ((dst_swiz & 0x7) == 5) { - // 1.0 - } else if ((dst_swiz & 0x7) == 6) { - // ? - } else if ((dst_swiz & 0x7) == 7) { - // Previous register value. - } else { - fetches_any_data = true; - break; - } - dst_swiz >>= 3; - } - if (!fetches_any_data) { - return; - } - - uint32_t fetch_slot = vtx->const_index * 3 + vtx->const_index_sel; - auto& inputs = buffer_inputs_; - VertexBufferResource::DeclElement* el = nullptr; - for (size_t n = 0; n < inputs.count; n++) { - auto& desc = inputs.descs[n]; - auto& info = desc.info; - if (desc.fetch_slot == fetch_slot) { - assert_true(info.element_count <= poly::countof(info.elements)); - // It may not hold that all strides are equal, but I hope it does. - assert_true(!vtx->stride || info.stride_words == vtx->stride); - el = &info.elements[info.element_count++]; - break; - } - } - if (!el) { - assert_not_zero(vtx->stride); - assert_true(inputs.count + 1 < poly::countof(inputs.descs)); - auto& desc = inputs.descs[inputs.count++]; - desc.input_index = inputs.count - 1; - desc.fetch_slot = fetch_slot; - desc.info.stride_words = vtx->stride; - el = &desc.info.elements[desc.info.element_count++]; - } - - el->vtx_fetch = *vtx; - el->format = vtx->format; - el->is_normalized = vtx->num_format_all == 0; - el->is_signed = vtx->format_comp_all == 1; - el->offset_words = vtx->offset; - el->size_words = 0; - switch (el->format) { - case FMT_8_8_8_8: - case FMT_2_10_10_10: - case FMT_10_11_11: - case FMT_11_11_10: - el->size_words = 1; - break; - case FMT_16_16: - case FMT_16_16_FLOAT: - el->size_words = 1; - break; - case FMT_16_16_16_16: - case FMT_16_16_16_16_FLOAT: - el->size_words = 2; - break; - case FMT_32: - case FMT_32_FLOAT: - el->size_words = 1; - break; - case FMT_32_32: - case FMT_32_32_FLOAT: - el->size_words = 2; - break; - case FMT_32_32_32_FLOAT: - el->size_words = 3; - break; - case FMT_32_32_32_32: - case FMT_32_32_32_32_FLOAT: - el->size_words = 4; - break; - default: - XELOGE("Unknown vertex format: %d", el->format); - assert_always(); - break; - } -} - -void ShaderResource::GatherTextureFetch(const xenos::instr_fetch_tex_t* tex) { - // TODO(benvanik): check dest_swiz to see if we are writing anything. - - assert_true(sampler_inputs_.count + 1 < poly::countof(sampler_inputs_.descs)); - auto& input = sampler_inputs_.descs[sampler_inputs_.count++]; - input.input_index = sampler_inputs_.count - 1; - input.fetch_slot = tex->const_idx & 0xF; // ? - input.tex_fetch = *tex; - - // Format mangling, size estimation, etc. -} - -VertexShaderResource::VertexShaderResource(const MemoryRange& memory_range, - const Info& info) - : ShaderResource(memory_range, info, XE_GPU_SHADER_TYPE_VERTEX) {} - -VertexShaderResource::~VertexShaderResource() = default; - -PixelShaderResource::PixelShaderResource(const MemoryRange& memory_range, - const Info& info) - : ShaderResource(memory_range, info, XE_GPU_SHADER_TYPE_PIXEL) {} - -PixelShaderResource::~PixelShaderResource() = default; diff --git a/src/xenia/gpu/shader_resource.h b/src/xenia/gpu/shader_resource.h deleted file mode 100644 index 85414daf8..000000000 --- a/src/xenia/gpu/shader_resource.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef XENIA_GPU_SHADER_RESOURCE_H_ -#define XENIA_GPU_SHADER_RESOURCE_H_ - -#include - -#include -#include -#include -#include - - -namespace xe { -namespace gpu { - - -class ShaderResource : public HashedResource { -public: - struct Info { - // type, etc? - }; - - ~ShaderResource() override; - - const Info& info() const { return info_; } - xenos::XE_GPU_SHADER_TYPE type() const { return type_; } - const uint32_t* dwords() const { return dwords_; } - const size_t dword_count() const { return dword_count_; } - - bool is_prepared() const { return is_prepared_; } - const char* disasm_src() const { return disasm_src_; } - - struct BufferDesc { - uint32_t input_index; - uint32_t fetch_slot; - VertexBufferResource::Info info; - // xenos::instr_fetch_vtx_t vtx_fetch; for each el - }; - struct BufferInputs { - uint32_t count; - BufferDesc descs[32]; - }; - const BufferInputs& buffer_inputs() { return buffer_inputs_; } - - struct SamplerDesc { - uint32_t input_index; - uint32_t fetch_slot; - uint32_t format; - xenos::instr_fetch_tex_t tex_fetch; - }; - struct SamplerInputs { - uint32_t count; - SamplerDesc descs[32]; - }; - const SamplerInputs& sampler_inputs() { return sampler_inputs_; } - - struct AllocCounts { - uint32_t positions; - uint32_t params; - uint32_t memories; - bool point_size; - }; - const AllocCounts& alloc_counts() const { return alloc_counts_; } - const std::vector& execs() const { return execs_; } - const std::vector& allocs() const { return allocs_; } - -private: - void GatherIO(); - void GatherAlloc(const xenos::instr_cf_alloc_t* cf); - void GatherExec(const xenos::instr_cf_exec_t* cf); - void GatherVertexFetch(const xenos::instr_fetch_vtx_t* vtx); - void GatherTextureFetch(const xenos::instr_fetch_tex_t* tex); - -protected: - ShaderResource(const MemoryRange& memory_range, - const Info& info, - xenos::XE_GPU_SHADER_TYPE type); - - Info info_; - xenos::XE_GPU_SHADER_TYPE type_; - size_t dword_count_; - uint32_t* dwords_; - char* disasm_src_; - - AllocCounts alloc_counts_; - std::vector execs_; - std::vector allocs_; - BufferInputs buffer_inputs_; - SamplerInputs sampler_inputs_; - - bool is_prepared_; -}; - - -class VertexShaderResource : public ShaderResource { -public: - VertexShaderResource(const MemoryRange& memory_range, - const Info& info); - ~VertexShaderResource() override; - - // buffer_inputs() matching VertexBufferResource::Info - - virtual int Prepare(const xenos::xe_gpu_program_cntl_t& program_cntl) = 0; -}; - - -class PixelShaderResource : public ShaderResource { -public: - PixelShaderResource(const MemoryRange& memory_range, - const Info& info); - ~PixelShaderResource() override; - - virtual int Prepare(const xenos::xe_gpu_program_cntl_t& program_cntl, - VertexShaderResource* vertex_shader) = 0; -}; - - -} // namespace gpu -} // namespace xe - - -#endif // XENIA_GPU_SHADER_RESOURCE_H_ diff --git a/src/xenia/gpu/sources.gypi b/src/xenia/gpu/sources.gypi index e1e0a0b14..d55d68409 100644 --- a/src/xenia/gpu/sources.gypi +++ b/src/xenia/gpu/sources.gypi @@ -1,42 +1,21 @@ # Copyright 2013 Ben Vanik. All Rights Reserved. { 'sources': [ - 'buffer_resource.cc', - 'buffer_resource.h', - 'command_processor.cc', - 'command_processor.h', - 'draw_command.h', 'gpu-private.h', 'gpu.cc', 'gpu.h', - 'graphics_driver.cc', - 'graphics_driver.h', 'graphics_system.cc', 'graphics_system.h', 'register_file.cc', 'register_file.h', - 'resource.cc', - 'resource.h', - 'resource_cache.cc', - 'resource_cache.h', - 'sampler_state_resource.cc', - 'sampler_state_resource.h', - 'shader_resource.cc', - 'shader_resource.h', - 'texture_resource.cc', - 'texture_resource.h', + 'register_table.inc', + 'ucode.h', + 'ucode_disassembler.cc', + 'ucode_disassembler.h', + 'xenos.h', ], 'includes': [ - 'nop/sources.gypi', - 'xenos/sources.gypi', - ], - - 'conditions': [ - ['OS == "win"', { - 'includes': [ - 'd3d11/sources.gypi', - ], - }], + 'gl4/sources.gypi', ], } diff --git a/src/xenia/gpu/texture_resource.cc b/src/xenia/gpu/texture_resource.cc deleted file mode 100644 index 0a6c1058f..000000000 --- a/src/xenia/gpu/texture_resource.cc +++ /dev/null @@ -1,363 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#include - -#include -#include -#include - - -using namespace std; -using namespace xe; -using namespace xe::gpu; -using namespace xe::gpu::xenos; - - -bool TextureResource::Info::Prepare(const xe_gpu_texture_fetch_t& fetch, - Info& info) { - // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308051(v=vs.85).aspx - // a2xx_sq_surfaceformat - - info.dimension = (TextureDimension)fetch.dimension; - switch (info.dimension) { - case TEXTURE_DIMENSION_1D: - info.width = fetch.size_1d.width; - break; - case TEXTURE_DIMENSION_2D: - info.width = fetch.size_2d.width; - info.height = fetch.size_2d.height; - break; - case TEXTURE_DIMENSION_3D: - case TEXTURE_DIMENSION_CUBE: - info.width = fetch.size_3d.width; - info.height = fetch.size_3d.height; - info.depth = fetch.size_3d.depth; - break; - } - info.block_size = 0; - info.texel_pitch = 0; - info.endianness = (XE_GPU_ENDIAN)fetch.endianness; - info.is_tiled = fetch.tiled; - info.is_compressed = false; - info.input_length = 0; - info.format = DXGI_FORMAT_UNKNOWN; - switch (fetch.format) { - case FMT_8: - switch (fetch.swizzle) { - case XE_GPU_SWIZZLE_RRR1: - info.format = DXGI_FORMAT_R8_UNORM; - break; - case XE_GPU_SWIZZLE_000R: - info.format = DXGI_FORMAT_A8_UNORM; - break; - default: - XELOGW("D3D11: unhandled swizzle for FMT_8"); - info.format = DXGI_FORMAT_A8_UNORM; - break; - } - info.block_size = 1; - info.texel_pitch = 1; - break; - case FMT_1_5_5_5: - switch (fetch.swizzle) { - case XE_GPU_SWIZZLE_BGRA: - info.format = DXGI_FORMAT_B5G5R5A1_UNORM; - break; - default: - XELOGW("D3D11: unhandled swizzle for FMT_1_5_5_5"); - info.format = DXGI_FORMAT_B5G5R5A1_UNORM; - break; - } - info.block_size = 1; - info.texel_pitch = 2; - break; - case FMT_8_8_8_8: - case FMT_8_8_8_8_AS_16_16_16_16: - switch (fetch.swizzle) { - case XE_GPU_SWIZZLE_RGBA: - info.format = DXGI_FORMAT_R8G8B8A8_UNORM; - break; - case XE_GPU_SWIZZLE_BGRA: - info.format = DXGI_FORMAT_B8G8R8A8_UNORM; - break; - case XE_GPU_SWIZZLE_RGB1: - info.format = DXGI_FORMAT_R8G8B8A8_UNORM; // ? - break; - case XE_GPU_SWIZZLE_BGR1: - info.format = DXGI_FORMAT_B8G8R8X8_UNORM; - break; - default: - XELOGW("D3D11: unhandled swizzle for FMT_8_8_8_8"); - info.format = DXGI_FORMAT_R8G8B8A8_UNORM; - break; - } - info.block_size = 1; - info.texel_pitch = 4; - break; - case FMT_4_4_4_4: - switch (fetch.swizzle) { - case XE_GPU_SWIZZLE_BGRA: - info.format = DXGI_FORMAT_B4G4R4A4_UNORM; // only supported on Windows 8+ - break; - default: - XELOGW("D3D11: unhandled swizzle for FMT_4_4_4_4"); - info.format = DXGI_FORMAT_B4G4R4A4_UNORM; // only supported on Windows 8+ - break; - } - info.block_size = 1; - info.texel_pitch = 2; - break; - case FMT_16_16_16_16_FLOAT: - switch (fetch.swizzle) { - case XE_GPU_SWIZZLE_RGBA: - info.format = DXGI_FORMAT_R16G16B16A16_FLOAT; - break; - default: - XELOGW("D3D11: unhandled swizzle for FMT_16_16_16_16_FLOAT"); - info.format = DXGI_FORMAT_R16G16B16A16_FLOAT; - break; - } - info.block_size = 1; - info.texel_pitch = 8; - break; - case FMT_32_FLOAT: - switch (fetch.swizzle) { - case XE_GPU_SWIZZLE_R111: - info.format = DXGI_FORMAT_R32_FLOAT; - break; - default: - XELOGW("D3D11: unhandled swizzle for FMT_32_FLOAT"); - info.format = DXGI_FORMAT_R32_FLOAT; - break; - } - info.block_size = 1; - info.texel_pitch = 4; - break; - case FMT_DXT1: - info.format = DXGI_FORMAT_BC1_UNORM; - info.block_size = 4; - info.texel_pitch = 8; - info.is_compressed = true; - break; - case FMT_DXT2_3: - case FMT_DXT4_5: - info.format = (fetch.format == FMT_DXT4_5 ? DXGI_FORMAT_BC3_UNORM : DXGI_FORMAT_BC2_UNORM); - info.block_size = 4; - info.texel_pitch = 16; - info.is_compressed = true; - break; - case FMT_DXT1_AS_16_16_16_16: - // TODO(benvanik): conversion? - info.format = DXGI_FORMAT_BC1_UNORM; - info.block_size = 4; - info.texel_pitch = 8; - info.is_compressed = true; - break; - case FMT_DXT2_3_AS_16_16_16_16: - case FMT_DXT4_5_AS_16_16_16_16: - // TODO(benvanik): conversion? - info.format = DXGI_FORMAT_BC3_UNORM; - info.block_size = 4; - info.texel_pitch = 16; - info.is_compressed = true; - break; - case FMT_1_REVERSE: - case FMT_1: - case FMT_5_6_5: - case FMT_6_5_5: - case FMT_2_10_10_10: - case FMT_8_A: - case FMT_8_B: - case FMT_8_8: - case FMT_Cr_Y1_Cb_Y0: - case FMT_Y1_Cr_Y0_Cb: - case FMT_5_5_5_1: - case FMT_8_8_8_8_A: - case FMT_10_11_11: - case FMT_11_11_10: - case FMT_24_8: - case FMT_24_8_FLOAT: - case FMT_16: - case FMT_16_16: - case FMT_16_16_16_16: - case FMT_16_EXPAND: - case FMT_16_16_EXPAND: - case FMT_16_16_16_16_EXPAND: - case FMT_16_FLOAT: - case FMT_16_16_FLOAT: - case FMT_32: - case FMT_32_32: - case FMT_32_32_32_32: - case FMT_32_32_FLOAT: - case FMT_32_32_32_32_FLOAT: - case FMT_32_AS_8: - case FMT_32_AS_8_8: - case FMT_16_MPEG: - case FMT_16_16_MPEG: - case FMT_8_INTERLACED: - case FMT_32_AS_8_INTERLACED: - case FMT_32_AS_8_8_INTERLACED: - case FMT_16_INTERLACED: - case FMT_16_MPEG_INTERLACED: - case FMT_16_16_MPEG_INTERLACED: - case FMT_DXN: - case FMT_2_10_10_10_AS_16_16_16_16: - case FMT_10_11_11_AS_16_16_16_16: - case FMT_11_11_10_AS_16_16_16_16: - case FMT_32_32_32_FLOAT: - case FMT_DXT3A: - case FMT_DXT5A: - case FMT_CTX1: - case FMT_DXT3A_AS_1_1_1_1: - info.format = DXGI_FORMAT_UNKNOWN; - break; - } - - if (info.format == DXGI_FORMAT_UNKNOWN) { - return false; - } - - // Must be called here when we know the format. - switch (info.dimension) { - case TEXTURE_DIMENSION_1D: - info.CalculateTextureSizes1D(fetch); - break; - case TEXTURE_DIMENSION_2D: - info.CalculateTextureSizes2D(fetch); - break; - case TEXTURE_DIMENSION_3D: - // TODO(benvanik): calculate size. - return false; - case TEXTURE_DIMENSION_CUBE: - // TODO(benvanik): calculate size. - return false; - } - return true; -} - -void TextureResource::Info::CalculateTextureSizes1D( - const xe_gpu_texture_fetch_t& fetch) { - // ? - size_1d.width = fetch.size_1d.width; -} - -void TextureResource::Info::CalculateTextureSizes2D( - const xe_gpu_texture_fetch_t& fetch) { - size_2d.logical_width = 1 + fetch.size_2d.width; - size_2d.logical_height = 1 + fetch.size_2d.height; - - size_2d.block_width = size_2d.logical_width / block_size; - size_2d.block_height = size_2d.logical_height / block_size; - - if (!is_compressed) { - // must be 32x32 but also must have a pitch that is a multiple of 256 bytes - uint32_t bytes_per_block = block_size * block_size * texel_pitch; - uint32_t width_multiple = 32; - if (bytes_per_block) { - uint32_t minimum_multiple = 256 / bytes_per_block; - if (width_multiple < minimum_multiple) { - width_multiple = minimum_multiple; - } - } - size_2d.input_width = poly::round_up(size_2d.logical_width, width_multiple); - size_2d.input_height = poly::round_up(size_2d.logical_height, 32); - size_2d.output_width = size_2d.logical_width; - size_2d.output_height = size_2d.logical_height; - } else { - // must be 128x128 - size_2d.input_width = poly::round_up(size_2d.logical_width, 128); - size_2d.input_height = poly::round_up(size_2d.logical_height, 128); - size_2d.output_width = poly::next_pow2(size_2d.logical_width); - size_2d.output_height = poly::next_pow2(size_2d.logical_height); - } - - size_2d.logical_pitch = (size_2d.logical_width / block_size) * texel_pitch; - size_2d.input_pitch = (size_2d.input_width / block_size) * texel_pitch; - - if (!is_tiled) { - input_length = size_2d.block_height * size_2d.logical_pitch; - } else { - input_length = size_2d.block_height * size_2d.logical_pitch; // ? - } -} - -TextureResource::TextureResource(const MemoryRange& memory_range, - const Info& info) - : PagedResource(memory_range), - info_(info) { -} - -TextureResource::~TextureResource() { -} - -int TextureResource::Prepare() { - if (!handle()) { - if (CreateHandle()) { - XELOGE("Unable to create texture handle"); - return 1; - } - } - - //if (!dirtied_) { - // return 0; - //} - //dirtied_ = false; - - // pass dirty regions? - return InvalidateRegion(memory_range_); -} - -void TextureResource::TextureSwap(uint8_t* dest, const uint8_t* src, - uint32_t pitch) const { - // TODO(benvanik): optimize swapping paths. - switch (info_.endianness) { - case XE_GPU_ENDIAN_8IN16: - for (uint32_t i = 0; i < pitch; i += 2, src += 2, dest += 2) { - *(uint16_t*)dest = poly::byte_swap(*(uint16_t*)src); - } - break; - case XE_GPU_ENDIAN_8IN32: // Swap bytes. - for (uint32_t i = 0; i < pitch; i += 4, src += 4, dest += 4) { - *(uint32_t*)dest = poly::byte_swap(*(uint32_t*)src); - } - break; - case XE_GPU_ENDIAN_16IN32: // Swap half words. - for (uint32_t i = 0; i < pitch; i += 4, src += 4, dest += 4) { - uint32_t value = *(uint32_t*)src; - *(uint32_t*)dest = ((value >> 16) & 0xFFFF) | (value << 16); - } - break; - default: - case XE_GPU_ENDIAN_NONE: - memcpy(dest, src, pitch); - break; - } -} - -// https://code.google.com/p/crunch/source/browse/trunk/inc/crn_decomp.h#4104 -uint32_t TextureResource::TiledOffset2DOuter(uint32_t y, uint32_t width, - uint32_t log_bpp) const { - uint32_t macro = ((y >> 5) * (width >> 5)) << (log_bpp + 7); - uint32_t micro = ((y & 6) << 2) << log_bpp; - return macro + - ((micro & ~15) << 1) + - (micro & 15) + - ((y & 8) << (3 + log_bpp)) + - ((y & 1) << 4); -} - -uint32_t TextureResource::TiledOffset2DInner(uint32_t x, uint32_t y, uint32_t bpp, - uint32_t base_offset) const { - uint32_t macro = (x >> 5) << (bpp + 7); - uint32_t micro = (x & 7) << bpp; - uint32_t offset = base_offset + (macro + ((micro & ~15) << 1) + (micro & 15)); - return ((offset & ~511) << 3) + ((offset & 448) << 2) + (offset & 63) + - ((y & 16) << 7) + (((((y & 8) >> 2) + (x >> 3)) & 3) << 6); -} diff --git a/src/xenia/gpu/texture_resource.h b/src/xenia/gpu/texture_resource.h deleted file mode 100644 index 57dc63422..000000000 --- a/src/xenia/gpu/texture_resource.h +++ /dev/null @@ -1,110 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef XENIA_GPU_TEXTURE_RESOURCE_H_ -#define XENIA_GPU_TEXTURE_RESOURCE_H_ - -#include -#include - -// TODO(benvanik): replace DXGI constants with xenia constants. -#include - - -namespace xe { -namespace gpu { - - -enum TextureDimension { - TEXTURE_DIMENSION_1D = 0, - TEXTURE_DIMENSION_2D = 1, - TEXTURE_DIMENSION_3D = 2, - TEXTURE_DIMENSION_CUBE = 3, -}; - - -class TextureResource : public PagedResource { -public: - struct Info { - TextureDimension dimension; - uint32_t width; - uint32_t height; - uint32_t depth; - uint32_t block_size; - uint32_t texel_pitch; - xenos::XE_GPU_ENDIAN endianness; - bool is_tiled; - bool is_compressed; - uint32_t input_length; - - // TODO(benvanik): replace with our own constants. - DXGI_FORMAT format; - - union { - struct { - uint32_t width; - } size_1d; - struct { - uint32_t logical_width; - uint32_t logical_height; - uint32_t block_width; - uint32_t block_height; - uint32_t input_width; - uint32_t input_height; - uint32_t output_width; - uint32_t output_height; - uint32_t logical_pitch; - uint32_t input_pitch; - } size_2d; - struct { - } size_3d; - struct { - } size_cube; - }; - - static bool Prepare(const xenos::xe_gpu_texture_fetch_t& fetch, - Info& out_info); - - private: - void CalculateTextureSizes1D(const xenos::xe_gpu_texture_fetch_t& fetch); - void CalculateTextureSizes2D(const xenos::xe_gpu_texture_fetch_t& fetch); - }; - - TextureResource(const MemoryRange& memory_range, - const Info& info); - ~TextureResource() override; - - const Info& info() const { return info_; } - - bool Equals(const void* info_ptr, size_t info_length) override { - return info_length == sizeof(Info) && - memcmp(info_ptr, &info_, info_length) == 0; - } - - virtual int Prepare(); - -protected: - virtual int CreateHandle() = 0; - virtual int InvalidateRegion(const MemoryRange& memory_range) = 0; - - void TextureSwap(uint8_t* dest, const uint8_t* src, uint32_t pitch) const; - uint32_t TiledOffset2DOuter(uint32_t y, uint32_t width, - uint32_t log_bpp) const; - uint32_t TiledOffset2DInner(uint32_t x, uint32_t y, uint32_t bpp, - uint32_t base_offset) const; - - Info info_; -}; - - -} // namespace gpu -} // namespace xe - - -#endif // XENIA_GPU_TEXTURE_RESOURCE_H_ diff --git a/src/xenia/gpu/xenos/ucode.h b/src/xenia/gpu/ucode.h similarity index 95% rename from src/xenia/gpu/xenos/ucode.h rename to src/xenia/gpu/ucode.h index 963e78d35..70a378407 100644 --- a/src/xenia/gpu/xenos/ucode.h +++ b/src/xenia/gpu/ucode.h @@ -1,557 +1,559 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef XENIA_GPU_XENOS_UCODE_H_ -#define XENIA_GPU_XENOS_UCODE_H_ - -#include - -namespace xe { -namespace gpu { -namespace xenos { - -#if XE_COMPILER_MSVC -#define XEPACKEDSTRUCT(name, value) \ - __pragma(pack(push, 1)) struct name##_s value __pragma(pack(pop)); \ - typedef struct name##_s name; -#define XEPACKEDSTRUCTANONYMOUS(value) \ - __pragma(pack(push, 1)) struct value __pragma(pack(pop)); -#define XEPACKEDUNION(name, value) \ - __pragma(pack(push, 1)) union name##_s value __pragma(pack(pop)); \ - typedef union name##_s name; -#else -#define XEPACKEDSTRUCT(name, value) struct __attribute__((packed)) name -#define XEPACKEDSTRUCTANONYMOUS(value) struct __attribute__((packed)) -#define XEPACKEDUNION(name, value) union __attribute__((packed)) name -#endif // MSVC - -// This code comes from the freedreno project: -// https://github.com/freedreno/freedreno/blob/master/includes/instr-a2xx.h -/* - * Copyright (c) 2012 Rob Clark - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -enum a2xx_sq_surfaceformat { - FMT_1_REVERSE = 0, - FMT_1 = 1, - FMT_8 = 2, - FMT_1_5_5_5 = 3, - FMT_5_6_5 = 4, - FMT_6_5_5 = 5, - FMT_8_8_8_8 = 6, - FMT_2_10_10_10 = 7, - FMT_8_A = 8, - FMT_8_B = 9, - FMT_8_8 = 10, - FMT_Cr_Y1_Cb_Y0 = 11, - FMT_Y1_Cr_Y0_Cb = 12, - FMT_5_5_5_1 = 13, - FMT_8_8_8_8_A = 14, - FMT_4_4_4_4 = 15, - FMT_10_11_11 = 16, - FMT_11_11_10 = 17, - FMT_DXT1 = 18, - FMT_DXT2_3 = 19, - FMT_DXT4_5 = 20, - FMT_24_8 = 22, - FMT_24_8_FLOAT = 23, - FMT_16 = 24, - FMT_16_16 = 25, - FMT_16_16_16_16 = 26, - FMT_16_EXPAND = 27, - FMT_16_16_EXPAND = 28, - FMT_16_16_16_16_EXPAND = 29, - FMT_16_FLOAT = 30, - FMT_16_16_FLOAT = 31, - FMT_16_16_16_16_FLOAT = 32, - FMT_32 = 33, - FMT_32_32 = 34, - FMT_32_32_32_32 = 35, - FMT_32_FLOAT = 36, - FMT_32_32_FLOAT = 37, - FMT_32_32_32_32_FLOAT = 38, - FMT_32_AS_8 = 39, - FMT_32_AS_8_8 = 40, - FMT_16_MPEG = 41, - FMT_16_16_MPEG = 42, - FMT_8_INTERLACED = 43, - FMT_32_AS_8_INTERLACED = 44, - FMT_32_AS_8_8_INTERLACED = 45, - FMT_16_INTERLACED = 46, - FMT_16_MPEG_INTERLACED = 47, - FMT_16_16_MPEG_INTERLACED = 48, - FMT_DXN = 49, - FMT_8_8_8_8_AS_16_16_16_16 = 50, - FMT_DXT1_AS_16_16_16_16 = 51, - FMT_DXT2_3_AS_16_16_16_16 = 52, - FMT_DXT4_5_AS_16_16_16_16 = 53, - FMT_2_10_10_10_AS_16_16_16_16 = 54, - FMT_10_11_11_AS_16_16_16_16 = 55, - FMT_11_11_10_AS_16_16_16_16 = 56, - FMT_32_32_32_FLOAT = 57, - FMT_DXT3A = 58, - FMT_DXT5A = 59, - FMT_CTX1 = 60, - FMT_DXT3A_AS_1_1_1_1 = 61, -}; - -/* - * ALU instructions: - */ - -typedef enum { - ADDs = 0, - ADD_PREVs = 1, - MULs = 2, - MUL_PREVs = 3, - MUL_PREV2s = 4, - MAXs = 5, - MINs = 6, - SETEs = 7, - SETGTs = 8, - SETGTEs = 9, - SETNEs = 10, - FRACs = 11, - TRUNCs = 12, - FLOORs = 13, - EXP_IEEE = 14, - LOG_CLAMP = 15, - LOG_IEEE = 16, - RECIP_CLAMP = 17, - RECIP_FF = 18, - RECIP_IEEE = 19, - RECIPSQ_CLAMP = 20, - RECIPSQ_FF = 21, - RECIPSQ_IEEE = 22, - MOVAs = 23, - MOVA_FLOORs = 24, - SUBs = 25, - SUB_PREVs = 26, - PRED_SETEs = 27, - PRED_SETNEs = 28, - PRED_SETGTs = 29, - PRED_SETGTEs = 30, - PRED_SET_INVs = 31, - PRED_SET_POPs = 32, - PRED_SET_CLRs = 33, - PRED_SET_RESTOREs = 34, - KILLEs = 35, - KILLGTs = 36, - KILLGTEs = 37, - KILLNEs = 38, - KILLONEs = 39, - SQRT_IEEE = 40, - MUL_CONST_0 = 42, - MUL_CONST_1 = 43, - ADD_CONST_0 = 44, - ADD_CONST_1 = 45, - SUB_CONST_0 = 46, - SUB_CONST_1 = 47, - SIN = 48, - COS = 49, - RETAIN_PREV = 50, -} instr_scalar_opc_t; - -typedef enum { - ADDv = 0, - MULv = 1, - MAXv = 2, - MINv = 3, - SETEv = 4, - SETGTv = 5, - SETGTEv = 6, - SETNEv = 7, - FRACv = 8, - TRUNCv = 9, - FLOORv = 10, - MULADDv = 11, - CNDEv = 12, - CNDGTEv = 13, - CNDGTv = 14, - DOT4v = 15, - DOT3v = 16, - DOT2ADDv = 17, - CUBEv = 18, - MAX4v = 19, - PRED_SETE_PUSHv = 20, - PRED_SETNE_PUSHv = 21, - PRED_SETGT_PUSHv = 22, - PRED_SETGTE_PUSHv = 23, - KILLEv = 24, - KILLGTv = 25, - KILLGTEv = 26, - KILLNEv = 27, - DSTv = 28, - MOVAv = 29, -} instr_vector_opc_t; - -XEPACKEDSTRUCT(instr_alu_t, { - /* dword0: */ - XEPACKEDSTRUCTANONYMOUS({ - uint32_t vector_dest : 6; - uint32_t vector_dest_rel : 1; - uint32_t abs_constants : 1; - uint32_t scalar_dest : 6; - uint32_t scalar_dest_rel : 1; - uint32_t export_data : 1; - uint32_t vector_write_mask : 4; - uint32_t scalar_write_mask : 4; - uint32_t vector_clamp : 1; - uint32_t scalar_clamp : 1; - uint32_t scalar_opc : 6; // instr_scalar_opc_t - }); - /* dword1: */ - XEPACKEDSTRUCTANONYMOUS({ - uint32_t src3_swiz : 8; - uint32_t src2_swiz : 8; - uint32_t src1_swiz : 8; - uint32_t src3_reg_negate : 1; - uint32_t src2_reg_negate : 1; - uint32_t src1_reg_negate : 1; - uint32_t pred_select : 2; - uint32_t relative_addr : 1; - uint32_t const_1_rel_abs : 1; - uint32_t const_0_rel_abs : 1; - }); - /* dword2: */ - XEPACKEDSTRUCTANONYMOUS({ - uint32_t src3_reg : 8; - uint32_t src2_reg : 8; - uint32_t src1_reg : 8; - uint32_t vector_opc : 5; // instr_vector_opc_t - uint32_t src3_sel : 1; - uint32_t src2_sel : 1; - uint32_t src1_sel : 1; - }); -}); - -inline uint32_t get_alu_scalar_dest(const instr_alu_t& alu) { - return alu.vector_write_mask ? alu.scalar_dest : alu.vector_dest; -} - -/* - * CF instructions: - */ - -typedef enum { - NOP = 0, - EXEC = 1, - EXEC_END = 2, - COND_EXEC = 3, - COND_EXEC_END = 4, - COND_PRED_EXEC = 5, - COND_PRED_EXEC_END = 6, - LOOP_START = 7, - LOOP_END = 8, - COND_CALL = 9, - RETURN = 10, - COND_JMP = 11, - ALLOC = 12, - COND_EXEC_PRED_CLEAN = 13, - COND_EXEC_PRED_CLEAN_END = 14, - MARK_VS_FETCH_DONE = 15, -} instr_cf_opc_t; - -typedef enum { - RELATIVE_ADDR = 0, - ABSOLUTE_ADDR = 1, -} instr_addr_mode_t; - -typedef enum { - SQ_NO_ALLOC = 0, - SQ_POSITION = 1, - SQ_PARAMETER_PIXEL = 2, - SQ_MEMORY = 3, -} instr_alloc_type_t; - -XEPACKEDSTRUCT(instr_cf_exec_t, { - XEPACKEDSTRUCTANONYMOUS({ - uint32_t address : 12; - uint32_t count : 3; - uint32_t yeild : 1; - uint32_t serialize : 12; - uint32_t vc_hi : 4; - }); - XEPACKEDSTRUCTANONYMOUS({ - uint32_t vc_lo : 2; /* vertex cache? */ - uint32_t bool_addr : 8; - uint32_t condition : 1; - uint32_t address_mode : 1; // instr_addr_mode_t - uint32_t opc : 4; // instr_cf_opc_t - }); - bool is_cond_exec() const { - return (this->opc == COND_EXEC) || (this->opc == COND_EXEC_END) || - (this->opc == COND_PRED_EXEC) || (this->opc == COND_PRED_EXEC_END) || - (this->opc == COND_EXEC_PRED_CLEAN) || - (this->opc == COND_EXEC_PRED_CLEAN_END); - } -}); - -XEPACKEDSTRUCT(instr_cf_loop_t, { - XEPACKEDSTRUCTANONYMOUS({ - uint32_t address : 13; - uint32_t repeat : 1; - uint32_t reserved0 : 2; - uint32_t loop_id : 5; - uint32_t pred_break : 1; - uint32_t reserved1_hi : 10; - }); - XEPACKEDSTRUCTANONYMOUS({ - uint32_t reserved1_lo : 10; - uint32_t condition : 1; - uint32_t address_mode : 1; // instr_addr_mode_t - uint32_t opc : 4; // instr_cf_opc_t - }); -}); - -XEPACKEDSTRUCT(instr_cf_jmp_call_t, { - XEPACKEDSTRUCTANONYMOUS({ - uint32_t address : 13; - uint32_t force_call : 1; - uint32_t predicated_jmp : 1; - uint32_t reserved1_hi : 17; - }); - XEPACKEDSTRUCTANONYMOUS({ - uint32_t reserved1_lo : 1; - uint32_t direction : 1; - uint32_t bool_addr : 8; - uint32_t condition : 1; - uint32_t address_mode : 1; // instr_addr_mode_t - uint32_t opc : 4; // instr_cf_opc_t - }); -}); - -XEPACKEDSTRUCT(instr_cf_alloc_t, { - XEPACKEDSTRUCTANONYMOUS({ - uint32_t size : 3; - uint32_t reserved0_hi : 29; - }); - XEPACKEDSTRUCTANONYMOUS({ - uint32_t reserved0_lo : 8; - uint32_t no_serial : 1; - uint32_t buffer_select : 2; // instr_alloc_type_t - uint32_t alloc_mode : 1; - uint32_t opc : 4; // instr_cf_opc_t - }); -}); - -XEPACKEDUNION(instr_cf_t, { - instr_cf_exec_t exec; - instr_cf_loop_t loop; - instr_cf_jmp_call_t jmp_call; - instr_cf_alloc_t alloc; - XEPACKEDSTRUCTANONYMOUS({ - uint32_t: - 32; - uint32_t: - 12; - uint32_t opc : 4; // instr_cf_opc_t - }); - XEPACKEDSTRUCTANONYMOUS({ - uint32_t dword_0; - uint32_t dword_1; - }); - - bool is_exec() const { - return (this->opc == EXEC) || (this->opc == EXEC_END) || - (this->opc == COND_EXEC) || (this->opc == COND_EXEC_END) || - (this->opc == COND_PRED_EXEC) || (this->opc == COND_PRED_EXEC_END) || - (this->opc == COND_EXEC_PRED_CLEAN) || - (this->opc == COND_EXEC_PRED_CLEAN_END); - } - bool is_cond_exec() const { - return (this->opc == COND_EXEC) || (this->opc == COND_EXEC_END) || - (this->opc == COND_PRED_EXEC) || (this->opc == COND_PRED_EXEC_END) || - (this->opc == COND_EXEC_PRED_CLEAN) || - (this->opc == COND_EXEC_PRED_CLEAN_END); - } -}); - -/* - * FETCH instructions: - */ - -typedef enum { - VTX_FETCH = 0, - TEX_FETCH = 1, - TEX_GET_BORDER_COLOR_FRAC = 16, - TEX_GET_COMP_TEX_LOD = 17, - TEX_GET_GRADIENTS = 18, - TEX_GET_WEIGHTS = 19, - TEX_SET_TEX_LOD = 24, - TEX_SET_GRADIENTS_H = 25, - TEX_SET_GRADIENTS_V = 26, - TEX_RESERVED_4 = 27, -} instr_fetch_opc_t; - -typedef enum { - TEX_FILTER_POINT = 0, - TEX_FILTER_LINEAR = 1, - TEX_FILTER_BASEMAP = 2, /* only applicable for mip-filter */ - TEX_FILTER_USE_FETCH_CONST = 3, -} instr_tex_filter_t; - -typedef enum { - ANISO_FILTER_DISABLED = 0, - ANISO_FILTER_MAX_1_1 = 1, - ANISO_FILTER_MAX_2_1 = 2, - ANISO_FILTER_MAX_4_1 = 3, - ANISO_FILTER_MAX_8_1 = 4, - ANISO_FILTER_MAX_16_1 = 5, - ANISO_FILTER_USE_FETCH_CONST = 7, -} instr_aniso_filter_t; - -typedef enum { - ARBITRARY_FILTER_2X4_SYM = 0, - ARBITRARY_FILTER_2X4_ASYM = 1, - ARBITRARY_FILTER_4X2_SYM = 2, - ARBITRARY_FILTER_4X2_ASYM = 3, - ARBITRARY_FILTER_4X4_SYM = 4, - ARBITRARY_FILTER_4X4_ASYM = 5, - ARBITRARY_FILTER_USE_FETCH_CONST = 7, -} instr_arbitrary_filter_t; - -typedef enum { - SAMPLE_CENTROID = 0, - SAMPLE_CENTER = 1, -} instr_sample_loc_t; - -typedef enum { - DIMENSION_1D = 0, - DIMENSION_2D = 1, - DIMENSION_3D = 2, - DIMENSION_CUBE = 3, -} instr_dimension_t; - -typedef enum a2xx_sq_surfaceformat instr_surf_fmt_t; - -XEPACKEDSTRUCT(instr_fetch_tex_t, { - /* dword0: */ - XEPACKEDSTRUCTANONYMOUS({ - uint32_t opc : 5; // instr_fetch_opc_t - uint32_t src_reg : 6; - uint32_t src_reg_am : 1; - uint32_t dst_reg : 6; - uint32_t dst_reg_am : 1; - uint32_t fetch_valid_only : 1; - uint32_t const_idx : 5; - uint32_t tx_coord_denorm : 1; - uint32_t src_swiz : 6; // xyz - }); - /* dword1: */ - XEPACKEDSTRUCTANONYMOUS({ - uint32_t dst_swiz : 12; // xyzw - uint32_t mag_filter : 2; // instr_tex_filter_t - uint32_t min_filter : 2; // instr_tex_filter_t - uint32_t mip_filter : 2; // instr_tex_filter_t - uint32_t aniso_filter : 3; // instr_aniso_filter_t - uint32_t arbitrary_filter : 3; // instr_arbitrary_filter_t - uint32_t vol_mag_filter : 2; // instr_tex_filter_t - uint32_t vol_min_filter : 2; // instr_tex_filter_t - uint32_t use_comp_lod : 1; - uint32_t use_reg_lod : 1; - uint32_t unk : 1; - uint32_t pred_select : 1; - }); - /* dword2: */ - XEPACKEDSTRUCTANONYMOUS({ - uint32_t use_reg_gradients : 1; - uint32_t sample_location : 1; // instr_sample_loc_t - uint32_t lod_bias : 7; - uint32_t unused : 5; - uint32_t dimension : 2; // instr_dimension_t - uint32_t offset_x : 5; - uint32_t offset_y : 5; - uint32_t offset_z : 5; - uint32_t pred_condition : 1; - }); -}); - -XEPACKEDSTRUCT(instr_fetch_vtx_t, { - /* dword0: */ - XEPACKEDSTRUCTANONYMOUS({ - uint32_t opc : 5; // instr_fetch_opc_t - uint32_t src_reg : 6; - uint32_t src_reg_am : 1; - uint32_t dst_reg : 6; - uint32_t dst_reg_am : 1; - uint32_t must_be_one : 1; - uint32_t const_index : 5; - uint32_t const_index_sel : 2; - uint32_t reserved0 : 3; - uint32_t src_swiz : 2; - }); - /* dword1: */ - XEPACKEDSTRUCTANONYMOUS({ - uint32_t dst_swiz : 12; - uint32_t format_comp_all : 1; /* '1' for signed, '0' for unsigned? */ - uint32_t num_format_all : 1; /* '0' for normalized, '1' for unnormalized */ - uint32_t signed_rf_mode_all : 1; - uint32_t reserved1 : 1; - uint32_t format : 6; // instr_surf_fmt_t - uint32_t reserved2 : 1; - uint32_t exp_adjust_all : 7; - uint32_t reserved3 : 1; - uint32_t pred_select : 1; - }); - /* dword2: */ - XEPACKEDSTRUCTANONYMOUS({ - uint32_t stride : 8; - uint32_t offset : 23; - uint32_t pred_condition : 1; - }); -}); - -XEPACKEDUNION(instr_fetch_t, { - instr_fetch_tex_t tex; - instr_fetch_vtx_t vtx; - XEPACKEDSTRUCTANONYMOUS({ - /* dword0: */ - XEPACKEDSTRUCTANONYMOUS({ - uint32_t opc : 5; // instr_fetch_opc_t - uint32_t: - 27; - }); - /* dword1: */ - XEPACKEDSTRUCTANONYMOUS({ - uint32_t: - 32; - }); - /* dword2: */ - XEPACKEDSTRUCTANONYMOUS({ - uint32_t: - 32; - }); - }); -}); - -} // namespace xenos -} // namespace gpu -} // namespace xe - -#endif // XENIA_GPU_XENOS_UCODE_H_ +/** + ****************************************************************************** + * Xenia : Xbox 360 Emulator Research Project * + ****************************************************************************** + * Copyright 2013 Ben Vanik. All rights reserved. * + * Released under the BSD license - see LICENSE in the root for more details. * + ****************************************************************************** + */ + +#ifndef XENIA_GPU_UCODE_H_ +#define XENIA_GPU_UCODE_H_ + +#include + +namespace xe { +namespace gpu { + +namespace ucode { + +#if XE_COMPILER_MSVC +#define XEPACKEDSTRUCT(name, value) \ + __pragma(pack(push, 1)) struct name##_s value __pragma(pack(pop)); \ + typedef struct name##_s name; +#define XEPACKEDSTRUCTANONYMOUS(value) \ + __pragma(pack(push, 1)) struct value __pragma(pack(pop)); +#define XEPACKEDUNION(name, value) \ + __pragma(pack(push, 1)) union name##_s value __pragma(pack(pop)); \ + typedef union name##_s name; +#else +#define XEPACKEDSTRUCT(name, value) struct __attribute__((packed)) name +#define XEPACKEDSTRUCTANONYMOUS(value) struct __attribute__((packed)) +#define XEPACKEDUNION(name, value) union __attribute__((packed)) name +#endif // MSVC + +// This code comes from the freedreno project: +// https://github.com/freedreno/freedreno/blob/master/includes/instr-a2xx.h +/* + * Copyright (c) 2012 Rob Clark + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +enum a2xx_sq_surfaceformat { + FMT_1_REVERSE = 0, + FMT_1 = 1, + FMT_8 = 2, + FMT_1_5_5_5 = 3, + FMT_5_6_5 = 4, + FMT_6_5_5 = 5, + FMT_8_8_8_8 = 6, + FMT_2_10_10_10 = 7, + FMT_8_A = 8, + FMT_8_B = 9, + FMT_8_8 = 10, + FMT_Cr_Y1_Cb_Y0 = 11, + FMT_Y1_Cr_Y0_Cb = 12, + FMT_5_5_5_1 = 13, + FMT_8_8_8_8_A = 14, + FMT_4_4_4_4 = 15, + FMT_10_11_11 = 16, + FMT_11_11_10 = 17, + FMT_DXT1 = 18, + FMT_DXT2_3 = 19, + FMT_DXT4_5 = 20, + FMT_24_8 = 22, + FMT_24_8_FLOAT = 23, + FMT_16 = 24, + FMT_16_16 = 25, + FMT_16_16_16_16 = 26, + FMT_16_EXPAND = 27, + FMT_16_16_EXPAND = 28, + FMT_16_16_16_16_EXPAND = 29, + FMT_16_FLOAT = 30, + FMT_16_16_FLOAT = 31, + FMT_16_16_16_16_FLOAT = 32, + FMT_32 = 33, + FMT_32_32 = 34, + FMT_32_32_32_32 = 35, + FMT_32_FLOAT = 36, + FMT_32_32_FLOAT = 37, + FMT_32_32_32_32_FLOAT = 38, + FMT_32_AS_8 = 39, + FMT_32_AS_8_8 = 40, + FMT_16_MPEG = 41, + FMT_16_16_MPEG = 42, + FMT_8_INTERLACED = 43, + FMT_32_AS_8_INTERLACED = 44, + FMT_32_AS_8_8_INTERLACED = 45, + FMT_16_INTERLACED = 46, + FMT_16_MPEG_INTERLACED = 47, + FMT_16_16_MPEG_INTERLACED = 48, + FMT_DXN = 49, + FMT_8_8_8_8_AS_16_16_16_16 = 50, + FMT_DXT1_AS_16_16_16_16 = 51, + FMT_DXT2_3_AS_16_16_16_16 = 52, + FMT_DXT4_5_AS_16_16_16_16 = 53, + FMT_2_10_10_10_AS_16_16_16_16 = 54, + FMT_10_11_11_AS_16_16_16_16 = 55, + FMT_11_11_10_AS_16_16_16_16 = 56, + FMT_32_32_32_FLOAT = 57, + FMT_DXT3A = 58, + FMT_DXT5A = 59, + FMT_CTX1 = 60, + FMT_DXT3A_AS_1_1_1_1 = 61, +}; + +/* + * ALU instructions: + */ + +typedef enum { + ADDs = 0, + ADD_PREVs = 1, + MULs = 2, + MUL_PREVs = 3, + MUL_PREV2s = 4, + MAXs = 5, + MINs = 6, + SETEs = 7, + SETGTs = 8, + SETGTEs = 9, + SETNEs = 10, + FRACs = 11, + TRUNCs = 12, + FLOORs = 13, + EXP_IEEE = 14, + LOG_CLAMP = 15, + LOG_IEEE = 16, + RECIP_CLAMP = 17, + RECIP_FF = 18, + RECIP_IEEE = 19, + RECIPSQ_CLAMP = 20, + RECIPSQ_FF = 21, + RECIPSQ_IEEE = 22, + MOVAs = 23, + MOVA_FLOORs = 24, + SUBs = 25, + SUB_PREVs = 26, + PRED_SETEs = 27, + PRED_SETNEs = 28, + PRED_SETGTs = 29, + PRED_SETGTEs = 30, + PRED_SET_INVs = 31, + PRED_SET_POPs = 32, + PRED_SET_CLRs = 33, + PRED_SET_RESTOREs = 34, + KILLEs = 35, + KILLGTs = 36, + KILLGTEs = 37, + KILLNEs = 38, + KILLONEs = 39, + SQRT_IEEE = 40, + MUL_CONST_0 = 42, + MUL_CONST_1 = 43, + ADD_CONST_0 = 44, + ADD_CONST_1 = 45, + SUB_CONST_0 = 46, + SUB_CONST_1 = 47, + SIN = 48, + COS = 49, + RETAIN_PREV = 50, +} instr_scalar_opc_t; + +typedef enum { + ADDv = 0, + MULv = 1, + MAXv = 2, + MINv = 3, + SETEv = 4, + SETGTv = 5, + SETGTEv = 6, + SETNEv = 7, + FRACv = 8, + TRUNCv = 9, + FLOORv = 10, + MULADDv = 11, + CNDEv = 12, + CNDGTEv = 13, + CNDGTv = 14, + DOT4v = 15, + DOT3v = 16, + DOT2ADDv = 17, + CUBEv = 18, + MAX4v = 19, + PRED_SETE_PUSHv = 20, + PRED_SETNE_PUSHv = 21, + PRED_SETGT_PUSHv = 22, + PRED_SETGTE_PUSHv = 23, + KILLEv = 24, + KILLGTv = 25, + KILLGTEv = 26, + KILLNEv = 27, + DSTv = 28, + MOVAv = 29, +} instr_vector_opc_t; + +XEPACKEDSTRUCT(instr_alu_t, { + /* dword0: */ + XEPACKEDSTRUCTANONYMOUS({ + uint32_t vector_dest : 6; + uint32_t vector_dest_rel : 1; + uint32_t abs_constants : 1; + uint32_t scalar_dest : 6; + uint32_t scalar_dest_rel : 1; + uint32_t export_data : 1; + uint32_t vector_write_mask : 4; + uint32_t scalar_write_mask : 4; + uint32_t vector_clamp : 1; + uint32_t scalar_clamp : 1; + uint32_t scalar_opc : 6; // instr_scalar_opc_t + }); + /* dword1: */ + XEPACKEDSTRUCTANONYMOUS({ + uint32_t src3_swiz : 8; + uint32_t src2_swiz : 8; + uint32_t src1_swiz : 8; + uint32_t src3_reg_negate : 1; + uint32_t src2_reg_negate : 1; + uint32_t src1_reg_negate : 1; + uint32_t pred_select : 2; + uint32_t relative_addr : 1; + uint32_t const_1_rel_abs : 1; + uint32_t const_0_rel_abs : 1; + }); + /* dword2: */ + XEPACKEDSTRUCTANONYMOUS({ + uint32_t src3_reg : 8; + uint32_t src2_reg : 8; + uint32_t src1_reg : 8; + uint32_t vector_opc : 5; // instr_vector_opc_t + uint32_t src3_sel : 1; + uint32_t src2_sel : 1; + uint32_t src1_sel : 1; + }); +}); + +inline uint32_t get_alu_scalar_dest(const instr_alu_t& alu) { + return alu.vector_write_mask ? alu.scalar_dest : alu.vector_dest; +} + +/* + * CF instructions: + */ + +typedef enum { + NOP = 0, + EXEC = 1, + EXEC_END = 2, + COND_EXEC = 3, + COND_EXEC_END = 4, + COND_PRED_EXEC = 5, + COND_PRED_EXEC_END = 6, + LOOP_START = 7, + LOOP_END = 8, + COND_CALL = 9, + RETURN = 10, + COND_JMP = 11, + ALLOC = 12, + COND_EXEC_PRED_CLEAN = 13, + COND_EXEC_PRED_CLEAN_END = 14, + MARK_VS_FETCH_DONE = 15, +} instr_cf_opc_t; + +typedef enum { + RELATIVE_ADDR = 0, + ABSOLUTE_ADDR = 1, +} instr_addr_mode_t; + +typedef enum { + SQ_NO_ALLOC = 0, + SQ_POSITION = 1, + SQ_PARAMETER_PIXEL = 2, + SQ_MEMORY = 3, +} instr_alloc_type_t; + +XEPACKEDSTRUCT(instr_cf_exec_t, { + XEPACKEDSTRUCTANONYMOUS({ + uint32_t address : 12; + uint32_t count : 3; + uint32_t yeild : 1; + uint32_t serialize : 12; + uint32_t vc_hi : 4; + }); + XEPACKEDSTRUCTANONYMOUS({ + uint32_t vc_lo : 2; /* vertex cache? */ + uint32_t bool_addr : 8; + uint32_t condition : 1; + uint32_t address_mode : 1; // instr_addr_mode_t + uint32_t opc : 4; // instr_cf_opc_t + }); + bool is_cond_exec() const { + return (this->opc == COND_EXEC) || (this->opc == COND_EXEC_END) || + (this->opc == COND_PRED_EXEC) || (this->opc == COND_PRED_EXEC_END) || + (this->opc == COND_EXEC_PRED_CLEAN) || + (this->opc == COND_EXEC_PRED_CLEAN_END); + } +}); + +XEPACKEDSTRUCT(instr_cf_loop_t, { + XEPACKEDSTRUCTANONYMOUS({ + uint32_t address : 13; + uint32_t repeat : 1; + uint32_t reserved0 : 2; + uint32_t loop_id : 5; + uint32_t pred_break : 1; + uint32_t reserved1_hi : 10; + }); + XEPACKEDSTRUCTANONYMOUS({ + uint32_t reserved1_lo : 10; + uint32_t condition : 1; + uint32_t address_mode : 1; // instr_addr_mode_t + uint32_t opc : 4; // instr_cf_opc_t + }); +}); + +XEPACKEDSTRUCT(instr_cf_jmp_call_t, { + XEPACKEDSTRUCTANONYMOUS({ + uint32_t address : 13; + uint32_t force_call : 1; + uint32_t predicated_jmp : 1; + uint32_t reserved1_hi : 17; + }); + XEPACKEDSTRUCTANONYMOUS({ + uint32_t reserved1_lo : 1; + uint32_t direction : 1; + uint32_t bool_addr : 8; + uint32_t condition : 1; + uint32_t address_mode : 1; // instr_addr_mode_t + uint32_t opc : 4; // instr_cf_opc_t + }); +}); + +XEPACKEDSTRUCT(instr_cf_alloc_t, { + XEPACKEDSTRUCTANONYMOUS({ + uint32_t size : 3; + uint32_t reserved0_hi : 29; + }); + XEPACKEDSTRUCTANONYMOUS({ + uint32_t reserved0_lo : 8; + uint32_t no_serial : 1; + uint32_t buffer_select : 2; // instr_alloc_type_t + uint32_t alloc_mode : 1; + uint32_t opc : 4; // instr_cf_opc_t + }); +}); + +XEPACKEDUNION(instr_cf_t, { + instr_cf_exec_t exec; + instr_cf_loop_t loop; + instr_cf_jmp_call_t jmp_call; + instr_cf_alloc_t alloc; + XEPACKEDSTRUCTANONYMOUS({ + uint32_t: + 32; + uint32_t: + 12; + uint32_t opc : 4; // instr_cf_opc_t + }); + XEPACKEDSTRUCTANONYMOUS({ + uint32_t dword_0; + uint32_t dword_1; + }); + + bool is_exec() const { + return (this->opc == EXEC) || (this->opc == EXEC_END) || + (this->opc == COND_EXEC) || (this->opc == COND_EXEC_END) || + (this->opc == COND_PRED_EXEC) || (this->opc == COND_PRED_EXEC_END) || + (this->opc == COND_EXEC_PRED_CLEAN) || + (this->opc == COND_EXEC_PRED_CLEAN_END); + } + bool is_cond_exec() const { + return (this->opc == COND_EXEC) || (this->opc == COND_EXEC_END) || + (this->opc == COND_PRED_EXEC) || (this->opc == COND_PRED_EXEC_END) || + (this->opc == COND_EXEC_PRED_CLEAN) || + (this->opc == COND_EXEC_PRED_CLEAN_END); + } +}); + +/* + * FETCH instructions: + */ + +typedef enum { + VTX_FETCH = 0, + TEX_FETCH = 1, + TEX_GET_BORDER_COLOR_FRAC = 16, + TEX_GET_COMP_TEX_LOD = 17, + TEX_GET_GRADIENTS = 18, + TEX_GET_WEIGHTS = 19, + TEX_SET_TEX_LOD = 24, + TEX_SET_GRADIENTS_H = 25, + TEX_SET_GRADIENTS_V = 26, + TEX_RESERVED_4 = 27, +} instr_fetch_opc_t; + +typedef enum { + TEX_FILTER_POINT = 0, + TEX_FILTER_LINEAR = 1, + TEX_FILTER_BASEMAP = 2, /* only applicable for mip-filter */ + TEX_FILTER_USE_FETCH_CONST = 3, +} instr_tex_filter_t; + +typedef enum { + ANISO_FILTER_DISABLED = 0, + ANISO_FILTER_MAX_1_1 = 1, + ANISO_FILTER_MAX_2_1 = 2, + ANISO_FILTER_MAX_4_1 = 3, + ANISO_FILTER_MAX_8_1 = 4, + ANISO_FILTER_MAX_16_1 = 5, + ANISO_FILTER_USE_FETCH_CONST = 7, +} instr_aniso_filter_t; + +typedef enum { + ARBITRARY_FILTER_2X4_SYM = 0, + ARBITRARY_FILTER_2X4_ASYM = 1, + ARBITRARY_FILTER_4X2_SYM = 2, + ARBITRARY_FILTER_4X2_ASYM = 3, + ARBITRARY_FILTER_4X4_SYM = 4, + ARBITRARY_FILTER_4X4_ASYM = 5, + ARBITRARY_FILTER_USE_FETCH_CONST = 7, +} instr_arbitrary_filter_t; + +typedef enum { + SAMPLE_CENTROID = 0, + SAMPLE_CENTER = 1, +} instr_sample_loc_t; + +typedef enum { + DIMENSION_1D = 0, + DIMENSION_2D = 1, + DIMENSION_3D = 2, + DIMENSION_CUBE = 3, +} instr_dimension_t; + +typedef enum a2xx_sq_surfaceformat instr_surf_fmt_t; + +XEPACKEDSTRUCT(instr_fetch_tex_t, { + /* dword0: */ + XEPACKEDSTRUCTANONYMOUS({ + uint32_t opc : 5; // instr_fetch_opc_t + uint32_t src_reg : 6; + uint32_t src_reg_am : 1; + uint32_t dst_reg : 6; + uint32_t dst_reg_am : 1; + uint32_t fetch_valid_only : 1; + uint32_t const_idx : 5; + uint32_t tx_coord_denorm : 1; + uint32_t src_swiz : 6; // xyz + }); + /* dword1: */ + XEPACKEDSTRUCTANONYMOUS({ + uint32_t dst_swiz : 12; // xyzw + uint32_t mag_filter : 2; // instr_tex_filter_t + uint32_t min_filter : 2; // instr_tex_filter_t + uint32_t mip_filter : 2; // instr_tex_filter_t + uint32_t aniso_filter : 3; // instr_aniso_filter_t + uint32_t arbitrary_filter : 3; // instr_arbitrary_filter_t + uint32_t vol_mag_filter : 2; // instr_tex_filter_t + uint32_t vol_min_filter : 2; // instr_tex_filter_t + uint32_t use_comp_lod : 1; + uint32_t use_reg_lod : 1; + uint32_t unk : 1; + uint32_t pred_select : 1; + }); + /* dword2: */ + XEPACKEDSTRUCTANONYMOUS({ + uint32_t use_reg_gradients : 1; + uint32_t sample_location : 1; // instr_sample_loc_t + uint32_t lod_bias : 7; + uint32_t unused : 5; + uint32_t dimension : 2; // instr_dimension_t + uint32_t offset_x : 5; + uint32_t offset_y : 5; + uint32_t offset_z : 5; + uint32_t pred_condition : 1; + }); +}); + +XEPACKEDSTRUCT(instr_fetch_vtx_t, { + /* dword0: */ + XEPACKEDSTRUCTANONYMOUS({ + uint32_t opc : 5; // instr_fetch_opc_t + uint32_t src_reg : 6; + uint32_t src_reg_am : 1; + uint32_t dst_reg : 6; + uint32_t dst_reg_am : 1; + uint32_t must_be_one : 1; + uint32_t const_index : 5; + uint32_t const_index_sel : 2; + uint32_t reserved0 : 3; + uint32_t src_swiz : 2; + }); + /* dword1: */ + XEPACKEDSTRUCTANONYMOUS({ + uint32_t dst_swiz : 12; + uint32_t format_comp_all : 1; /* '1' for signed, '0' for unsigned? */ + uint32_t num_format_all : 1; /* '0' for normalized, '1' for unnormalized */ + uint32_t signed_rf_mode_all : 1; + uint32_t reserved1 : 1; + uint32_t format : 6; // instr_surf_fmt_t + uint32_t reserved2 : 1; + uint32_t exp_adjust_all : 7; + uint32_t reserved3 : 1; + uint32_t pred_select : 1; + }); + /* dword2: */ + XEPACKEDSTRUCTANONYMOUS({ + uint32_t stride : 8; + uint32_t offset : 23; + uint32_t pred_condition : 1; + }); +}); + +XEPACKEDUNION(instr_fetch_t, { + instr_fetch_tex_t tex; + instr_fetch_vtx_t vtx; + XEPACKEDSTRUCTANONYMOUS({ + /* dword0: */ + XEPACKEDSTRUCTANONYMOUS({ + uint32_t opc : 5; // instr_fetch_opc_t + uint32_t: + 27; + }); + /* dword1: */ + XEPACKEDSTRUCTANONYMOUS({ + uint32_t: + 32; + }); + /* dword2: */ + XEPACKEDSTRUCTANONYMOUS({ + uint32_t: + 32; + }); + }); +}); + +} // namespace ucode + +} // namespace gpu +} // namespace xe + +#endif // XENIA_GPU_UCODE_H_ diff --git a/src/xenia/gpu/xenos/ucode_disassembler.cc b/src/xenia/gpu/ucode_disassembler.cc similarity index 58% rename from src/xenia/gpu/xenos/ucode_disassembler.cc rename to src/xenia/gpu/ucode_disassembler.cc index 01bd23093..d0b4e751b 100644 --- a/src/xenia/gpu/xenos/ucode_disassembler.cc +++ b/src/xenia/gpu/ucode_disassembler.cc @@ -1,771 +1,748 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -/* - * Copyright (c) 2012 Rob Clark - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include - -#include -#include -#include -#include - - -using namespace xe; -using namespace xe::gpu; -using namespace xe::gpu::xenos; - - -namespace { - -const int OUTPUT_CAPACITY = 32 * 1024; -struct Output { - char buffer[OUTPUT_CAPACITY]; - size_t capacity; - size_t offset; - Output() : - capacity(OUTPUT_CAPACITY), - offset(0) { - buffer[0] = 0; - } - void append(const char* format, ...) { - va_list args; - va_start(args, format); - int len = vsnprintf(buffer + offset, capacity - offset, format, args); - va_end(args); - offset += len; - buffer[offset] = 0; - } -}; - -static const char *levels[] = { - "", - "\t", - "\t\t", - "\t\t\t", - "\t\t\t\t", - "\t\t\t\t\t", - "\t\t\t\t\t\t", - "\t\t\t\t\t\t\t", - "\t\t\t\t\t\t\t\t", - "\t\t\t\t\t\t\t\t\t", - "x", - "x", - "x", - "x", - "x", - "x", -}; - -/* - * ALU instructions: - */ - -static const char chan_names[] = { - 'x', 'y', 'z', 'w', - /* these only apply to FETCH dst's: */ - '0', '1', '?', '_', -}; - -void print_srcreg( - Output* output, - uint32_t num, uint32_t type, - uint32_t swiz, uint32_t negate, uint32_t abs_constants, - XE_GPU_SHADER_TYPE shader_type) { - if (negate) { - output->append("-"); - } - if (type) { - if (num & 0x80) { - output->append("abs("); - } - output->append("R%u", num & 0x7F); - if (num & 0x80) { - output->append(")"); - } - } else { - if (abs_constants) { - output->append("|"); - } - num += shader_type == XE_GPU_SHADER_TYPE_PIXEL ? 256 : 0; - output->append("C%u", num); - if (abs_constants) { - output->append("|"); - } - } - if (swiz) { - output->append("."); - for (int i = 0; i < 4; i++) { - output->append("%c", chan_names[(swiz + i) & 0x3]); - swiz >>= 2; - } - } -} - -void print_dstreg( - Output* output, uint32_t num, uint32_t mask, uint32_t dst_exp) { - output->append("%s%u", dst_exp ? "export" : "R", num); - if (mask != 0xf) { - output->append("."); - for (int i = 0; i < 4; i++) { - output->append("%c", (mask & 0x1) ? chan_names[i] : '_'); - mask >>= 1; - } - } -} - -void print_export_comment( - Output* output, uint32_t num, XE_GPU_SHADER_TYPE type) { - const char *name = NULL; - switch (type) { - case XE_GPU_SHADER_TYPE_VERTEX: - switch (num) { - case 62: name = "gl_Position"; break; - case 63: name = "gl_PointSize"; break; - } - break; - case XE_GPU_SHADER_TYPE_PIXEL: - switch (num) { - case 0: name = "gl_FragColor"; break; - } - break; - } - /* if we had a symbol table here, we could look - * up the name of the varying.. - */ - if (name) { - output->append("\t; %s", name); - } -} - -struct { - uint32_t num_srcs; - const char *name; -} vector_instructions[0x20] = { -#define INSTR(opc, num_srcs) { num_srcs, #opc } - INSTR(ADDv, 2), // 0 - INSTR(MULv, 2), // 1 - INSTR(MAXv, 2), // 2 - INSTR(MINv, 2), // 3 - INSTR(SETEv, 2), // 4 - INSTR(SETGTv, 2), // 5 - INSTR(SETGTEv, 2), // 6 - INSTR(SETNEv, 2), // 7 - INSTR(FRACv, 1), // 8 - INSTR(TRUNCv, 1), // 9 - INSTR(FLOORv, 1), // 10 - INSTR(MULADDv, 3), // 111 - INSTR(CNDEv, 3), // 12 - INSTR(CNDGTEv, 3), // 13 - INSTR(CNDGTv, 3), // 14 - INSTR(DOT4v, 2), // 15 - INSTR(DOT3v, 2), // 16 - INSTR(DOT2ADDv, 3), // 17 -- ??? - INSTR(CUBEv, 2), // 18 - INSTR(MAX4v, 1), // 19 - INSTR(PRED_SETE_PUSHv, 2), // 20 - INSTR(PRED_SETNE_PUSHv, 2), // 21 - INSTR(PRED_SETGT_PUSHv, 2), // 22 - INSTR(PRED_SETGTE_PUSHv, 2), // 23 - INSTR(KILLEv, 2), // 24 - INSTR(KILLGTv, 2), // 25 - INSTR(KILLGTEv, 2), // 26 - INSTR(KILLNEv, 2), // 27 - INSTR(DSTv, 2), // 28 - INSTR(MOVAv, 1), // 29 -}, scalar_instructions[0x40] = { - INSTR(ADDs, 1), // 0 - INSTR(ADD_PREVs, 1), // 1 - INSTR(MULs, 1), // 2 - INSTR(MUL_PREVs, 1), // 3 - INSTR(MUL_PREV2s, 1), // 4 - INSTR(MAXs, 1), // 5 - INSTR(MINs, 1), // 6 - INSTR(SETEs, 1), // 7 - INSTR(SETGTs, 1), // 8 - INSTR(SETGTEs, 1), // 9 - INSTR(SETNEs, 1), // 10 - INSTR(FRACs, 1), // 11 - INSTR(TRUNCs, 1), // 12 - INSTR(FLOORs, 1), // 13 - INSTR(EXP_IEEE, 1), // 14 - INSTR(LOG_CLAMP, 1), // 15 - INSTR(LOG_IEEE, 1), // 16 - INSTR(RECIP_CLAMP, 1), // 17 - INSTR(RECIP_FF, 1), // 18 - INSTR(RECIP_IEEE, 1), // 19 - INSTR(RECIPSQ_CLAMP, 1), // 20 - INSTR(RECIPSQ_FF, 1), // 21 - INSTR(RECIPSQ_IEEE, 1), // 22 - INSTR(MOVAs, 1), // 23 - INSTR(MOVA_FLOORs, 1), // 24 - INSTR(SUBs, 1), // 25 - INSTR(SUB_PREVs, 1), // 26 - INSTR(PRED_SETEs, 1), // 27 - INSTR(PRED_SETNEs, 1), // 28 - INSTR(PRED_SETGTs, 1), // 29 - INSTR(PRED_SETGTEs, 1), // 30 - INSTR(PRED_SET_INVs, 1), // 31 - INSTR(PRED_SET_POPs, 1), // 32 - INSTR(PRED_SET_CLRs, 1), // 33 - INSTR(PRED_SET_RESTOREs, 1), // 34 - INSTR(KILLEs, 1), // 35 - INSTR(KILLGTs, 1), // 36 - INSTR(KILLGTEs, 1), // 37 - INSTR(KILLNEs, 1), // 38 - INSTR(KILLONEs, 1), // 39 - INSTR(SQRT_IEEE, 1), // 40 - {0, 0}, - INSTR(MUL_CONST_0, 2), // 42 - INSTR(MUL_CONST_1, 2), // 43 - INSTR(ADD_CONST_0, 2), // 44 - INSTR(ADD_CONST_1, 2), // 45 - INSTR(SUB_CONST_0, 2), // 46 - INSTR(SUB_CONST_1, 2), // 47 - INSTR(SIN, 1), // 48 - INSTR(COS, 1), // 49 - INSTR(RETAIN_PREV, 1), // 50 -#undef INSTR -}; - -int disasm_alu( - Output* output, const uint32_t* dwords, uint32_t alu_off, - int level, int sync, XE_GPU_SHADER_TYPE type) { - const instr_alu_t* alu = (const instr_alu_t*)dwords; - - output->append("%s", levels[level]); - output->append("%02x: %08x %08x %08x\t", alu_off, - dwords[0], dwords[1], dwords[2]); - - output->append(" %sALU:\t", sync ? "(S)" : " "); - - if (!alu->scalar_write_mask && !alu->vector_write_mask) { - output->append(" \n"); - } - - if (alu->vector_write_mask) { - output->append("%s", vector_instructions[alu->vector_opc].name); - - if (alu->pred_select & 0x2) { - // seems to work similar to conditional execution in ARM instruction - // set, so let's use a similar syntax for now: - output->append((alu->pred_select & 0x1) ? "EQ" : "NE"); - } - - output->append("\t"); - - print_dstreg(output, - alu->vector_dest, alu->vector_write_mask, alu->export_data); - output->append(" = "); - if (vector_instructions[alu->vector_opc].num_srcs == 3) { - print_srcreg(output, - alu->src3_reg, alu->src3_sel, alu->src3_swiz, - alu->src3_reg_negate, alu->abs_constants, type); - output->append(", "); - } - print_srcreg(output, - alu->src1_reg, alu->src1_sel, alu->src1_swiz, - alu->src1_reg_negate, alu->abs_constants, type); - if (vector_instructions[alu->vector_opc].num_srcs > 1) { - output->append(", "); - print_srcreg(output, - alu->src2_reg, alu->src2_sel, alu->src2_swiz, - alu->src2_reg_negate, alu->abs_constants, type); - } - - if (alu->vector_clamp) { - output->append(" CLAMP"); - } - - if (alu->export_data) { - print_export_comment(output, alu->vector_dest, type); - } - - output->append("\n"); - } - - if (alu->scalar_write_mask || !alu->vector_write_mask) { - // 2nd optional scalar op: - - if (alu->vector_write_mask) { - output->append("%s", levels[level]); - output->append(" \t\t\t\t\t\t \t"); - } - - if (scalar_instructions[alu->scalar_opc].name) { - output->append("%s\t", scalar_instructions[alu->scalar_opc].name); - } else { - output->append("OP(%u)\t", alu->scalar_opc); - } - - print_dstreg(output, - get_alu_scalar_dest(*alu), alu->scalar_write_mask, alu->export_data); - output->append(" = "); - if (scalar_instructions[alu->scalar_opc].num_srcs == 2) { - // MUL/ADD/etc - // Clever, CONST_0 and CONST_1 are just an extra storage bit. - // ADD_CONST_0 dest, [const], [reg] - uint32_t src3_swiz = alu->src3_swiz & ~0x3C; - uint32_t swiz_a = ((src3_swiz >> 6) - 1) & 0x3; - uint32_t swiz_b = (src3_swiz & 0x3); - print_srcreg(output, - alu->src3_reg, 0, 0, - alu->src3_reg_negate, alu->abs_constants, type); - output->append(".%c", chan_names[swiz_a]); - output->append(", "); - uint32_t reg2 = (alu->scalar_opc & 1) | (alu->src3_swiz & 0x3C) | (alu->src3_sel << 1); - print_srcreg(output, - reg2, 1, 0, - alu->src3_reg_negate, alu->abs_constants, type); - output->append(".%c", chan_names[swiz_b]); - } else { - print_srcreg(output, - alu->src3_reg, alu->src3_sel, alu->src3_swiz, - alu->src3_reg_negate, alu->abs_constants, type); - } - if (alu->scalar_clamp) { - output->append(" CLAMP"); - } - if (alu->export_data) { - print_export_comment(output, get_alu_scalar_dest(*alu), type); - } - output->append("\n"); - } - - return 0; -} - -struct { - const char *name; -} fetch_types[0xff] = { -#define TYPE(id) { #id } - TYPE(FMT_1_REVERSE), // 0 - {0}, - TYPE(FMT_8), // 2 - {0}, - {0}, - {0}, - TYPE(FMT_8_8_8_8), // 6 - TYPE(FMT_2_10_10_10), // 7 - {0}, - {0}, - TYPE(FMT_8_8), // 10 - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - TYPE(FMT_16), // 24 - TYPE(FMT_16_16), // 25 - TYPE(FMT_16_16_16_16), // 26 - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - TYPE(FMT_32), // 33 - TYPE(FMT_32_32), // 34 - TYPE(FMT_32_32_32_32), // 35 - TYPE(FMT_32_FLOAT), // 36 - TYPE(FMT_32_32_FLOAT), // 37 - TYPE(FMT_32_32_32_32_FLOAT), // 38 - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - TYPE(FMT_32_32_32_FLOAT), // 57 -#undef TYPE -}; - -void print_fetch_dst(Output* output, uint32_t dst_reg, uint32_t dst_swiz) { - output->append("\tR%u.", dst_reg); - for (int i = 0; i < 4; i++) { - output->append("%c", chan_names[dst_swiz & 0x7]); - dst_swiz >>= 3; - } -} - -void print_fetch_vtx(Output* output, const instr_fetch_t* fetch) { - const instr_fetch_vtx_t* vtx = &fetch->vtx; - - if (vtx->pred_select) { - // seems to work similar to conditional execution in ARM instruction - // set, so let's use a similar syntax for now: - output->append(vtx->pred_condition ? "EQ" : "NE"); - } - - print_fetch_dst(output, vtx->dst_reg, vtx->dst_swiz); - output->append(" = R%u.", vtx->src_reg); - output->append("%c", chan_names[vtx->src_swiz & 0x3]); - if (fetch_types[vtx->format].name) { - output->append(" %s", fetch_types[vtx->format].name); - } else { - output->append(" TYPE(0x%x)", vtx->format); - } - output->append(" %s", vtx->format_comp_all ? "SIGNED" : "UNSIGNED"); - if (!vtx->num_format_all) { - output->append(" NORMALIZED"); - } - output->append(" STRIDE(%u)", vtx->stride); - if (vtx->offset) { - output->append(" OFFSET(%u)", vtx->offset); - } - output->append(" CONST(%u, %u)", vtx->const_index, vtx->const_index_sel); - if (1) { - // XXX - output->append(" src_reg_am=%u", vtx->src_reg_am); - output->append(" dst_reg_am=%u", vtx->dst_reg_am); - output->append(" num_format_all=%u", vtx->num_format_all); - output->append(" signed_rf_mode_all=%u", vtx->signed_rf_mode_all); - output->append(" exp_adjust_all=%u", vtx->exp_adjust_all); - } -} - -void print_fetch_tex(Output* output, const instr_fetch_t* fetch) { - static const char *filter[] = { - "POINT", // TEX_FILTER_POINT - "LINEAR", // TEX_FILTER_LINEAR - "BASEMAP", // TEX_FILTER_BASEMAP - }; - static const char *aniso_filter[] = { - "DISABLED", // ANISO_FILTER_DISABLED - "MAX_1_1", // ANISO_FILTER_MAX_1_1 - "MAX_2_1", // ANISO_FILTER_MAX_2_1 - "MAX_4_1", // ANISO_FILTER_MAX_4_1 - "MAX_8_1", // ANISO_FILTER_MAX_8_1 - "MAX_16_1", // ANISO_FILTER_MAX_16_1 - }; - static const char *arbitrary_filter[] = { - "2x4_SYM", // ARBITRARY_FILTER_2X4_SYM - "2x4_ASYM", // ARBITRARY_FILTER_2X4_ASYM - "4x2_SYM", // ARBITRARY_FILTER_4X2_SYM - "4x2_ASYM", // ARBITRARY_FILTER_4X2_ASYM - "4x4_SYM", // ARBITRARY_FILTER_4X4_SYM - "4x4_ASYM", // ARBITRARY_FILTER_4X4_ASYM - }; - static const char *sample_loc[] = { - "CENTROID", // SAMPLE_CENTROID - "CENTER", // SAMPLE_CENTER - }; - const instr_fetch_tex_t* tex = &fetch->tex; - uint32_t src_swiz = tex->src_swiz; - - if (tex->pred_select) { - // seems to work similar to conditional execution in ARM instruction - // set, so let's use a similar syntax for now: - output->append(tex->pred_condition ? "EQ" : "NE"); - } - - print_fetch_dst(output, tex->dst_reg, tex->dst_swiz); - output->append(" = R%u.", tex->src_reg); - for (int i = 0; i < 3; i++) { - output->append("%c", chan_names[src_swiz & 0x3]); - src_swiz >>= 2; - } - output->append(" CONST(%u)", tex->const_idx); - if (tex->fetch_valid_only) { - output->append(" VALID_ONLY"); - } - if (tex->tx_coord_denorm) { - output->append(" DENORM"); - } - if (tex->mag_filter != TEX_FILTER_USE_FETCH_CONST) { - output->append(" MAG(%s)", filter[tex->mag_filter]); - } - if (tex->min_filter != TEX_FILTER_USE_FETCH_CONST) { - output->append(" MIN(%s)", filter[tex->min_filter]); - } - if (tex->mip_filter != TEX_FILTER_USE_FETCH_CONST) { - output->append(" MIP(%s)", filter[tex->mip_filter]); - } - if (tex->aniso_filter != ANISO_FILTER_USE_FETCH_CONST) { - output->append(" ANISO(%s)", aniso_filter[tex->aniso_filter]); - } - if (tex->arbitrary_filter != ARBITRARY_FILTER_USE_FETCH_CONST) { - output->append(" ARBITRARY(%s)", arbitrary_filter[tex->arbitrary_filter]); - } - if (tex->vol_mag_filter != TEX_FILTER_USE_FETCH_CONST) { - output->append(" VOL_MAG(%s)", filter[tex->vol_mag_filter]); - } - if (tex->vol_min_filter != TEX_FILTER_USE_FETCH_CONST) { - output->append(" VOL_MIN(%s)", filter[tex->vol_min_filter]); - } - if (!tex->use_comp_lod) { - output->append(" LOD(%u)", tex->use_comp_lod); - output->append(" LOD_BIAS(%u)", tex->lod_bias); - } - if (tex->use_reg_lod) { - output->append(" REG_LOD(%u)", tex->use_reg_lod); - } - if (tex->use_reg_gradients) { - output->append(" USE_REG_GRADIENTS"); - } - output->append(" LOCATION(%s)", sample_loc[tex->sample_location]); - if (tex->offset_x || tex->offset_y || tex->offset_z) { - output->append(" OFFSET(%u,%u,%u)", tex->offset_x, tex->offset_y, tex->offset_z); - } -} - -struct { - const char *name; - void (*fxn)(Output* output, const instr_fetch_t* cf); -} fetch_instructions[] = { -#define INSTR(opc, name, fxn) { name, fxn } - INSTR(VTX_FETCH, "VERTEX", print_fetch_vtx), // 0 - INSTR(TEX_FETCH, "SAMPLE", print_fetch_tex), // 1 - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}, - INSTR(TEX_GET_BORDER_COLOR_FRAC, "?", print_fetch_tex), // 16 - INSTR(TEX_GET_COMP_TEX_LOD, "?", print_fetch_tex), // 17 - INSTR(TEX_GET_GRADIENTS, "?", print_fetch_tex), // 18 - INSTR(TEX_GET_WEIGHTS, "?", print_fetch_tex), // 19 - {0, 0}, - {0, 0}, - {0, 0}, - {0, 0}, - INSTR(TEX_SET_TEX_LOD, "SET_TEX_LOD", print_fetch_tex), // 24 - INSTR(TEX_SET_GRADIENTS_H, "?", print_fetch_tex), // 25 - INSTR(TEX_SET_GRADIENTS_V, "?", print_fetch_tex), // 26 - INSTR(TEX_RESERVED_4, "?", print_fetch_tex), // 27 -#undef INSTR -}; - -int disasm_fetch( - Output* output, const uint32_t* dwords, uint32_t alu_off, int level, int sync) { - const instr_fetch_t* fetch = (const instr_fetch_t*)dwords; - - output->append("%s", levels[level]); - output->append("%02x: %08x %08x %08x\t", alu_off, - dwords[0], dwords[1], dwords[2]); - - output->append(" %sFETCH:\t", sync ? "(S)" : " "); - if (fetch_instructions[fetch->opc].fxn) { - output->append("%s", fetch_instructions[fetch->opc].name); - fetch_instructions[fetch->opc].fxn(output, fetch); - } else { - output->append("???"); - } - output->append("\n"); - - return 0; -} - -void print_cf_nop(Output* output, const instr_cf_t* cf) { -} - -void print_cf_exec(Output* output, const instr_cf_t* cf) { - output->append(" ADDR(0x%x) CNT(0x%x)", cf->exec.address, cf->exec.count); - if (cf->exec.yeild) { - output->append(" YIELD"); - } - uint8_t vc = cf->exec.vc_hi | (cf->exec.vc_lo << 2); - if (vc) { - output->append(" VC(0x%x)", vc); - } - if (cf->exec.bool_addr) { - output->append(" BOOL_ADDR(0x%x)", cf->exec.bool_addr); - } - if (cf->exec.address_mode == ABSOLUTE_ADDR) { - output->append(" ABSOLUTE_ADDR"); - } - if (cf->is_cond_exec()) { - output->append(" COND(%d)", cf->exec.condition); - } -} - -void print_cf_loop(Output* output, const instr_cf_t* cf) { - output->append(" ADDR(0x%x) LOOP_ID(%d)", cf->loop.address, cf->loop.loop_id); - if (cf->loop.address_mode == ABSOLUTE_ADDR) { - output->append(" ABSOLUTE_ADDR"); - } -} - -void print_cf_jmp_call(Output* output, const instr_cf_t* cf) { - output->append(" ADDR(0x%x) DIR(%d)", cf->jmp_call.address, cf->jmp_call.direction); - if (cf->jmp_call.force_call) { - output->append(" FORCE_CALL"); - } - if (cf->jmp_call.predicated_jmp) { - output->append(" COND(%d)", cf->jmp_call.condition); - } - if (cf->jmp_call.bool_addr) { - output->append(" BOOL_ADDR(0x%x)", cf->jmp_call.bool_addr); - } - if (cf->jmp_call.address_mode == ABSOLUTE_ADDR) { - output->append(" ABSOLUTE_ADDR"); - } -} - -void print_cf_alloc(Output* output, const instr_cf_t* cf) { - static const char *bufname[] = { - "NO ALLOC", // SQ_NO_ALLOC - "POSITION", // SQ_POSITION - "PARAM/PIXEL", // SQ_PARAMETER_PIXEL - "MEMORY", // SQ_MEMORY - }; - output->append(" %s SIZE(0x%x)", bufname[cf->alloc.buffer_select], cf->alloc.size); - if (cf->alloc.no_serial) { - output->append(" NO_SERIAL"); - } - if (cf->alloc.alloc_mode) { - // ??? - output->append(" ALLOC_MODE"); - } -} - -struct { - const char *name; - void (*fxn)(Output* output, const instr_cf_t* cf); -} cf_instructions[] = { -#define INSTR(opc, fxn) { #opc, fxn } - INSTR(NOP, print_cf_nop), - INSTR(EXEC, print_cf_exec), - INSTR(EXEC_END, print_cf_exec), - INSTR(COND_EXEC, print_cf_exec), - INSTR(COND_EXEC_END, print_cf_exec), - INSTR(COND_PRED_EXEC, print_cf_exec), - INSTR(COND_PRED_EXEC_END, print_cf_exec), - INSTR(LOOP_START, print_cf_loop), - INSTR(LOOP_END, print_cf_loop), - INSTR(COND_CALL, print_cf_jmp_call), - INSTR(RETURN, print_cf_jmp_call), - INSTR(COND_JMP, print_cf_jmp_call), - INSTR(ALLOC, print_cf_alloc), - INSTR(COND_EXEC_PRED_CLEAN, print_cf_exec), - INSTR(COND_EXEC_PRED_CLEAN_END, print_cf_exec), - INSTR(MARK_VS_FETCH_DONE, print_cf_nop), // ?? -#undef INSTR -}; - -static void print_cf(Output* output, const instr_cf_t* cf, int level) { - output->append("%s", levels[level]); - - const uint16_t* words = (uint16_t*)cf; - output->append(" %04x %04x %04x \t", - words[0], words[1], words[2]); - - output->append("%s", cf_instructions[cf->opc].name); - cf_instructions[cf->opc].fxn(output, cf); - output->append("\n"); -} - -/* - * The adreno shader microcode consists of two parts: - * 1) A CF (control-flow) program, at the header of the compiled shader, - * which refers to ALU/FETCH instructions that follow it by address. - * 2) ALU and FETCH instructions - */ -void disasm_exec( - Output* output, const uint32_t* dwords, size_t dword_count, - int level, XE_GPU_SHADER_TYPE type, const instr_cf_t* cf) { - uint32_t sequence = cf->exec.serialize; - for (uint32_t i = 0; i < cf->exec.count; i++) { - uint32_t alu_off = (cf->exec.address + i); - if (sequence & 0x1) { - disasm_fetch(output, dwords + alu_off * 3, - alu_off, level, sequence & 0x2); - } else { - disasm_alu(output, dwords + alu_off * 3, - alu_off, level, sequence & 0x2, type); - } - sequence >>= 2; - } -} - -} // anonymous namespace - - -char* xenos::DisassembleShader( - XE_GPU_SHADER_TYPE type, - const uint32_t* dwords, size_t dword_count) { - Output* output = new Output(); - - instr_cf_t cfa; - instr_cf_t cfb; - for (int idx = 0; idx < dword_count; idx += 3) { - uint32_t dword_0 = dwords[idx + 0]; - uint32_t dword_1 = dwords[idx + 1]; - uint32_t dword_2 = dwords[idx + 2]; - cfa.dword_0 = dword_0; - cfa.dword_1 = dword_1 & 0xFFFF; - cfb.dword_0 = (dword_1 >> 16) | (dword_2 << 16); - cfb.dword_1 = dword_2 >> 16; - print_cf(output, &cfa, 0); - if (cfa.is_exec()) { - disasm_exec(output, dwords, dword_count, 0, type, &cfa); - } - print_cf(output, &cfb, 0); - if (cfb.is_exec()) { - disasm_exec(output, dwords, dword_count, 0, type, &cfb); - } - if (cfa.opc == EXEC_END || cfb.opc == EXEC_END) { - break; - } - } - - char* result = strdup(output->buffer); - delete output; - return result; -} +/** + ****************************************************************************** + * Xenia : Xbox 360 Emulator Research Project * + ****************************************************************************** + * Copyright 2013 Ben Vanik. All rights reserved. * + * Released under the BSD license - see LICENSE in the root for more details. * + ****************************************************************************** + */ + +/* + * Copyright (c) 2012 Rob Clark + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include + +#include +#include +#include +#include + +namespace xe { +namespace gpu { + +using namespace xe::gpu::ucode; +using namespace xe::gpu::xenos; + +const int OUTPUT_CAPACITY = 32 * 1024; +struct Output { + char buffer[OUTPUT_CAPACITY]; + size_t capacity; + size_t offset; + Output() : capacity(OUTPUT_CAPACITY), offset(0) { buffer[0] = 0; } + void append(const char* format, ...) { + va_list args; + va_start(args, format); + int len = vsnprintf(buffer + offset, capacity - offset, format, args); + va_end(args); + offset += len; + buffer[offset] = 0; + } +}; + +static const char* levels[] = { + "", "\t", "\t\t", "\t\t\t", "\t\t\t\t", "\t\t\t\t\t", "\t\t\t\t\t\t", + "\t\t\t\t\t\t\t", "\t\t\t\t\t\t\t\t", "\t\t\t\t\t\t\t\t\t", "x", "x", "x", + "x", "x", "x", +}; + +/* + * ALU instructions: + */ + +static const char chan_names[] = { + 'x', 'y', 'z', 'w', + /* these only apply to FETCH dst's: */ + '0', '1', '?', '_', +}; + +void print_srcreg(Output* output, uint32_t num, uint32_t type, uint32_t swiz, + uint32_t negate, uint32_t abs_constants, + ShaderType shader_type) { + if (negate) { + output->append("-"); + } + if (type) { + if (num & 0x80) { + output->append("abs("); + } + output->append("R%u", num & 0x7F); + if (num & 0x80) { + output->append(")"); + } + } else { + if (abs_constants) { + output->append("|"); + } + num += shader_type == ShaderType::kPixel ? 256 : 0; + output->append("C%u", num); + if (abs_constants) { + output->append("|"); + } + } + if (swiz) { + output->append("."); + for (int i = 0; i < 4; i++) { + output->append("%c", chan_names[(swiz + i) & 0x3]); + swiz >>= 2; + } + } +} + +void print_dstreg(Output* output, uint32_t num, uint32_t mask, + uint32_t dst_exp) { + output->append("%s%u", dst_exp ? "export" : "R", num); + if (mask != 0xf) { + output->append("."); + for (int i = 0; i < 4; i++) { + output->append("%c", (mask & 0x1) ? chan_names[i] : '_'); + mask >>= 1; + } + } +} + +void print_export_comment(Output* output, uint32_t num, ShaderType type) { + const char* name = NULL; + switch (type) { + case ShaderType::kVertex: + switch (num) { + case 62: + name = "gl_Position"; + break; + case 63: + name = "gl_PointSize"; + break; + } + break; + case ShaderType::kPixel: + switch (num) { + case 0: + name = "gl_FragColor"; + break; + } + break; + } + /* if we had a symbol table here, we could look + * up the name of the varying.. + */ + if (name) { + output->append("\t; %s", name); + } +} + +struct { + uint32_t num_srcs; + const char* name; +} vector_instructions[0x20] = + { +#define INSTR(opc, num_srcs) \ + { num_srcs, #opc } + INSTR(ADDv, 2), // 0 + INSTR(MULv, 2), // 1 + INSTR(MAXv, 2), // 2 + INSTR(MINv, 2), // 3 + INSTR(SETEv, 2), // 4 + INSTR(SETGTv, 2), // 5 + INSTR(SETGTEv, 2), // 6 + INSTR(SETNEv, 2), // 7 + INSTR(FRACv, 1), // 8 + INSTR(TRUNCv, 1), // 9 + INSTR(FLOORv, 1), // 10 + INSTR(MULADDv, 3), // 111 + INSTR(CNDEv, 3), // 12 + INSTR(CNDGTEv, 3), // 13 + INSTR(CNDGTv, 3), // 14 + INSTR(DOT4v, 2), // 15 + INSTR(DOT3v, 2), // 16 + INSTR(DOT2ADDv, 3), // 17 -- ??? + INSTR(CUBEv, 2), // 18 + INSTR(MAX4v, 1), // 19 + INSTR(PRED_SETE_PUSHv, 2), // 20 + INSTR(PRED_SETNE_PUSHv, 2), // 21 + INSTR(PRED_SETGT_PUSHv, 2), // 22 + INSTR(PRED_SETGTE_PUSHv, 2), // 23 + INSTR(KILLEv, 2), // 24 + INSTR(KILLGTv, 2), // 25 + INSTR(KILLGTEv, 2), // 26 + INSTR(KILLNEv, 2), // 27 + INSTR(DSTv, 2), // 28 + INSTR(MOVAv, 1), // 29 +}, + scalar_instructions[0x40] = { + INSTR(ADDs, 1), // 0 + INSTR(ADD_PREVs, 1), // 1 + INSTR(MULs, 1), // 2 + INSTR(MUL_PREVs, 1), // 3 + INSTR(MUL_PREV2s, 1), // 4 + INSTR(MAXs, 1), // 5 + INSTR(MINs, 1), // 6 + INSTR(SETEs, 1), // 7 + INSTR(SETGTs, 1), // 8 + INSTR(SETGTEs, 1), // 9 + INSTR(SETNEs, 1), // 10 + INSTR(FRACs, 1), // 11 + INSTR(TRUNCs, 1), // 12 + INSTR(FLOORs, 1), // 13 + INSTR(EXP_IEEE, 1), // 14 + INSTR(LOG_CLAMP, 1), // 15 + INSTR(LOG_IEEE, 1), // 16 + INSTR(RECIP_CLAMP, 1), // 17 + INSTR(RECIP_FF, 1), // 18 + INSTR(RECIP_IEEE, 1), // 19 + INSTR(RECIPSQ_CLAMP, 1), // 20 + INSTR(RECIPSQ_FF, 1), // 21 + INSTR(RECIPSQ_IEEE, 1), // 22 + INSTR(MOVAs, 1), // 23 + INSTR(MOVA_FLOORs, 1), // 24 + INSTR(SUBs, 1), // 25 + INSTR(SUB_PREVs, 1), // 26 + INSTR(PRED_SETEs, 1), // 27 + INSTR(PRED_SETNEs, 1), // 28 + INSTR(PRED_SETGTs, 1), // 29 + INSTR(PRED_SETGTEs, 1), // 30 + INSTR(PRED_SET_INVs, 1), // 31 + INSTR(PRED_SET_POPs, 1), // 32 + INSTR(PRED_SET_CLRs, 1), // 33 + INSTR(PRED_SET_RESTOREs, 1), // 34 + INSTR(KILLEs, 1), // 35 + INSTR(KILLGTs, 1), // 36 + INSTR(KILLGTEs, 1), // 37 + INSTR(KILLNEs, 1), // 38 + INSTR(KILLONEs, 1), // 39 + INSTR(SQRT_IEEE, 1), // 40 + {0, 0}, + INSTR(MUL_CONST_0, 2), // 42 + INSTR(MUL_CONST_1, 2), // 43 + INSTR(ADD_CONST_0, 2), // 44 + INSTR(ADD_CONST_1, 2), // 45 + INSTR(SUB_CONST_0, 2), // 46 + INSTR(SUB_CONST_1, 2), // 47 + INSTR(SIN, 1), // 48 + INSTR(COS, 1), // 49 + INSTR(RETAIN_PREV, 1), // 50 +#undef INSTR +}; + +int disasm_alu(Output* output, const uint32_t* dwords, uint32_t alu_off, + int level, int sync, ShaderType type) { + const instr_alu_t* alu = (const instr_alu_t*)dwords; + + output->append("%s", levels[level]); + output->append("%02x: %08x %08x %08x\t", alu_off, dwords[0], dwords[1], + dwords[2]); + + output->append(" %sALU:\t", sync ? "(S)" : " "); + + if (!alu->scalar_write_mask && !alu->vector_write_mask) { + output->append(" \n"); + } + + if (alu->vector_write_mask) { + output->append("%s", vector_instructions[alu->vector_opc].name); + + if (alu->pred_select & 0x2) { + // seems to work similar to conditional execution in ARM instruction + // set, so let's use a similar syntax for now: + output->append((alu->pred_select & 0x1) ? "EQ" : "NE"); + } + + output->append("\t"); + + print_dstreg(output, alu->vector_dest, alu->vector_write_mask, + alu->export_data); + output->append(" = "); + if (vector_instructions[alu->vector_opc].num_srcs == 3) { + print_srcreg(output, alu->src3_reg, alu->src3_sel, alu->src3_swiz, + alu->src3_reg_negate, alu->abs_constants, type); + output->append(", "); + } + print_srcreg(output, alu->src1_reg, alu->src1_sel, alu->src1_swiz, + alu->src1_reg_negate, alu->abs_constants, type); + if (vector_instructions[alu->vector_opc].num_srcs > 1) { + output->append(", "); + print_srcreg(output, alu->src2_reg, alu->src2_sel, alu->src2_swiz, + alu->src2_reg_negate, alu->abs_constants, type); + } + + if (alu->vector_clamp) { + output->append(" CLAMP"); + } + + if (alu->export_data) { + print_export_comment(output, alu->vector_dest, type); + } + + output->append("\n"); + } + + if (alu->scalar_write_mask || !alu->vector_write_mask) { + // 2nd optional scalar op: + + if (alu->vector_write_mask) { + output->append("%s", levels[level]); + output->append(" \t\t\t\t\t\t \t"); + } + + if (scalar_instructions[alu->scalar_opc].name) { + output->append("%s\t", scalar_instructions[alu->scalar_opc].name); + } else { + output->append("OP(%u)\t", alu->scalar_opc); + } + + print_dstreg(output, get_alu_scalar_dest(*alu), alu->scalar_write_mask, + alu->export_data); + output->append(" = "); + if (scalar_instructions[alu->scalar_opc].num_srcs == 2) { + // MUL/ADD/etc + // Clever, CONST_0 and CONST_1 are just an extra storage bit. + // ADD_CONST_0 dest, [const], [reg] + uint32_t src3_swiz = alu->src3_swiz & ~0x3C; + uint32_t swiz_a = ((src3_swiz >> 6) - 1) & 0x3; + uint32_t swiz_b = (src3_swiz & 0x3); + print_srcreg(output, alu->src3_reg, 0, 0, alu->src3_reg_negate, + alu->abs_constants, type); + output->append(".%c", chan_names[swiz_a]); + output->append(", "); + uint32_t reg2 = (alu->scalar_opc & 1) | (alu->src3_swiz & 0x3C) | + (alu->src3_sel << 1); + print_srcreg(output, reg2, 1, 0, alu->src3_reg_negate, alu->abs_constants, + type); + output->append(".%c", chan_names[swiz_b]); + } else { + print_srcreg(output, alu->src3_reg, alu->src3_sel, alu->src3_swiz, + alu->src3_reg_negate, alu->abs_constants, type); + } + if (alu->scalar_clamp) { + output->append(" CLAMP"); + } + if (alu->export_data) { + print_export_comment(output, get_alu_scalar_dest(*alu), type); + } + output->append("\n"); + } + + return 0; +} + +struct { + const char* name; +} fetch_types[0xff] = { +#define TYPE(id) \ + { #id } + TYPE(FMT_1_REVERSE), // 0 + {0}, + TYPE(FMT_8), // 2 + {0}, + {0}, + {0}, + TYPE(FMT_8_8_8_8), // 6 + TYPE(FMT_2_10_10_10), // 7 + {0}, + {0}, + TYPE(FMT_8_8), // 10 + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + TYPE(FMT_16), // 24 + TYPE(FMT_16_16), // 25 + TYPE(FMT_16_16_16_16), // 26 + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + TYPE(FMT_32), // 33 + TYPE(FMT_32_32), // 34 + TYPE(FMT_32_32_32_32), // 35 + TYPE(FMT_32_FLOAT), // 36 + TYPE(FMT_32_32_FLOAT), // 37 + TYPE(FMT_32_32_32_32_FLOAT), // 38 + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + TYPE(FMT_32_32_32_FLOAT), // 57 +#undef TYPE +}; + +void print_fetch_dst(Output* output, uint32_t dst_reg, uint32_t dst_swiz) { + output->append("\tR%u.", dst_reg); + for (int i = 0; i < 4; i++) { + output->append("%c", chan_names[dst_swiz & 0x7]); + dst_swiz >>= 3; + } +} + +void print_fetch_vtx(Output* output, const instr_fetch_t* fetch) { + const instr_fetch_vtx_t* vtx = &fetch->vtx; + + if (vtx->pred_select) { + // seems to work similar to conditional execution in ARM instruction + // set, so let's use a similar syntax for now: + output->append(vtx->pred_condition ? "EQ" : "NE"); + } + + print_fetch_dst(output, vtx->dst_reg, vtx->dst_swiz); + output->append(" = R%u.", vtx->src_reg); + output->append("%c", chan_names[vtx->src_swiz & 0x3]); + if (fetch_types[vtx->format].name) { + output->append(" %s", fetch_types[vtx->format].name); + } else { + output->append(" TYPE(0x%x)", vtx->format); + } + output->append(" %s", vtx->format_comp_all ? "SIGNED" : "UNSIGNED"); + if (!vtx->num_format_all) { + output->append(" NORMALIZED"); + } + output->append(" STRIDE(%u)", vtx->stride); + if (vtx->offset) { + output->append(" OFFSET(%u)", vtx->offset); + } + output->append(" CONST(%u, %u)", vtx->const_index, vtx->const_index_sel); + if (1) { + // XXX + output->append(" src_reg_am=%u", vtx->src_reg_am); + output->append(" dst_reg_am=%u", vtx->dst_reg_am); + output->append(" num_format_all=%u", vtx->num_format_all); + output->append(" signed_rf_mode_all=%u", vtx->signed_rf_mode_all); + output->append(" exp_adjust_all=%u", vtx->exp_adjust_all); + } +} + +void print_fetch_tex(Output* output, const instr_fetch_t* fetch) { + static const char* filter[] = { + "POINT", // TEX_FILTER_POINT + "LINEAR", // TEX_FILTER_LINEAR + "BASEMAP", // TEX_FILTER_BASEMAP + }; + static const char* aniso_filter[] = { + "DISABLED", // ANISO_FILTER_DISABLED + "MAX_1_1", // ANISO_FILTER_MAX_1_1 + "MAX_2_1", // ANISO_FILTER_MAX_2_1 + "MAX_4_1", // ANISO_FILTER_MAX_4_1 + "MAX_8_1", // ANISO_FILTER_MAX_8_1 + "MAX_16_1", // ANISO_FILTER_MAX_16_1 + }; + static const char* arbitrary_filter[] = { + "2x4_SYM", // ARBITRARY_FILTER_2X4_SYM + "2x4_ASYM", // ARBITRARY_FILTER_2X4_ASYM + "4x2_SYM", // ARBITRARY_FILTER_4X2_SYM + "4x2_ASYM", // ARBITRARY_FILTER_4X2_ASYM + "4x4_SYM", // ARBITRARY_FILTER_4X4_SYM + "4x4_ASYM", // ARBITRARY_FILTER_4X4_ASYM + }; + static const char* sample_loc[] = { + "CENTROID", // SAMPLE_CENTROID + "CENTER", // SAMPLE_CENTER + }; + const instr_fetch_tex_t* tex = &fetch->tex; + uint32_t src_swiz = tex->src_swiz; + + if (tex->pred_select) { + // seems to work similar to conditional execution in ARM instruction + // set, so let's use a similar syntax for now: + output->append(tex->pred_condition ? "EQ" : "NE"); + } + + print_fetch_dst(output, tex->dst_reg, tex->dst_swiz); + output->append(" = R%u.", tex->src_reg); + for (int i = 0; i < 3; i++) { + output->append("%c", chan_names[src_swiz & 0x3]); + src_swiz >>= 2; + } + output->append(" CONST(%u)", tex->const_idx); + if (tex->fetch_valid_only) { + output->append(" VALID_ONLY"); + } + if (tex->tx_coord_denorm) { + output->append(" DENORM"); + } + if (tex->mag_filter != TEX_FILTER_USE_FETCH_CONST) { + output->append(" MAG(%s)", filter[tex->mag_filter]); + } + if (tex->min_filter != TEX_FILTER_USE_FETCH_CONST) { + output->append(" MIN(%s)", filter[tex->min_filter]); + } + if (tex->mip_filter != TEX_FILTER_USE_FETCH_CONST) { + output->append(" MIP(%s)", filter[tex->mip_filter]); + } + if (tex->aniso_filter != ANISO_FILTER_USE_FETCH_CONST) { + output->append(" ANISO(%s)", aniso_filter[tex->aniso_filter]); + } + if (tex->arbitrary_filter != ARBITRARY_FILTER_USE_FETCH_CONST) { + output->append(" ARBITRARY(%s)", arbitrary_filter[tex->arbitrary_filter]); + } + if (tex->vol_mag_filter != TEX_FILTER_USE_FETCH_CONST) { + output->append(" VOL_MAG(%s)", filter[tex->vol_mag_filter]); + } + if (tex->vol_min_filter != TEX_FILTER_USE_FETCH_CONST) { + output->append(" VOL_MIN(%s)", filter[tex->vol_min_filter]); + } + if (!tex->use_comp_lod) { + output->append(" LOD(%u)", tex->use_comp_lod); + output->append(" LOD_BIAS(%u)", tex->lod_bias); + } + if (tex->use_reg_lod) { + output->append(" REG_LOD(%u)", tex->use_reg_lod); + } + if (tex->use_reg_gradients) { + output->append(" USE_REG_GRADIENTS"); + } + output->append(" LOCATION(%s)", sample_loc[tex->sample_location]); + if (tex->offset_x || tex->offset_y || tex->offset_z) { + output->append(" OFFSET(%u,%u,%u)", tex->offset_x, tex->offset_y, + tex->offset_z); + } +} + +struct { + const char* name; + void (*fxn)(Output* output, const instr_fetch_t* cf); +} fetch_instructions[] = { +#define INSTR(opc, name, fxn) \ + { name, fxn } + INSTR(VTX_FETCH, "VERTEX", print_fetch_vtx), // 0 + INSTR(TEX_FETCH, "SAMPLE", print_fetch_tex), // 1 + {0, 0}, + {0, 0}, + {0, 0}, + {0, 0}, + {0, 0}, + {0, 0}, + {0, 0}, + {0, 0}, + {0, 0}, + {0, 0}, + {0, 0}, + {0, 0}, + {0, 0}, + {0, 0}, + INSTR(TEX_GET_BORDER_COLOR_FRAC, "?", print_fetch_tex), // 16 + INSTR(TEX_GET_COMP_TEX_LOD, "?", print_fetch_tex), // 17 + INSTR(TEX_GET_GRADIENTS, "?", print_fetch_tex), // 18 + INSTR(TEX_GET_WEIGHTS, "?", print_fetch_tex), // 19 + {0, 0}, + {0, 0}, + {0, 0}, + {0, 0}, + INSTR(TEX_SET_TEX_LOD, "SET_TEX_LOD", print_fetch_tex), // 24 + INSTR(TEX_SET_GRADIENTS_H, "?", print_fetch_tex), // 25 + INSTR(TEX_SET_GRADIENTS_V, "?", print_fetch_tex), // 26 + INSTR(TEX_RESERVED_4, "?", print_fetch_tex), // 27 +#undef INSTR +}; + +int disasm_fetch(Output* output, const uint32_t* dwords, uint32_t alu_off, + int level, int sync) { + const instr_fetch_t* fetch = (const instr_fetch_t*)dwords; + + output->append("%s", levels[level]); + output->append("%02x: %08x %08x %08x\t", alu_off, dwords[0], dwords[1], + dwords[2]); + + output->append(" %sFETCH:\t", sync ? "(S)" : " "); + if (fetch_instructions[fetch->opc].fxn) { + output->append("%s", fetch_instructions[fetch->opc].name); + fetch_instructions[fetch->opc].fxn(output, fetch); + } else { + output->append("???"); + } + output->append("\n"); + + return 0; +} + +void print_cf_nop(Output* output, const instr_cf_t* cf) {} + +void print_cf_exec(Output* output, const instr_cf_t* cf) { + output->append(" ADDR(0x%x) CNT(0x%x)", cf->exec.address, cf->exec.count); + if (cf->exec.yeild) { + output->append(" YIELD"); + } + uint8_t vc = cf->exec.vc_hi | (cf->exec.vc_lo << 2); + if (vc) { + output->append(" VC(0x%x)", vc); + } + if (cf->exec.bool_addr) { + output->append(" BOOL_ADDR(0x%x)", cf->exec.bool_addr); + } + if (cf->exec.address_mode == ABSOLUTE_ADDR) { + output->append(" ABSOLUTE_ADDR"); + } + if (cf->is_cond_exec()) { + output->append(" COND(%d)", cf->exec.condition); + } +} + +void print_cf_loop(Output* output, const instr_cf_t* cf) { + output->append(" ADDR(0x%x) LOOP_ID(%d)", cf->loop.address, cf->loop.loop_id); + if (cf->loop.address_mode == ABSOLUTE_ADDR) { + output->append(" ABSOLUTE_ADDR"); + } +} + +void print_cf_jmp_call(Output* output, const instr_cf_t* cf) { + output->append(" ADDR(0x%x) DIR(%d)", cf->jmp_call.address, + cf->jmp_call.direction); + if (cf->jmp_call.force_call) { + output->append(" FORCE_CALL"); + } + if (cf->jmp_call.predicated_jmp) { + output->append(" COND(%d)", cf->jmp_call.condition); + } + if (cf->jmp_call.bool_addr) { + output->append(" BOOL_ADDR(0x%x)", cf->jmp_call.bool_addr); + } + if (cf->jmp_call.address_mode == ABSOLUTE_ADDR) { + output->append(" ABSOLUTE_ADDR"); + } +} + +void print_cf_alloc(Output* output, const instr_cf_t* cf) { + static const char* bufname[] = { + "NO ALLOC", // SQ_NO_ALLOC + "POSITION", // SQ_POSITION + "PARAM/PIXEL", // SQ_PARAMETER_PIXEL + "MEMORY", // SQ_MEMORY + }; + output->append(" %s SIZE(0x%x)", bufname[cf->alloc.buffer_select], + cf->alloc.size); + if (cf->alloc.no_serial) { + output->append(" NO_SERIAL"); + } + if (cf->alloc.alloc_mode) { + // ??? + output->append(" ALLOC_MODE"); + } +} + +struct { + const char* name; + void (*fxn)(Output* output, const instr_cf_t* cf); +} cf_instructions[] = { +#define INSTR(opc, fxn) \ + { #opc, fxn } + INSTR(NOP, print_cf_nop), INSTR(EXEC, print_cf_exec), + INSTR(EXEC_END, print_cf_exec), INSTR(COND_EXEC, print_cf_exec), + INSTR(COND_EXEC_END, print_cf_exec), INSTR(COND_PRED_EXEC, print_cf_exec), + INSTR(COND_PRED_EXEC_END, print_cf_exec), INSTR(LOOP_START, print_cf_loop), + INSTR(LOOP_END, print_cf_loop), INSTR(COND_CALL, print_cf_jmp_call), + INSTR(RETURN, print_cf_jmp_call), INSTR(COND_JMP, print_cf_jmp_call), + INSTR(ALLOC, print_cf_alloc), INSTR(COND_EXEC_PRED_CLEAN, print_cf_exec), + INSTR(COND_EXEC_PRED_CLEAN_END, print_cf_exec), + INSTR(MARK_VS_FETCH_DONE, print_cf_nop), // ?? +#undef INSTR +}; + +static void print_cf(Output* output, const instr_cf_t* cf, int level) { + output->append("%s", levels[level]); + + const uint16_t* words = (uint16_t*)cf; + output->append(" %04x %04x %04x \t", words[0], words[1], + words[2]); + + output->append("%s", cf_instructions[cf->opc].name); + cf_instructions[cf->opc].fxn(output, cf); + output->append("\n"); +} + +/* + * The adreno shader microcode consists of two parts: + * 1) A CF (control-flow) program, at the header of the compiled shader, + * which refers to ALU/FETCH instructions that follow it by address. + * 2) ALU and FETCH instructions + */ +void disasm_exec(Output* output, const uint32_t* dwords, size_t dword_count, + int level, ShaderType type, const instr_cf_t* cf) { + uint32_t sequence = cf->exec.serialize; + for (uint32_t i = 0; i < cf->exec.count; i++) { + uint32_t alu_off = (cf->exec.address + i); + if (sequence & 0x1) { + disasm_fetch(output, dwords + alu_off * 3, alu_off, level, + sequence & 0x2); + } else { + disasm_alu(output, dwords + alu_off * 3, alu_off, level, sequence & 0x2, + type); + } + sequence >>= 2; + } +} + +std::string DisassembleShader(ShaderType type, const uint32_t* dwords, + size_t dword_count) { + Output* output = new Output(); + + instr_cf_t cfa; + instr_cf_t cfb; + for (int idx = 0; idx < dword_count; idx += 3) { + uint32_t dword_0 = dwords[idx + 0]; + uint32_t dword_1 = dwords[idx + 1]; + uint32_t dword_2 = dwords[idx + 2]; + cfa.dword_0 = dword_0; + cfa.dword_1 = dword_1 & 0xFFFF; + cfb.dword_0 = (dword_1 >> 16) | (dword_2 << 16); + cfb.dword_1 = dword_2 >> 16; + print_cf(output, &cfa, 0); + if (cfa.is_exec()) { + disasm_exec(output, dwords, dword_count, 0, type, &cfa); + } + print_cf(output, &cfb, 0); + if (cfb.is_exec()) { + disasm_exec(output, dwords, dword_count, 0, type, &cfb); + } + if (cfa.opc == EXEC_END || cfb.opc == EXEC_END) { + break; + } + } + + auto result = std::string(output->buffer); + delete output; + return result; +} + +} // namespace gpu +} // namespace xe diff --git a/src/xenia/gpu/xenos/ucode_disassembler.h b/src/xenia/gpu/ucode_disassembler.h similarity index 57% rename from src/xenia/gpu/xenos/ucode_disassembler.h rename to src/xenia/gpu/ucode_disassembler.h index d6fdf47e2..fe3cb2868 100644 --- a/src/xenia/gpu/xenos/ucode_disassembler.h +++ b/src/xenia/gpu/ucode_disassembler.h @@ -1,33 +1,27 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef XENIA_GPU_XENOS_UCODE_DISASSEMBLER_H_ -#define XENIA_GPU_XENOS_UCODE_DISASSEMBLER_H_ - -#include -#include -#include - - -namespace xe { -namespace gpu { -namespace xenos { - - -char* DisassembleShader( - XE_GPU_SHADER_TYPE type, - const uint32_t* dwords, size_t dword_count); - - -} // namespace xenos -} // namespace gpu -} // namespace xe - - -#endif // XENIA_GPU_XENOS_UCODE_DISASSEMBLER_H_ +/** + ****************************************************************************** + * Xenia : Xbox 360 Emulator Research Project * + ****************************************************************************** + * Copyright 2013 Ben Vanik. All rights reserved. * + * Released under the BSD license - see LICENSE in the root for more details. * + ****************************************************************************** + */ + +#ifndef XENIA_GPU_UCODE_DISASSEMBLER_H_ +#define XENIA_GPU_UCODE_DISASSEMBLER_H_ + +#include + +#include +#include + +namespace xe { +namespace gpu { + +std::string DisassembleShader(xenos::ShaderType type, const uint32_t* dwords, + size_t dword_count); + +} // namespace gpu +} // namespace xe + +#endif // XENIA_GPU_UCODE_DISASSEMBLER_H_ diff --git a/src/xenia/gpu/xenos/xenos.h b/src/xenia/gpu/xenos.h similarity index 55% rename from src/xenia/gpu/xenos/xenos.h rename to src/xenia/gpu/xenos.h index 63beb54ec..e7c386cc5 100644 --- a/src/xenia/gpu/xenos/xenos.h +++ b/src/xenia/gpu/xenos.h @@ -1,239 +1,303 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef XENIA_GPU_XENOS_XENOS_H_ -#define XENIA_GPU_XENOS_XENOS_H_ - -#include -#include - -namespace xe { -namespace gpu { -namespace xenos { - - -typedef enum { - XE_GPU_SHADER_TYPE_VERTEX = 0x00, - XE_GPU_SHADER_TYPE_PIXEL = 0x01, -} XE_GPU_SHADER_TYPE; - -typedef enum { - XE_GPU_INVALIDATE_MASK_VERTEX_SHADER = 1 << 8, - XE_GPU_INVALIDATE_MASK_PIXEL_SHADER = 1 << 9, - - XE_GPU_INVALIDATE_MASK_ALL = 0x7FFF, -} XE_GPU_INVALIDATE_MASK; - -typedef enum { - XE_GPU_PRIMITIVE_TYPE_POINT_LIST = 0x01, - XE_GPU_PRIMITIVE_TYPE_LINE_LIST = 0x02, - XE_GPU_PRIMITIVE_TYPE_LINE_STRIP = 0x03, - XE_GPU_PRIMITIVE_TYPE_TRIANGLE_LIST = 0x04, - XE_GPU_PRIMITIVE_TYPE_TRIANGLE_FAN = 0x05, - XE_GPU_PRIMITIVE_TYPE_TRIANGLE_STRIP = 0x06, - XE_GPU_PRIMITIVE_TYPE_UNKNOWN_07 = 0x07, - XE_GPU_PRIMITIVE_TYPE_RECTANGLE_LIST = 0x08, - XE_GPU_PRIMITIVE_TYPE_LINE_LOOP = 0x0C, - XE_GPU_PRIMITIVE_TYPE_QUAD_LIST = 0x0D, -} XE_GPU_PRIMITIVE_TYPE; - -typedef enum { - XE_GPU_ENDIAN_NONE = 0x0, - XE_GPU_ENDIAN_8IN16 = 0x1, - XE_GPU_ENDIAN_8IN32 = 0x2, - XE_GPU_ENDIAN_16IN32 = 0x3, -} XE_GPU_ENDIAN; - -#define XE_GPU_MAKE_SWIZZLE(x, y, z, w) \ - (((XE_GPU_SWIZZLE_##x) << 0) | ((XE_GPU_SWIZZLE_##y) << 3) | ((XE_GPU_SWIZZLE_##z) << 6) | ((XE_GPU_SWIZZLE_##w) << 9)) -typedef enum { - XE_GPU_SWIZZLE_X = 0, - XE_GPU_SWIZZLE_R = 0, - XE_GPU_SWIZZLE_Y = 1, - XE_GPU_SWIZZLE_G = 1, - XE_GPU_SWIZZLE_Z = 2, - XE_GPU_SWIZZLE_B = 2, - XE_GPU_SWIZZLE_W = 3, - XE_GPU_SWIZZLE_A = 3, - XE_GPU_SWIZZLE_0 = 4, - XE_GPU_SWIZZLE_1 = 5, - XE_GPU_SWIZZLE_RGBA = XE_GPU_MAKE_SWIZZLE(R, G, B, A), - XE_GPU_SWIZZLE_BGRA = XE_GPU_MAKE_SWIZZLE(B, G, R, A), - XE_GPU_SWIZZLE_RGB1 = XE_GPU_MAKE_SWIZZLE(R, G, B, 1), - XE_GPU_SWIZZLE_BGR1 = XE_GPU_MAKE_SWIZZLE(B, G, R, 1), - XE_GPU_SWIZZLE_000R = XE_GPU_MAKE_SWIZZLE(0, 0, 0, R), - XE_GPU_SWIZZLE_RRR1 = XE_GPU_MAKE_SWIZZLE(R, R, R, 1), - XE_GPU_SWIZZLE_R111 = XE_GPU_MAKE_SWIZZLE(R, 1, 1, 1), - XE_GPU_SWIZZLE_R000 = XE_GPU_MAKE_SWIZZLE(R, 0, 0, 0), -} XE_GPU_SWIZZLE; - -inline uint32_t GpuSwap(uint32_t value, XE_GPU_ENDIAN endianness) { - switch (endianness) { - default: - case XE_GPU_ENDIAN_NONE: // No swap. - return value; - case XE_GPU_ENDIAN_8IN16: // Swap bytes in half words. - return ((value << 8) & 0xFF00FF00) | - ((value >> 8) & 0x00FF00FF); - case XE_GPU_ENDIAN_8IN32: // Swap bytes. - // NOTE: we are likely doing two swaps here. Wasteful. Oh well. - return poly::byte_swap(value); - case XE_GPU_ENDIAN_16IN32: // Swap half words. - return ((value >> 16) & 0xFFFF) | (value << 16); - } -} - -inline uint32_t GpuToCpu(uint32_t p) { - return p; -} - -inline uint32_t GpuToCpu(uint32_t base, uint32_t p) { - // Some AMD docs say relative to base ptr, some say just this. - // Some games use some crazy shift magic, but it seems to nop. - uint32_t upper = 0;//base & 0xFF000000; - uint32_t lower = p & 0x01FFFFFF; - return upper + lower;// -(((base >> 20) + 0x200) & 0x1000); -} - - -// XE_GPU_REG_SQ_PROGRAM_CNTL -typedef union { - XEPACKEDSTRUCTANONYMOUS({ - uint32_t vs_regs : 6; - uint32_t : 2; - uint32_t ps_regs : 6; - uint32_t : 2; - uint32_t vs_resource : 1; - uint32_t ps_resource : 1; - uint32_t param_gen : 1; - uint32_t unknown0 : 1; - uint32_t vs_export_count : 4; - uint32_t vs_export_mode : 3; - uint32_t ps_export_depth : 1; - uint32_t ps_export_count : 3; - uint32_t gen_index_vtx : 1; - }); - XEPACKEDSTRUCTANONYMOUS({ - uint32_t dword_0; - }); -} xe_gpu_program_cntl_t; - -// XE_GPU_REG_SHADER_CONSTANT_FETCH_* -XEPACKEDUNION(xe_gpu_vertex_fetch_t, { - XEPACKEDSTRUCTANONYMOUS({ - uint32_t type : 2; - uint32_t address : 30; - uint32_t endian : 2; - uint32_t size : 24; - uint32_t unk1 : 6; - }); - XEPACKEDSTRUCTANONYMOUS({ - uint32_t dword_0; - uint32_t dword_1; - }); -}); - -// XE_GPU_REG_SHADER_CONSTANT_FETCH_* -XEPACKEDUNION(xe_gpu_texture_fetch_t, { - XEPACKEDSTRUCTANONYMOUS({ - uint32_t type : 2; // dword_0 - uint32_t sign_x : 2; - uint32_t sign_y : 2; - uint32_t sign_z : 2; - uint32_t sign_w : 2; - uint32_t clamp_x : 3; - uint32_t clamp_y : 3; - uint32_t clamp_z : 3; - uint32_t unk0 : 3; - uint32_t pitch : 9; - uint32_t tiled : 1; - uint32_t format : 6; // dword_1 - uint32_t endianness : 2; - uint32_t unk1 : 4; - uint32_t address : 20; - union { // dword_2 - struct { - uint32_t width : 24; - uint32_t unused : 8; - } size_1d; - struct { - uint32_t width : 13; - uint32_t height : 13; - uint32_t unused : 6; - } size_2d; - struct { - uint32_t width : 13; - uint32_t height : 13; - uint32_t depth : 6; - } size_stack; - struct { - uint32_t width : 11; - uint32_t height : 11; - uint32_t depth : 10; - } size_3d; - }; - uint32_t unk3_0 : 1; // dword_3 - uint32_t swizzle : 12; // xyzw, 3b each (XE_GPU_SWIZZLE) - uint32_t unk3_1 : 6; - uint32_t mag_filter : 2; - uint32_t min_filter : 2; - uint32_t mip_filter : 2; - uint32_t unk3_2 : 6; - uint32_t border : 1; - uint32_t unk4; // dword_4 - uint32_t unk5 : 9; // dword_5 - uint32_t dimension : 2; - uint32_t unk5b : 21; - }); - XEPACKEDSTRUCTANONYMOUS({ - uint32_t dword_0; - uint32_t dword_1; - uint32_t dword_2; - uint32_t dword_3; - uint32_t dword_4; - uint32_t dword_5; - }); -}); - -// XE_GPU_REG_SHADER_CONSTANT_FETCH_* -XEPACKEDUNION(xe_gpu_fetch_group_t, { - xe_gpu_texture_fetch_t texture_fetch; - XEPACKEDSTRUCTANONYMOUS({ - xe_gpu_vertex_fetch_t vertex_fetch_0; - xe_gpu_vertex_fetch_t vertex_fetch_1; - xe_gpu_vertex_fetch_t vertex_fetch_2; - }); - XEPACKEDSTRUCTANONYMOUS({ - uint32_t dword_0; - uint32_t dword_1; - uint32_t dword_2; - uint32_t dword_3; - uint32_t dword_4; - uint32_t dword_5; - }); - XEPACKEDSTRUCTANONYMOUS({ - uint32_t type_0 : 2; - uint32_t : 30; - uint32_t : 32; - uint32_t type_1 : 2; - uint32_t : 30; - uint32_t : 32; - uint32_t type_2 : 2; - uint32_t : 30; - uint32_t : 32; - }); -}); - - -} // namespace xenos -} // namespace gpu -} // namespace xe - - -#endif // XENIA_GPU_XENOS_XENOS_H_ +/** + ****************************************************************************** + * Xenia : Xbox 360 Emulator Research Project * + ****************************************************************************** + * Copyright 2013 Ben Vanik. All rights reserved. * + * Released under the BSD license - see LICENSE in the root for more details. * + ****************************************************************************** + */ + +#ifndef XENIA_GPU_XENOS_H_ +#define XENIA_GPU_XENOS_H_ + +#include +#include + +namespace xe { +namespace gpu { +namespace xenos { + +enum class ShaderType : uint32_t { + kVertex = 0, + kPixel = 1, +}; + +typedef enum { + XE_GPU_INVALIDATE_MASK_VERTEX_SHADER = 1 << 8, + XE_GPU_INVALIDATE_MASK_PIXEL_SHADER = 1 << 9, + + XE_GPU_INVALIDATE_MASK_ALL = 0x7FFF, +} XE_GPU_INVALIDATE_MASK; + +enum class PrimitiveType : uint32_t { + kNone = 0x00, + kPointList = 0x01, + kLineList = 0x02, + kLineStrip = 0x03, + kTriangleList = 0x04, + kTriangleFan = 0x05, + kTriangleStrip = 0x06, + kUnknown0x07 = 0x07, + kRectangleList = 0x08, + kLineLoop = 0x0C, + kQuadList = 0x0D, +}; + +enum class Endian : uint32_t { + kUnspecified = 0, + k8in16 = 1, + k8in32 = 2, + k16in32 = 3, +}; + +#define XE_GPU_MAKE_SWIZZLE(x, y, z, w) \ + (((XE_GPU_SWIZZLE_##x) << 0) | ((XE_GPU_SWIZZLE_##y) << 3) | ((XE_GPU_SWIZZLE_##z) << 6) | ((XE_GPU_SWIZZLE_##w) << 9)) +typedef enum { + XE_GPU_SWIZZLE_X = 0, + XE_GPU_SWIZZLE_R = 0, + XE_GPU_SWIZZLE_Y = 1, + XE_GPU_SWIZZLE_G = 1, + XE_GPU_SWIZZLE_Z = 2, + XE_GPU_SWIZZLE_B = 2, + XE_GPU_SWIZZLE_W = 3, + XE_GPU_SWIZZLE_A = 3, + XE_GPU_SWIZZLE_0 = 4, + XE_GPU_SWIZZLE_1 = 5, + XE_GPU_SWIZZLE_RGBA = XE_GPU_MAKE_SWIZZLE(R, G, B, A), + XE_GPU_SWIZZLE_BGRA = XE_GPU_MAKE_SWIZZLE(B, G, R, A), + XE_GPU_SWIZZLE_RGB1 = XE_GPU_MAKE_SWIZZLE(R, G, B, 1), + XE_GPU_SWIZZLE_BGR1 = XE_GPU_MAKE_SWIZZLE(B, G, R, 1), + XE_GPU_SWIZZLE_000R = XE_GPU_MAKE_SWIZZLE(0, 0, 0, R), + XE_GPU_SWIZZLE_RRR1 = XE_GPU_MAKE_SWIZZLE(R, R, R, 1), + XE_GPU_SWIZZLE_R111 = XE_GPU_MAKE_SWIZZLE(R, 1, 1, 1), + XE_GPU_SWIZZLE_R000 = XE_GPU_MAKE_SWIZZLE(R, 0, 0, 0), +} XE_GPU_SWIZZLE; + +inline uint32_t GpuSwap(uint32_t value, Endian endianness) { + switch (endianness) { + default: + case Endian::kUnspecified: + // No swap. + return value; + case Endian::k8in16: + // Swap bytes in half words. + return ((value << 8) & 0xFF00FF00) | ((value >> 8) & 0x00FF00FF); + case Endian::k8in32: + // Swap bytes. + // NOTE: we are likely doing two swaps here. Wasteful. Oh well. + return poly::byte_swap(value); + case Endian::k16in32: + // Swap half words. + return ((value >> 16) & 0xFFFF) | (value << 16); + } +} + +inline uint32_t GpuToCpu(uint32_t p) { + return p; +} + +inline uint32_t GpuToCpu(uint32_t base, uint32_t p) { + // Some AMD docs say relative to base ptr, some say just this. + // Some games use some crazy shift magic, but it seems to nop. + uint32_t upper = 0;//base & 0xFF000000; + uint32_t lower = p & 0x01FFFFFF; + return upper + lower;// -(((base >> 20) + 0x200) & 0x1000); +} + +// XE_GPU_REG_SQ_PROGRAM_CNTL +typedef union { + XEPACKEDSTRUCTANONYMOUS({ + uint32_t vs_regs : 6; + uint32_t : 2; + uint32_t ps_regs : 6; + uint32_t : 2; + uint32_t vs_resource : 1; + uint32_t ps_resource : 1; + uint32_t param_gen : 1; + uint32_t unknown0 : 1; + uint32_t vs_export_count : 4; + uint32_t vs_export_mode : 3; + uint32_t ps_export_depth : 1; + uint32_t ps_export_count : 3; + uint32_t gen_index_vtx : 1; + }); + XEPACKEDSTRUCTANONYMOUS({ + uint32_t dword_0; + }); +} xe_gpu_program_cntl_t; + +// XE_GPU_REG_SHADER_CONSTANT_FETCH_* +XEPACKEDUNION(xe_gpu_vertex_fetch_t, { + XEPACKEDSTRUCTANONYMOUS({ + uint32_t type : 2; + uint32_t address : 30; + uint32_t endian : 2; + uint32_t size : 24; + uint32_t unk1 : 6; + }); + XEPACKEDSTRUCTANONYMOUS({ + uint32_t dword_0; + uint32_t dword_1; + }); +}); + +// XE_GPU_REG_SHADER_CONSTANT_FETCH_* +XEPACKEDUNION(xe_gpu_texture_fetch_t, { + XEPACKEDSTRUCTANONYMOUS({ + uint32_t type : 2; // dword_0 + uint32_t sign_x : 2; + uint32_t sign_y : 2; + uint32_t sign_z : 2; + uint32_t sign_w : 2; + uint32_t clamp_x : 3; + uint32_t clamp_y : 3; + uint32_t clamp_z : 3; + uint32_t unk0 : 3; + uint32_t pitch : 9; + uint32_t tiled : 1; + uint32_t format : 6; // dword_1 + uint32_t endianness : 2; + uint32_t unk1 : 4; + uint32_t address : 20; + union { // dword_2 + struct { + uint32_t width : 24; + uint32_t unused : 8; + } size_1d; + struct { + uint32_t width : 13; + uint32_t height : 13; + uint32_t unused : 6; + } size_2d; + struct { + uint32_t width : 13; + uint32_t height : 13; + uint32_t depth : 6; + } size_stack; + struct { + uint32_t width : 11; + uint32_t height : 11; + uint32_t depth : 10; + } size_3d; + }; + uint32_t unk3_0 : 1; // dword_3 + uint32_t swizzle : 12; // xyzw, 3b each (XE_GPU_SWIZZLE) + uint32_t unk3_1 : 6; + uint32_t mag_filter : 2; + uint32_t min_filter : 2; + uint32_t mip_filter : 2; + uint32_t unk3_2 : 6; + uint32_t border : 1; + uint32_t unk4; // dword_4 + uint32_t unk5 : 9; // dword_5 + uint32_t dimension : 2; + uint32_t unk5b : 21; + }); + XEPACKEDSTRUCTANONYMOUS({ + uint32_t dword_0; + uint32_t dword_1; + uint32_t dword_2; + uint32_t dword_3; + uint32_t dword_4; + uint32_t dword_5; + }); +}); + +// XE_GPU_REG_SHADER_CONSTANT_FETCH_* +XEPACKEDUNION(xe_gpu_fetch_group_t, { + xe_gpu_texture_fetch_t texture_fetch; + XEPACKEDSTRUCTANONYMOUS({ + xe_gpu_vertex_fetch_t vertex_fetch_0; + xe_gpu_vertex_fetch_t vertex_fetch_1; + xe_gpu_vertex_fetch_t vertex_fetch_2; + }); + XEPACKEDSTRUCTANONYMOUS({ + uint32_t dword_0; + uint32_t dword_1; + uint32_t dword_2; + uint32_t dword_3; + uint32_t dword_4; + uint32_t dword_5; + }); + XEPACKEDSTRUCTANONYMOUS({ + uint32_t type_0 : 2; + uint32_t : 30; + uint32_t : 32; + uint32_t type_1 : 2; + uint32_t : 30; + uint32_t : 32; + uint32_t type_2 : 2; + uint32_t : 30; + uint32_t : 32; + }); +}); + +// Opcodes (IT_OPCODE) for Type-3 commands in the ringbuffer. +// https://github.com/freedreno/amd-gpu/blob/master/include/api/gsl_pm4types.h +// Not sure if all of these are used. +enum Type3Opcode { + PM4_ME_INIT = 0x48, // initialize CP's micro-engine + + PM4_NOP = 0x10, // skip N 32-bit words to get to the next packet + + PM4_INDIRECT_BUFFER = 0x3f, // indirect buffer dispatch. prefetch parser uses this packet type to determine whether to pre-fetch the IB + PM4_INDIRECT_BUFFER_PFD = 0x37, // indirect buffer dispatch. same as IB, but init is pipelined + + PM4_WAIT_FOR_IDLE = 0x26, // wait for the IDLE state of the engine + PM4_WAIT_REG_MEM = 0x3c, // wait until a register or memory location is a specific value + PM4_WAIT_REG_EQ = 0x52, // wait until a register location is equal to a specific value + PM4_WAT_REG_GTE = 0x53, // wait until a register location is >= a specific value + PM4_WAIT_UNTIL_READ = 0x5c, // wait until a read completes + PM4_WAIT_IB_PFD_COMPLETE = 0x5d, // wait until all base/size writes from an IB_PFD packet have completed + + PM4_REG_RMW = 0x21, // register read/modify/write + PM4_REG_TO_MEM = 0x3e, // reads register in chip and writes to memory + PM4_MEM_WRITE = 0x3d, // write N 32-bit words to memory + PM4_MEM_WRITE_CNTR = 0x4f, // write CP_PROG_COUNTER value to memory + PM4_COND_EXEC = 0x44, // conditional execution of a sequence of packets + PM4_COND_WRITE = 0x45, // conditional write to memory or register + + PM4_EVENT_WRITE = 0x46, // generate an event that creates a write to memory when completed + PM4_EVENT_WRITE_SHD = 0x58, // generate a VS|PS_done event + PM4_EVENT_WRITE_CFL = 0x59, // generate a cache flush done event + PM4_EVENT_WRITE_ZPD = 0x5b, // generate a z_pass done event + + PM4_DRAW_INDX = 0x22, // initiate fetch of index buffer and draw + PM4_DRAW_INDX_2 = 0x36, // draw using supplied indices in packet + PM4_DRAW_INDX_BIN = 0x34, // initiate fetch of index buffer and binIDs and draw + PM4_DRAW_INDX_2_BIN = 0x35, // initiate fetch of bin IDs and draw using supplied indices + + PM4_VIZ_QUERY = 0x23, // begin/end initiator for viz query extent processing + PM4_SET_STATE = 0x25, // fetch state sub-blocks and initiate shader code DMAs + PM4_SET_CONSTANT = 0x2d, // load constant into chip and to memory + PM4_LOAD_ALU_CONSTANT = 0x2f, // load constants from memory + PM4_IM_LOAD = 0x27, // load sequencer instruction memory (pointer-based) + PM4_IM_LOAD_IMMEDIATE = 0x2b, // load sequencer instruction memory (code embedded in packet) + PM4_LOAD_CONSTANT_CONTEXT = 0x2e, // load constants from a location in memory + PM4_INVALIDATE_STATE = 0x3b, // selective invalidation of state pointers + + PM4_SET_SHADER_BASES = 0x4A, // dynamically changes shader instruction memory partition + PM4_SET_BIN_BASE_OFFSET = 0x4B, // program an offset that will added to the BIN_BASE value of the 3D_DRAW_INDX_BIN packet + PM4_SET_BIN_MASK = 0x50, // sets the 64-bit BIN_MASK register in the PFP + PM4_SET_BIN_SELECT = 0x51, // sets the 64-bit BIN_SELECT register in the PFP + + PM4_CONTEXT_UPDATE = 0x5e, // updates the current context, if needed + PM4_INTERRUPT = 0x54, // generate interrupt from the command stream + + PM4_XE_SWAP = 0x55, // Xenia only: VdSwap uses this to trigger a swap. + + PM4_IM_STORE = 0x2c, // copy sequencer instruction memory to system memory + + // Tiled rendering: + // https://www.google.com/patents/US20060055701 + PM4_SET_BIN_MASK_LO = 0x60, + PM4_SET_BIN_MASK_HI = 0x61, + PM4_SET_BIN_SELECT_LO = 0x62, + PM4_SET_BIN_SELECT_HI = 0x63, +}; + +} // namespace xenos +} // namespace gpu +} // namespace xe + +#endif // XENIA_GPU_XENOS_H_ diff --git a/src/xenia/gpu/xenos/packets.h b/src/xenia/gpu/xenos/packets.h deleted file mode 100644 index 492b836bb..000000000 --- a/src/xenia/gpu/xenos/packets.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef XENIA_GPU_XENOS_PACKETS_H_ -#define XENIA_GPU_XENOS_PACKETS_H_ - -#include - -namespace xe { -namespace gpu { -namespace xenos { - -// Opcodes (IT_OPCODE) for Type-3 commands in the ringbuffer. -// https://github.com/freedreno/amd-gpu/blob/master/include/api/gsl_pm4types.h -// Not sure if all of these are used. -enum Type3Opcode { - PM4_ME_INIT = 0x48, // initialize CP's micro-engine - - PM4_NOP = 0x10, // skip N 32-bit words to get to the next packet - - PM4_INDIRECT_BUFFER = 0x3f, // indirect buffer dispatch. prefetch parser uses this packet type to determine whether to pre-fetch the IB - PM4_INDIRECT_BUFFER_PFD = 0x37, // indirect buffer dispatch. same as IB, but init is pipelined - - PM4_WAIT_FOR_IDLE = 0x26, // wait for the IDLE state of the engine - PM4_WAIT_REG_MEM = 0x3c, // wait until a register or memory location is a specific value - PM4_WAIT_REG_EQ = 0x52, // wait until a register location is equal to a specific value - PM4_WAT_REG_GTE = 0x53, // wait until a register location is >= a specific value - PM4_WAIT_UNTIL_READ = 0x5c, // wait until a read completes - PM4_WAIT_IB_PFD_COMPLETE = 0x5d, // wait until all base/size writes from an IB_PFD packet have completed - - PM4_REG_RMW = 0x21, // register read/modify/write - PM4_REG_TO_MEM = 0x3e, // reads register in chip and writes to memory - PM4_MEM_WRITE = 0x3d, // write N 32-bit words to memory - PM4_MEM_WRITE_CNTR = 0x4f, // write CP_PROG_COUNTER value to memory - PM4_COND_EXEC = 0x44, // conditional execution of a sequence of packets - PM4_COND_WRITE = 0x45, // conditional write to memory or register - - PM4_EVENT_WRITE = 0x46, // generate an event that creates a write to memory when completed - PM4_EVENT_WRITE_SHD = 0x58, // generate a VS|PS_done event - PM4_EVENT_WRITE_CFL = 0x59, // generate a cache flush done event - PM4_EVENT_WRITE_ZPD = 0x5b, // generate a z_pass done event - - PM4_DRAW_INDX = 0x22, // initiate fetch of index buffer and draw - PM4_DRAW_INDX_2 = 0x36, // draw using supplied indices in packet - PM4_DRAW_INDX_BIN = 0x34, // initiate fetch of index buffer and binIDs and draw - PM4_DRAW_INDX_2_BIN = 0x35, // initiate fetch of bin IDs and draw using supplied indices - - PM4_VIZ_QUERY = 0x23, // begin/end initiator for viz query extent processing - PM4_SET_STATE = 0x25, // fetch state sub-blocks and initiate shader code DMAs - PM4_SET_CONSTANT = 0x2d, // load constant into chip and to memory - PM4_LOAD_ALU_CONSTANT = 0x2f, // load constants from memory - PM4_IM_LOAD = 0x27, // load sequencer instruction memory (pointer-based) - PM4_IM_LOAD_IMMEDIATE = 0x2b, // load sequencer instruction memory (code embedded in packet) - PM4_LOAD_CONSTANT_CONTEXT = 0x2e, // load constants from a location in memory - PM4_INVALIDATE_STATE = 0x3b, // selective invalidation of state pointers - - PM4_SET_SHADER_BASES = 0x4A, // dynamically changes shader instruction memory partition - PM4_SET_BIN_BASE_OFFSET = 0x4B, // program an offset that will added to the BIN_BASE value of the 3D_DRAW_INDX_BIN packet - PM4_SET_BIN_MASK = 0x50, // sets the 64-bit BIN_MASK register in the PFP - PM4_SET_BIN_SELECT = 0x51, // sets the 64-bit BIN_SELECT register in the PFP - - PM4_CONTEXT_UPDATE = 0x5e, // updates the current context, if needed - PM4_INTERRUPT = 0x54, // generate interrupt from the command stream - - PM4_XE_SWAP = 0x55, // Xenia only: VdSwap uses this to trigger a swap. - - PM4_IM_STORE = 0x2c, // copy sequencer instruction memory to system memory - - // Tiled rendering: - // https://www.google.com/patents/US20060055701 - PM4_SET_BIN_MASK_LO = 0x60, - PM4_SET_BIN_MASK_HI = 0x61, - PM4_SET_BIN_SELECT_LO = 0x62, - PM4_SET_BIN_SELECT_HI = 0x63, -}; - -} // namespace xenos -} // namespace gpu -} // namespace xe - -#endif // XENIA_GPU_XENOS_PACKETS_H_ diff --git a/src/xenia/gpu/xenos/sources.gypi b/src/xenia/gpu/xenos/sources.gypi deleted file mode 100644 index 998444938..000000000 --- a/src/xenia/gpu/xenos/sources.gypi +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright 2013 Ben Vanik. All Rights Reserved. -{ - 'sources': [ - 'packets.h', - 'register_table.inc', - 'ucode.h', - 'ucode_disassembler.cc', - 'ucode_disassembler.h', - 'xenos.h', - ], -} diff --git a/src/xenia/kernel/xboxkrnl_video.cc b/src/xenia/kernel/xboxkrnl_video.cc index 3d00a9b30..e21d02ace 100644 --- a/src/xenia/kernel/xboxkrnl_video.cc +++ b/src/xenia/kernel/xboxkrnl_video.cc @@ -10,8 +10,8 @@ #include #include #include -#include -#include +#include +#include #include #include #include diff --git a/src/xenia/ui/main_window.cc b/src/xenia/ui/main_window.cc index 235c4c557..b8f4a4ac5 100644 --- a/src/xenia/ui/main_window.cc +++ b/src/xenia/ui/main_window.cc @@ -10,30 +10,68 @@ #include #include +#include namespace xe { namespace ui { -MainWindow::MainWindow() : PlatformWindow(L"xenia") {} +MainWindow::MainWindow(Emulator* emulator) + : PlatformWindow(L"xenia"), emulator_(emulator) {} -MainWindow::~MainWindow() {} +MainWindow::~MainWindow() = default; void MainWindow::Start() { - loop_.Post([this]() { + poly::threading::Fence fence; + + loop_.Post([&]() { if (!Initialize()) { PFATAL("Failed to initialize main window"); exit(1); } + + fence.Signal(); }); + + fence.Wait(); } bool MainWindow::Initialize() { - if (!Window::Initialize()) { + if (!PlatformWindow::Initialize()) { return false; } - // + Resize(1280, 720); return true; } +void MainWindow::OnClose() { + loop_.Quit(); + + // TODO(benvanik): proper exit. + PLOGI("User-initiated death!"); + exit(1); +} + +X_STATUS MainWindow::LaunchPath(std::wstring path) { + X_STATUS result; + + // Launch based on file type. + // This is a silly guess based on file extension. + // NOTE: this blocks! + auto file_system_type = emulator_->file_system()->InferType(path); + switch (file_system_type) { + case kernel::fs::FileSystemType::STFS_TITLE: + result = emulator_->LaunchSTFSTitle(path); + break; + case kernel::fs::FileSystemType::XEX_FILE: + result = emulator_->LaunchXexFile(path); + break; + case kernel::fs::FileSystemType::DISC_IMAGE: + result = emulator_->LaunchDiscImage(path); + break; + } + + return result; +} + } // namespace ui } // namespace xe diff --git a/src/xenia/ui/main_window.h b/src/xenia/ui/main_window.h index 49b75a0f4..a6eb4e533 100644 --- a/src/xenia/ui/main_window.h +++ b/src/xenia/ui/main_window.h @@ -11,6 +11,7 @@ #define XENIA_UI_MAIN_WINDOW_H_ #include +#include // TODO(benvanik): only on windows. #include @@ -24,16 +25,22 @@ using PlatformWindow = poly::ui::win32::Win32Window; class MainWindow : public PlatformWindow { public: - MainWindow(); - ~MainWindow(); + explicit MainWindow(Emulator* emulator); + ~MainWindow() override; + Emulator* emulator() const { return emulator_; } PlatformLoop* loop() { return &loop_; } void Start(); + X_STATUS LaunchPath(std::wstring path); + private: bool Initialize(); + void OnClose() override; + + Emulator* emulator_; PlatformLoop loop_; }; diff --git a/src/xenia/xenia_main.cc b/src/xenia/xenia_main.cc index 83a1a8241..165607bcc 100644 --- a/src/xenia/xenia_main.cc +++ b/src/xenia/xenia_main.cc @@ -11,33 +11,16 @@ #include #include #include - -using namespace xe; +#include DEFINE_string(target, "", "Specifies the target .xex or .iso to execute."); +namespace xe { + int xenia_main(std::vector& args) { Profiler::Initialize(); Profiler::ThreadEnter("main"); - // Grab path from the flag or unnamed argument. - if (!FLAGS_target.size() && args.size() < 2) { - google::ShowUsageWithFlags("xenia"); - PFATAL("Pass a file to launch."); - return 1; - } - std::wstring path; - if (FLAGS_target.size()) { - // Passed as a named argument. - // TODO(benvanik): find something better than gflags that supports unicode. - path = poly::to_wstring(FLAGS_target); - } else { - // Passed as an unnamed argument. - path = args[1]; - } - // Normalize the path and make absolute. - std::wstring abs_path = poly::to_absolute_path(path); - // Create the emulator. auto emulator = std::make_unique(L""); X_STATUS result = emulator->Setup(); @@ -46,29 +29,37 @@ int xenia_main(std::vector& args) { return 1; } - // Launch based on file type. - // This is a silly guess based on file extension. - auto file_system_type = emulator->file_system()->InferType(abs_path); - switch (file_system_type) { - case kernel::fs::FileSystemType::STFS_TITLE: - result = emulator->LaunchSTFSTitle(abs_path); - break; - case kernel::fs::FileSystemType::XEX_FILE: - result = emulator->LaunchXexFile(abs_path); - break; - case kernel::fs::FileSystemType::DISC_IMAGE: - result = emulator->LaunchDiscImage(abs_path); - break; - } - if (XFAILED(result)) { - XELOGE("Failed to launch target: %.8X", result); - return 1; + // Grab path from the flag or unnamed argument. + if (FLAGS_target.size() && args.size() >= 2) { + std::wstring path; + if (FLAGS_target.size()) { + // Passed as a named argument. + // TODO(benvanik): find something better than gflags that supports + // unicode. + path = poly::to_wstring(FLAGS_target); + } else { + // Passed as an unnamed argument. + path = args[1]; + } + // Normalize the path and make absolute. + std::wstring abs_path = poly::to_absolute_path(path); + + result = emulator->main_window()->LaunchPath(abs_path); + if (XFAILED(result)) { + XELOGE("Failed to launch target: %.8X", result); + return 1; + } } + // Wait until we are exited. + emulator->main_window()->loop()->AwaitQuit(); + emulator.reset(); Profiler::Dump(); Profiler::Shutdown(); return 0; } -DEFINE_ENTRY_POINT(L"xenia", L"xenia some.xex", xenia_main); +} // namespace xe + +DEFINE_ENTRY_POINT(L"xenia", L"xenia some.xex", xe::xenia_main);