From 55fe3aca057792c6d3740849368b91a2978e58d6 Mon Sep 17 00:00:00 2001
From: Ben Vanik <ben.vanik@gmail.com>
Date: Sun, 19 Jan 2014 11:07:12 -0800
Subject: [PATCH] RECIP_IEEE.

---
 docs/gpu.md                         | 10 ++++++++++
 src/xenia/gpu/d3d11/d3d11_shader.cc | 20 +++++++++++++++++++-
 2 files changed, 29 insertions(+), 1 deletion(-)
 create mode 100644 docs/gpu.md

diff --git a/docs/gpu.md b/docs/gpu.md
new file mode 100644
index 000000000..077f55522
--- /dev/null
+++ b/docs/gpu.md
@@ -0,0 +1,10 @@
+# GPU Documentation
+
+## References
+
+### Command Buffer/Registers
+
+### Shaders
+
+* [LLVM R600 Tables](https://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600Instructions.td)
+** The opcode formats don't match, but the name->psuedo code is correct.
diff --git a/src/xenia/gpu/d3d11/d3d11_shader.cc b/src/xenia/gpu/d3d11/d3d11_shader.cc
index 62e0d9c70..557d00a7f 100644
--- a/src/xenia/gpu/d3d11/d3d11_shader.cc
+++ b/src/xenia/gpu/d3d11/d3d11_shader.cc
@@ -1242,6 +1242,24 @@ int TranslateALU_SETNEs(
   return TranslateALU_SETXXs(ctx, alu, "!=");
 }
 
+int TranslateALU_RECIP_IEEE(
+    xe_gpu_translate_ctx_t& ctx, const instr_alu_t& alu) {
+  AppendDestReg(ctx, alu.scalar_dest, alu.scalar_write_mask, alu.export_data);
+  ctx.output->append(" = ");
+  if (alu.scalar_clamp) {
+    ctx.output->append("saturate(");
+  }
+  ctx.output->append("(1.0 / ");
+  AppendSrcReg(ctx, alu.src3_reg, alu.src3_sel, alu.src3_swiz, alu.src3_reg_negate, alu.src3_reg_abs);
+  ctx.output->append(")");
+  if (alu.scalar_clamp) {
+    ctx.output->append(")");
+  }
+  ctx.output->append(";\n");
+  AppendDestRegPost(ctx, alu.scalar_dest, alu.scalar_write_mask, alu.export_data);
+  return 0;
+}
+
 int TranslateALU_MUL_CONST_0(
     xe_gpu_translate_ctx_t& ctx, const instr_alu_t& alu) {
   AppendDestReg(ctx, alu.scalar_dest, alu.scalar_write_mask, alu.export_data);
@@ -1392,7 +1410,7 @@ static xe_gpu_translate_alu_info_t scalar_alu_instrs[0x40] = {
   ALU_INSTR(LOG_IEEE,           1),  // 16
   ALU_INSTR(RECIP_CLAMP,        1),  // 17
   ALU_INSTR(RECIP_FF,           1),  // 18
-  ALU_INSTR(RECIP_IEEE,         1),  // 19
+  ALU_INSTR_IMPL(RECIP_IEEE,         1),  // 19
   ALU_INSTR(RECIPSQ_CLAMP,      1),  // 20
   ALU_INSTR(RECIPSQ_FF,         1),  // 21
   ALU_INSTR(RECIPSQ_IEEE,       1),  // 22