diff --git a/src/xenia/cpu/frontend/ppc_emit_altivec.cc b/src/xenia/cpu/frontend/ppc_emit_altivec.cc
index a9949f9e1..df29d2091 100644
--- a/src/xenia/cpu/frontend/ppc_emit_altivec.cc
+++ b/src/xenia/cpu/frontend/ppc_emit_altivec.cc
@@ -1470,8 +1470,9 @@ XEEMITTER(vsldoi128, VX128_5(4, 16), VX128_5)(PPCHIRBuilder& f, InstrData& i) {
 int InstrEmit_vslo_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
   // (VD) <- (VA) << (VB.b[F] & 0x78) (by octet)
   // TODO(benvanik): flag for shift-by-octet as optimization.
-  Value* sh =
-      f.And(f.Extract(f.LoadVR(vb), 15, INT8_TYPE), f.LoadConstantInt8(0x78));
+  Value* sh = f.Shr(
+      f.And(f.Extract(f.LoadVR(vb), 15, INT8_TYPE), f.LoadConstantInt8(0x78)),
+      3);
   Value* v = f.Permute(f.LoadVectorShl(sh), f.LoadVR(va), f.LoadZeroVec128(),
                        INT8_TYPE);
   f.StoreVR(vd, v);
@@ -1622,9 +1623,10 @@ XEEMITTER(vsrh, 0x10000244, VX)(PPCHIRBuilder& f, InstrData& i) {
 int InstrEmit_vsro_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
   // (VD) <- (VA) >> (VB.b[F] & 0x78) (by octet)
   // TODO(benvanik): flag for shift-by-octet as optimization.
-  Value* sh =
-      f.And(f.Extract(f.LoadVR(vb), 15, INT8_TYPE), f.LoadConstantInt8(0x78));
-  Value* v = f.Permute(f.LoadVectorShr(sh), f.LoadVR(va), f.LoadZeroVec128(),
+  Value* sh = f.Shr(
+      f.And(f.Extract(f.LoadVR(vb), 15, INT8_TYPE), f.LoadConstantInt8(0x78)),
+      3);
+  Value* v = f.Permute(f.LoadVectorShr(sh), f.LoadZeroVec128(), f.LoadVR(va),
                        INT8_TYPE);
   f.StoreVR(vd, v);
   return 0;
diff --git a/src/xenia/cpu/frontend/testing/instr_vslo.s b/src/xenia/cpu/frontend/testing/instr_vslo.s
new file mode 100644
index 000000000..34dc03bc8
--- /dev/null
+++ b/src/xenia/cpu/frontend/testing/instr_vslo.s
@@ -0,0 +1,39 @@
+test_vslo_1:
+  #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
+  vslo v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
+
+test_vslo_2:
+  #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_IN v4 [08080808, 08080808, 08080808, 08080808]
+  vslo v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF00]
+  #_ REGISTER_OUT v4 [08080808, 08080808, 08080808, 08080808]
+
+test_vslo_3:
+  #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_IN v4 [12121212, 12121212, 12121212, 12121212]
+  vslo v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF0000]
+  #_ REGISTER_OUT v4 [12121212, 12121212, 12121212, 12121212]
+
+test_vslo_4:
+  #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_IN v4 [80808080, 80808080, 80808080, 80808080]
+  vslo v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v4 [80808080, 80808080, 80808080, 80808080]
+
+test_vslo_5:
+  #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vslo v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FF000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
diff --git a/src/xenia/cpu/frontend/testing/instr_vsro.s b/src/xenia/cpu/frontend/testing/instr_vsro.s
new file mode 100644
index 000000000..4cc52ca1b
--- /dev/null
+++ b/src/xenia/cpu/frontend/testing/instr_vsro.s
@@ -0,0 +1,39 @@
+test_vsro_1:
+  #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
+  vsro v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
+
+test_vsro_2:
+  #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_IN v4 [08080808, 08080808, 08080808, 08080808]
+  vsro v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00001122, 33445566, 778899AA, BBCCDDEE]
+  #_ REGISTER_OUT v4 [08080808, 08080808, 08080808, 08080808]
+
+test_vsro_3:
+  #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_IN v4 [12121212, 12121212, 12121212, 12121212]
+  vsro v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000011, 22334455, 66778899, AABBCCDD]
+  #_ REGISTER_OUT v4 [12121212, 12121212, 12121212, 12121212]
+
+test_vsro_4:
+  #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_IN v4 [80808080, 80808080, 80808080, 80808080]
+  vsro v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v4 [80808080, 80808080, 80808080, 80808080]
+
+test_vsro_5:
+  #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vsro v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]