Generated tests from Rick

src/xenia/cpu/ppc/testing/instr__gen_fabs.s

@@ -0,0 +1,180 @@
+test_fabs_1_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fabs_1_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fabs_2_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fabs_2_cr_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fabs_3_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x0000000000000001
+
+test_fabs_3_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x0000000000000001
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fabs_4_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
+
+test_fabs_4_cr_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fabs_5_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+
+test_fabs_5_cr_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fabs_6_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+
+test_fabs_6_cr_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fabs_7_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0x41E0000000000000
+
+test_fabs_7_cr_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0x41E0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fabs_8_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
+
+test_fabs_8_cr_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fabs_9_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+
+test_fabs_9_cr_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fabs_10_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+
+test_fabs_10_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fabs_11_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+
+test_fabs_11_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fabs_12_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0x7FF4000000000000
+
+test_fabs_12_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0x7FF4000000000000
+  #_ REGISTER_OUT cr 0x00000000
+

src/xenia/cpu/ppc/testing/instr__gen_fcfid.s

@@ -0,0 +1,180 @@
+test_fcfid_1_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fcfid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fcfid_1_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fcfid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fcfid_2_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fcfid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0xC3E0000000000000
+
+test_fcfid_2_cr_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fcfid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0xC3E0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fcfid_3_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fcfid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+
+test_fcfid_3_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fcfid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fcfid_4_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fcfid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x432FFFFFFFFFFFFE
+
+test_fcfid_4_cr_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fcfid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x432FFFFFFFFFFFFE
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fcfid_5_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fcfid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x43CFF80000000000
+
+test_fcfid_5_cr_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fcfid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x43CFF80000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fcfid_6_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fcfid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xC3D0040000000000
+
+test_fcfid_6_cr_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fcfid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xC3D0040000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fcfid_7_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fcfid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xC3CF100000000000
+
+test_fcfid_7_cr_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fcfid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xC3CF100000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fcfid_8_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fcfid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x43D077FFFFFFF000
+
+test_fcfid_8_cr_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fcfid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x43D077FFFFFFF000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fcfid_9_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fcfid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x43DFFC0000000000
+
+test_fcfid_9_cr_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fcfid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x43DFFC0000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fcfid_10_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fcfid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0xC330000000000000
+
+test_fcfid_10_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fcfid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0xC330000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fcfid_11_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fcfid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xC320000000000000
+
+test_fcfid_11_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fcfid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xC320000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fcfid_12_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fcfid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xC328000000000000
+
+test_fcfid_12_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fcfid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xC328000000000000
+  #_ REGISTER_OUT cr 0x00000000
+

src/xenia/cpu/ppc/testing/instr__gen_fctid.s

@@ -0,0 +1,180 @@
+test_fctid_1_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fctid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctid_1_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fctid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctid_2_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fctid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctid_2_cr_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fctid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctid_3_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fctid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctid_3_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fctid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_fctid_4_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fctid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctid_4_cr_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fctid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_fctid_5_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fctid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x0000000000000001
+
+test_fctid_5_cr_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fctid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x0000000000000001
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctid_6_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fctid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFFFFFFFFFF
+
+test_fctid_6_cr_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fctid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctid_7_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fctid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+
+test_fctid_7_cr_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fctid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctid_8_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fctid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x000000007FFFFFFF
+
+test_fctid_8_cr_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fctid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x000000007FFFFFFF
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctid_9_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fctid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x7FFFFFFFFFFFFFFF
+
+test_fctid_9_cr_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fctid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fctid_10_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fctid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+
+test_fctid_10_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fctid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fctid_11_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fctid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+
+test_fctid_11_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fctid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fctid_12_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fctid f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+
+test_fctid_12_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fctid. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+

src/xenia/cpu/ppc/testing/instr__gen_fctidz.s

@@ -0,0 +1,180 @@
+test_fctidz_1_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fctidz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctidz_1_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fctidz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctidz_2_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fctidz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctidz_2_cr_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fctidz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctidz_3_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fctidz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctidz_3_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fctidz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_fctidz_4_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fctidz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctidz_4_cr_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fctidz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_fctidz_5_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fctidz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x0000000000000001
+
+test_fctidz_5_cr_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fctidz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x0000000000000001
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctidz_6_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fctidz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFFFFFFFFFF
+
+test_fctidz_6_cr_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fctidz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctidz_7_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fctidz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+
+test_fctidz_7_cr_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fctidz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctidz_8_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fctidz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x000000007FFFFFFF
+
+test_fctidz_8_cr_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fctidz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x000000007FFFFFFF
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctidz_9_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fctidz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x7FFFFFFFFFFFFFFF
+
+test_fctidz_9_cr_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fctidz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fctidz_10_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fctidz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+
+test_fctidz_10_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fctidz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fctidz_11_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fctidz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+
+test_fctidz_11_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fctidz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fctidz_12_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fctidz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+
+test_fctidz_12_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fctidz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+

src/xenia/cpu/ppc/testing/instr__gen_fctiw.s

@@ -0,0 +1,180 @@
+test_fctiw_1_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fctiw f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctiw_1_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fctiw. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctiw_2_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fctiw f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctiw_2_cr_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fctiw. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctiw_3_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fctiw f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctiw_3_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fctiw. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_fctiw_4_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fctiw f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctiw_4_cr_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fctiw. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_fctiw_5_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fctiw f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x0000000000000001
+
+test_fctiw_5_cr_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fctiw. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x0000000000000001
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctiw_6_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fctiw f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFFFFFFFFFF
+
+test_fctiw_6_cr_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fctiw. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctiw_7_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fctiw f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+
+test_fctiw_7_cr_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fctiw. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctiw_8_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fctiw f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x000000007FFFFFFF
+
+test_fctiw_8_cr_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fctiw. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x000000007FFFFFFF
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctiw_9_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fctiw f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x000000007FFFFFFF
+
+test_fctiw_9_cr_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fctiw. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x000000007FFFFFFF
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fctiw_10_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fctiw f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+
+test_fctiw_10_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fctiw. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fctiw_11_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fctiw f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+
+test_fctiw_11_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fctiw. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fctiw_12_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fctiw f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+
+test_fctiw_12_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fctiw. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+  #_ REGISTER_OUT cr 0x0A000000
+

src/xenia/cpu/ppc/testing/instr__gen_fctiwz.s

@@ -0,0 +1,180 @@
+test_fctiwz_1_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fctiwz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctiwz_1_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fctiwz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctiwz_2_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fctiwz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctiwz_2_cr_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fctiwz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctiwz_3_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fctiwz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctiwz_3_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fctiwz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_fctiwz_4_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fctiwz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fctiwz_4_cr_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fctiwz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_fctiwz_5_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fctiwz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x0000000000000001
+
+test_fctiwz_5_cr_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fctiwz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x0000000000000001
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctiwz_6_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fctiwz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFFFFFFFFFF
+
+test_fctiwz_6_cr_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fctiwz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctiwz_7_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fctiwz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+
+test_fctiwz_7_cr_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fctiwz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctiwz_8_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fctiwz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x000000007FFFFFFF
+
+test_fctiwz_8_cr_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fctiwz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x000000007FFFFFFF
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fctiwz_9_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fctiwz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x000000007FFFFFFF
+
+test_fctiwz_9_cr_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fctiwz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x000000007FFFFFFF
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fctiwz_10_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fctiwz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+
+test_fctiwz_10_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fctiwz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fctiwz_11_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fctiwz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+
+test_fctiwz_11_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fctiwz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fctiwz_12_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fctiwz f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFFFFFFF80000000
+
+test_fctiwz_12_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fctiwz. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+

src/xenia/cpu/ppc/testing/instr__gen_fmr.s

@@ -0,0 +1,180 @@
+test_fmr_1_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fmr f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fmr_1_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fmr. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fmr_2_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fmr f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+
+test_fmr_2_cr_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fmr. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fmr_3_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fmr f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x0000000000000001
+
+test_fmr_3_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fmr. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x0000000000000001
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fmr_4_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fmr f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
+
+test_fmr_4_cr_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fmr. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fmr_5_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fmr f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+
+test_fmr_5_cr_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fmr. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fmr_6_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fmr f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xBFF0000000000000
+
+test_fmr_6_cr_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fmr. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xBFF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fmr_7_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fmr f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xC1E0000000000000
+
+test_fmr_7_cr_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fmr. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xC1E0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fmr_8_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fmr f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
+
+test_fmr_8_cr_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fmr. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fmr_9_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fmr f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+
+test_fmr_9_cr_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fmr. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fmr_10_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fmr f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0xFFF0000000000000
+
+test_fmr_10_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fmr. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0xFFF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fmr_11_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fmr f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFF8000000000000
+
+test_fmr_11_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fmr. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFF8000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fmr_12_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fmr f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFF4000000000000
+
+test_fmr_12_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fmr. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFF4000000000000
+  #_ REGISTER_OUT cr 0x00000000
+

src/xenia/cpu/ppc/testing/instr__gen_fnabs.s

@@ -0,0 +1,180 @@
+test_fnabs_1_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fnabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+
+test_fnabs_1_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fnabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fnabs_2_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fnabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+
+test_fnabs_2_cr_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fnabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fnabs_3_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fnabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x8000000000000001
+
+test_fnabs_3_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fnabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x8000000000000001
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fnabs_4_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fnabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x800FFFFFFFFFFFFF
+
+test_fnabs_4_cr_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fnabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x800FFFFFFFFFFFFF
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fnabs_5_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fnabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0xBFF0000000000000
+
+test_fnabs_5_cr_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fnabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0xBFF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fnabs_6_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fnabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xBFF0000000000000
+
+test_fnabs_6_cr_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fnabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xBFF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fnabs_7_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fnabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xC1E0000000000000
+
+test_fnabs_7_cr_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fnabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xC1E0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fnabs_8_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fnabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0xC1DFFFFFFFC00000
+
+test_fnabs_8_cr_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fnabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0xC1DFFFFFFFC00000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fnabs_9_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fnabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0xFFF0000000000000
+
+test_fnabs_9_cr_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fnabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0xFFF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fnabs_10_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fnabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0xFFF0000000000000
+
+test_fnabs_10_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fnabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0xFFF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fnabs_11_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fnabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFF8000000000000
+
+test_fnabs_11_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fnabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFF8000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fnabs_12_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fnabs f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFF4000000000000
+
+test_fnabs_12_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fnabs. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFF4000000000000
+  #_ REGISTER_OUT cr 0x00000000
+

src/xenia/cpu/ppc/testing/instr__gen_fneg.s

@@ -0,0 +1,180 @@
+test_fneg_1_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fneg f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+
+test_fneg_1_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fneg. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fneg_2_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fneg f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fneg_2_cr_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fneg. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fneg_3_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fneg f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x8000000000000001
+
+test_fneg_3_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fneg. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x8000000000000001
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fneg_4_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fneg f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x800FFFFFFFFFFFFF
+
+test_fneg_4_cr_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fneg. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x800FFFFFFFFFFFFF
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fneg_5_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fneg f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0xBFF0000000000000
+
+test_fneg_5_cr_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fneg. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0xBFF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fneg_6_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fneg f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+
+test_fneg_6_cr_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fneg. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fneg_7_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fneg f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0x41E0000000000000
+
+test_fneg_7_cr_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fneg. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0x41E0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fneg_8_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fneg f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0xC1DFFFFFFFC00000
+
+test_fneg_8_cr_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fneg. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0xC1DFFFFFFFC00000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fneg_9_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fneg f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0xFFF0000000000000
+
+test_fneg_9_cr_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fneg. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0xFFF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fneg_10_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fneg f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+
+test_fneg_10_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fneg. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fneg_11_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fneg f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+
+test_fneg_11_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fneg. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fneg_12_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fneg f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0x7FF4000000000000
+
+test_fneg_12_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fneg. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0x7FF4000000000000
+  #_ REGISTER_OUT cr 0x00000000
+

src/xenia/cpu/ppc/testing/instr__gen_fres.s

@@ -0,0 +1,180 @@
+test_fres_1_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fres f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+
+test_fres_1_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fres. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_fres_2_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fres f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0xFFF0000000000000
+
+test_fres_2_cr_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fres. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0xFFF0000000000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_fres_3_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fres f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+
+test_fres_3_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fres. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+  #_ REGISTER_OUT cr 0x09000000
+
+test_fres_4_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fres f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+
+test_fres_4_cr_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fres. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+  #_ REGISTER_OUT cr 0x09000000
+
+test_fres_5_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fres f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x3FEFE00000000000
+
+test_fres_5_cr_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fres. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x3FEFE00000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fres_6_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fres f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xBFEFE00000000000
+
+test_fres_6_cr_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fres. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xBFEFE00000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fres_7_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fres f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xBDFFE00000000000
+
+test_fres_7_cr_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fres. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xBDFFE00000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fres_8_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fres f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x3E00000000000000
+
+test_fres_8_cr_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fres. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x3E00000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fres_9_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fres f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fres_9_cr_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fres. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fres_10_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fres f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+
+test_fres_10_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fres. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fres_11_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fres f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFF8000000000000
+
+test_fres_11_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fres. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFF8000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fres_12_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fres f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFFC000000000000
+
+test_fres_12_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fres. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFFC000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+

src/xenia/cpu/ppc/testing/instr__gen_frsp.s

@@ -0,0 +1,180 @@
+test_frsp_1_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  frsp f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_frsp_1_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  frsp. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_frsp_2_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  frsp f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+
+test_frsp_2_cr_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  frsp. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_frsp_3_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  frsp f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_frsp_3_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  frsp. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_frsp_4_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  frsp f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_frsp_4_cr_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  frsp. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_frsp_5_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  frsp f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+
+test_frsp_5_cr_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  frsp. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_frsp_6_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  frsp f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xBFF0000000000000
+
+test_frsp_6_cr_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  frsp. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0xBFF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_frsp_7_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  frsp f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xC1E0000000000000
+
+test_frsp_7_cr_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  frsp. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0xC1E0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_frsp_8_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  frsp f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x41E0000000000000
+
+test_frsp_8_cr_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  frsp. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x41E0000000000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_frsp_9_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  frsp f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+
+test_frsp_9_cr_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  frsp. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_frsp_10_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  frsp f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0xFFF0000000000000
+
+test_frsp_10_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  frsp. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0xFFF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_frsp_11_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  frsp f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFF8000000000000
+
+test_frsp_11_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  frsp. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFF8000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_frsp_12_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  frsp f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFFC000000000000
+
+test_frsp_12_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  frsp. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFFC000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+

src/xenia/cpu/ppc/testing/instr__gen_frsqrte.s

@@ -0,0 +1,180 @@
+test_frsqrte_1_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  frsqrte f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+
+test_frsqrte_1_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  frsqrte. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_frsqrte_2_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  frsqrte f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0xFFF0000000000000
+
+test_frsqrte_2_cr_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  frsqrte. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0xFFF0000000000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_frsqrte_3_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  frsqrte f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x617F100000000000
+
+test_frsqrte_3_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  frsqrte. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x617F100000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_frsqrte_4_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  frsqrte f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x5FE0800000000000
+
+test_frsqrte_4_cr_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  frsqrte. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x5FE0800000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_frsqrte_5_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  frsqrte f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x3FEF100000000000
+
+test_frsqrte_5_cr_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  frsqrte. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x3FEF100000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_frsqrte_6_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  frsqrte f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+
+test_frsqrte_6_cr_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  frsqrte. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_frsqrte_7_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  frsqrte f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+
+test_frsqrte_7_cr_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  frsqrte. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_frsqrte_8_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  frsqrte f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x3EF7000000000000
+
+test_frsqrte_8_cr_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  frsqrte. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x3EF7000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_frsqrte_9_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  frsqrte f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_frsqrte_9_cr_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  frsqrte. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_frsqrte_10_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  frsqrte f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+
+test_frsqrte_10_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  frsqrte. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_frsqrte_11_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  frsqrte f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFF8000000000000
+
+test_frsqrte_11_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  frsqrte. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFF8000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_frsqrte_12_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  frsqrte f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFFC000000000000
+
+test_frsqrte_12_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  frsqrte. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFFC000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+

src/xenia/cpu/ppc/testing/instr__gen_fsqrt.s

@@ -0,0 +1,180 @@
+test_fsqrt_1_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fsqrt f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fsqrt_1_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fsqrt. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fsqrt_2_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fsqrt f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+
+test_fsqrt_2_cr_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fsqrt. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fsqrt_3_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fsqrt f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x1E60000000000000
+
+test_fsqrt_3_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fsqrt. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x1E60000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fsqrt_4_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fsqrt f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x1FFFFFFFFFFFFFFF
+
+test_fsqrt_4_cr_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fsqrt. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x1FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT cr 0x08000000
+
+test_fsqrt_5_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fsqrt f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+
+test_fsqrt_5_cr_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fsqrt. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fsqrt_6_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fsqrt f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+
+test_fsqrt_6_cr_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fsqrt. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fsqrt_7_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fsqrt f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+
+test_fsqrt_7_cr_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fsqrt. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fsqrt_8_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fsqrt f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x40E6A09E66689B2E
+
+test_fsqrt_8_cr_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fsqrt. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x40E6A09E66689B2E
+  #_ REGISTER_OUT cr 0x08000000
+
+test_fsqrt_9_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fsqrt f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+
+test_fsqrt_9_cr_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fsqrt. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fsqrt_10_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fsqrt f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+
+test_fsqrt_10_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fsqrt. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fsqrt_11_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fsqrt f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFF8000000000000
+
+test_fsqrt_11_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fsqrt. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFF8000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fsqrt_12_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fsqrt f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFFC000000000000
+
+test_fsqrt_12_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fsqrt. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFFC000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+

src/xenia/cpu/ppc/testing/instr__gen_fsqrts.s

@@ -0,0 +1,180 @@
+test_fsqrts_1_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fsqrts f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+
+test_fsqrts_1_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fsqrts. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000000
+  #_ REGISTER_OUT f2 0x0000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fsqrts_2_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fsqrts f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+
+test_fsqrts_2_cr_GEN:
+  #_ REGISTER_IN f1 0x8000000000000000
+  fsqrts. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x8000000000000000
+  #_ REGISTER_OUT f2 0x8000000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fsqrts_3_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fsqrts f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x1E60000000000000
+
+test_fsqrts_3_cr_GEN:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fsqrts. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x0000000000000001
+  #_ REGISTER_OUT f2 0x1E60000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fsqrts_4_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fsqrts f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x1FFFFFFFFFFFFFFF
+
+test_fsqrts_4_cr_GEN:
+  #_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
+  fsqrts. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
+  #_ REGISTER_OUT f2 0x1FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT cr 0x08000000
+
+test_fsqrts_5_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fsqrts f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+
+test_fsqrts_5_cr_GEN:
+  #_ REGISTER_IN f1 0x3FF0000000000000
+  fsqrts. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x3FF0000000000000
+  #_ REGISTER_OUT f2 0x3FF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fsqrts_6_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fsqrts f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+
+test_fsqrts_6_cr_GEN:
+  #_ REGISTER_IN f1 0xBFF0000000000000
+  fsqrts. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xBFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fsqrts_7_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fsqrts f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+
+test_fsqrts_7_cr_GEN:
+  #_ REGISTER_IN f1 0xC1E0000000000000
+  fsqrts. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xC1E0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fsqrts_8_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fsqrts f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x40E6A09E60000000
+
+test_fsqrts_8_cr_GEN:
+  #_ REGISTER_IN f1 0x41DFFFFFFFC00000
+  fsqrts. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x41DFFFFFFFC00000
+  #_ REGISTER_OUT f2 0x40E6A09E60000000
+  #_ REGISTER_OUT cr 0x08000000
+
+test_fsqrts_9_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fsqrts f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+
+test_fsqrts_9_cr_GEN:
+  #_ REGISTER_IN f1 0x7FF0000000000000
+  fsqrts. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0x7FF0000000000000
+  #_ REGISTER_OUT f2 0x7FF0000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fsqrts_10_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fsqrts f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+
+test_fsqrts_10_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF0000000000000
+  fsqrts. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF0000000000000
+  #_ REGISTER_OUT f2 0x7FF8000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+
+test_fsqrts_11_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fsqrts f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFF8000000000000
+
+test_fsqrts_11_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF8000000000000
+  fsqrts. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF8000000000000
+  #_ REGISTER_OUT f2 0xFFF8000000000000
+  #_ REGISTER_OUT cr 0x00000000
+
+test_fsqrts_12_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fsqrts f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFFC000000000000
+
+test_fsqrts_12_cr_GEN:
+  #_ REGISTER_IN f1 0xFFF4000000000000
+  fsqrts. f2, f1
+  blr
+  #_ REGISTER_OUT f1 0xFFF4000000000000
+  #_ REGISTER_OUT f2 0xFFFC000000000000
+  #_ REGISTER_OUT cr 0x0A000000
+

src/xenia/cpu/ppc/testing/instr__gen_vcfsx.s

@@ -0,0 +1,728 @@
+test_vcfsx_1_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vcfsx_2_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vcfsx_3_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vcfsx_4_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vcfsx_5_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [3F800000, 3F800000, 3F800000, 3F800000]
+
+test_vcfsx_6_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [3F000000, 3F000000, 3F000000, 3F000000]
+
+test_vcfsx_7_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [3E800000, 3E800000, 3E800000, 3E800000]
+
+test_vcfsx_8_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [3C000000, 3C000000, 3C000000, 3C000000]
+
+test_vcfsx_9_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [477FFF00, C7800000, 00000000, C7800000]
+
+test_vcfsx_10_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [46FFFF00, C7000000, 00000000, C7000000]
+
+test_vcfsx_11_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [467FFF00, C6800000, 00000000, C6800000]
+
+test_vcfsx_12_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [43FFFF00, C4000000, 00000000, C4000000]
+
+test_vcfsx_13_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [47810180, 4C80A0C1, 4D0090A1, 4D40D0E1]
+
+test_vcfsx_14_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [47010180, 4C00A0C1, 4C8090A1, 4CC0D0E1]
+
+test_vcfsx_15_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [46810180, 4B80A0C1, 4C0090A1, 4C40D0E1]
+
+test_vcfsx_16_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [44010180, 4900A0C1, 498090A1, 49C0D0E1]
+
+test_vcfsx_17_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [495000D0, 495000D0, 495000D0, 495000D0]
+
+test_vcfsx_18_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [48D000D0, 48D000D0, 48D000D0, 48D000D0]
+
+test_vcfsx_19_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [485000D0, 485000D0, 485000D0, 485000D0]
+
+test_vcfsx_20_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [45D000D0, 45D000D0, 45D000D0, 45D000D0]
+
+test_vcfsx_21_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [49891198, 4E88AACD, CEEECCAB, CE4C8844]
+
+test_vcfsx_22_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [49091198, 4E08AACD, CE6ECCAB, CDCC8844]
+
+test_vcfsx_23_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [48891198, 4D88AACD, CDEECCAB, CD4C8844]
+
+test_vcfsx_24_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [46091198, 4B08AACD, CB6ECCAB, CACC8844]
+
+test_vcfsx_25_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [4B7FFF00, 477F0000, CB7FFF01, C77F0100]
+
+test_vcfsx_26_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [4AFFFF00, 46FF0000, CAFFFF01, C6FF0100]
+
+test_vcfsx_27_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [4A7FFF00, 467F0000, CA7FFF01, C67F0100]
+
+test_vcfsx_28_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [47FFFF00, 43FF0000, C7FFFF01, C3FF0100]
+
+test_vcfsx_29_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [4C808080, 4C808080, 4C808080, 4C808080]
+
+test_vcfsx_30_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [4C008080, 4C008080, 4C008080, 4C008080]
+
+test_vcfsx_31_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [4B808080, 4B808080, 4B808080, 4B808080]
+
+test_vcfsx_32_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [49008080, 49008080, 49008080, 49008080]
+
+test_vcfsx_33_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [4CE0E0E1, 4CE0E0E1, 4CE0E0E1, 4CE0E0E1]
+
+test_vcfsx_34_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [4C60E0E1, 4C60E0E1, 4C60E0E1, 4C60E0E1]
+
+test_vcfsx_35_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [4BE0E0E1, 4BE0E0E1, 4BE0E0E1, 4BE0E0E1]
+
+test_vcfsx_36_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [4960E0E1, 4960E0E1, 4960E0E1, 4960E0E1]
+
+test_vcfsx_37_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [4D008080, 4D008080, 4D008080, 4D008080]
+
+test_vcfsx_38_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [4C808080, 4C808080, 4C808080, 4C808080]
+
+test_vcfsx_39_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [4C008080, 4C008080, 4C008080, 4C008080]
+
+test_vcfsx_40_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [49808080, 49808080, 49808080, 49808080]
+
+test_vcfsx_41_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [4D909091, 4D909091, 4D909091, 4D909091]
+
+test_vcfsx_42_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [4D109091, 4D109091, 4D109091, 4D109091]
+
+test_vcfsx_43_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [4C909091, 4C909091, 4C909091, 4C909091]
+
+test_vcfsx_44_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [4A109091, 4A109091, 4A109091, 4A109091]
+
+test_vcfsx_45_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [4D91A2B4, CEF1357A, 4D89119A, 4EAACCEF]
+
+test_vcfsx_46_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [4D11A2B4, CE71357A, 4D09119A, 4E2ACCEF]
+
+test_vcfsx_47_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [4C91A2B4, CDF1357A, 4C89119A, 4DAACCEF]
+
+test_vcfsx_48_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [4A11A2B4, CB71357A, 4A09119A, 4B2ACCEF]
+
+test_vcfsx_49_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [4E7E0000, 4E7F0000, 4E7E3333, 4E7FCCCD]
+
+test_vcfsx_50_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [4DFE0000, 4DFF0000, 4DFE3333, 4DFFCCCD]
+
+test_vcfsx_51_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [4D7E0000, 4D7F0000, 4D7E3333, 4D7FCCCD]
+
+test_vcfsx_52_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [4AFE0000, 4AFF0000, 4AFE3333, 4AFFCCCD]
+
+test_vcfsx_53_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [4E824000, CE7B8000, 4E82E000, CE7A4000]
+
+test_vcfsx_54_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [4E024000, CDFB8000, 4E02E000, CDFA4000]
+
+test_vcfsx_55_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [4D824000, CD7B8000, 4D82E000, CD7A4000]
+
+test_vcfsx_56_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [4B024000, CAFB8000, 4B02E000, CAFA4000]
+
+test_vcfsx_57_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [4EFF0004, 4C80A0C1, 4EFF0014, 4D40D0E1]
+
+test_vcfsx_58_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [4E7F0004, 4C00A0C1, 4E7F0014, 4CC0D0E1]
+
+test_vcfsx_59_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [4DFF0004, 4B80A0C1, 4DFF0014, 4C40D0E1]
+
+test_vcfsx_60_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [4B7F0004, 4900A0C1, 4B7F0014, 49C0D0E1]
+
+test_vcfsx_61_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [CEFFEFE0, CEFEE200, 4F000000, CEE00000]
+
+test_vcfsx_62_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [CE7FEFE0, CE7EE200, 4E800000, CE600000]
+
+test_vcfsx_63_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [CDFFEFE0, CDFEE200, 4E000000, CDE00000]
+
+test_vcfsx_64_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [CB7FEFE0, CB7EE200, 4B800000, CB600000]
+
+test_vcfsx_65_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [CE810000, CE808000, CE80E666, CE80199A]
+
+test_vcfsx_66_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [CE010000, CE008000, CE00E666, CE00199A]
+
+test_vcfsx_67_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [CD810000, CD808000, CD80E666, CD80199A]
+
+test_vcfsx_68_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [CB010000, CB008000, CB00E666, CB00199A]
+
+test_vcfsx_69_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [CE7B8000, 4E834000, CE798000, 4E83E000]
+
+test_vcfsx_70_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [CDFB8000, 4E034000, CDF98000, 4E03E000]
+
+test_vcfsx_71_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [CD7B8000, 4D834000, CD798000, 4D83E000]
+
+test_vcfsx_72_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [CAFB8000, 4B034000, CAF98000, 4B03E000]
+
+test_vcfsx_73_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [CE48C8C9, CE48C8C9, CE48C8C9, 4C802040]
+
+test_vcfsx_74_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [CDC8C8C9, CDC8C8C9, CDC8C8C9, 4C002040]
+
+test_vcfsx_75_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [CD48C8C9, CD48C8C9, CD48C8C9, 4B802040]
+
+test_vcfsx_76_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [CAC8C8C9, CAC8C8C9, CAC8C8C9, 49002040]
+
+test_vcfsx_77_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [CCE0C0A1, CC408040, 47810180, 4C80A0C1]
+
+test_vcfsx_78_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [CC60C0A1, CBC08040, 47010180, 4C00A0C1]
+
+test_vcfsx_79_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [CBE0C0A1, CB408040, 46810180, 4B80A0C1]
+
+test_vcfsx_80_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [C960C0A1, C8C08040, 44010180, 4900A0C1]
+
+test_vcfsx_81_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [CB808081, CB808081, CB808081, CB808081]
+
+test_vcfsx_82_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [CB008081, CB008081, CB008081, CB008081]
+
+test_vcfsx_83_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [CA808081, CA808081, CA808081, CA808081]
+
+test_vcfsx_84_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [C8008081, C8008081, C8008081, C8008081]
+
+test_vcfsx_85_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [C84000C0, C7800080, 3F800000, 480000C0]
+
+test_vcfsx_86_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [C7C000C0, C7000080, 3F000000, 478000C0]
+
+test_vcfsx_87_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [C74000C0, C6800080, 3E800000, 470000C0]
+
+test_vcfsx_88_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [C4C000C0, C4000080, 3C000000, 448000C0]
+
+test_vcfsx_89_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [C8002080, 48002040, C84020C0, 48402080]
+
+test_vcfsx_90_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [C7802080, 47802040, C7C020C0, 47C02080]
+
+test_vcfsx_91_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [C7002080, 47002040, C74020C0, 47402080]
+
+test_vcfsx_92_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [C4802080, 44802040, C4C020C0, 44C02080]
+
+test_vcfsx_93_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [C77EFF00, 4EE0E200, BF800000, 00000000]
+
+test_vcfsx_94_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [C6FEFF00, 4E60E200, BF000000, 00000000]
+
+test_vcfsx_95_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [C67EFF00, 4DE0E200, BE800000, 00000000]
+
+test_vcfsx_96_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [C3FEFF00, 4B60E200, BC000000, 00000000]
+
+test_vcfsx_97_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [C3000000, 42FE0000, C7804080, 47804000]
+
+test_vcfsx_98_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [C2800000, 427E0000, C7004080, 47004000]
+
+test_vcfsx_99_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [C2000000, 41FE0000, C6804080, 46804000]
+
+test_vcfsx_100_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [BF800000, 3F7E0000, C4004080, 44004000]
+
+test_vcfsx_101_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vcfsx v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [BF800000, BF800000, BF800000, BF800000]
+
+test_vcfsx_102_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vcfsx v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [BF000000, BF000000, BF000000, BF000000]
+
+test_vcfsx_103_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vcfsx v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [BE800000, BE800000, BE800000, BE800000]
+
+test_vcfsx_104_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vcfsx v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [BC000000, BC000000, BC000000, BC000000]
+

src/xenia/cpu/ppc/testing/instr__gen_vcfux.s

@@ -0,0 +1,728 @@
+test_vcfux_1_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vcfux_2_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vcfux_3_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vcfux_4_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vcfux_5_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [3F800000, 3F800000, 3F800000, 3F800000]
+
+test_vcfux_6_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [3F000000, 3F000000, 3F000000, 3F000000]
+
+test_vcfux_7_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [3E800000, 3E800000, 3E800000, 3E800000]
+
+test_vcfux_8_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [3C000000, 3C000000, 3C000000, 3C000000]
+
+test_vcfux_9_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [477FFF00, 4F7FFF00, 00000000, 4F7FFF00]
+
+test_vcfux_10_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [46FFFF00, 4EFFFF00, 00000000, 4EFFFF00]
+
+test_vcfux_11_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [467FFF00, 4E7FFF00, 00000000, 4E7FFF00]
+
+test_vcfux_12_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [43FFFF00, 4BFFFF00, 00000000, 4BFFFF00]
+
+test_vcfux_13_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [47810180, 4C80A0C1, 4D0090A1, 4D40D0E1]
+
+test_vcfux_14_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [47010180, 4C00A0C1, 4C8090A1, 4CC0D0E1]
+
+test_vcfux_15_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [46810180, 4B80A0C1, 4C0090A1, 4C40D0E1]
+
+test_vcfux_16_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [44010180, 4900A0C1, 498090A1, 49C0D0E1]
+
+test_vcfux_17_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [495000D0, 495000D0, 495000D0, 495000D0]
+
+test_vcfux_18_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [48D000D0, 48D000D0, 48D000D0, 48D000D0]
+
+test_vcfux_19_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [485000D0, 485000D0, 485000D0, 485000D0]
+
+test_vcfux_20_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [45D000D0, 45D000D0, 45D000D0, 45D000D0]
+
+test_vcfux_21_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [49891198, 4E88AACD, 4F0899AB, 4F4CDDEF]
+
+test_vcfux_22_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [49091198, 4E08AACD, 4E8899AB, 4ECCDDEF]
+
+test_vcfux_23_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [48891198, 4D88AACD, 4E0899AB, 4E4CDDEF]
+
+test_vcfux_24_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [46091198, 4B08AACD, 4B8899AB, 4BCCDDEF]
+
+test_vcfux_25_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [4B7FFF00, 477F0000, 4F7F0001, 4F7FFF01]
+
+test_vcfux_26_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [4AFFFF00, 46FF0000, 4EFF0001, 4EFFFF01]
+
+test_vcfux_27_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [4A7FFF00, 467F0000, 4E7F0001, 4E7FFF01]
+
+test_vcfux_28_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [47FFFF00, 43FF0000, 4BFF0001, 4BFFFF01]
+
+test_vcfux_29_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [4C808080, 4C808080, 4C808080, 4C808080]
+
+test_vcfux_30_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [4C008080, 4C008080, 4C008080, 4C008080]
+
+test_vcfux_31_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [4B808080, 4B808080, 4B808080, 4B808080]
+
+test_vcfux_32_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [49008080, 49008080, 49008080, 49008080]
+
+test_vcfux_33_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [4CE0E0E1, 4CE0E0E1, 4CE0E0E1, 4CE0E0E1]
+
+test_vcfux_34_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [4C60E0E1, 4C60E0E1, 4C60E0E1, 4C60E0E1]
+
+test_vcfux_35_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [4BE0E0E1, 4BE0E0E1, 4BE0E0E1, 4BE0E0E1]
+
+test_vcfux_36_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [4960E0E1, 4960E0E1, 4960E0E1, 4960E0E1]
+
+test_vcfux_37_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [4D008080, 4D008080, 4D008080, 4D008080]
+
+test_vcfux_38_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [4C808080, 4C808080, 4C808080, 4C808080]
+
+test_vcfux_39_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [4C008080, 4C008080, 4C008080, 4C008080]
+
+test_vcfux_40_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [49808080, 49808080, 49808080, 49808080]
+
+test_vcfux_41_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [4D909091, 4D909091, 4D909091, 4D909091]
+
+test_vcfux_42_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [4D109091, 4D109091, 4D109091, 4D109091]
+
+test_vcfux_43_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [4C909091, 4C909091, 4C909091, 4C909091]
+
+test_vcfux_44_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [4A109091, 4A109091, 4A109091, 4A109091]
+
+test_vcfux_45_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [4D91A2B4, 4F076543, 4D89119A, 4EAACCEF]
+
+test_vcfux_46_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [4D11A2B4, 4E876543, 4D09119A, 4E2ACCEF]
+
+test_vcfux_47_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [4C91A2B4, 4E076543, 4C89119A, 4DAACCEF]
+
+test_vcfux_48_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [4A11A2B4, 4B876543, 4A09119A, 4B2ACCEF]
+
+test_vcfux_49_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [4E7E0000, 4E7F0000, 4E7E3333, 4E7FCCCD]
+
+test_vcfux_50_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [4DFE0000, 4DFF0000, 4DFE3333, 4DFFCCCD]
+
+test_vcfux_51_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [4D7E0000, 4D7F0000, 4D7E3333, 4D7FCCCD]
+
+test_vcfux_52_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [4AFE0000, 4AFF0000, 4AFE3333, 4AFFCCCD]
+
+test_vcfux_53_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [4E824000, 4F412000, 4E82E000, 4F417000]
+
+test_vcfux_54_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [4E024000, 4EC12000, 4E02E000, 4EC17000]
+
+test_vcfux_55_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [4D824000, 4E412000, 4D82E000, 4E417000]
+
+test_vcfux_56_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [4B024000, 4BC12000, 4B02E000, 4BC17000]
+
+test_vcfux_57_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [4EFF0004, 4C80A0C1, 4EFF0014, 4D40D0E1]
+
+test_vcfux_58_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [4E7F0004, 4C00A0C1, 4E7F0014, 4CC0D0E1]
+
+test_vcfux_59_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [4DFF0004, 4B80A0C1, 4DFF0014, 4C40D0E1]
+
+test_vcfux_60_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [4B7F0004, 4900A0C1, 4B7F0014, 49C0D0E1]
+
+test_vcfux_61_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [4F000810, 4F008F00, 4F000000, 4F100000]
+
+test_vcfux_62_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [4E800810, 4E808F00, 4E800000, 4E900000]
+
+test_vcfux_63_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [4E000810, 4E008F00, 4E000000, 4E100000]
+
+test_vcfux_64_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [4B800810, 4B808F00, 4B800000, 4B900000]
+
+test_vcfux_65_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [4F3F8000, 4F3FC000, 4F3F8CCD, 4F3FF333]
+
+test_vcfux_66_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [4EBF8000, 4EBFC000, 4EBF8CCD, 4EBFF333]
+
+test_vcfux_67_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [4E3F8000, 4E3FC000, 4E3F8CCD, 4E3FF333]
+
+test_vcfux_68_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [4BBF8000, 4BBFC000, 4BBF8CCD, 4BBFF333]
+
+test_vcfux_69_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [4F412000, 4E834000, 4F41A000, 4E83E000]
+
+test_vcfux_70_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [4EC12000, 4E034000, 4EC1A000, 4E03E000]
+
+test_vcfux_71_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [4E412000, 4D834000, 4E41A000, 4D83E000]
+
+test_vcfux_72_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [4BC12000, 4B034000, 4BC1A000, 4B03E000]
+
+test_vcfux_73_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [4F4DCDCE, 4F4DCDCE, 4F4DCDCE, 4C802040]
+
+test_vcfux_74_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [4ECDCDCE, 4ECDCDCE, 4ECDCDCE, 4C002040]
+
+test_vcfux_75_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [4E4DCDCE, 4E4DCDCE, 4E4DCDCE, 4B802040]
+
+test_vcfux_76_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [4BCDCDCE, 4BCDCDCE, 4BCDCDCE, 49002040]
+
+test_vcfux_77_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [4F78F9FB, 4F7CFDFF, 47810180, 4C80A0C1]
+
+test_vcfux_78_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [4EF8F9FB, 4EFCFDFF, 47010180, 4C00A0C1]
+
+test_vcfux_79_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [4E78F9FB, 4E7CFDFF, 46810180, 4B80A0C1]
+
+test_vcfux_80_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [4BF8F9FB, 4BFCFDFF, 44010180, 4900A0C1]
+
+test_vcfux_81_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [4F7EFEFF, 4F7EFEFF, 4F7EFEFF, 4F7EFEFF]
+
+test_vcfux_82_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [4EFEFEFF, 4EFEFEFF, 4EFEFEFF, 4EFEFEFF]
+
+test_vcfux_83_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [4E7EFEFF, 4E7EFEFF, 4E7EFEFF, 4E7EFEFF]
+
+test_vcfux_84_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [4BFEFEFF, 4BFEFEFF, 4BFEFEFF, 4BFEFEFF]
+
+test_vcfux_85_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [4F7FFD00, 4F7FFF00, 3F800000, 480000C0]
+
+test_vcfux_86_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [4EFFFD00, 4EFFFF00, 3F000000, 478000C0]
+
+test_vcfux_87_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [4E7FFD00, 4E7FFF00, 3E800000, 470000C0]
+
+test_vcfux_88_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [4BFFFD00, 4BFFFF00, 3C000000, 448000C0]
+
+test_vcfux_89_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [4F7FFDFF, 48002040, 4F7FFCFF, 48402080]
+
+test_vcfux_90_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [4EFFFDFF, 47802040, 4EFFFCFF, 47C02080]
+
+test_vcfux_91_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [4E7FFDFF, 47002040, 4E7FFCFF, 47402080]
+
+test_vcfux_92_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [4BFFFDFF, 44802040, 4BFFFCFF, 44C02080]
+
+test_vcfux_93_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [4F7FFF01, 4EE0E200, 4F800000, 00000000]
+
+test_vcfux_94_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [4EFFFF01, 4E60E200, 4F000000, 00000000]
+
+test_vcfux_95_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [4E7FFF01, 4DE0E200, 4E800000, 00000000]
+
+test_vcfux_96_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [4BFFFF01, 4B60E200, 4C000000, 00000000]
+
+test_vcfux_97_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [4F800000, 42FE0000, 4F7FFEFF, 47804000]
+
+test_vcfux_98_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [4F000000, 427E0000, 4EFFFEFF, 47004000]
+
+test_vcfux_99_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [4E800000, 41FE0000, 4E7FFEFF, 46804000]
+
+test_vcfux_100_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [4C000000, 3F7E0000, 4BFFFEFF, 44004000]
+
+test_vcfux_101_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vcfux v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [4F800000, 4F800000, 4F800000, 4F800000]
+
+test_vcfux_102_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vcfux v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [4F000000, 4F000000, 4F000000, 4F000000]
+
+test_vcfux_103_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vcfux v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [4E800000, 4E800000, 4E800000, 4E800000]
+
+test_vcfux_104_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vcfux v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [4C000000, 4C000000, 4C000000, 4C000000]
+

src/xenia/cpu/ppc/testing/instr__gen_vctsxs.s

@@ -0,0 +1,728 @@
+test_vctsxs_1_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_2_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_3_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_4_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_5_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_6_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_7_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_8_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_9_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_10_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_11_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_12_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_13_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_14_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_15_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_16_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_17_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_18_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_19_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_20_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_21_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [00000000, 00000355, 00000000, F9108808]
+
+test_vctsxs_22_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [00000000, 000006AB, 00000000, F2211010]
+
+test_vctsxs_23_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [00000000, 00000D56, 00000000, E4422020]
+
+test_vctsxs_24_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [00000000, 0001AACC, 00000000, 80000000]
+
+test_vctsxs_25_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 80000000, 00000000]
+
+test_vctsxs_26_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 80000000, 00000000]
+
+test_vctsxs_27_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 80000000, 00000000]
+
+test_vctsxs_28_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 80000000, 00000000]
+
+test_vctsxs_29_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_30_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_31_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_32_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_33_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_34_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_35_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_36_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_37_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_38_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_39_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_40_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_41_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_42_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_43_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_44_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_45_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 7FFFFFFF]
+
+test_vctsxs_46_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 7FFFFFFF]
+
+test_vctsxs_47_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 7FFFFFFF]
+
+test_vctsxs_48_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 7FFFFFFF]
+
+test_vctsxs_49_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
+
+test_vctsxs_50_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [00000002, 00000003, 00000002, 00000003]
+
+test_vctsxs_51_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [00000004, 00000006, 00000004, 00000007]
+
+test_vctsxs_52_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [00000080, 000000C0, 0000008C, 000000F3]
+
+test_vctsxs_53_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [0000000A, FFFFFFF6, 0000000F, FFFFFFF1]
+
+test_vctsxs_54_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [00000014, FFFFFFEC, 0000001E, FFFFFFE2]
+
+test_vctsxs_55_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [00000028, FFFFFFD8, 0000003C, FFFFFFC4]
+
+test_vctsxs_56_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [00000500, FFFFFB00, 00000780, FFFFF880]
+
+test_vctsxs_57_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_58_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_59_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_60_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_61_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_62_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_63_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_64_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_65_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vctsxs_66_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [FFFFFFFE, FFFFFFFD, FFFFFFFE, FFFFFFFD]
+
+test_vctsxs_67_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [FFFFFFFC, FFFFFFFA, FFFFFFFC, FFFFFFF9]
+
+test_vctsxs_68_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [FFFFFF80, FFFFFF40, FFFFFF74, FFFFFF0D]
+
+test_vctsxs_69_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [FFFFFFF6, 00000014, FFFFFFEC, 0000001E]
+
+test_vctsxs_70_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [FFFFFFEC, 00000028, FFFFFFD8, 0000003C]
+
+test_vctsxs_71_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [FFFFFFD8, 00000050, FFFFFFB0, 00000078]
+
+test_vctsxs_72_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [FFFFFB00, 00000A00, FFFFF600, 00000F00]
+
+test_vctsxs_73_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [E6464660, E6464660, E6464660, 00000000]
+
+test_vctsxs_74_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [CC8C8CC0, CC8C8CC0, CC8C8CC0, 00000000]
+
+test_vctsxs_75_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [99191980, 99191980, 99191980, 00000000]
+
+test_vctsxs_76_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [80000000, 80000000, 80000000, 00000000]
+
+test_vctsxs_77_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [80000000, 80000000, 00000000, 00000000]
+
+test_vctsxs_78_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [80000000, 80000000, 00000000, 00000000]
+
+test_vctsxs_79_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [80000000, 80000000, 00000000, 00000000]
+
+test_vctsxs_80_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [80000000, 80000000, 00000000, 00000000]
+
+test_vctsxs_81_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [80000000, 80000000, 80000000, 80000000]
+
+test_vctsxs_82_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [80000000, 80000000, 80000000, 80000000]
+
+test_vctsxs_83_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [80000000, 80000000, 80000000, 80000000]
+
+test_vctsxs_84_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [80000000, 80000000, 80000000, 80000000]
+
+test_vctsxs_85_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_86_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_87_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_88_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_89_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_90_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_91_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_92_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_93_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 7FFFFFFF, 00000000, 00000000]
+
+test_vctsxs_94_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 7FFFFFFF, 00000000, 00000000]
+
+test_vctsxs_95_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 7FFFFFFF, 00000000, 00000000]
+
+test_vctsxs_96_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 7FFFFFFF, 00000000, 00000000]
+
+test_vctsxs_97_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_98_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_99_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_100_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_101_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vctsxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_102_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vctsxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_103_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vctsxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctsxs_104_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vctsxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+

src/xenia/cpu/ppc/testing/instr__gen_vctuxs.s

@@ -0,0 +1,728 @@
+test_vctuxs_1_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_2_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_3_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_4_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_5_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_6_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_7_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_8_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_9_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_10_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_11_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_12_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_13_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_14_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_15_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_16_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_17_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_18_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_19_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_20_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_21_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [00000000, 00000355, 00000000, 00000000]
+
+test_vctuxs_22_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [00000000, 000006AB, 00000000, 00000000]
+
+test_vctuxs_23_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [00000000, 00000D56, 00000000, 00000000]
+
+test_vctuxs_24_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [00000000, 0001AACC, 00000000, 00000000]
+
+test_vctuxs_25_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_26_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_27_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_28_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_29_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_30_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_31_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_32_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_33_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_34_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_35_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_36_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_37_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_38_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_39_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_40_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_41_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_42_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_43_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_44_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_45_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, FFFFFFFF]
+
+test_vctuxs_46_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, FFFFFFFF]
+
+test_vctuxs_47_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, FFFFFFFF]
+
+test_vctuxs_48_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, FFFFFFFF]
+
+test_vctuxs_49_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
+
+test_vctuxs_50_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [00000002, 00000003, 00000002, 00000003]
+
+test_vctuxs_51_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [00000004, 00000006, 00000004, 00000007]
+
+test_vctuxs_52_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [00000080, 000000C0, 0000008C, 000000F3]
+
+test_vctuxs_53_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [0000000A, 00000000, 0000000F, 00000000]
+
+test_vctuxs_54_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [00000014, 00000000, 0000001E, 00000000]
+
+test_vctuxs_55_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [00000028, 00000000, 0000003C, 00000000]
+
+test_vctuxs_56_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [00000500, 00000000, 00000780, 00000000]
+
+test_vctuxs_57_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_58_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_59_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_60_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_61_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_62_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_63_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_64_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_65_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_66_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_67_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_68_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_69_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [00000000, 00000014, 00000000, 0000001E]
+
+test_vctuxs_70_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [00000000, 00000028, 00000000, 0000003C]
+
+test_vctuxs_71_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [00000000, 00000050, 00000000, 00000078]
+
+test_vctuxs_72_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [00000000, 00000A00, 00000000, 00000F00]
+
+test_vctuxs_73_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_74_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_75_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_76_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_77_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_78_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_79_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_80_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_81_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_82_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_83_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_84_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_85_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_86_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_87_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_88_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_89_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_90_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_91_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_92_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_93_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [00000000, FFFFFFFF, 00000000, 00000000]
+
+test_vctuxs_94_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [00000000, FFFFFFFF, 00000000, 00000000]
+
+test_vctuxs_95_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [00000000, FFFFFFFF, 00000000, 00000000]
+
+test_vctuxs_96_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [00000000, FFFFFFFF, 00000000, 00000000]
+
+test_vctuxs_97_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_98_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_99_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_100_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_101_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vctuxs v2, v1, 0
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_102_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vctuxs v2, v1, 1
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_103_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vctuxs v2, v1, 2
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vctuxs_104_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vctuxs v2, v1, 7
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+

src/xenia/cpu/ppc/testing/instr__gen_vexptefp.s

@@ -0,0 +1,182 @@
+test_vexptefp_1_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [3F800000, 3F800000, 3F800000, 3F800000]
+
+test_vexptefp_2_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [3F800000, 3F800000, 3F800000, 3F800000]
+
+test_vexptefp_3_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [3F800000, FFFF0000, 3F800000, FFFF0000]
+
+test_vexptefp_4_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [3F800000, 3F800000, 3F800000, 3F800000]
+
+test_vexptefp_5_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [3F800000, 3F800000, 3F800000, 3F800000]
+
+test_vexptefp_6_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [3F800000, 7F800000, 3F800000, 00000000]
+
+test_vexptefp_7_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [3F800000, 3F800000, 00000000, FFFF00FF]
+
+test_vexptefp_8_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [3F800000, 3F800000, 3F800000, 3F800000]
+
+test_vexptefp_9_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [3F800000, 3F800000, 3F800000, 3F800000]
+
+test_vexptefp_10_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [3F800000, 3F800000, 3F800000, 3F800000]
+
+test_vexptefp_11_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [3F800000, 3F800000, 3F800000, 3F800000]
+
+test_vexptefp_12_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [3F800000, 3F800000, 3F800000, 7F800000]
+
+test_vexptefp_13_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [40000000, 40350000, 40099000, 406E0000]
+
+test_vexptefp_14_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [44800000, 3A800000, 47000000, 38000000]
+
+test_vexptefp_15_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [7FC00203, 3F800000, 7FC00A0B, 3F800000]
+
+test_vexptefp_16_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [3F800000, 3F800000, 7FFFFFFF, 3F800000]
+
+test_vexptefp_17_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [3F000000, 3EB50000, 3EEE0000, 3E899000]
+
+test_vexptefp_18_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [3A800000, 49800000, 35800000, 4E800000]
+
+test_vexptefp_19_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 3F800000]
+
+test_vexptefp_20_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 3F800000, 3F800000]
+
+test_vexptefp_21_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
+
+test_vexptefp_22_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 3F800000, 3F800000]
+
+test_vexptefp_23_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [FFFDFF7E, 3F800000, FFFCFF7D, 3F800000]
+
+test_vexptefp_24_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [FFFF0101, 7F800000, FFFFFFFF, 3F800000]
+
+test_vexptefp_25_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [FFFFFF80, 3F800000, FFFEFF7F, 3F800000]
+
+test_vexptefp_26_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vexptefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+

src/xenia/cpu/ppc/testing/instr__gen_vlogefp.s

@@ -0,0 +1,182 @@
+test_vlogefp_1_GEN:
+  #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v2 [FF800000, FF800000, FF800000, FF800000]
+
+test_vlogefp_2_GEN:
+  #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v2 [FF800000, FF800000, FF800000, FF800000]
+
+test_vlogefp_3_GEN:
+  #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+  #_ REGISTER_OUT v2 [FF800000, FFFF0000, FF800000, FFFF0000]
+
+test_vlogefp_4_GEN:
+  #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [FF800000, C2EDE200, C2DDCB00, C2CDB700]
+
+test_vlogefp_5_GEN:
+  #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
+  #_ REGISTER_OUT v2 [FF800000, FF800000, FF800000, FF800000]
+
+test_vlogefp_6_GEN:
+  #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_OUT v2 [FF800000, 411BD600, 7FC00000, 7FC00000]
+
+test_vlogefp_7_GEN:
+  #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  #_ REGISTER_OUT v2 [C2FA0040, FF800000, 7FC00000, FFFF00FF]
+
+test_vlogefp_8_GEN:
+  #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
+  #_ REGISTER_OUT v2 [C2EDE800, C2EDE800, C2EDE800, C2EDE800]
+
+test_vlogefp_9_GEN:
+  #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
+  #_ REGISTER_OUT v2 [C2E1D600, C2E1D600, C2E1D600, C2E1D600]
+
+test_vlogefp_10_GEN:
+  #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
+  #_ REGISTER_OUT v2 [C2DDD000, C2DDD000, C2DDD000, C2DDD000]
+
+test_vlogefp_11_GEN:
+  #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
+  #_ REGISTER_OUT v2 [C2B59DC0, C2B59DC0, C2B59DC0, C2B59DC0]
+
+test_vlogefp_12_GEN:
+  #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
+  #_ REGISTER_OUT v2 [C2B502C0, 7FC00000, C2B95240, 422F6680]
+
+test_vlogefp_13_GEN:
+  #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
+  #_ REGISTER_OUT v2 [00000000, 3F160000, 3E0F8000, 3F6CC000]
+
+test_vlogefp_14_GEN:
+  #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v2 [40548000, 7FC00000, 4079F800, 7FC00000]
+
+test_vlogefp_15_GEN:
+  #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v2 [7FC00203, C2EDE200, 7FC00A0B, C2CDB700]
+
+test_vlogefp_16_GEN:
+  #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v2 [FF800000, 7FC00000, 7FFFFFFF, 7FC00000]
+
+test_vlogefp_17_GEN:
+  #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
+  #_ REGISTER_OUT v2 [7FC00000, 7FC00000, 7FC00000, 7FC00000]
+
+test_vlogefp_18_GEN:
+  #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
+  #_ REGISTER_OUT v2 [7FC00000, 408A4000, 7FC00000, 409CFC00]
+
+test_vlogefp_19_GEN:
+  #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+  #_ REGISTER_OUT v2 [7FC00000, 7FC00000, 7FC00000, C2EDFA00]
+
+test_vlogefp_20_GEN:
+  #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  #_ REGISTER_OUT v2 [7FC00000, 7FC00000, FF800000, C2EDE200]
+
+test_vlogefp_21_GEN:
+  #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v2 [7FC00000, 7FC00000, 7FC00000, 7FC00000]
+
+test_vlogefp_22_GEN:
+  #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+  #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, FF800000, FF800000]
+
+test_vlogefp_23_GEN:
+  #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  #_ REGISTER_OUT v2 [FFFDFF7E, FF800000, FFFCFF7D, FF800000]
+
+test_vlogefp_24_GEN:
+  #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v2 [FFFF0101, 42C3D2C0, FFFFFFFF, FF800000]
+
+test_vlogefp_25_GEN:
+  #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v2 [FFFFFF80, FF800000, FFFEFF7F, FF800000]
+
+test_vlogefp_26_GEN:
+  #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vlogefp v2, v1
+  blr
+  #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+