diff --git a/src/xenia/gpu/d3d12/d3d12_command_processor.cc b/src/xenia/gpu/d3d12/d3d12_command_processor.cc index f8a7bc562..96b7fb5d0 100644 --- a/src/xenia/gpu/d3d12/d3d12_command_processor.cc +++ b/src/xenia/gpu/d3d12/d3d12_command_processor.cc @@ -225,7 +225,7 @@ ID3D12RootSignature* D3D12CommandProcessor::GetRootSignature( parameter.ParameterType = D3D12_ROOT_PARAMETER_TYPE_DESCRIPTOR_TABLE; parameter.DescriptorTable.NumDescriptorRanges = 1; parameter.DescriptorTable.pDescriptorRanges = ⦥ - parameter.ShaderVisibility = D3D12_SHADER_VISIBILITY_VERTEX; + parameter.ShaderVisibility = D3D12_SHADER_VISIBILITY_ALL; range.RangeType = D3D12_DESCRIPTOR_RANGE_TYPE_SRV; range.NumDescriptors = 1; range.BaseShaderRegister = 0; @@ -245,7 +245,7 @@ ID3D12RootSignature* D3D12CommandProcessor::GetRootSignature( parameter.ShaderVisibility = D3D12_SHADER_VISIBILITY_PIXEL; range.RangeType = D3D12_DESCRIPTOR_RANGE_TYPE_SRV; range.NumDescriptors = pixel_texture_count; - range.BaseShaderRegister = 0; + range.BaseShaderRegister = 1; range.RegisterSpace = 0; range.OffsetInDescriptorsFromTableStart = 0; ++desc.NumParameters; diff --git a/src/xenia/gpu/hlsl_shader_translator.cc b/src/xenia/gpu/hlsl_shader_translator.cc index 205e77bfb..a964be74e 100644 --- a/src/xenia/gpu/hlsl_shader_translator.cc +++ b/src/xenia/gpu/hlsl_shader_translator.cc @@ -228,10 +228,10 @@ std::vector HlslShaderTranslator::CompleteTranslation() { srv_name_suffix = "2d"; break; } - // t0 is shared memory in vertex shaders. + // t0 is shared memory for vfetch, so textures start from t1. source.AppendFormat("Texture%s xe_texture%u_%s : register(t%u);\n", srv_type_dimension, srv.fetch_constant, srv_name_suffix, - i + (is_vertex_shader() ? 1 : 0)); + i + 1); } for (uint32_t i = 0; i < sampler_count_; ++i) { source.AppendFormat("SamplerState xe_sampler%u : register(s%u);\n",