From 4f5c640f3c5d61f4b6ed45b91c500b4136b4fbff Mon Sep 17 00:00:00 2001
From: Wunkolo <Wunkolo@gmail.com>
Date: Mon, 6 May 2024 12:57:16 -0700
Subject: [PATCH] [a64] Refactor `REV{32,64}` to `REV`

Let the register type determine the reverse-size

REV32 was also the wrong instruction to use.
---
 src/xenia/cpu/backend/a64/a64_seq_memory.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/xenia/cpu/backend/a64/a64_seq_memory.cc b/src/xenia/cpu/backend/a64/a64_seq_memory.cc
index 63ae0d810..9c8f2535d 100644
--- a/src/xenia/cpu/backend/a64/a64_seq_memory.cc
+++ b/src/xenia/cpu/backend/a64/a64_seq_memory.cc
@@ -642,7 +642,7 @@ struct LOAD_OFFSET_I32
     auto addr_reg = ComputeMemoryAddressOffset(e, i.src1, i.src2);
     if (i.instr->flags & LoadStoreFlags::LOAD_STORE_BYTE_SWAP) {
       e.LDR(i.dest, addr_reg);
-      e.REV32(i.dest.reg().toX(), i.dest.reg().toX());
+      e.REV(i.dest.reg().toX(), i.dest.reg().toX());
     } else {
       e.LDR(i.dest, addr_reg);
     }
@@ -655,7 +655,7 @@ struct LOAD_OFFSET_I64
     auto addr_reg = ComputeMemoryAddressOffset(e, i.src1, i.src2);
     if (i.instr->flags & LoadStoreFlags::LOAD_STORE_BYTE_SWAP) {
       e.LDR(i.dest, addr_reg);
-      e.REV64(i.dest, i.dest);
+      e.REV(i.dest, i.dest);
     } else {
       e.LDR(i.dest, addr_reg);
     }
@@ -774,7 +774,7 @@ struct LOAD_I32 : Sequence<LOAD_I32, I<OPCODE_LOAD, I32Op, I64Op>> {
     auto addr_reg = ComputeMemoryAddress(e, i.src1);
     if (i.instr->flags & LoadStoreFlags::LOAD_STORE_BYTE_SWAP) {
       e.LDR(i.dest, addr_reg);
-      e.REV32(i.dest.reg().toX(), i.dest.reg().toX());
+      e.REV(i.dest, i.dest);
     } else {
       e.LDR(i.dest, addr_reg);
     }