From 4a72010e5fcee7676b182f1cd96f212203b1b520 Mon Sep 17 00:00:00 2001 From: Ben Vanik Date: Sat, 19 Oct 2013 19:03:30 -0700 Subject: [PATCH] addcx --- src/xenia/cpu/x64/x64_emit_alu.cc | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/src/xenia/cpu/x64/x64_emit_alu.cc b/src/xenia/cpu/x64/x64_emit_alu.cc index 919afdadc..485d72fe4 100644 --- a/src/xenia/cpu/x64/x64_emit_alu.cc +++ b/src/xenia/cpu/x64/x64_emit_alu.cc @@ -51,8 +51,32 @@ XEEMITTER(addx, 0x7C000214, XO )(X64Emitter& e, X86Compiler& c, InstrDat } XEEMITTER(addcx, 0x7C000014, XO )(X64Emitter& e, X86Compiler& c, InstrData& i) { - XEINSTRNOTIMPLEMENTED(); - return 1; + // RD <- (RA) + (RB) + // CA <- carry bit + + GpVar v(c.newGpVar()); + c.mov(v, e.gpr_value(i.XO.RA)); + c.add(v, e.gpr_value(i.XO.RB)); + GpVar cc(c.newGpVar()); + c.setc(cc.r8()); + + if (i.XO.OE) { + // With XER update. + XEASSERTALWAYS(); + //e.update_xer_with_overflow(EFLAGS OF?); + } + + e.update_gpr_value(i.XO.RT, v); + e.update_xer_with_carry(cc); + + if (i.XO.Rc) { + // With cr0 update. + e.update_cr_with_cond(0, v); + } + + e.clear_constant_gpr_value(i.XO.RT); + + return 0; } XEEMITTER(addex, 0x7C000114, XO )(X64Emitter& e, X86Compiler& c, InstrData& i) {