diff --git a/src/xenia/gpu/d3d12/d3d12_command_processor.cc b/src/xenia/gpu/d3d12/d3d12_command_processor.cc
index 477ec9731..b8c90444e 100644
--- a/src/xenia/gpu/d3d12/d3d12_command_processor.cc
+++ b/src/xenia/gpu/d3d12/d3d12_command_processor.cc
@@ -628,6 +628,12 @@ bool D3D12CommandProcessor::IssueDraw(PrimitiveType primitive_type,
     // Doesn't actually draw.
     return true;
   }
+  uint32_t color_mask = enable_mode == xenos::ModeControl::kColorDepth ?
+                        regs[XE_GPU_REG_RB_COLOR_MASK].u32 & 0xFFFF : 0;
+  if (!color_mask && !(regs[XE_GPU_REG_RB_DEPTHCONTROL].u32 & (0x1 | 0x4))) {
+    // Not writing to color, depth or doing stencil test, so doesn't draw.
+    return true;
+  }
   if ((regs[XE_GPU_REG_PA_SU_SC_MODE_CNTL].u32 & 0x3) == 0x3 &&
       primitive_type != PrimitiveType::kPointList &&
       primitive_type != PrimitiveType::kRectangleList) {
diff --git a/src/xenia/gpu/d3d12/pipeline_cache.cc b/src/xenia/gpu/d3d12/pipeline_cache.cc
index 1aed37a68..137359d6c 100644
--- a/src/xenia/gpu/d3d12/pipeline_cache.cc
+++ b/src/xenia/gpu/d3d12/pipeline_cache.cc
@@ -411,7 +411,7 @@ PipelineCache::UpdateStatus PipelineCache::UpdateRasterizerState(
 
   bool dirty = current_pipeline_ == nullptr;
   uint32_t pa_su_sc_mode_cntl =
-      register_file_->values[XE_GPU_REG_RB_COLOR_MASK].u32;
+      register_file_->values[XE_GPU_REG_PA_SU_SC_MODE_CNTL].u32;
   uint32_t cull_mode = pa_su_sc_mode_cntl & 0x3;
   if (primitive_type == PrimitiveType::kPointList ||
       primitive_type == PrimitiveType::kRectangleList) {
diff --git a/src/xenia/gpu/d3d12/render_target_cache.cc b/src/xenia/gpu/d3d12/render_target_cache.cc
index 2c9b6433d..71dbdb43c 100644
--- a/src/xenia/gpu/d3d12/render_target_cache.cc
+++ b/src/xenia/gpu/d3d12/render_target_cache.cc
@@ -117,8 +117,8 @@ void RenderTargetCache::UpdateRenderTargets(/* const D3D12_VIEWPORT& viewport,
   uint32_t surface_pitch = rb_surface_info & 0x3FFF;
   MsaaSamples msaa_samples = MsaaSamples((rb_surface_info >> 16) & 0x3);
   uint32_t rb_color_mask = regs[XE_GPU_REG_RB_COLOR_MASK].u32;
-  if (xenos::ModeControl(regs[XE_GPU_REG_RB_MODECONTROL].u32 & 0x7) ==
-      xenos::ModeControl::kDepth) {
+  if (xenos::ModeControl(regs[XE_GPU_REG_RB_MODECONTROL].u32 & 0x7) !=
+      xenos::ModeControl::kColorDepth) {
     rb_color_mask = 0;
   }
   bool color_enabled[4] = {
@@ -129,7 +129,8 @@ void RenderTargetCache::UpdateRenderTargets(/* const D3D12_VIEWPORT& viewport,
       regs[XE_GPU_REG_RB_COLOR2_INFO].u32, regs[XE_GPU_REG_RB_COLOR3_INFO].u32};
   uint32_t rb_depthcontrol = regs[XE_GPU_REG_RB_DEPTHCONTROL].u32;
   uint32_t rb_depth_info = regs[XE_GPU_REG_RB_DEPTH_INFO].u32;
-  bool depth_enabled = (rb_depthcontrol & (0x2 | 0x4)) != 0;
+  // 0x1 = stencil test enabled, 0x2 = depth test enabled, 0x4 = depth write enabled.
+  bool depth_enabled = (rb_depthcontrol & (0x1 | 0x2 | 0x4)) != 0;
 
   bool full_update = false;