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Swizzling some textures.

This commit is contained in:
Ben Vanik 2014-01-21 00:31:24 -08:00
parent 175e21bea1
commit 44c15342f5
2 changed files with 38 additions and 5 deletions
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17
src/xenia/gpu/d3d11/d3d11_graphics_driver.cc
View File

@ -1111,7 +1111,24 @@ D3D11GraphicsDriver::TextureInfo D3D11GraphicsDriver::GetTextureInfo(
info.pitch = 1; info.pitch = 1;
break; break;
case FMT_8_8_8_8: case FMT_8_8_8_8:
switch (fetch.swizzle) {
case XE_GPU_SWIZZLE_RGBA:
info.format = DXGI_FORMAT_R8G8B8A8_UNORM;
break;
case XE_GPU_SWIZZLE_BGRA:
info.format = DXGI_FORMAT_B8G8R8A8_UNORM; info.format = DXGI_FORMAT_B8G8R8A8_UNORM;
break;
case XE_GPU_SWIZZLE_RGB1:
info.format = DXGI_FORMAT_R8G8B8A8_UNORM; // ?
break;
case XE_GPU_SWIZZLE_BGR1:
info.format = DXGI_FORMAT_B8G8R8X8_UNORM;
break;
default:
XELOGW("D3D11: unhandled swizzle for FMT_8_8_8_8");
info.format = DXGI_FORMAT_R8G8B8A8_UNORM;
break;
}
info.block_size = 1; info.block_size = 1;
info.pitch = 4; info.pitch = 4;
break; break;

24
src/xenia/gpu/xenos/xenos.h
View File

@ -50,6 +50,25 @@ typedef enum {
XE_GPU_ENDIAN_16IN32 = 0x3, XE_GPU_ENDIAN_16IN32 = 0x3,
} XE_GPU_ENDIAN; } XE_GPU_ENDIAN;
#define XE_GPU_MAKE_SWIZZLE(x, y, z, w) \
(((XE_GPU_SWIZZLE_##x) << 0) | ((XE_GPU_SWIZZLE_##y) << 3) | ((XE_GPU_SWIZZLE_##z) << 6) | ((XE_GPU_SWIZZLE_##w) << 9))
typedef enum {
XE_GPU_SWIZZLE_X = 0,
XE_GPU_SWIZZLE_R = 0,
XE_GPU_SWIZZLE_Y = 1,
XE_GPU_SWIZZLE_G = 1,
XE_GPU_SWIZZLE_Z = 2,
XE_GPU_SWIZZLE_B = 2,
XE_GPU_SWIZZLE_W = 3,
XE_GPU_SWIZZLE_A = 3,
XE_GPU_SWIZZLE_0 = 4,
XE_GPU_SWIZZLE_1 = 5,
XE_GPU_SWIZZLE_RGBA = XE_GPU_MAKE_SWIZZLE(R, G, B, A),
XE_GPU_SWIZZLE_BGRA = XE_GPU_MAKE_SWIZZLE(B, G, R, A),
XE_GPU_SWIZZLE_RGB1 = XE_GPU_MAKE_SWIZZLE(R, G, B, 1),
XE_GPU_SWIZZLE_BGR1 = XE_GPU_MAKE_SWIZZLE(B, G, R, 1),
} XE_GPU_SWIZZLE;
XEFORCEINLINE uint32_t GpuSwap(uint32_t value, XE_GPU_ENDIAN endianness) { XEFORCEINLINE uint32_t GpuSwap(uint32_t value, XE_GPU_ENDIAN endianness) {
switch (endianness) { switch (endianness) {
default: default:
@ -147,10 +166,7 @@ XEPACKEDUNION(xe_gpu_texture_fetch_t, {
} size_3d; } size_3d;
}; };
uint32_t unk3_0 : 1; // dword_3 uint32_t unk3_0 : 1; // dword_3
uint32_t swiz_x : 3; uint32_t swizzle : 12; // xyzw, 3b each (XE_GPU_SWIZZLE)
uint32_t swiz_y : 3;
uint32_t swiz_z : 3;
uint32_t swiz_w : 3;
uint32_t unk3_1 : 6; uint32_t unk3_1 : 6;
uint32_t mag_filter : 2; uint32_t mag_filter : 2;
uint32_t min_filter : 2; uint32_t min_filter : 2;