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Constant tests for eqv, lvexx, lvl, lvr, lssl, lvsr, mulhd.

This commit is contained in:
gibbed 2015-05-13 01:52:40 -05:00
parent 4248268b4f
commit 3ba6598caf
7 changed files with 219 additions and 0 deletions
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66
src/xenia/cpu/frontend/test/instr_eqv.s
View File

@ -7,6 +7,15 @@ test_eqv_1:
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r5 1
test_eqv_1_constant:
li r4, 0
li r5, 1
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0xfffffffffffffffe
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r5 1
test_eqv_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
@ -16,6 +25,15 @@ test_eqv_2:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
test_eqv_2_constant:
li r4, -1
li r5, 0
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
test_eqv_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
@ -25,6 +43,15 @@ test_eqv_3:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_eqv_3_constant:
li r4, -1
li r5, -1
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_eqv_4:
#_ REGISTER_IN r4 0xDEADBEEFDEADBEEF
#_ REGISTER_IN r5 0xDEADBEEFDEADBEEF
@ -34,6 +61,19 @@ test_eqv_4:
#_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
#_ REGISTER_OUT r5 0xDEADBEEFDEADBEEF
test_eqv_4_constant:
lis r4, 0xDEAD
ori r4, r4, 0xBEEF
sldi r5, r4, 32
clrldi r4, r4, 32
or r4, r5, r4
mr r5, r4
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
#_ REGISTER_OUT r5 0xDEADBEEFDEADBEEF
test_eqv_5:
#_ REGISTER_IN r4 0xDEADBEEFDEADBEEF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
@ -43,6 +83,19 @@ test_eqv_5:
#_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_eqv_5_constant:
lis r4, 0xDEAD
ori r4, r4, 0xBEEF
sldi r5, r4, 32
clrldi r4, r4, 32
or r4, r5, r4
li r5, -1
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0xDEADBEEFDEADBEEF
#_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_eqv_6:
#_ REGISTER_IN r4 0xDEADBEEFDEADBEEF
#_ REGISTER_IN r5 0
@ -51,3 +104,16 @@ test_eqv_6:
#_ REGISTER_OUT r3 0x2152411021524110
#_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
#_ REGISTER_OUT r5 0
test_eqv_6_constant:
lis r4, 0xDEAD
ori r4, r4, 0xBEEF
sldi r5, r4, 32
clrldi r4, r4, 32
or r4, r5, r4
li r5, 0
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0x2152411021524110
#_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
#_ REGISTER_OUT r5 0

48
src/xenia/cpu/frontend/test/instr_lvexx.s
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@ -6,6 +6,14 @@ test_lvebx_1:
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvebx_1_constant:
#_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
li r4, 0
lvebx v3, r0, r4
blr
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvebx_2:
#_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 4
@ -14,6 +22,14 @@ test_lvebx_2:
#_ REGISTER_OUT r4 4
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvebx_2_constant:
#_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
li r4, 4
lvebx v3, r0, r4
blr
#_ REGISTER_OUT r4 4
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvehx_1:
#_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0
@ -22,6 +38,14 @@ test_lvehx_1:
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvehx_1_constant:
#_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
li r4, 0
lvehx v3, r0, r4
blr
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvehx_2:
#_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 4
@ -30,6 +54,14 @@ test_lvehx_2:
#_ REGISTER_OUT r4 4
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvehx_2_constant:
#_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
li r4, 4
lvehx v3, r0, r4
blr
#_ REGISTER_OUT r4 4
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx_1:
#_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0
@ -38,6 +70,14 @@ test_lvewx_1:
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx_1_constant:
#_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
li r4, 0
lvewx v3, r0, r4
blr
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx_2:
#_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 4
@ -45,3 +85,11 @@ test_lvewx_2:
blr
#_ REGISTER_OUT r4 4
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx_2_constant:
#_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
li r4, 4
lvewx v3, r0, r4
blr
#_ REGISTER_OUT r4 4
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]

8
src/xenia/cpu/frontend/test/instr_lvl.s
View File

@ -5,3 +5,11 @@ test_lvl_1:
blr
#_ REGISTER_OUT r4 0x1077
#_ REGISTER_OUT v3 [0A0B0C0D, 0E0F1013, 0C000000, 00000000]
test_lvl_1_constant:
#_ MEMORY_IN 00001077 0a 0b 0c 0d 0e 0f 10 13 0c 0d 0e 10 11 12 13 14 ff ff ff ff ff ff
li r4, 0x1077
lvlx v3, r4, r0
blr
#_ REGISTER_OUT r4 0x1077
#_ REGISTER_OUT v3 [0A0B0C0D, 0E0F1013, 0C000000, 00000000]

10
src/xenia/cpu/frontend/test/instr_lvr.s
View File

@ -7,3 +7,13 @@ test_lvr_1:
#_ REGISTER_OUT r4 0x10B7
#_ REGISTER_OUT r5 0x10
#_ REGISTER_OUT v3 [00000000, 00000000, 000D0E10, 11121314]
test_lvr_1_constant:
#_ MEMORY_IN 000010B0 090A0A0B 0C0F120A 0B0C0D0E 0F10130C 0D0E1011 121314FF FFFFFFFF
li r4, 0x10B7
li r5, 0x10
lvrx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x10B7
#_ REGISTER_OUT r5 0x10
#_ REGISTER_OUT v3 [00000000, 00000000, 000D0E10, 11121314]

21
src/xenia/cpu/frontend/test/instr_lvsl.s
View File

@ -5,6 +5,13 @@ test_lvsl_1:
#_ REGISTER_OUT r4 0x1070
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvsl_1_constant:
li r4, 0x1070
lvsl v3, r4, r0
blr
#_ REGISTER_OUT r4 0x1070
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvsl_2:
#_ REGISTER_IN r4 0x1071
lvsl v3, r4, r0
@ -12,9 +19,23 @@ test_lvsl_2:
#_ REGISTER_OUT r4 0x1071
#_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
test_lvsl_2_constant:
li r4, 0x1071
lvsl v3, r4, r0
blr
#_ REGISTER_OUT r4 0x1071
#_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
test_lvsl_3:
#_ REGISTER_IN r4 0x107F
lvsl v3, r4, r0
blr
#_ REGISTER_OUT r4 0x107F
#_ REGISTER_OUT v3 [0F101112, 13141516, 1718191A, 1B1C1D1E]
test_lvsl_3_constant:
li r4, 0x107F
lvsl v3, r4, r0
blr
#_ REGISTER_OUT r4 0x107F
#_ REGISTER_OUT v3 [0F101112, 13141516, 1718191A, 1B1C1D1E]

21
src/xenia/cpu/frontend/test/instr_lvsr.s
View File

@ -5,6 +5,13 @@ test_lvsr_1:
#_ REGISTER_OUT r4 0x1070
#_ REGISTER_OUT v3 [10111213, 14151617, 18191A1B, 1C1D1E1F]
test_lvsr_1_constant:
li r4, 0x1070
lvsr v3, r4, r0
blr
#_ REGISTER_OUT r4 0x1070
#_ REGISTER_OUT v3 [10111213, 14151617, 18191A1B, 1C1D1E1F]
test_lvsr_2:
#_ REGISTER_IN r4 0x1071
lvsr v3, r4, r0
@ -12,9 +19,23 @@ test_lvsr_2:
#_ REGISTER_OUT r4 0x1071
#_ REGISTER_OUT v3 [0F101112, 13141516, 1718191A, 1B1C1D1E]
test_lvsr_2_constant:
li r4, 0x1071
lvsr v3, r4, r0
blr
#_ REGISTER_OUT r4 0x1071
#_ REGISTER_OUT v3 [0F101112, 13141516, 1718191A, 1B1C1D1E]
test_lvsr_3:
#_ REGISTER_IN r4 0x107F
lvsr v3, r4, r0
blr
#_ REGISTER_OUT r4 0x107F
#_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
test_lvsr_3_constant:
li r4, 0x107F
lvsr v3, r4, r0
blr
#_ REGISTER_OUT r4 0x107F
#_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]

45
src/xenia/cpu/frontend/test/instr_mulhd.s
View File

@ -7,6 +7,15 @@ test_mulhd_1:
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhd_1_constant:
li r4, 1
li r5, 0
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhd_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
@ -16,6 +25,15 @@ test_mulhd_2:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhd_2_constant:
li r4, -1
li r5, 1
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhd_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 2
@ -25,6 +43,15 @@ test_mulhd_3:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mulhd_3_constant:
li r4, -1
li r5, 2
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mulhd_4:
#_ REGISTER_IN r4 0x8000000000000000
#_ REGISTER_IN r5 1
@ -34,6 +61,15 @@ test_mulhd_4:
#_ REGISTER_OUT r4 0x8000000000000000
#_ REGISTER_OUT r5 1
test_mulhd_4_constant:
li r5, 1
sldi r4, r5, 63
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x8000000000000000
#_ REGISTER_OUT r5 1
test_mulhd_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
@ -42,3 +78,12 @@ test_mulhd_5:
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_mulhd_5_constant:
li r4, -1
li r5, -1
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF