From 388c622ecd68947cd718309f62f8bde017fa1ab0 Mon Sep 17 00:00:00 2001 From: espes Date: Sun, 2 Jun 2013 17:11:54 +1000 Subject: [PATCH] fill in some more xenos registers --- src/xenia/gpu/xenos/register_table.inc | 62 ++++++++++++++++---------- 1 file changed, 39 insertions(+), 23 deletions(-) diff --git a/src/xenia/gpu/xenos/register_table.inc b/src/xenia/gpu/xenos/register_table.inc index ebc7d0d70..5babebe9b 100644 --- a/src/xenia/gpu/xenos/register_table.inc +++ b/src/xenia/gpu/xenos/register_table.inc @@ -38,6 +38,7 @@ XE_GPU_REGISTER(0x0A2F, dword, COHER_SIZE_HOST) XE_GPU_REGISTER(0x0A30, dword, COHER_BASE_HOST) XE_GPU_REGISTER(0x0A31, dword, COHER_STATUS_HOST) +XE_GPU_REGISTER(0x0D00, dword, SQ_GPR_MANAGEMENT) XE_GPU_REGISTER(0x0D01, dword, SQ_FLOW_CONTROL) XE_GPU_REGISTER(0x0D02, dword, SQ_INST_STORE_MANAGMENT) XE_GPU_REGISTER(0x0D04, dword, SQ_EO_RT) @@ -48,7 +49,22 @@ XE_GPU_REGISTER(0x0E42, dword, UNKNOWN_0E42) XE_GPU_REGISTER(0x0F01, dword, RB_BC_CONTROL) +XE_GPU_REGISTER(0x2000, dword, RB_SURFACE_INFO) +XE_GPU_REGISTER(0x2001, dword, RB_COLOR_INFO) +XE_GPU_REGISTER(0x2002, dword, RB_DEPTH_INFO) +XE_GPU_REGISTER(0x2003, dword, RB_COLOR1_INFO) +XE_GPU_REGISTER(0x2004, dword, RB_COLOR2_INFO) +XE_GPU_REGISTER(0x2005, dword, RB_COLOR3_INFO) +XE_GPU_REGISTER(0x2006, dword, COHER_DEST_BASE_0) +XE_GPU_REGISTER(0x2007, dword, COHER_DEST_BASE_1) +XE_GPU_REGISTER(0x2008, dword, COHER_DEST_BASE_2) +XE_GPU_REGISTER(0x2009, dword, COHER_DEST_BASE_3) +XE_GPU_REGISTER(0x200A, dword, COHER_DEST_BASE_4) +XE_GPU_REGISTER(0x200B, dword, COHER_DEST_BASE_5) +XE_GPU_REGISTER(0x200C, dword, COHER_DEST_BASE_6) XE_GPU_REGISTER(0x200D, dword, COHER_DEST_BASE_7) +XE_GPU_REGISTER(0x200E, dword, PA_SC_WINDOW_SCISSOR_TL) +XE_GPU_REGISTER(0x200F, dword, PA_SC_SCREEN_SCISSOR_BR) XE_GPU_REGISTER(0x2080, dword, PA_SC_WINDOW_OFFSET) XE_GPU_REGISTER(0x2081, dword, PA_SC_WINDOW_SCISSOR_TL) @@ -85,7 +101,7 @@ XE_GPU_REGISTER(0x2184, dword, SQ_WRAPPING_1) XE_GPU_REGISTER(0x2200, dword, RB_DEPTHCONTROL) XE_GPU_REGISTER(0x2201, dword, RB_BLENDCONTROL_0) XE_GPU_REGISTER(0x2202, dword, RB_COLORCONTROL) -XE_GPU_REGISTER(0x2203, dword, VGT_CURRENT_BIN_ID_MAX) +XE_GPU_REGISTER(0x2203, dword, RB_TILECONTROL) XE_GPU_REGISTER(0x2204, dword, PA_CL_CLIP_CNTL) XE_GPU_REGISTER(0x2205, dword, PA_SU_SC_MODE_CNTL) XE_GPU_REGISTER(0x2206, dword, PA_CL_VTE_CNTL) @@ -99,21 +115,21 @@ XE_GPU_REGISTER(0x2280, dword, PA_SU_POINT_SIZE) XE_GPU_REGISTER(0x2281, dword, PA_SU_POINT_MINMAX) XE_GPU_REGISTER(0x2282, dword, PA_SU_LINE_CNTL) XE_GPU_REGISTER(0x2283, dword, PA_SC_LINE_STIPPLE) -XE_GPU_REGISTER(0x2284, dword, UNKNOWN_2284) -XE_GPU_REGISTER(0x2285, dword, UNKNOWN_2285) -XE_GPU_REGISTER(0x2286, float, UNKNOWN_2286) -XE_GPU_REGISTER(0x2287, float, UNKNOWN_2287) -XE_GPU_REGISTER(0x2288, dword, UNKNOWN_2288) -XE_GPU_REGISTER(0x2289, dword, UNKNOWN_2289) -XE_GPU_REGISTER(0x228A, dword, UNKNOWN_228A) -XE_GPU_REGISTER(0x228B, dword, UNKNOWN_228B) -XE_GPU_REGISTER(0x228C, dword, UNKNOWN_228C) -XE_GPU_REGISTER(0x228D, dword, UNKNOWN_228D) -XE_GPU_REGISTER(0x228E, dword, UNKNOWN_228E) -XE_GPU_REGISTER(0x228F, dword, UNKNOWN_228F) +XE_GPU_REGISTER(0x2284, dword, VGT_OUTPUT_PATH_CNTL) +XE_GPU_REGISTER(0x2285, dword, VGT_HOS_CNTL) +XE_GPU_REGISTER(0x2286, float, VGT_HOS_MAX_TESS_LEVEL) +XE_GPU_REGISTER(0x2287, float, VGT_HOS_MIN_TESS_LEVEL) +XE_GPU_REGISTER(0x2288, dword, VGT_HOS_REUSE_DEPTH) +XE_GPU_REGISTER(0x2289, dword, VGT_GROUP_PRIM_TYPE) +XE_GPU_REGISTER(0x228A, dword, VGT_GROUP_FIRST_DECR) +XE_GPU_REGISTER(0x228B, dword, VGT_GROUP_DECR) +XE_GPU_REGISTER(0x228C, dword, VGT_GROUP_VECT_0_CNTL) +XE_GPU_REGISTER(0x228D, dword, VGT_GROUP_VECT_1_CNTL) +XE_GPU_REGISTER(0x228E, dword, VGT_GROUP_VECT_0_FMT_CNTL) +XE_GPU_REGISTER(0x228F, dword, VGT_GROUP_VECT_1_FMT_CNTL) XE_GPU_REGISTER(0x2290, dword, UNKNOWN_2290) XE_GPU_REGISTER(0x2291, dword, UNKNOWN_2291) -XE_GPU_REGISTER(0x2292, dword, UNKNOWN_2292) +XE_GPU_REGISTER(0x2292, dword, PA_SC_MPASS_PS_CNTL) XE_GPU_REGISTER(0x2293, dword, PA_SC_VIZ_QUERY) XE_GPU_REGISTER(0x2294, dword, VGT_ENHANCE) @@ -145,14 +161,14 @@ XE_GPU_REGISTER(0x2318, dword, RB_COPY_CONTROL) XE_GPU_REGISTER(0x2319, dword, RB_COPY_DEST_BASE) XE_GPU_REGISTER(0x231A, dword, RB_COPY_DEST_PITCH) XE_GPU_REGISTER(0x231B, dword, RB_COPY_DEST_INFO) -XE_GPU_REGISTER(0x231C, dword, RB_HI_CLEAR) +XE_GPU_REGISTER(0x231C, dword, RB_TILE_CLEAR) XE_GPU_REGISTER(0x231D, dword, RB_DEPTH_CLEAR) XE_GPU_REGISTER(0x231E, dword, RB_COLOR_CLEAR) XE_GPU_REGISTER(0x231F, dword, RB_COLOR_CLEAR_LOW) -XE_GPU_REGISTER(0x2320, dword, UNKNOWN_2320) -XE_GPU_REGISTER(0x2321, dword, UNKNOWN_2321) -XE_GPU_REGISTER(0x2322, dword, UNKNOWN_2322) -XE_GPU_REGISTER(0x2323, dword, UNKNOWN_2323) +XE_GPU_REGISTER(0x2320, dword, RB_COPY_FUNC) +XE_GPU_REGISTER(0x2321, dword, RB_COPY_REF) +XE_GPU_REGISTER(0x2322, dword, RB_COPY_MASK) +XE_GPU_REGISTER(0x2323, dword, RB_COPY_SURFACE_SLICE) XE_GPU_REGISTER(0x2324, dword, RB_SAMPLE_COUNT_CTL) XE_GPU_REGISTER(0x2325, dword, RB_SAMPLE_COUNT_ADDR) @@ -160,10 +176,10 @@ XE_GPU_REGISTER(0x2380, float, PA_SU_POLY_OFFSET_FRONT_SCALE) XE_GPU_REGISTER(0x2381, float, PA_SU_POLY_OFFSET_FRONT_OFFSET) XE_GPU_REGISTER(0x2382, float, PA_SU_POLY_OFFSET_BACK_SCALE) XE_GPU_REGISTER(0x2383, float, PA_SU_POLY_OFFSET_BACK_OFFSET) -XE_GPU_REGISTER(0x2384, float, UNKNOWN_2384) -XE_GPU_REGISTER(0x2385, float, UNKNOWN_2385) -XE_GPU_REGISTER(0x2386, float, UNKNOWN_2386) -XE_GPU_REGISTER(0x2387, float, UNKNOWN_2387) +XE_GPU_REGISTER(0x2384, float, PA_CL_POINT_X_RAD) +XE_GPU_REGISTER(0x2385, float, PA_CL_POINT_Y_RAD) +XE_GPU_REGISTER(0x2386, float, PA_CL_POINT_SIZE) +XE_GPU_REGISTER(0x2387, float, PA_CL_POINT_CULL_RAD) // Ignored because I have no clue what these are. // XE_GPU_REGISTER(0x8D00, dword, UNKNOWN_8D00)