diff --git a/src/xenia/gpu/d3d12/d3d12_command_processor.cc b/src/xenia/gpu/d3d12/d3d12_command_processor.cc index 9a49e43c6..b92a61d77 100644 --- a/src/xenia/gpu/d3d12/d3d12_command_processor.cc +++ b/src/xenia/gpu/d3d12/d3d12_command_processor.cc @@ -2428,13 +2428,25 @@ bool D3D12CommandProcessor::IssueDraw(xenos::PrimitiveType primitive_type, switch (primitive_processing_result.host_primitive_type) { // TODO(Triang3l): Support all primitive types. case xenos::PrimitiveType::kTriangleList: - case xenos::PrimitiveType::kTrianglePatch: primitive_topology = D3D_PRIMITIVE_TOPOLOGY_3_CONTROL_POINT_PATCHLIST; break; case xenos::PrimitiveType::kQuadList: - case xenos::PrimitiveType::kQuadPatch: primitive_topology = D3D_PRIMITIVE_TOPOLOGY_4_CONTROL_POINT_PATCHLIST; break; + case xenos::PrimitiveType::kTrianglePatch: + primitive_topology = + (regs.Get().tess_mode == + xenos::TessellationMode::kAdaptive) + ? D3D_PRIMITIVE_TOPOLOGY_3_CONTROL_POINT_PATCHLIST + : D3D_PRIMITIVE_TOPOLOGY_1_CONTROL_POINT_PATCHLIST; + break; + case xenos::PrimitiveType::kQuadPatch: + primitive_topology = + (regs.Get().tess_mode == + xenos::TessellationMode::kAdaptive) + ? D3D_PRIMITIVE_TOPOLOGY_4_CONTROL_POINT_PATCHLIST + : D3D_PRIMITIVE_TOPOLOGY_1_CONTROL_POINT_PATCHLIST; + break; default: XELOGE( "Host tessellated primitive type {} returned by the primitive " diff --git a/src/xenia/gpu/d3d12/pipeline_cache.cc b/src/xenia/gpu/d3d12/pipeline_cache.cc index 8095199dd..91ac56a91 100644 --- a/src/xenia/gpu/d3d12/pipeline_cache.cc +++ b/src/xenia/gpu/d3d12/pipeline_cache.cc @@ -70,10 +70,14 @@ namespace d3d12 { namespace shaders { #include "xenia/gpu/shaders/bytecode/d3d12_5_1/adaptive_quad_hs.h" #include "xenia/gpu/shaders/bytecode/d3d12_5_1/adaptive_triangle_hs.h" -#include "xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_quad_hs.h" -#include "xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_triangle_hs.h" -#include "xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_quad_hs.h" -#include "xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_triangle_hs.h" +#include "xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_quad_1cp_hs.h" +#include "xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_quad_4cp_hs.h" +#include "xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_triangle_1cp_hs.h" +#include "xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_triangle_3cp_hs.h" +#include "xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_quad_1cp_hs.h" +#include "xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_quad_4cp_hs.h" +#include "xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_triangle_1cp_hs.h" +#include "xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_triangle_3cp_hs.h" #include "xenia/gpu/shaders/bytecode/d3d12_5_1/float24_round_ps.h" #include "xenia/gpu/shaders/bytecode/d3d12_5_1/float24_truncate_ps.h" #include "xenia/gpu/shaders/bytecode/d3d12_5_1/tessellation_adaptive_vs.h" @@ -2855,15 +2859,24 @@ ID3D12PipelineState* PipelineCache::CreateD3D12Pipeline( case xenos::TessellationMode::kDiscrete: switch (host_vertex_shader_type) { case Shader::HostVertexShaderType::kTriangleDomainCPIndexed: - case Shader::HostVertexShaderType::kTriangleDomainPatchIndexed: - state_desc.HS.pShaderBytecode = shaders::discrete_triangle_hs; + state_desc.HS.pShaderBytecode = shaders::discrete_triangle_3cp_hs; state_desc.HS.BytecodeLength = - sizeof(shaders::discrete_triangle_hs); + sizeof(shaders::discrete_triangle_3cp_hs); + break; + case Shader::HostVertexShaderType::kTriangleDomainPatchIndexed: + state_desc.HS.pShaderBytecode = shaders::discrete_triangle_1cp_hs; + state_desc.HS.BytecodeLength = + sizeof(shaders::discrete_triangle_1cp_hs); break; case Shader::HostVertexShaderType::kQuadDomainCPIndexed: + state_desc.HS.pShaderBytecode = shaders::discrete_quad_4cp_hs; + state_desc.HS.BytecodeLength = + sizeof(shaders::discrete_quad_4cp_hs); + break; case Shader::HostVertexShaderType::kQuadDomainPatchIndexed: - state_desc.HS.pShaderBytecode = shaders::discrete_quad_hs; - state_desc.HS.BytecodeLength = sizeof(shaders::discrete_quad_hs); + state_desc.HS.pShaderBytecode = shaders::discrete_quad_1cp_hs; + state_desc.HS.BytecodeLength = + sizeof(shaders::discrete_quad_1cp_hs); break; default: assert_unhandled_case(host_vertex_shader_type); @@ -2873,15 +2886,24 @@ ID3D12PipelineState* PipelineCache::CreateD3D12Pipeline( case xenos::TessellationMode::kContinuous: switch (host_vertex_shader_type) { case Shader::HostVertexShaderType::kTriangleDomainCPIndexed: - case Shader::HostVertexShaderType::kTriangleDomainPatchIndexed: - state_desc.HS.pShaderBytecode = shaders::continuous_triangle_hs; + state_desc.HS.pShaderBytecode = shaders::continuous_triangle_3cp_hs; state_desc.HS.BytecodeLength = - sizeof(shaders::continuous_triangle_hs); + sizeof(shaders::continuous_triangle_3cp_hs); + break; + case Shader::HostVertexShaderType::kTriangleDomainPatchIndexed: + state_desc.HS.pShaderBytecode = shaders::continuous_triangle_1cp_hs; + state_desc.HS.BytecodeLength = + sizeof(shaders::continuous_triangle_1cp_hs); break; case Shader::HostVertexShaderType::kQuadDomainCPIndexed: + state_desc.HS.pShaderBytecode = shaders::continuous_quad_4cp_hs; + state_desc.HS.BytecodeLength = + sizeof(shaders::continuous_quad_4cp_hs); + break; case Shader::HostVertexShaderType::kQuadDomainPatchIndexed: - state_desc.HS.pShaderBytecode = shaders::continuous_quad_hs; - state_desc.HS.BytecodeLength = sizeof(shaders::continuous_quad_hs); + state_desc.HS.pShaderBytecode = shaders::continuous_quad_1cp_hs; + state_desc.HS.BytecodeLength = + sizeof(shaders::continuous_quad_1cp_hs); break; default: assert_unhandled_case(host_vertex_shader_type); diff --git a/src/xenia/gpu/dxbc_shader_translator.cc b/src/xenia/gpu/dxbc_shader_translator.cc index 0a325aca0..0f4917cf9 100644 --- a/src/xenia/gpu/dxbc_shader_translator.cc +++ b/src/xenia/gpu/dxbc_shader_translator.cc @@ -150,7 +150,6 @@ void DxbcShaderTranslator::Reset() { in_reg_ps_front_face_sample_index_ = UINT32_MAX; in_domain_location_used_ = 0; - in_primitive_id_used_ = false; in_control_point_index_used_ = false; in_position_used_ = 0; in_front_face_used_ = false; @@ -523,18 +522,14 @@ void DxbcShaderTranslator::StartVertexOrDomainShader() { : dxbc::Dest::R(0, 0b0111), dxbc::Src::VDomain(0b000110)); if (register_count() >= 2) { - // Remap and write the primitive index to r1.x as floating-point. - uint32_t primitive_id_temp = - uses_register_dynamic_addressing ? PushSystemTemp() : 1; - in_primitive_id_used_ = true; - RemapAndConvertVertexIndices(primitive_id_temp, 0b0001, - dxbc::Src::VPrim()); - if (uses_register_dynamic_addressing) { - a_.OpMov(dxbc::Dest::X(0, 1, 0b0001), - dxbc::Src::R(primitive_id_temp, dxbc::Src::kXXXX)); - // Release primitive_id_temp. - PopSystemTemp(); - } + // Copy the patch index (already swapped and converted to float by the + // host vertex and hull shaders) to r1.x. + in_control_point_index_used_ = true; + a_.OpMov(uses_register_dynamic_addressing + ? dxbc::Dest::X(0, 1, 0b0001) + : dxbc::Dest::R(1, 0b0001), + dxbc::Src::VICP(0, kInRegisterDSControlPointIndex, + dxbc::Src::kXXXX)); // Write the swizzle of the barycentric coordinates to r1.y. It // appears that the tessellator offloads the reordering of coordinates // for edges to game shaders. @@ -604,19 +599,13 @@ void DxbcShaderTranslator::StartVertexOrDomainShader() { a_.OpMov(uses_register_dynamic_addressing ? dxbc::Dest::X(0, 0, 0b0110) : dxbc::Dest::R(0, 0b0110), dxbc::Src::VDomain(0b010000)); - // Remap and write the primitive index to r0.x as floating-point. - // 4D5307F1 ground quad patches use the primitive index offset. - uint32_t primitive_id_temp = - uses_register_dynamic_addressing ? PushSystemTemp() : 0; - in_primitive_id_used_ = true; - RemapAndConvertVertexIndices(primitive_id_temp, 0b0001, - dxbc::Src::VPrim()); - if (uses_register_dynamic_addressing) { - a_.OpMov(dxbc::Dest::X(0, 0, 0b0001), - dxbc::Src::R(primitive_id_temp, dxbc::Src::kXXXX)); - // Release primitive_id_temp. - PopSystemTemp(); - } + // Copy the patch index (already swapped and converted to float by the + // host vertex and hull shaders) to r0.x. + in_control_point_index_used_ = true; + a_.OpMov(uses_register_dynamic_addressing ? dxbc::Dest::X(0, 0, 0b0001) + : dxbc::Dest::R(0, 0b0001), + dxbc::Src::VICP(0, kInRegisterDSControlPointIndex, + dxbc::Src::kXXXX)); if (register_count() >= 2) { // Write the swizzle of the UV coordinates to r1.x. It appears that // the tessellator offloads the reordering of coordinates for edges to @@ -2763,10 +2752,7 @@ void DxbcShaderTranslator::WriteInputSignature() { } else if (IsDxbcDomainShader()) { // Control point indices, byte-swapped, biased according to the base index // and converted to float by the host vertex and hull shaders - // (XEVERTEXID). Needed even for patch-indexed tessellation modes because - // hull and domain shaders have strict linkage requirements, all hull shader - // outputs must be declared in a domain shader, and the same hull shaders - // are used for control-point-indexed and patch-indexed tessellation modes. + // (XEVERTEXID). size_t control_point_index_position = shader_object_.size(); shader_object_.resize(shader_object_.size() + kParameterDwords); ++parameter_count; @@ -3351,23 +3337,27 @@ void DxbcShaderTranslator::WriteShaderCode() { Modification shader_modification = GetDxbcShaderModification(); + uint32_t control_point_count = 1; if (IsDxbcDomainShader()) { - // Not using control point data since Xenos only has a vertex shader acting - // as both vertex shader and domain shader. - uint32_t control_point_count = 3; dxbc::TessellatorDomain tessellator_domain = dxbc::TessellatorDomain::kTriangle; switch (shader_modification.vertex.host_vertex_shader_type) { case Shader::HostVertexShaderType::kTriangleDomainCPIndexed: - case Shader::HostVertexShaderType::kTriangleDomainPatchIndexed: control_point_count = 3; tessellator_domain = dxbc::TessellatorDomain::kTriangle; break; + case Shader::HostVertexShaderType::kTriangleDomainPatchIndexed: + control_point_count = 1; + tessellator_domain = dxbc::TessellatorDomain::kTriangle; + break; case Shader::HostVertexShaderType::kQuadDomainCPIndexed: - case Shader::HostVertexShaderType::kQuadDomainPatchIndexed: control_point_count = 4; tessellator_domain = dxbc::TessellatorDomain::kQuad; break; + case Shader::HostVertexShaderType::kQuadDomainPatchIndexed: + control_point_count = 1; + tessellator_domain = dxbc::TessellatorDomain::kQuad; + break; default: // TODO(Triang3l): Support line patches. assert_unhandled_case( @@ -3543,30 +3533,9 @@ void DxbcShaderTranslator::WriteShaderCode() { // Domain location input. ao_.OpDclInput(dxbc::Dest::VDomain(in_domain_location_used_)); } - if (in_primitive_id_used_) { - // Primitive (patch) index input. - ao_.OpDclInput(dxbc::Dest::VPrim()); - } if (in_control_point_index_used_) { - // Control point indices as float input. - uint32_t control_point_array_size = 3; - switch (shader_modification.vertex.host_vertex_shader_type) { - case Shader::HostVertexShaderType::kTriangleDomainCPIndexed: - control_point_array_size = 3; - break; - case Shader::HostVertexShaderType::kQuadDomainCPIndexed: - control_point_array_size = 4; - break; - default: - // TODO(Triang3l): Support line patches. - assert_unhandled_case( - shader_modification.vertex.host_vertex_shader_type); - EmitTranslationError( - "Unsupported host vertex shader type in " - "StartVertexOrDomainShader"); - } ao_.OpDclInput(dxbc::Dest::VICP( - control_point_array_size, kInRegisterDSControlPointIndex, 0b0001)); + control_point_count, kInRegisterDSControlPointIndex, 0b0001)); } } else { if (register_count()) { diff --git a/src/xenia/gpu/dxbc_shader_translator.h b/src/xenia/gpu/dxbc_shader_translator.h index 66646c381..9679e43a2 100644 --- a/src/xenia/gpu/dxbc_shader_translator.h +++ b/src/xenia/gpu/dxbc_shader_translator.h @@ -1106,8 +1106,6 @@ class DxbcShaderTranslator : public ShaderTranslator { // Mask of domain location actually used in the domain shader. uint32_t in_domain_location_used_; - // Whether the primitive ID has been used in the domain shader. - bool in_primitive_id_used_; // Whether kInRegisterDSControlPointIndex has been used in the shader. bool in_control_point_index_used_; // Mask of the pixel/sample position actually used in the pixel shader. diff --git a/src/xenia/gpu/primitive_processor.cc b/src/xenia/gpu/primitive_processor.cc index 3e32afa6d..a41b8a432 100644 --- a/src/xenia/gpu/primitive_processor.cc +++ b/src/xenia/gpu/primitive_processor.cc @@ -222,8 +222,7 @@ bool PrimitiveProcessor::Process(ProcessingResult& result_out) { // Parse the primitive type and the tessellation state (VGT_OUTPUT_PATH_CNTL // is only used in the explicit major mode) - there are cases in games when // this register is left over after usage of tessellation in draws that don't - // need it. Also perform needed vertex count adjustments based on the - // primitive type. + // need it. xenos::PrimitiveType guest_primitive_type = vgt_draw_initiator.prim_type; xenos::PrimitiveType host_primitive_type = guest_primitive_type; bool tessellation_enabled = @@ -234,7 +233,6 @@ bool PrimitiveProcessor::Process(ProcessingResult& result_out) { xenos::TessellationMode tessellation_mode = regs.Get().tess_mode; Shader::HostVertexShaderType host_vertex_shader_type; - uint32_t guest_draw_vertex_count = vgt_draw_initiator.num_indices; if (tessellation_enabled) { // Currently only supporting tessellation in known cases for safety, and not // yet converting patch strips / fans to patch lists until games using them @@ -291,29 +289,12 @@ bool PrimitiveProcessor::Process(ProcessingResult& result_out) { // - 4D5307ED - water - adaptive. host_vertex_shader_type = Shader::HostVertexShaderType::kTriangleDomainPatchIndexed; - // See the comment about the rounding for kQuadPatch. - guest_draw_vertex_count = - xe::round_up(guest_draw_vertex_count, uint32_t(3), false); break; case xenos::PrimitiveType::kQuadPatch: // - 4D5307F1 - ground - continuous. // - 4D5307F2 - garden ground - adaptive. host_vertex_shader_type = Shader::HostVertexShaderType::kQuadDomainPatchIndexed; - // While it's known that num_indices represents the control point count - // (4D5307E6, for example, for water triangle patches, performs N - // invocations of the memexporting shader calculating the edge - // tessellation factors for one patch, and then draws the water with - // num_indices = 3 * N), 4D5307F1 ground is drawn with num_indices = 1 - // rather than 4. Unlike Direct3D 11 tessellation, where the patch count - // is `floor(vertex count / control points per patch)`, on the Xenos, - // the count appears to be `ceil` of that value (like a - // `for (i = 0; i < num_indices; i += 4)` loop is used to emit the - // patches). It's unlikely, however, that this adjustment should also be - // done for regular primitive types with tessellation enabled, as - // they're handled as usual primitive topologies, just post-tessellated. - guest_draw_vertex_count = - xe::align(guest_draw_vertex_count, uint32_t(4)); break; default: // TODO(Triang3l): Support line patches. @@ -365,6 +346,7 @@ bool PrimitiveProcessor::Process(ProcessingResult& result_out) { } // Process the indices. + uint32_t guest_draw_vertex_count = vgt_draw_initiator.num_indices; auto vgt_dma_size = regs.Get(); if (vgt_draw_initiator.source_select == xenos::SourceSelect::kDMA && guest_draw_vertex_count > vgt_dma_size.num_words) { diff --git a/src/xenia/gpu/shaders/adaptive_quad.hs.hlsl b/src/xenia/gpu/shaders/adaptive_quad.hs.hlsl index 1e5abf42a..74a942392 100644 --- a/src/xenia/gpu/shaders/adaptive_quad.hs.hlsl +++ b/src/xenia/gpu/shaders/adaptive_quad.hs.hlsl @@ -46,12 +46,17 @@ XeHSConstantDataOutput XePatchConstant( [domain("quad")] [partitioning("fractional_even")] [outputtopology("triangle_cw")] -[outputcontrolpoints(4)] +[outputcontrolpoints(1)] [patchconstantfunc("XePatchConstant")] XeHSControlPointOutput main( - InputPatch xe_input_patch) { + InputPatch xe_input_patch, + uint xe_primitive_id : SV_PrimitiveID) { XeHSControlPointOutput output; - // Not used with control point indices. - output.index = 0.0f; + // Only the lower 24 bits of the vertex index are used (tested on an Adreno + // 200 phone). `((index & 0xFFFFFF) + offset) & 0xFFFFFF` is the same as + // `(index + offset) & 0xFFFFFF`. + output.index = + float(clamp((xe_primitive_id + xe_vertex_index_offset) & 0xFFFFFFu, + xe_vertex_index_min_max.x, xe_vertex_index_min_max.y)); return output; } diff --git a/src/xenia/gpu/shaders/adaptive_triangle.hs.hlsl b/src/xenia/gpu/shaders/adaptive_triangle.hs.hlsl index c88563d79..ce78e3126 100644 --- a/src/xenia/gpu/shaders/adaptive_triangle.hs.hlsl +++ b/src/xenia/gpu/shaders/adaptive_triangle.hs.hlsl @@ -51,12 +51,17 @@ XeHSConstantDataOutput XePatchConstant( [domain("tri")] [partitioning("fractional_even")] [outputtopology("triangle_cw")] -[outputcontrolpoints(3)] +[outputcontrolpoints(1)] [patchconstantfunc("XePatchConstant")] XeHSControlPointOutput main( - InputPatch xe_input_patch) { + InputPatch xe_input_patch, + uint xe_primitive_id : SV_PrimitiveID) { XeHSControlPointOutput output; - // Not used with control point indices. - output.index = 0.0f; + // Only the lower 24 bits of the vertex index are used (tested on an Adreno + // 200 phone). `((index & 0xFFFFFF) + offset) & 0xFFFFFF` is the same as + // `(index + offset) & 0xFFFFFF`. + output.index = + float(clamp((xe_primitive_id + xe_vertex_index_offset) & 0xFFFFFFu, + xe_vertex_index_min_max.x, xe_vertex_index_min_max.y)); return output; } diff --git a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/adaptive_quad_hs.h b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/adaptive_quad_hs.h index 1ff1d3d38..9de916831 100644 --- a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/adaptive_quad_hs.h +++ b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/adaptive_quad_hs.h @@ -3,6 +3,52 @@ // Generated by Microsoft (R) HLSL Shader Compiler 10.1 // // +// Buffer Definitions: +// +// cbuffer xe_system_cbuffer +// { +// +// uint xe_flags; // Offset: 0 Size: 4 [unused] +// float2 xe_tessellation_factor_range;// Offset: 4 Size: 8 [unused] +// uint xe_line_loop_closing_index; // Offset: 12 Size: 4 [unused] +// uint xe_vertex_index_endian; // Offset: 16 Size: 4 [unused] +// uint xe_vertex_index_offset; // Offset: 20 Size: 4 +// uint2 xe_vertex_index_min_max; // Offset: 24 Size: 8 +// float4 xe_user_clip_planes[6]; // Offset: 32 Size: 96 [unused] +// float3 xe_ndc_scale; // Offset: 128 Size: 12 [unused] +// float xe_point_vertex_diameter_min;// Offset: 140 Size: 4 [unused] +// float3 xe_ndc_offset; // Offset: 144 Size: 12 [unused] +// float xe_point_vertex_diameter_max;// Offset: 156 Size: 4 [unused] +// float2 xe_point_constant_diameter; // Offset: 160 Size: 8 [unused] +// float2 xe_point_screen_diameter_to_ndc_radius;// Offset: 168 Size: 8 [unused] +// uint4 xe_texture_swizzled_signs[2];// Offset: 176 Size: 32 [unused] +// uint xe_textures_resolved; // Offset: 208 Size: 4 [unused] +// uint2 xe_sample_count_log2; // Offset: 212 Size: 8 [unused] +// float xe_alpha_test_reference; // Offset: 220 Size: 4 [unused] +// uint xe_alpha_to_mask; // Offset: 224 Size: 4 [unused] +// uint xe_edram_32bpp_tile_pitch_dwords_scaled;// Offset: 228 Size: 4 [unused] +// uint xe_edram_depth_base_dwords_scaled;// Offset: 232 Size: 4 [unused] +// float4 xe_color_exp_bias; // Offset: 240 Size: 16 [unused] +// float2 xe_edram_poly_offset_front; // Offset: 256 Size: 8 [unused] +// float2 xe_edram_poly_offset_back; // Offset: 264 Size: 8 [unused] +// uint4 xe_edram_stencil[2]; // Offset: 272 Size: 32 [unused] +// uint4 xe_edram_rt_base_dwords_scaled;// Offset: 304 Size: 16 [unused] +// uint4 xe_edram_rt_format_flags; // Offset: 320 Size: 16 [unused] +// float4 xe_edram_rt_clamp[4]; // Offset: 336 Size: 64 [unused] +// uint4 xe_edram_rt_keep_mask[2]; // Offset: 400 Size: 32 [unused] +// uint4 xe_edram_rt_blend_factors_ops;// Offset: 432 Size: 16 [unused] +// float4 xe_edram_blend_constant; // Offset: 448 Size: 16 [unused] +// +// } +// +// +// Resource Bindings: +// +// Name Type Format Dim ID HLSL Bind Count +// ------------------------------ ---------- ------- ----------- ------- -------------- ------ +// xe_system_cbuffer cbuffer NA NA CB0 cb0 1 +// +// // // Patch Constant signature: // @@ -31,7 +77,7 @@ // // Tessellation Domain # of control points // -------------------- -------------------- -// Quadrilateral 4 +// Quadrilateral 1 // // Tessellation Output Primitive Partitioning Type // ------------------------------ ------------------ @@ -40,14 +86,21 @@ hs_5_1 hs_decls dcl_input_control_point_count 4 -dcl_output_control_point_count 4 +dcl_output_control_point_count 1 dcl_tessellator_domain domain_quad dcl_tessellator_partitioning partitioning_fractional_even dcl_tessellator_output_primitive output_triangle_cw dcl_globalFlags refactoringAllowed +dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0 hs_control_point_phase +dcl_input vPrim dcl_output o0.x -mov o0.x, l(0) +dcl_temps 1 +iadd r0.x, vPrim, CB0[0][1].y +and r0.x, r0.x, l(0x00ffffff) +umax r0.x, r0.x, CB0[0][1].z +umin r0.x, r0.x, CB0[0][1].w +utof o0.x, r0.x ret hs_fork_phase dcl_hs_fork_phase_instance_count 4 @@ -79,209 +132,656 @@ min r0.x, vicp[r0.y + 2][0].x, vicp[r0.x + 0][0].x mov r0.y, vForkInstanceID.x mov o[r0.y + 4].x, r0.x ret -// Approximately 14 instruction slots used +// Approximately 18 instruction slots used #endif const BYTE adaptive_quad_hs[] = { - 68, 88, 66, 67, 91, 114, - 196, 93, 35, 195, 210, 49, - 154, 70, 168, 244, 8, 132, - 25, 246, 1, 0, 0, 0, - 176, 4, 0, 0, 6, 0, + 68, 88, 66, 67, 239, 150, + 141, 161, 148, 167, 208, 252, + 147, 2, 216, 119, 8, 207, + 171, 137, 1, 0, 0, 0, + 40, 15, 0, 0, 6, 0, 0, 0, 56, 0, 0, 0, - 164, 0, 0, 0, 220, 0, - 0, 0, 16, 1, 0, 0, - 212, 1, 0, 0, 20, 4, + 108, 10, 0, 0, 164, 10, + 0, 0, 216, 10, 0, 0, + 156, 11, 0, 0, 140, 14, 0, 0, 82, 68, 69, 70, - 100, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 60, 0, + 44, 10, 0, 0, 1, 0, + 0, 0, 120, 0, 0, 0, + 1, 0, 0, 0, 60, 0, 0, 0, 1, 5, 83, 72, - 0, 5, 0, 0, 60, 0, + 0, 5, 0, 0, 2, 10, 0, 0, 19, 19, 68, 37, 60, 0, 0, 0, 24, 0, 0, 0, 40, 0, 0, 0, 40, 0, 0, 0, 36, 0, 0, 0, 12, 0, 0, 0, - 0, 0, 0, 0, 77, 105, + 0, 0, 0, 0, 100, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 120, 101, 95, 115, + 121, 115, 116, 101, 109, 95, + 99, 98, 117, 102, 102, 101, + 114, 0, 171, 171, 100, 0, + 0, 0, 30, 0, 0, 0, + 144, 0, 0, 0, 208, 1, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 64, 5, + 0, 0, 0, 0, 0, 0, + 4, 0, 0, 0, 0, 0, + 0, 0, 80, 5, 0, 0, + 0, 0, 0, 0, 255, 255, + 255, 255, 0, 0, 0, 0, + 255, 255, 255, 255, 0, 0, + 0, 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1, 0, 0, 0, 0, 0, - 0, 0, 6, 0, 0, 0, - 1, 0, 0, 0, 2, 0, - 0, 0, 2, 0, 0, 0, + 0, 0, 11, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 3, 0, + 0, 0, 4, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 5, 0, 0, 0, 1, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 11, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 4, 0, 0, 0, - 3, 0, 0, 0, 4, 0, - 0, 0, 3, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 + 0, 0, 0, 0 }; diff --git a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/adaptive_triangle_hs.h b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/adaptive_triangle_hs.h index 4d9950a38..2a7f73920 100644 --- a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/adaptive_triangle_hs.h +++ b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/adaptive_triangle_hs.h @@ -3,6 +3,52 @@ // Generated by Microsoft (R) HLSL Shader Compiler 10.1 // // +// Buffer Definitions: +// +// cbuffer xe_system_cbuffer +// { +// +// uint xe_flags; // Offset: 0 Size: 4 [unused] +// float2 xe_tessellation_factor_range;// Offset: 4 Size: 8 [unused] +// uint xe_line_loop_closing_index; // Offset: 12 Size: 4 [unused] +// uint xe_vertex_index_endian; // Offset: 16 Size: 4 [unused] +// uint xe_vertex_index_offset; // Offset: 20 Size: 4 +// uint2 xe_vertex_index_min_max; // Offset: 24 Size: 8 +// float4 xe_user_clip_planes[6]; // Offset: 32 Size: 96 [unused] +// float3 xe_ndc_scale; // Offset: 128 Size: 12 [unused] +// float xe_point_vertex_diameter_min;// Offset: 140 Size: 4 [unused] +// float3 xe_ndc_offset; // Offset: 144 Size: 12 [unused] +// float xe_point_vertex_diameter_max;// Offset: 156 Size: 4 [unused] +// float2 xe_point_constant_diameter; // Offset: 160 Size: 8 [unused] +// float2 xe_point_screen_diameter_to_ndc_radius;// Offset: 168 Size: 8 [unused] +// uint4 xe_texture_swizzled_signs[2];// Offset: 176 Size: 32 [unused] +// uint xe_textures_resolved; // Offset: 208 Size: 4 [unused] +// uint2 xe_sample_count_log2; // Offset: 212 Size: 8 [unused] +// float xe_alpha_test_reference; // Offset: 220 Size: 4 [unused] +// uint xe_alpha_to_mask; // Offset: 224 Size: 4 [unused] +// uint xe_edram_32bpp_tile_pitch_dwords_scaled;// Offset: 228 Size: 4 [unused] +// uint xe_edram_depth_base_dwords_scaled;// Offset: 232 Size: 4 [unused] +// float4 xe_color_exp_bias; // Offset: 240 Size: 16 [unused] +// float2 xe_edram_poly_offset_front; // Offset: 256 Size: 8 [unused] +// float2 xe_edram_poly_offset_back; // Offset: 264 Size: 8 [unused] +// uint4 xe_edram_stencil[2]; // Offset: 272 Size: 32 [unused] +// uint4 xe_edram_rt_base_dwords_scaled;// Offset: 304 Size: 16 [unused] +// uint4 xe_edram_rt_format_flags; // Offset: 320 Size: 16 [unused] +// float4 xe_edram_rt_clamp[4]; // Offset: 336 Size: 64 [unused] +// uint4 xe_edram_rt_keep_mask[2]; // Offset: 400 Size: 32 [unused] +// uint4 xe_edram_rt_blend_factors_ops;// Offset: 432 Size: 16 [unused] +// float4 xe_edram_blend_constant; // Offset: 448 Size: 16 [unused] +// +// } +// +// +// Resource Bindings: +// +// Name Type Format Dim ID HLSL Bind Count +// ------------------------------ ---------- ------- ----------- ------- -------------- ------ +// xe_system_cbuffer cbuffer NA NA CB0 cb0 1 +// +// // // Patch Constant signature: // @@ -29,7 +75,7 @@ // // Tessellation Domain # of control points // -------------------- -------------------- -// Triangle 3 +// Triangle 1 // // Tessellation Output Primitive Partitioning Type // ------------------------------ ------------------ @@ -38,14 +84,21 @@ hs_5_1 hs_decls dcl_input_control_point_count 3 -dcl_output_control_point_count 3 +dcl_output_control_point_count 1 dcl_tessellator_domain domain_tri dcl_tessellator_partitioning partitioning_fractional_even dcl_tessellator_output_primitive output_triangle_cw dcl_globalFlags refactoringAllowed +dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0 hs_control_point_phase +dcl_input vPrim dcl_output o0.x -mov o0.x, l(0) +dcl_temps 1 +iadd r0.x, vPrim, CB0[0][1].y +and r0.x, r0.x, l(0x00ffffff) +umax r0.x, r0.x, CB0[0][1].z +umin r0.x, r0.x, CB0[0][1].w +utof o0.x, r0.x ret hs_fork_phase dcl_hs_fork_phase_instance_count 3 @@ -68,175 +121,621 @@ dcl_temps 1 min r0.x, vicp[2][0].x, vicp[1][0].x min o3.x, r0.x, vicp[0][0].x ret -// Approximately 10 instruction slots used +// Approximately 14 instruction slots used #endif const BYTE adaptive_triangle_hs[] = { - 68, 88, 66, 67, 10, 165, - 117, 176, 19, 12, 130, 108, - 171, 104, 195, 161, 52, 251, - 99, 193, 1, 0, 0, 0, - 224, 3, 0, 0, 6, 0, + 68, 88, 66, 67, 213, 151, + 26, 214, 48, 115, 215, 10, + 67, 36, 129, 21, 5, 111, + 231, 249, 1, 0, 0, 0, + 88, 14, 0, 0, 6, 0, 0, 0, 56, 0, 0, 0, - 164, 0, 0, 0, 220, 0, - 0, 0, 16, 1, 0, 0, - 164, 1, 0, 0, 68, 3, + 108, 10, 0, 0, 164, 10, + 0, 0, 216, 10, 0, 0, + 108, 11, 0, 0, 188, 13, 0, 0, 82, 68, 69, 70, - 100, 0, 0, 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0, - 0, 0, 10, 144, 33, 0, + 83, 84, 65, 84, 148, 0, + 0, 0, 14, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 0, 51, 0, 0, 8, - 18, 32, 16, 0, 3, 0, - 0, 0, 10, 0, 16, 0, - 0, 0, 0, 0, 10, 144, - 33, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 62, 0, - 0, 1, 83, 84, 65, 84, - 148, 0, 0, 0, 10, 0, + 0, 0, 5, 0, 0, 0, + 2, 0, 0, 0, 2, 0, + 0, 0, 4, 0, 0, 0, + 3, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 2, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, - 0, 0, 0, 0, 5, 0, + 0, 0, 0, 0, 10, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 1, 0, 0, 0, + 3, 0, 0, 0, 4, 0, 0, 0, 2, 0, 0, 0, - 1, 0, 0, 0, 1, 0, - 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 3, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 10, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 3, 0, - 0, 0, 3, 0, 0, 0, - 4, 0, 0, 0, 2, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0 + 0, 0, 0, 0, 0, 0 }; diff --git a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_quad_1cp_hs.h b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_quad_1cp_hs.h new file mode 100644 index 000000000..24e011399 --- /dev/null +++ b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_quad_1cp_hs.h @@ -0,0 +1,719 @@ +#if 0 +// +// Generated by Microsoft (R) HLSL Shader Compiler 10.1 +// +// +// Buffer Definitions: +// +// cbuffer xe_system_cbuffer +// { +// +// uint xe_flags; // Offset: 0 Size: 4 [unused] +// float2 xe_tessellation_factor_range;// Offset: 4 Size: 8 +// uint xe_line_loop_closing_index; // Offset: 12 Size: 4 [unused] +// uint xe_vertex_index_endian; // Offset: 16 Size: 4 [unused] +// uint xe_vertex_index_offset; // Offset: 20 Size: 4 [unused] +// uint2 xe_vertex_index_min_max; // Offset: 24 Size: 8 [unused] +// float4 xe_user_clip_planes[6]; // Offset: 32 Size: 96 [unused] +// float3 xe_ndc_scale; // Offset: 128 Size: 12 [unused] +// float xe_point_vertex_diameter_min;// Offset: 140 Size: 4 [unused] +// float3 xe_ndc_offset; // Offset: 144 Size: 12 [unused] +// float xe_point_vertex_diameter_max;// Offset: 156 Size: 4 [unused] +// float2 xe_point_constant_diameter; // Offset: 160 Size: 8 [unused] +// float2 xe_point_screen_diameter_to_ndc_radius;// Offset: 168 Size: 8 [unused] +// uint4 xe_texture_swizzled_signs[2];// Offset: 176 Size: 32 [unused] +// uint xe_textures_resolved; // Offset: 208 Size: 4 [unused] +// uint2 xe_sample_count_log2; // Offset: 212 Size: 8 [unused] +// float xe_alpha_test_reference; // Offset: 220 Size: 4 [unused] +// uint xe_alpha_to_mask; // Offset: 224 Size: 4 [unused] +// uint xe_edram_32bpp_tile_pitch_dwords_scaled;// Offset: 228 Size: 4 [unused] +// uint xe_edram_depth_base_dwords_scaled;// Offset: 232 Size: 4 [unused] +// float4 xe_color_exp_bias; // Offset: 240 Size: 16 [unused] +// float2 xe_edram_poly_offset_front; // Offset: 256 Size: 8 [unused] +// float2 xe_edram_poly_offset_back; // Offset: 264 Size: 8 [unused] +// uint4 xe_edram_stencil[2]; // Offset: 272 Size: 32 [unused] +// uint4 xe_edram_rt_base_dwords_scaled;// Offset: 304 Size: 16 [unused] +// uint4 xe_edram_rt_format_flags; // Offset: 320 Size: 16 [unused] +// float4 xe_edram_rt_clamp[4]; // Offset: 336 Size: 64 [unused] +// uint4 xe_edram_rt_keep_mask[2]; // Offset: 400 Size: 32 [unused] +// uint4 xe_edram_rt_blend_factors_ops;// Offset: 432 Size: 16 [unused] +// float4 xe_edram_blend_constant; // Offset: 448 Size: 16 [unused] +// +// } +// +// +// Resource Bindings: +// +// Name Type Format Dim ID HLSL Bind Count +// ------------------------------ ---------- ------- ----------- ------- -------------- ------ +// xe_system_cbuffer cbuffer NA NA CB0 cb0 1 +// +// +// +// Patch Constant signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// SV_TessFactor 0 x 0 QUADEDGE float x +// SV_TessFactor 1 x 1 QUADEDGE float x +// SV_TessFactor 2 x 2 QUADEDGE float x +// SV_TessFactor 3 x 3 QUADEDGE float x +// SV_InsideTessFactor 0 x 4 QUADINT float x +// SV_InsideTessFactor 1 x 5 QUADINT float x +// +// +// Input signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// XEVERTEXID 0 x 0 NONE float x +// +// +// Output signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// XEVERTEXID 0 x 0 NONE float x +// +// Tessellation Domain # of control points +// -------------------- -------------------- +// Quadrilateral 1 +// +// Tessellation Output Primitive Partitioning Type +// ------------------------------ ------------------ +// Clockwise Triangles Even Fractional +// +hs_5_1 +hs_decls +dcl_input_control_point_count 1 +dcl_output_control_point_count 1 +dcl_tessellator_domain domain_quad +dcl_tessellator_partitioning partitioning_fractional_even +dcl_tessellator_output_primitive output_triangle_cw +dcl_globalFlags refactoringAllowed +dcl_constantbuffer CB0[0:0][1], immediateIndexed, space=0 +hs_control_point_phase +dcl_input v[1][0].x +dcl_output o0.x +mov o0.x, v[0][0].x +ret +hs_fork_phase +dcl_hs_fork_phase_instance_count 4 +dcl_input vForkInstanceID +dcl_output_siv o0.x, finalQuadUeq0EdgeTessFactor +dcl_output_siv o1.x, finalQuadVeq0EdgeTessFactor +dcl_output_siv o2.x, finalQuadUeq1EdgeTessFactor +dcl_output_siv o3.x, finalQuadVeq1EdgeTessFactor +dcl_temps 1 +dcl_indexrange o0.x 4 +mov r0.x, vForkInstanceID.x +mov o[r0.x + 0].x, CB0[0][0].z +ret +hs_fork_phase +dcl_hs_fork_phase_instance_count 2 +dcl_input vForkInstanceID +dcl_output_siv o4.x, finalQuadUInsideTessFactor +dcl_output_siv o5.x, finalQuadVInsideTessFactor +dcl_temps 1 +dcl_indexrange o4.x 2 +mov r0.x, vForkInstanceID.x +mov o[r0.x + 4].x, CB0[0][0].z +ret +// Approximately 8 instruction slots used +#endif + +const BYTE continuous_quad_1cp_hs[] = +{ + 68, 88, 66, 67, 255, 166, + 36, 40, 167, 89, 99, 45, + 74, 91, 165, 30, 112, 56, + 14, 246, 1, 0, 0, 0, + 220, 13, 0, 0, 6, 0, + 0, 0, 56, 0, 0, 0, + 108, 10, 0, 0, 160, 10, + 0, 0, 212, 10, 0, 0, + 152, 11, 0, 0, 64, 13, + 0, 0, 82, 68, 69, 70, + 44, 10, 0, 0, 1, 0, + 0, 0, 120, 0, 0, 0, + 1, 0, 0, 0, 60, 0, + 0, 0, 1, 5, 83, 72, + 0, 5, 0, 0, 2, 10, + 0, 0, 19, 19, 68, 37, + 60, 0, 0, 0, 24, 0, + 0, 0, 40, 0, 0, 0, + 40, 0, 0, 0, 36, 0, + 0, 0, 12, 0, 0, 0, + 0, 0, 0, 0, 100, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 120, 101, 95, 115, + 121, 115, 116, 101, 109, 95, + 99, 98, 117, 102, 102, 101, + 114, 0, 171, 171, 100, 0, + 0, 0, 30, 0, 0, 0, + 144, 0, 0, 0, 208, 1, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 64, 5, + 0, 0, 0, 0, 0, 0, + 4, 0, 0, 0, 0, 0, + 0, 0, 80, 5, 0, 0, + 0, 0, 0, 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0, + 103, 0, 0, 4, 18, 32, + 16, 0, 3, 0, 0, 0, + 14, 0, 0, 0, 104, 0, + 0, 2, 1, 0, 0, 0, + 91, 0, 0, 4, 18, 32, + 16, 0, 0, 0, 0, 0, + 4, 0, 0, 0, 54, 0, + 0, 4, 18, 0, 16, 0, + 0, 0, 0, 0, 10, 112, + 1, 0, 54, 0, 0, 8, + 18, 32, 144, 0, 10, 0, + 16, 0, 0, 0, 0, 0, + 42, 128, 48, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 62, 0, + 0, 1, 115, 0, 0, 1, + 153, 0, 0, 2, 2, 0, + 0, 0, 95, 0, 0, 2, + 0, 112, 1, 0, 103, 0, + 0, 4, 18, 32, 16, 0, + 4, 0, 0, 0, 15, 0, + 0, 0, 103, 0, 0, 4, + 18, 32, 16, 0, 5, 0, + 0, 0, 16, 0, 0, 0, + 104, 0, 0, 2, 1, 0, + 0, 0, 91, 0, 0, 4, + 18, 32, 16, 0, 4, 0, + 0, 0, 2, 0, 0, 0, + 54, 0, 0, 4, 18, 0, + 16, 0, 0, 0, 0, 0, + 10, 112, 1, 0, 54, 0, + 0, 9, 18, 32, 208, 0, + 4, 0, 0, 0, 10, 0, + 16, 0, 0, 0, 0, 0, + 42, 128, 48, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 62, 0, + 0, 1, 83, 84, 65, 84, + 148, 0, 0, 0, 8, 0, + 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 5, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 3, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 5, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 8, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 0, + 0, 0, 3, 0, 0, 0, + 4, 0, 0, 0, 3, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0 +}; diff --git a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_quad_hs.h b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_quad_4cp_hs.h similarity index 99% rename from src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_quad_hs.h rename to src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_quad_4cp_hs.h index 65fcd3997..d5b9c9482 100644 --- a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_quad_hs.h +++ b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_quad_4cp_hs.h @@ -117,7 +117,7 @@ ret // Approximately 6 instruction slots used #endif -const BYTE continuous_quad_hs[] = +const BYTE continuous_quad_4cp_hs[] = { 68, 88, 66, 67, 196, 234, 51, 156, 242, 124, 98, 132, diff --git a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_triangle_1cp_hs.h b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_triangle_1cp_hs.h new file mode 100644 index 000000000..fe4cd78fa --- /dev/null +++ b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_triangle_1cp_hs.h @@ -0,0 +1,686 @@ +#if 0 +// +// Generated by Microsoft (R) HLSL Shader Compiler 10.1 +// +// +// Buffer Definitions: +// +// cbuffer xe_system_cbuffer +// { +// +// uint xe_flags; // Offset: 0 Size: 4 [unused] +// float2 xe_tessellation_factor_range;// Offset: 4 Size: 8 +// uint xe_line_loop_closing_index; // Offset: 12 Size: 4 [unused] +// uint xe_vertex_index_endian; // Offset: 16 Size: 4 [unused] +// uint xe_vertex_index_offset; // Offset: 20 Size: 4 [unused] +// uint2 xe_vertex_index_min_max; // Offset: 24 Size: 8 [unused] +// float4 xe_user_clip_planes[6]; // Offset: 32 Size: 96 [unused] +// float3 xe_ndc_scale; // Offset: 128 Size: 12 [unused] +// float xe_point_vertex_diameter_min;// Offset: 140 Size: 4 [unused] +// float3 xe_ndc_offset; // Offset: 144 Size: 12 [unused] +// float xe_point_vertex_diameter_max;// Offset: 156 Size: 4 [unused] +// float2 xe_point_constant_diameter; // Offset: 160 Size: 8 [unused] +// float2 xe_point_screen_diameter_to_ndc_radius;// Offset: 168 Size: 8 [unused] +// uint4 xe_texture_swizzled_signs[2];// Offset: 176 Size: 32 [unused] +// uint xe_textures_resolved; // Offset: 208 Size: 4 [unused] +// uint2 xe_sample_count_log2; // Offset: 212 Size: 8 [unused] +// float xe_alpha_test_reference; // Offset: 220 Size: 4 [unused] +// uint xe_alpha_to_mask; // Offset: 224 Size: 4 [unused] +// uint xe_edram_32bpp_tile_pitch_dwords_scaled;// Offset: 228 Size: 4 [unused] +// uint xe_edram_depth_base_dwords_scaled;// Offset: 232 Size: 4 [unused] +// float4 xe_color_exp_bias; // Offset: 240 Size: 16 [unused] +// float2 xe_edram_poly_offset_front; // Offset: 256 Size: 8 [unused] +// float2 xe_edram_poly_offset_back; // Offset: 264 Size: 8 [unused] +// uint4 xe_edram_stencil[2]; // Offset: 272 Size: 32 [unused] +// uint4 xe_edram_rt_base_dwords_scaled;// Offset: 304 Size: 16 [unused] +// uint4 xe_edram_rt_format_flags; // Offset: 320 Size: 16 [unused] +// float4 xe_edram_rt_clamp[4]; // Offset: 336 Size: 64 [unused] +// uint4 xe_edram_rt_keep_mask[2]; // Offset: 400 Size: 32 [unused] +// uint4 xe_edram_rt_blend_factors_ops;// Offset: 432 Size: 16 [unused] +// float4 xe_edram_blend_constant; // Offset: 448 Size: 16 [unused] +// +// } +// +// +// Resource Bindings: +// +// Name Type Format Dim ID HLSL Bind Count +// ------------------------------ ---------- ------- ----------- ------- -------------- ------ +// xe_system_cbuffer cbuffer NA NA CB0 cb0 1 +// +// +// +// Patch Constant signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// SV_TessFactor 0 x 0 TRIEDGE float x +// SV_TessFactor 1 x 1 TRIEDGE float x +// SV_TessFactor 2 x 2 TRIEDGE float x +// SV_InsideTessFactor 0 x 3 TRIINT float x +// +// +// Input signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// XEVERTEXID 0 x 0 NONE float x +// +// +// Output signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// XEVERTEXID 0 x 0 NONE float x +// +// Tessellation Domain # of control points +// -------------------- -------------------- +// Triangle 1 +// +// Tessellation Output Primitive Partitioning Type +// ------------------------------ ------------------ +// Clockwise Triangles Even Fractional +// +hs_5_1 +hs_decls +dcl_input_control_point_count 1 +dcl_output_control_point_count 1 +dcl_tessellator_domain domain_tri +dcl_tessellator_partitioning partitioning_fractional_even +dcl_tessellator_output_primitive output_triangle_cw +dcl_globalFlags refactoringAllowed +dcl_constantbuffer CB0[0:0][1], immediateIndexed, space=0 +hs_control_point_phase +dcl_input v[1][0].x +dcl_output o0.x +mov o0.x, v[0][0].x +ret +hs_fork_phase +dcl_hs_fork_phase_instance_count 3 +dcl_input vForkInstanceID +dcl_output_siv o0.x, finalTriUeq0EdgeTessFactor +dcl_output_siv o1.x, finalTriVeq0EdgeTessFactor +dcl_output_siv o2.x, finalTriWeq0EdgeTessFactor +dcl_temps 1 +dcl_indexrange o0.x 3 +mov r0.x, vForkInstanceID.x +mov o[r0.x + 0].x, CB0[0][0].z +ret +hs_fork_phase +dcl_output_siv o3.x, finalTriInsideTessFactor +mov o3.x, CB0[0][0].z +ret +// Approximately 7 instruction slots used +#endif + +const BYTE continuous_triangle_1cp_hs[] = +{ + 68, 88, 66, 67, 90, 24, + 246, 119, 168, 170, 239, 21, + 106, 76, 181, 188, 133, 81, + 250, 172, 1, 0, 0, 0, + 76, 13, 0, 0, 6, 0, + 0, 0, 56, 0, 0, 0, + 108, 10, 0, 0, 160, 10, + 0, 0, 212, 10, 0, 0, + 104, 11, 0, 0, 176, 12, + 0, 0, 82, 68, 69, 70, + 44, 10, 0, 0, 1, 0, + 0, 0, 120, 0, 0, 0, + 1, 0, 0, 0, 60, 0, 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0, 0, 3, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 4, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 8, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 0, + 0, 0, 3, 0, 0, 0, + 4, 0, 0, 0, 2, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0 +}; diff --git a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_triangle_hs.h b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_triangle_3cp_hs.h similarity index 99% rename from src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_triangle_hs.h rename to src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_triangle_3cp_hs.h index 3e6f39bfe..18e207dd2 100644 --- a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_triangle_hs.h +++ b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/continuous_triangle_3cp_hs.h @@ -108,7 +108,7 @@ ret // Approximately 5 instruction slots used #endif -const BYTE continuous_triangle_hs[] = +const BYTE continuous_triangle_3cp_hs[] = { 68, 88, 66, 67, 40, 16, 64, 130, 119, 149, 137, 0, diff --git a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_quad_1cp_hs.h b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_quad_1cp_hs.h new file mode 100644 index 000000000..1ee226351 --- /dev/null +++ b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_quad_1cp_hs.h @@ -0,0 +1,719 @@ +#if 0 +// +// Generated by Microsoft (R) HLSL Shader Compiler 10.1 +// +// +// Buffer Definitions: +// +// cbuffer xe_system_cbuffer +// { +// +// uint xe_flags; // Offset: 0 Size: 4 [unused] +// float2 xe_tessellation_factor_range;// Offset: 4 Size: 8 +// uint xe_line_loop_closing_index; // Offset: 12 Size: 4 [unused] +// uint xe_vertex_index_endian; // Offset: 16 Size: 4 [unused] +// uint xe_vertex_index_offset; // Offset: 20 Size: 4 [unused] +// uint2 xe_vertex_index_min_max; // Offset: 24 Size: 8 [unused] +// float4 xe_user_clip_planes[6]; // Offset: 32 Size: 96 [unused] +// float3 xe_ndc_scale; // Offset: 128 Size: 12 [unused] +// float xe_point_vertex_diameter_min;// Offset: 140 Size: 4 [unused] +// float3 xe_ndc_offset; // Offset: 144 Size: 12 [unused] +// float xe_point_vertex_diameter_max;// Offset: 156 Size: 4 [unused] +// float2 xe_point_constant_diameter; // Offset: 160 Size: 8 [unused] +// float2 xe_point_screen_diameter_to_ndc_radius;// Offset: 168 Size: 8 [unused] +// uint4 xe_texture_swizzled_signs[2];// Offset: 176 Size: 32 [unused] +// uint xe_textures_resolved; // Offset: 208 Size: 4 [unused] +// uint2 xe_sample_count_log2; // Offset: 212 Size: 8 [unused] +// float xe_alpha_test_reference; // Offset: 220 Size: 4 [unused] +// uint xe_alpha_to_mask; // Offset: 224 Size: 4 [unused] +// uint xe_edram_32bpp_tile_pitch_dwords_scaled;// Offset: 228 Size: 4 [unused] +// uint xe_edram_depth_base_dwords_scaled;// Offset: 232 Size: 4 [unused] +// float4 xe_color_exp_bias; // Offset: 240 Size: 16 [unused] +// float2 xe_edram_poly_offset_front; // Offset: 256 Size: 8 [unused] +// float2 xe_edram_poly_offset_back; // Offset: 264 Size: 8 [unused] +// uint4 xe_edram_stencil[2]; // Offset: 272 Size: 32 [unused] +// uint4 xe_edram_rt_base_dwords_scaled;// Offset: 304 Size: 16 [unused] +// uint4 xe_edram_rt_format_flags; // Offset: 320 Size: 16 [unused] +// float4 xe_edram_rt_clamp[4]; // Offset: 336 Size: 64 [unused] +// uint4 xe_edram_rt_keep_mask[2]; // Offset: 400 Size: 32 [unused] +// uint4 xe_edram_rt_blend_factors_ops;// Offset: 432 Size: 16 [unused] +// float4 xe_edram_blend_constant; // Offset: 448 Size: 16 [unused] +// +// } +// +// +// Resource Bindings: +// +// Name Type Format Dim ID HLSL Bind Count +// ------------------------------ ---------- ------- ----------- ------- -------------- ------ +// xe_system_cbuffer cbuffer NA NA CB0 cb0 1 +// +// +// +// Patch Constant signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// SV_TessFactor 0 x 0 QUADEDGE float x +// SV_TessFactor 1 x 1 QUADEDGE float x +// SV_TessFactor 2 x 2 QUADEDGE float x +// SV_TessFactor 3 x 3 QUADEDGE float x +// SV_InsideTessFactor 0 x 4 QUADINT float x +// SV_InsideTessFactor 1 x 5 QUADINT float x +// +// +// Input signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// XEVERTEXID 0 x 0 NONE float x +// +// +// Output signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// XEVERTEXID 0 x 0 NONE float x +// +// Tessellation Domain # of control points +// -------------------- -------------------- +// Quadrilateral 1 +// +// Tessellation Output Primitive Partitioning Type +// ------------------------------ ------------------ +// Clockwise Triangles Integer +// +hs_5_1 +hs_decls +dcl_input_control_point_count 1 +dcl_output_control_point_count 1 +dcl_tessellator_domain domain_quad +dcl_tessellator_partitioning partitioning_integer +dcl_tessellator_output_primitive output_triangle_cw +dcl_globalFlags refactoringAllowed +dcl_constantbuffer CB0[0:0][1], immediateIndexed, space=0 +hs_control_point_phase +dcl_input v[1][0].x +dcl_output o0.x +mov o0.x, v[0][0].x +ret +hs_fork_phase +dcl_hs_fork_phase_instance_count 4 +dcl_input vForkInstanceID +dcl_output_siv o0.x, finalQuadUeq0EdgeTessFactor +dcl_output_siv o1.x, finalQuadVeq0EdgeTessFactor +dcl_output_siv o2.x, finalQuadUeq1EdgeTessFactor +dcl_output_siv o3.x, finalQuadVeq1EdgeTessFactor +dcl_temps 1 +dcl_indexrange o0.x 4 +mov r0.x, vForkInstanceID.x +mov o[r0.x + 0].x, CB0[0][0].z +ret +hs_fork_phase +dcl_hs_fork_phase_instance_count 2 +dcl_input vForkInstanceID +dcl_output_siv o4.x, finalQuadUInsideTessFactor +dcl_output_siv o5.x, finalQuadVInsideTessFactor +dcl_temps 1 +dcl_indexrange o4.x 2 +mov r0.x, vForkInstanceID.x +mov o[r0.x + 4].x, CB0[0][0].z +ret +// Approximately 8 instruction slots used +#endif + +const BYTE discrete_quad_1cp_hs[] = +{ + 68, 88, 66, 67, 166, 226, + 56, 134, 119, 149, 47, 144, + 135, 3, 42, 236, 243, 129, + 164, 56, 1, 0, 0, 0, + 220, 13, 0, 0, 6, 0, + 0, 0, 56, 0, 0, 0, + 108, 10, 0, 0, 160, 10, + 0, 0, 212, 10, 0, 0, + 152, 11, 0, 0, 64, 13, + 0, 0, 82, 68, 69, 70, + 44, 10, 0, 0, 1, 0, + 0, 0, 120, 0, 0, 0, + 1, 0, 0, 0, 60, 0, + 0, 0, 1, 5, 83, 72, + 0, 5, 0, 0, 2, 10, + 0, 0, 19, 19, 68, 37, + 60, 0, 0, 0, 24, 0, + 0, 0, 40, 0, 0, 0, + 40, 0, 0, 0, 36, 0, + 0, 0, 12, 0, 0, 0, + 0, 0, 0, 0, 100, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 120, 101, 95, 115, + 121, 115, 116, 101, 109, 95, + 99, 98, 117, 102, 102, 101, + 114, 0, 171, 171, 100, 0, + 0, 0, 30, 0, 0, 0, + 144, 0, 0, 0, 208, 1, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 64, 5, + 0, 0, 0, 0, 0, 0, + 4, 0, 0, 0, 0, 0, + 0, 0, 80, 5, 0, 0, + 0, 0, 0, 0, 255, 255, + 255, 255, 0, 0, 0, 0, + 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0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 143, 7, + 0, 0, 120, 101, 95, 101, + 100, 114, 97, 109, 95, 114, + 116, 95, 102, 111, 114, 109, + 97, 116, 95, 102, 108, 97, + 103, 115, 0, 120, 101, 95, + 101, 100, 114, 97, 109, 95, + 114, 116, 95, 99, 108, 97, + 109, 112, 0, 171, 1, 0, + 3, 0, 1, 0, 4, 0, + 4, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 92, 6, 0, 0, 120, 101, + 95, 101, 100, 114, 97, 109, + 95, 114, 116, 95, 107, 101, + 101, 112, 95, 109, 97, 115, + 107, 0, 171, 171, 1, 0, + 19, 0, 1, 0, 4, 0, + 2, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 143, 7, 0, 0, 120, 101, + 95, 101, 100, 114, 97, 109, + 95, 114, 116, 95, 98, 108, + 101, 110, 100, 95, 102, 97, + 99, 116, 111, 114, 115, 95, + 111, 112, 115, 0, 120, 101, + 95, 101, 100, 114, 97, 109, + 95, 98, 108, 101, 110, 100, + 95, 99, 111, 110, 115, 116, + 97, 110, 116, 0, 77, 105, + 99, 114, 111, 115, 111, 102, + 116, 32, 40, 82, 41, 32, + 72, 76, 83, 76, 32, 83, + 104, 97, 100, 101, 114, 32, + 67, 111, 109, 112, 105, 108, + 101, 114, 32, 49, 48, 46, + 49, 0, 171, 171, 73, 83, + 71, 78, 44, 0, 0, 0, + 1, 0, 0, 0, 8, 0, + 0, 0, 32, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 3, 0, 0, 0, + 0, 0, 0, 0, 1, 1, + 0, 0, 88, 69, 86, 69, + 82, 84, 69, 88, 73, 68, + 0, 171, 79, 83, 71, 78, + 44, 0, 0, 0, 1, 0, + 0, 0, 8, 0, 0, 0, + 32, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 3, 0, 0, 0, 0, 0, + 0, 0, 1, 14, 0, 0, + 88, 69, 86, 69, 82, 84, + 69, 88, 73, 68, 0, 171, + 80, 67, 83, 71, 188, 0, + 0, 0, 6, 0, 0, 0, + 8, 0, 0, 0, 152, 0, + 0, 0, 0, 0, 0, 0, + 11, 0, 0, 0, 3, 0, + 0, 0, 0, 0, 0, 0, + 1, 14, 0, 0, 152, 0, + 0, 0, 1, 0, 0, 0, + 11, 0, 0, 0, 3, 0, + 0, 0, 1, 0, 0, 0, + 1, 14, 0, 0, 152, 0, + 0, 0, 2, 0, 0, 0, + 11, 0, 0, 0, 3, 0, + 0, 0, 2, 0, 0, 0, + 1, 14, 0, 0, 152, 0, + 0, 0, 3, 0, 0, 0, + 11, 0, 0, 0, 3, 0, + 0, 0, 3, 0, 0, 0, + 1, 14, 0, 0, 166, 0, + 0, 0, 0, 0, 0, 0, + 12, 0, 0, 0, 3, 0, + 0, 0, 4, 0, 0, 0, + 1, 14, 0, 0, 166, 0, + 0, 0, 1, 0, 0, 0, + 12, 0, 0, 0, 3, 0, + 0, 0, 5, 0, 0, 0, + 1, 14, 0, 0, 83, 86, + 95, 84, 101, 115, 115, 70, + 97, 99, 116, 111, 114, 0, + 83, 86, 95, 73, 110, 115, + 105, 100, 101, 84, 101, 115, + 115, 70, 97, 99, 116, 111, + 114, 0, 171, 171, 83, 72, + 69, 88, 160, 1, 0, 0, + 81, 0, 3, 0, 104, 0, + 0, 0, 113, 0, 0, 1, + 147, 8, 0, 1, 148, 8, + 0, 1, 149, 24, 0, 1, + 150, 8, 0, 1, 151, 24, + 0, 1, 106, 8, 0, 1, + 89, 0, 0, 7, 70, 142, + 48, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 114, 0, + 0, 1, 95, 0, 0, 4, + 18, 16, 32, 0, 1, 0, + 0, 0, 0, 0, 0, 0, + 101, 0, 0, 3, 18, 32, + 16, 0, 0, 0, 0, 0, + 54, 0, 0, 6, 18, 32, + 16, 0, 0, 0, 0, 0, + 10, 16, 32, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 62, 0, 0, 1, 115, 0, + 0, 1, 153, 0, 0, 2, + 4, 0, 0, 0, 95, 0, + 0, 2, 0, 112, 1, 0, + 103, 0, 0, 4, 18, 32, + 16, 0, 0, 0, 0, 0, + 11, 0, 0, 0, 103, 0, + 0, 4, 18, 32, 16, 0, + 1, 0, 0, 0, 12, 0, + 0, 0, 103, 0, 0, 4, + 18, 32, 16, 0, 2, 0, + 0, 0, 13, 0, 0, 0, + 103, 0, 0, 4, 18, 32, + 16, 0, 3, 0, 0, 0, + 14, 0, 0, 0, 104, 0, + 0, 2, 1, 0, 0, 0, + 91, 0, 0, 4, 18, 32, + 16, 0, 0, 0, 0, 0, + 4, 0, 0, 0, 54, 0, + 0, 4, 18, 0, 16, 0, + 0, 0, 0, 0, 10, 112, + 1, 0, 54, 0, 0, 8, + 18, 32, 144, 0, 10, 0, + 16, 0, 0, 0, 0, 0, + 42, 128, 48, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 62, 0, + 0, 1, 115, 0, 0, 1, + 153, 0, 0, 2, 2, 0, + 0, 0, 95, 0, 0, 2, + 0, 112, 1, 0, 103, 0, + 0, 4, 18, 32, 16, 0, + 4, 0, 0, 0, 15, 0, + 0, 0, 103, 0, 0, 4, + 18, 32, 16, 0, 5, 0, + 0, 0, 16, 0, 0, 0, + 104, 0, 0, 2, 1, 0, + 0, 0, 91, 0, 0, 4, + 18, 32, 16, 0, 4, 0, + 0, 0, 2, 0, 0, 0, + 54, 0, 0, 4, 18, 0, + 16, 0, 0, 0, 0, 0, + 10, 112, 1, 0, 54, 0, + 0, 9, 18, 32, 208, 0, + 4, 0, 0, 0, 10, 0, + 16, 0, 0, 0, 0, 0, + 42, 128, 48, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 62, 0, + 0, 1, 83, 84, 65, 84, + 148, 0, 0, 0, 8, 0, + 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 5, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 3, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 5, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 8, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 0, + 0, 0, 3, 0, 0, 0, + 1, 0, 0, 0, 3, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0 +}; diff --git a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_quad_hs.h b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_quad_4cp_hs.h similarity index 99% rename from src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_quad_hs.h rename to src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_quad_4cp_hs.h index 8e83c6f7a..5c1bff113 100644 --- a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_quad_hs.h +++ b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_quad_4cp_hs.h @@ -117,7 +117,7 @@ ret // Approximately 6 instruction slots used #endif -const BYTE discrete_quad_hs[] = +const BYTE discrete_quad_4cp_hs[] = { 68, 88, 66, 67, 192, 34, 77, 20, 70, 107, 155, 33, diff --git a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_triangle_1cp_hs.h b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_triangle_1cp_hs.h new file mode 100644 index 000000000..e33fd446e --- /dev/null +++ b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_triangle_1cp_hs.h @@ -0,0 +1,686 @@ +#if 0 +// +// Generated by Microsoft (R) HLSL Shader Compiler 10.1 +// +// +// Buffer Definitions: +// +// cbuffer xe_system_cbuffer +// { +// +// uint xe_flags; // Offset: 0 Size: 4 [unused] +// float2 xe_tessellation_factor_range;// Offset: 4 Size: 8 +// uint xe_line_loop_closing_index; // Offset: 12 Size: 4 [unused] +// uint xe_vertex_index_endian; // Offset: 16 Size: 4 [unused] +// uint xe_vertex_index_offset; // Offset: 20 Size: 4 [unused] +// uint2 xe_vertex_index_min_max; // Offset: 24 Size: 8 [unused] +// float4 xe_user_clip_planes[6]; // Offset: 32 Size: 96 [unused] +// float3 xe_ndc_scale; // Offset: 128 Size: 12 [unused] +// float xe_point_vertex_diameter_min;// Offset: 140 Size: 4 [unused] +// float3 xe_ndc_offset; // Offset: 144 Size: 12 [unused] +// float xe_point_vertex_diameter_max;// Offset: 156 Size: 4 [unused] +// float2 xe_point_constant_diameter; // Offset: 160 Size: 8 [unused] +// float2 xe_point_screen_diameter_to_ndc_radius;// Offset: 168 Size: 8 [unused] +// uint4 xe_texture_swizzled_signs[2];// Offset: 176 Size: 32 [unused] +// uint xe_textures_resolved; // Offset: 208 Size: 4 [unused] +// uint2 xe_sample_count_log2; // Offset: 212 Size: 8 [unused] +// float xe_alpha_test_reference; // Offset: 220 Size: 4 [unused] +// uint xe_alpha_to_mask; // Offset: 224 Size: 4 [unused] +// uint xe_edram_32bpp_tile_pitch_dwords_scaled;// Offset: 228 Size: 4 [unused] +// uint xe_edram_depth_base_dwords_scaled;// Offset: 232 Size: 4 [unused] +// float4 xe_color_exp_bias; // Offset: 240 Size: 16 [unused] +// float2 xe_edram_poly_offset_front; // Offset: 256 Size: 8 [unused] +// float2 xe_edram_poly_offset_back; // Offset: 264 Size: 8 [unused] +// uint4 xe_edram_stencil[2]; // Offset: 272 Size: 32 [unused] +// uint4 xe_edram_rt_base_dwords_scaled;// Offset: 304 Size: 16 [unused] +// uint4 xe_edram_rt_format_flags; // Offset: 320 Size: 16 [unused] +// float4 xe_edram_rt_clamp[4]; // Offset: 336 Size: 64 [unused] +// uint4 xe_edram_rt_keep_mask[2]; // Offset: 400 Size: 32 [unused] +// uint4 xe_edram_rt_blend_factors_ops;// Offset: 432 Size: 16 [unused] +// float4 xe_edram_blend_constant; // Offset: 448 Size: 16 [unused] +// +// } +// +// +// Resource Bindings: +// +// Name Type Format Dim ID HLSL Bind Count +// ------------------------------ ---------- ------- ----------- ------- -------------- ------ +// xe_system_cbuffer cbuffer NA NA CB0 cb0 1 +// +// +// +// Patch Constant signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// SV_TessFactor 0 x 0 TRIEDGE float x +// SV_TessFactor 1 x 1 TRIEDGE float x +// SV_TessFactor 2 x 2 TRIEDGE float x +// SV_InsideTessFactor 0 x 3 TRIINT float x +// +// +// Input signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// XEVERTEXID 0 x 0 NONE float x +// +// +// Output signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// XEVERTEXID 0 x 0 NONE float x +// +// Tessellation Domain # of control points +// -------------------- -------------------- +// Triangle 1 +// +// Tessellation Output Primitive Partitioning Type +// ------------------------------ ------------------ +// Clockwise Triangles Integer +// +hs_5_1 +hs_decls +dcl_input_control_point_count 1 +dcl_output_control_point_count 1 +dcl_tessellator_domain domain_tri +dcl_tessellator_partitioning partitioning_integer +dcl_tessellator_output_primitive output_triangle_cw +dcl_globalFlags refactoringAllowed +dcl_constantbuffer CB0[0:0][1], immediateIndexed, space=0 +hs_control_point_phase +dcl_input v[1][0].x +dcl_output o0.x +mov o0.x, v[0][0].x +ret +hs_fork_phase +dcl_hs_fork_phase_instance_count 3 +dcl_input vForkInstanceID +dcl_output_siv o0.x, finalTriUeq0EdgeTessFactor +dcl_output_siv o1.x, finalTriVeq0EdgeTessFactor +dcl_output_siv o2.x, finalTriWeq0EdgeTessFactor +dcl_temps 1 +dcl_indexrange o0.x 3 +mov r0.x, vForkInstanceID.x +mov o[r0.x + 0].x, CB0[0][0].z +ret +hs_fork_phase +dcl_output_siv o3.x, finalTriInsideTessFactor +mov o3.x, CB0[0][0].z +ret +// Approximately 7 instruction slots used +#endif + +const BYTE discrete_triangle_1cp_hs[] = +{ + 68, 88, 66, 67, 227, 140, + 35, 65, 156, 178, 224, 139, + 122, 75, 128, 231, 90, 78, + 65, 91, 1, 0, 0, 0, + 76, 13, 0, 0, 6, 0, + 0, 0, 56, 0, 0, 0, + 108, 10, 0, 0, 160, 10, + 0, 0, 212, 10, 0, 0, + 104, 11, 0, 0, 176, 12, + 0, 0, 82, 68, 69, 70, + 44, 10, 0, 0, 1, 0, + 0, 0, 120, 0, 0, 0, + 1, 0, 0, 0, 60, 0, + 0, 0, 1, 5, 83, 72, + 0, 5, 0, 0, 2, 10, + 0, 0, 19, 19, 68, 37, + 60, 0, 0, 0, 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0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 4, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 8, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 0, + 0, 0, 3, 0, 0, 0, + 1, 0, 0, 0, 2, 0, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, + 0, 0 +}; diff --git a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_triangle_hs.h b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_triangle_3cp_hs.h similarity index 99% rename from src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_triangle_hs.h rename to src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_triangle_3cp_hs.h index f2a53e630..7f853cbc1 100644 --- a/src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_triangle_hs.h +++ b/src/xenia/gpu/shaders/bytecode/d3d12_5_1/discrete_triangle_3cp_hs.h @@ -108,7 +108,7 @@ ret // Approximately 5 instruction slots used #endif -const BYTE discrete_triangle_hs[] = +const BYTE discrete_triangle_3cp_hs[] = { 68, 88, 66, 67, 159, 101, 17, 163, 1, 25, 162, 203, diff --git a/src/xenia/gpu/shaders/continuous_quad.hs.hlsl b/src/xenia/gpu/shaders/continuous_quad.hlsli similarity index 89% rename from src/xenia/gpu/shaders/continuous_quad.hs.hlsl rename to src/xenia/gpu/shaders/continuous_quad.hlsli index 424731eff..a0aa08c73 100644 --- a/src/xenia/gpu/shaders/continuous_quad.hs.hlsl +++ b/src/xenia/gpu/shaders/continuous_quad.hlsli @@ -33,10 +33,11 @@ XeHSConstantDataOutput XePatchConstant() { [domain("quad")] [partitioning("fractional_even")] [outputtopology("triangle_cw")] -[outputcontrolpoints(4)] +[outputcontrolpoints(XE_TESSELLATION_CONTROL_POINT_COUNT)] [patchconstantfunc("XePatchConstant")] XeHSControlPointOutput main( - InputPatch xe_input_patch, + InputPatch xe_input_patch, uint xe_control_point_id : SV_OutputControlPointID) { XeHSControlPointOutput output; output.index = xe_input_patch[xe_control_point_id].index; diff --git a/src/xenia/gpu/shaders/continuous_quad_1cp.hs.hlsl b/src/xenia/gpu/shaders/continuous_quad_1cp.hs.hlsl new file mode 100644 index 000000000..d109b11c4 --- /dev/null +++ b/src/xenia/gpu/shaders/continuous_quad_1cp.hs.hlsl @@ -0,0 +1,2 @@ +#define XE_TESSELLATION_CONTROL_POINT_COUNT 1 +#include "continuous_quad.hlsli" diff --git a/src/xenia/gpu/shaders/continuous_quad_4cp.hs.hlsl b/src/xenia/gpu/shaders/continuous_quad_4cp.hs.hlsl new file mode 100644 index 000000000..824c6ae65 --- /dev/null +++ b/src/xenia/gpu/shaders/continuous_quad_4cp.hs.hlsl @@ -0,0 +1,2 @@ +#define XE_TESSELLATION_CONTROL_POINT_COUNT 4 +#include "continuous_quad.hlsli" diff --git a/src/xenia/gpu/shaders/continuous_triangle.hs.hlsl b/src/xenia/gpu/shaders/continuous_triangle.hlsli similarity index 87% rename from src/xenia/gpu/shaders/continuous_triangle.hs.hlsl rename to src/xenia/gpu/shaders/continuous_triangle.hlsli index 4e5b36c39..bb8058be6 100644 --- a/src/xenia/gpu/shaders/continuous_triangle.hs.hlsl +++ b/src/xenia/gpu/shaders/continuous_triangle.hlsli @@ -28,10 +28,11 @@ XeHSConstantDataOutput XePatchConstant() { [domain("tri")] [partitioning("fractional_even")] [outputtopology("triangle_cw")] -[outputcontrolpoints(3)] +[outputcontrolpoints(XE_TESSELLATION_CONTROL_POINT_COUNT)] [patchconstantfunc("XePatchConstant")] XeHSControlPointOutput main( - InputPatch xe_input_patch, + InputPatch xe_input_patch, uint xe_control_point_id : SV_OutputControlPointID) { XeHSControlPointOutput output; output.index = xe_input_patch[xe_control_point_id].index; diff --git a/src/xenia/gpu/shaders/continuous_triangle_1cp.hs.hlsl b/src/xenia/gpu/shaders/continuous_triangle_1cp.hs.hlsl new file mode 100644 index 000000000..bafbbb0b9 --- /dev/null +++ b/src/xenia/gpu/shaders/continuous_triangle_1cp.hs.hlsl @@ -0,0 +1,2 @@ +#define XE_TESSELLATION_CONTROL_POINT_COUNT 1 +#include "continuous_triangle.hlsli" diff --git a/src/xenia/gpu/shaders/continuous_triangle_3cp.hs.hlsl b/src/xenia/gpu/shaders/continuous_triangle_3cp.hs.hlsl new file mode 100644 index 000000000..7c8bbb979 --- /dev/null +++ b/src/xenia/gpu/shaders/continuous_triangle_3cp.hs.hlsl @@ -0,0 +1,2 @@ +#define XE_TESSELLATION_CONTROL_POINT_COUNT 3 +#include "continuous_triangle.hlsli" diff --git a/src/xenia/gpu/shaders/discrete_quad.hs.hlsl b/src/xenia/gpu/shaders/discrete_quad.hlsli similarity index 89% rename from src/xenia/gpu/shaders/discrete_quad.hs.hlsl rename to src/xenia/gpu/shaders/discrete_quad.hlsli index ece12a97e..3e54340d1 100644 --- a/src/xenia/gpu/shaders/discrete_quad.hs.hlsl +++ b/src/xenia/gpu/shaders/discrete_quad.hlsli @@ -33,10 +33,11 @@ XeHSConstantDataOutput XePatchConstant() { [domain("quad")] [partitioning("integer")] [outputtopology("triangle_cw")] -[outputcontrolpoints(4)] +[outputcontrolpoints(XE_TESSELLATION_CONTROL_POINT_COUNT)] [patchconstantfunc("XePatchConstant")] XeHSControlPointOutput main( - InputPatch xe_input_patch, + InputPatch xe_input_patch, uint xe_control_point_id : SV_OutputControlPointID) { XeHSControlPointOutput output; output.index = xe_input_patch[xe_control_point_id].index; diff --git a/src/xenia/gpu/shaders/discrete_quad_1cp.hs.hlsl b/src/xenia/gpu/shaders/discrete_quad_1cp.hs.hlsl new file mode 100644 index 000000000..ba6bacaa1 --- /dev/null +++ b/src/xenia/gpu/shaders/discrete_quad_1cp.hs.hlsl @@ -0,0 +1,2 @@ +#define XE_TESSELLATION_CONTROL_POINT_COUNT 1 +#include "discrete_quad.hlsli" diff --git a/src/xenia/gpu/shaders/discrete_quad_4cp.hs.hlsl b/src/xenia/gpu/shaders/discrete_quad_4cp.hs.hlsl new file mode 100644 index 000000000..0c770792a --- /dev/null +++ b/src/xenia/gpu/shaders/discrete_quad_4cp.hs.hlsl @@ -0,0 +1,2 @@ +#define XE_TESSELLATION_CONTROL_POINT_COUNT 4 +#include "discrete_quad.hlsli" diff --git a/src/xenia/gpu/shaders/discrete_triangle.hs.hlsl b/src/xenia/gpu/shaders/discrete_triangle.hlsli similarity index 88% rename from src/xenia/gpu/shaders/discrete_triangle.hs.hlsl rename to src/xenia/gpu/shaders/discrete_triangle.hlsli index c1d31153d..236404986 100644 --- a/src/xenia/gpu/shaders/discrete_triangle.hs.hlsl +++ b/src/xenia/gpu/shaders/discrete_triangle.hlsli @@ -32,10 +32,11 @@ XeHSConstantDataOutput XePatchConstant() { [domain("tri")] [partitioning("integer")] [outputtopology("triangle_cw")] -[outputcontrolpoints(3)] +[outputcontrolpoints(XE_TESSELLATION_CONTROL_POINT_COUNT)] [patchconstantfunc("XePatchConstant")] XeHSControlPointOutput main( - InputPatch xe_input_patch, + InputPatch xe_input_patch, uint xe_control_point_id : SV_OutputControlPointID) { XeHSControlPointOutput output; output.index = xe_input_patch[xe_control_point_id].index; diff --git a/src/xenia/gpu/shaders/discrete_triangle_1cp.hs.hlsl b/src/xenia/gpu/shaders/discrete_triangle_1cp.hs.hlsl new file mode 100644 index 000000000..7550091a5 --- /dev/null +++ b/src/xenia/gpu/shaders/discrete_triangle_1cp.hs.hlsl @@ -0,0 +1,2 @@ +#define XE_TESSELLATION_CONTROL_POINT_COUNT 1 +#include "discrete_triangle.hlsli" diff --git a/src/xenia/gpu/shaders/discrete_triangle_3cp.hs.hlsl b/src/xenia/gpu/shaders/discrete_triangle_3cp.hs.hlsl new file mode 100644 index 000000000..26c86519d --- /dev/null +++ b/src/xenia/gpu/shaders/discrete_triangle_3cp.hs.hlsl @@ -0,0 +1,2 @@ +#define XE_TESSELLATION_CONTROL_POINT_COUNT 3 +#include "discrete_triangle.hlsli" diff --git a/src/xenia/gpu/xenos.h b/src/xenia/gpu/xenos.h index 5dc461a6f..644874ffd 100644 --- a/src/xenia/gpu/xenos.h +++ b/src/xenia/gpu/xenos.h @@ -72,8 +72,21 @@ enum class PrimitiveType : uint32_t { k2DTriStrip = 0x16, // Tessellation patches when VGT_OUTPUT_PATH_CNTL::path_select is - // VGTOutputPath::kTessellationEnable. The vertex shader receives patch index - // rather than control point indices. + // VGTOutputPath::kTessellationEnable. The vertex shader receives the patch + // index rather than control point indices. + // With non-adaptive tessellation, VGT_DRAW_INITIATOR::num_indices is the + // patch count (4D5307F1 draws single ground patches by passing 1 as the index + // count). VGT_INDX_OFFSET is also applied to the patch index - 4D5307F1 uses + // auto-indexed patches with a nonzero VGT_INDX_OFFSET, which contains the + // base patch index there. + // With adaptive tessellation, however, num_indices is the number of + // tessellation factors in the "index buffer" reused for tessellation factors, + // which is the patch count multiplied by the edge count (if num_indices is + // multiplied further by 4 for quad patches for the ground in 4D5307F2, for + // example, some incorrect patches are drawn, so Xenia shouldn't do that; also + // 4D5307E6 draws water triangle patches with the number of indices that is 3 + // times the invocation count of the memexporting shader that calculates the + // tessellation factors for a single patch for each "point"). kLinePatch = 0x10, kTrianglePatch = 0x11, kQuadPatch = 0x12,