From 359e5b578a034017933c51db957620230ac2bbe4 Mon Sep 17 00:00:00 2001 From: Ben Vanik Date: Mon, 17 Aug 2015 07:57:15 -0700 Subject: [PATCH] Fixing vsl and vsr for out of range values. --- src/xenia/cpu/frontend/ppc_emit_altivec.cc | 4 ++-- src/xenia/cpu/frontend/testing/instr_vsl.s | 8 ++++++++ src/xenia/cpu/frontend/testing/instr_vsr.s | 8 ++++++++ 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/src/xenia/cpu/frontend/ppc_emit_altivec.cc b/src/xenia/cpu/frontend/ppc_emit_altivec.cc index 70353a8cc..a9949f9e1 100644 --- a/src/xenia/cpu/frontend/ppc_emit_altivec.cc +++ b/src/xenia/cpu/frontend/ppc_emit_altivec.cc @@ -1390,7 +1390,7 @@ XEEMITTER(vsel128, VX128(5, 848), VX128)(PPCHIRBuilder& f, InstrData& i) { XEEMITTER(vsl, 0x100001C4, VX)(PPCHIRBuilder& f, InstrData& i) { Value* v = f.Shl(f.LoadVR(i.VX.VA), f.And(f.Extract(f.LoadVR(i.VX.VB), 15, INT8_TYPE), - f.LoadConstantInt8(0x7F))); + f.LoadConstantInt8(0b111))); f.StoreVR(i.VX.VD, v); return 0; } @@ -1573,7 +1573,7 @@ XEEMITTER(vspltisw128, VX128_3(6, 1904), VX128_3)(PPCHIRBuilder& f, XEEMITTER(vsr, 0x100002C4, VX)(PPCHIRBuilder& f, InstrData& i) { Value* v = f.Shr(f.LoadVR(i.VX.VA), f.And(f.Extract(f.LoadVR(i.VX.VB), 15, INT8_TYPE), - f.LoadConstantInt8(0x7F))); + f.LoadConstantInt8(0b111))); f.StoreVR(i.VX.VD, v); return 0; } diff --git a/src/xenia/cpu/frontend/testing/instr_vsl.s b/src/xenia/cpu/frontend/testing/instr_vsl.s index b0bf4d03e..48d847a0f 100644 --- a/src/xenia/cpu/frontend/testing/instr_vsl.s +++ b/src/xenia/cpu/frontend/testing/instr_vsl.s @@ -21,3 +21,11 @@ test_vsl_3: blr #_ REGISTER_OUT v3 [089119A2, 2AB33BC4, 4CD55DE6, 6EF77F80] #_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707] + +test_vsl_4: + #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF] + #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + vsl v3, v3, v4 + blr + #_ REGISTER_OUT v3 [089119A2, 2AB33BC4, 4CD55DE6, 6EF77F80] + #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] diff --git a/src/xenia/cpu/frontend/testing/instr_vsr.s b/src/xenia/cpu/frontend/testing/instr_vsr.s index 128cfaa66..d6c6a8d11 100644 --- a/src/xenia/cpu/frontend/testing/instr_vsr.s +++ b/src/xenia/cpu/frontend/testing/instr_vsr.s @@ -21,3 +21,11 @@ test_vsr_3: blr #_ REGISTER_OUT v3 [00002244, 6688AACC, EF113355, 7799BBDD] #_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707] + +test_vsr_4: + #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF] + #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + vsr v3, v3, v4 + blr + #_ REGISTER_OUT v3 [00002244, 6688AACC, EF113355, 7799BBDD] + #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]