vsl[bhw] tests.

src/alloy/frontend/ppc/test/bin/instr_vslb.dis

@@ -0,0 +1,25 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vslb.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vslb_1>:
+  100000:	10 63 21 04 	vslb    v3,v3,v4
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vslb_2>:
+  100008:	10 63 21 04 	vslb    v3,v3,v4
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vslb_3>:
+  100010:	10 63 21 04 	vslb    v3,v3,v4
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_vslb_4>:
+  100018:	10 63 21 04 	vslb    v3,v3,v4
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_vslb_5>:
+  100020:	10 63 21 04 	vslb    v3,v3,v4
+  100024:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vslb.map

@@ -0,0 +1,5 @@
+0000000000000000 t test_vslb_1
+0000000000000008 t test_vslb_2
+0000000000000010 t test_vslb_3
+0000000000000018 t test_vslb_4
+0000000000000020 t test_vslb_5

src/alloy/frontend/ppc/test/bin/instr_vslh.dis

@@ -0,0 +1,29 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vslh.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vslh_1>:
+  100000:	10 63 21 44 	vslh    v3,v3,v4
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vslh_2>:
+  100008:	10 63 21 44 	vslh    v3,v3,v4
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vslh_3>:
+  100010:	10 63 21 44 	vslh    v3,v3,v4
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_vslh_4>:
+  100018:	10 63 21 44 	vslh    v3,v3,v4
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_vslh_5>:
+  100020:	10 63 21 44 	vslh    v3,v3,v4
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_vslh_6>:
+  100028:	10 63 21 44 	vslh    v3,v3,v4
+  10002c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vslh.map

@@ -0,0 +1,6 @@
+0000000000000000 t test_vslh_1
+0000000000000008 t test_vslh_2
+0000000000000010 t test_vslh_3
+0000000000000018 t test_vslh_4
+0000000000000020 t test_vslh_5
+0000000000000028 t test_vslh_6

src/alloy/frontend/ppc/test/bin/instr_vslw.dis

@@ -0,0 +1,29 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vslw.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vslw_1>:
+  100000:	10 63 21 84 	vslw    v3,v3,v4
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vslw_2>:
+  100008:	10 63 21 84 	vslw    v3,v3,v4
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vslw_3>:
+  100010:	10 63 21 84 	vslw    v3,v3,v4
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_vslw_4>:
+  100018:	10 63 21 84 	vslw    v3,v3,v4
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_vslw_5>:
+  100020:	10 63 21 84 	vslw    v3,v3,v4
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_vslw_6>:
+  100028:	10 63 21 84 	vslw    v3,v3,v4
+  10002c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vslw.map

@@ -0,0 +1,6 @@
+0000000000000000 t test_vslw_1
+0000000000000008 t test_vslw_2
+0000000000000010 t test_vslw_3
+0000000000000018 t test_vslw_4
+0000000000000020 t test_vslw_5
+0000000000000028 t test_vslw_6

src/alloy/frontend/ppc/test/instr_vslb.s

@@ -0,0 +1,39 @@
+test_vslb_1:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vslb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+
+test_vslb_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vslb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+
+test_vslb_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [07070707, 07070707, 07070707, 07070707]
+  vslb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707]
+
+test_vslb_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [08080808, 08080808, 08080808, 08080808]
+  vslb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [08080808, 08080808, 08080808, 08080808]
+
+test_vslb_5:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [09090909, 09090909, 09090909, 09090909]
+  vslb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v4 [09090909, 09090909, 09090909, 09090909]

src/alloy/frontend/ppc/test/instr_vslh.s

@@ -0,0 +1,47 @@
+test_vslh_1:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vslh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+
+test_vslh_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vslh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFEFFFE, FFFEFFFE, FFFEFFFE, FFFEFFFE]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+
+test_vslh_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [000F000F, 000F000F, 000F000F, 000F000F]
+  vslh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80008000, 80008000, 80008000, 80008000]
+  #_ REGISTER_OUT v4 [000F000F, 000F000F, 000F000F, 000F000F]
+
+test_vslh_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00100010, 00100010, 00100010, 00100010]
+  vslh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00100010, 00100010, 00100010, 00100010]
+
+test_vslh_5:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00090009, 00090009, 00090009, 00090009]
+  vslh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FE00FE00, FE00FE00, FE00FE00, FE00FE00]
+  #_ REGISTER_OUT v4 [00090009, 00090009, 00090009, 00090009]
+
+test_vslh_6:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00110011, 00110011, 00110011, 00110011]
+  vslh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFEFFFE, FFFEFFFE, FFFEFFFE, FFFEFFFE]
+  #_ REGISTER_OUT v4 [00110011, 00110011, 00110011, 00110011]

src/alloy/frontend/ppc/test/instr_vslw.s

@@ -0,0 +1,47 @@
+test_vslw_1:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vslw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+
+test_vslw_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vslw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+
+test_vslw_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [0000001F, 0000001F, 0000001F, 0000001F]
+  vslw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_OUT v4 [0000001F, 0000001F, 0000001F, 0000001F]
+
+test_vslw_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000020, 00000020, 00000020, 00000020]
+  vslw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000020, 00000020, 00000020, 00000020]
+
+test_vslw_5:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000009, 00000009, 00000009, 00000009]
+  vslw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFE00, FFFFFE00, FFFFFE00, FFFFFE00]
+  #_ REGISTER_OUT v4 [00000009, 00000009, 00000009, 00000009]
+
+test_vslw_6:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000021, 00000021, 00000021, 00000021]
+  vslw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
+  #_ REGISTER_OUT v4 [00000021, 00000021, 00000021, 00000021]