vsl[bhw] tests.
This commit is contained in:
Ben Vanik
parent
f2100a78bc
commit
338b5809b4
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/vagrant/src/alloy/frontend/ppc/test/bin//instr_vslb.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_vslb_1>:
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100000: 10 63 21 04 vslb v3,v3,v4
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100004: 4e 80 00 20 blr
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0000000000100008 <test_vslb_2>:
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100008: 10 63 21 04 vslb v3,v3,v4
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10000c: 4e 80 00 20 blr
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0000000000100010 <test_vslb_3>:
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100010: 10 63 21 04 vslb v3,v3,v4
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100014: 4e 80 00 20 blr
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0000000000100018 <test_vslb_4>:
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100018: 10 63 21 04 vslb v3,v3,v4
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10001c: 4e 80 00 20 blr
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0000000000100020 <test_vslb_5>:
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100020: 10 63 21 04 vslb v3,v3,v4
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100024: 4e 80 00 20 blr
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@ -0,0 +1,5 @@
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0000000000000000 t test_vslb_1
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0000000000000008 t test_vslb_2
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0000000000000010 t test_vslb_3
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0000000000000018 t test_vslb_4
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0000000000000020 t test_vslb_5
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/vagrant/src/alloy/frontend/ppc/test/bin//instr_vslh.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_vslh_1>:
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100000: 10 63 21 44 vslh v3,v3,v4
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100004: 4e 80 00 20 blr
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0000000000100008 <test_vslh_2>:
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100008: 10 63 21 44 vslh v3,v3,v4
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10000c: 4e 80 00 20 blr
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0000000000100010 <test_vslh_3>:
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100010: 10 63 21 44 vslh v3,v3,v4
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100014: 4e 80 00 20 blr
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0000000000100018 <test_vslh_4>:
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100018: 10 63 21 44 vslh v3,v3,v4
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10001c: 4e 80 00 20 blr
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0000000000100020 <test_vslh_5>:
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100020: 10 63 21 44 vslh v3,v3,v4
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100024: 4e 80 00 20 blr
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0000000000100028 <test_vslh_6>:
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100028: 10 63 21 44 vslh v3,v3,v4
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10002c: 4e 80 00 20 blr
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0000000000000000 t test_vslh_1
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0000000000000008 t test_vslh_2
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0000000000000010 t test_vslh_3
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0000000000000018 t test_vslh_4
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0000000000000020 t test_vslh_5
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0000000000000028 t test_vslh_6
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/vagrant/src/alloy/frontend/ppc/test/bin//instr_vslw.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_vslw_1>:
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100000: 10 63 21 84 vslw v3,v3,v4
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100004: 4e 80 00 20 blr
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0000000000100008 <test_vslw_2>:
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100008: 10 63 21 84 vslw v3,v3,v4
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10000c: 4e 80 00 20 blr
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0000000000100010 <test_vslw_3>:
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100010: 10 63 21 84 vslw v3,v3,v4
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100014: 4e 80 00 20 blr
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0000000000100018 <test_vslw_4>:
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100018: 10 63 21 84 vslw v3,v3,v4
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10001c: 4e 80 00 20 blr
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0000000000100020 <test_vslw_5>:
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100020: 10 63 21 84 vslw v3,v3,v4
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100024: 4e 80 00 20 blr
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0000000000100028 <test_vslw_6>:
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100028: 10 63 21 84 vslw v3,v3,v4
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10002c: 4e 80 00 20 blr
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0000000000000000 t test_vslw_1
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0000000000000008 t test_vslw_2
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0000000000000010 t test_vslw_3
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0000000000000018 t test_vslw_4
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0000000000000020 t test_vslw_5
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0000000000000028 t test_vslw_6
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test_vslb_1:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vslb v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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test_vslb_2:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
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vslb v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
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#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
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test_vslb_3:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [07070707, 07070707, 07070707, 07070707]
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vslb v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
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#_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707]
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test_vslb_4:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [08080808, 08080808, 08080808, 08080808]
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vslb v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [08080808, 08080808, 08080808, 08080808]
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test_vslb_5:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [09090909, 09090909, 09090909, 09090909]
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vslb v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
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#_ REGISTER_OUT v4 [09090909, 09090909, 09090909, 09090909]
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test_vslh_1:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vslh v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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test_vslh_2:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
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vslh v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFEFFFE, FFFEFFFE, FFFEFFFE, FFFEFFFE]
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#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
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test_vslh_3:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [000F000F, 000F000F, 000F000F, 000F000F]
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vslh v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [80008000, 80008000, 80008000, 80008000]
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#_ REGISTER_OUT v4 [000F000F, 000F000F, 000F000F, 000F000F]
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test_vslh_4:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00100010, 00100010, 00100010, 00100010]
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vslh v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [00100010, 00100010, 00100010, 00100010]
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test_vslh_5:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00090009, 00090009, 00090009, 00090009]
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vslh v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FE00FE00, FE00FE00, FE00FE00, FE00FE00]
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#_ REGISTER_OUT v4 [00090009, 00090009, 00090009, 00090009]
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test_vslh_6:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00110011, 00110011, 00110011, 00110011]
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vslh v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFEFFFE, FFFEFFFE, FFFEFFFE, FFFEFFFE]
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#_ REGISTER_OUT v4 [00110011, 00110011, 00110011, 00110011]
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test_vslw_1:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vslw v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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test_vslw_2:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
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vslw v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
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#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
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test_vslw_3:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [0000001F, 0000001F, 0000001F, 0000001F]
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vslw v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
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#_ REGISTER_OUT v4 [0000001F, 0000001F, 0000001F, 0000001F]
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test_vslw_4:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00000020, 00000020, 00000020, 00000020]
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vslw v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [00000020, 00000020, 00000020, 00000020]
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test_vslw_5:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00000009, 00000009, 00000009, 00000009]
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vslw v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFE00, FFFFFE00, FFFFFE00, FFFFFE00]
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#_ REGISTER_OUT v4 [00000009, 00000009, 00000009, 00000009]
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test_vslw_6:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [00000021, 00000021, 00000021, 00000021]
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vslw v3, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
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#_ REGISTER_OUT v4 [00000021, 00000021, 00000021, 00000021]
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