VECTOR_ADD signed/saturate.
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@ -2745,7 +2745,17 @@ EMITTER(VECTOR_ADD, MATCH(I<OPCODE_VECTOR_ADD, V128<>, V128<>, V128<>>)) {
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// dest.f[n] = xmm1.f[n] ? xmm1.f[n] : dest.f[n];
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// dest.f[n] = xmm1.f[n] ? xmm1.f[n] : dest.f[n];
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e.vblendvps(dest, dest, e.xmm1, e.xmm1);
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e.vblendvps(dest, dest, e.xmm1, e.xmm1);
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} else {
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} else {
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assert_always();
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// https://software.intel.com/en-us/forums/topic/285219
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// We reuse all these temps...
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assert_true(src1 != e.xmm0 && src1 != e.xmm1 && src1 != e.xmm2);
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assert_true(src2 != e.xmm0 && src2 != e.xmm1 && src2 != e.xmm2);
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e.vpaddd(e.xmm0, src1, src2); // res
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e.vpand(e.xmm1, src1, src2); // sign_and
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e.vpandn(e.xmm2, e.xmm0, e.xmm1); // min_sat_mask
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e.vblendvps(e.xmm2, e.xmm0, e.GetXmmConstPtr(XMMSignMaskPS), e.xmm2);
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e.vpor(e.xmm1, src1, src2); // sign_or
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e.vpandn(e.xmm1, e.xmm0); // max_sat_mask
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e.vblendvps(e.xmm2, e.GetXmmConstPtr(XMMAbsMaskPS), e.xmm1);
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}
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}
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} else {
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} else {
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e.vpaddd(dest, src1, src2);
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e.vpaddd(dest, src1, src2);
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