Fixing wraparound.
This still needs a tremendous amount of cleanup.
This commit is contained in:
Ben Vanik
parent
4887234bba
commit
2eed0b1575
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@ -30,6 +30,7 @@ RingBufferWorker::RingBufferWorker(xe_memory_ref memory) :
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read_ptr_update_freq_ = 0;
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read_ptr_writeback_ptr_ = 0;
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write_ptr_index_ = 0;
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write_ptr_max_index_ = 0;
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}
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RingBufferWorker::~RingBufferWorker() {
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@ -46,6 +47,9 @@ void RingBufferWorker::Initialize(GraphicsDriver* driver,
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uint32_t original_size = 1 << (0x1C - page_count - 1);
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primary_buffer_size_ = original_size;
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read_ptr_index_ = 0;
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// Tell the driver what to use for translation.
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driver_->set_address_translation(primary_buffer_ptr_ & ~0x1FFFFFFF);
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}
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void RingBufferWorker::EnableReadPointerWriteBack(uint32_t ptr,
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@ -60,7 +64,8 @@ void RingBufferWorker::EnableReadPointerWriteBack(uint32_t ptr,
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}
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void RingBufferWorker::UpdateWritePointer(uint32_t value) {
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write_ptr_index_ = value;
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write_ptr_max_index_ = MAX(write_ptr_max_index_, value);
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write_ptr_index_ = value;
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SetEvent(write_ptr_index_event_);
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}
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@ -82,6 +87,7 @@ void RingBufferWorker::Pump() {
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// Bring local so we don't have to worry about them changing out from under
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// us.
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uint32_t write_ptr_index = write_ptr_index_;
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uint32_t write_ptr_max_index = write_ptr_max_index_;
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if (read_ptr_index_ == write_ptr_index) {
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return;
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}
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@ -89,24 +95,9 @@ void RingBufferWorker::Pump() {
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// Process the new commands.
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XELOGGPU("Ring buffer thread work");
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// Handle wrapping around.
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// TODO(benvanik): verify this is correct.
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if (write_ptr_index_ < read_ptr_index_) {
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// We wrapped. Execute all instructions until the end and go back to 0.
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XELOGGPU("Ring buffer wrapped back to zero (read %0.8X, write %0.8X)",
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read_ptr_index_, write_ptr_index);
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uint32_t pre_length = (primary_buffer_size_ / 4) - read_ptr_index_;
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if (pre_length) {
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ExecuteSegment(primary_buffer_ptr_ + read_ptr_index_ * 4, pre_length);
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}
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read_ptr_index_ = 0;
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}
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uint32_t length = write_ptr_index - read_ptr_index_;
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if (length) {
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ExecuteSegment(primary_buffer_ptr_ + read_ptr_index_ * 4, length);
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read_ptr_index_ = write_ptr_index;
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}
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// Execute. Note that we handle wraparound transparently.
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ExecutePrimaryBuffer(read_ptr_index_, write_ptr_index);
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read_ptr_index_ = write_ptr_index;
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// TODO(benvanik): use read_ptr_update_freq_ and only issue after moving
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// that many indices.
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@ -115,270 +106,330 @@ void RingBufferWorker::Pump() {
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}
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}
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void RingBufferWorker::ExecuteSegment(uint32_t ptr, uint32_t length) {
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uint8_t* p = xe_memory_addr(memory_);
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RegisterFile* regs = driver_->register_file();
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void RingBufferWorker::ExecutePrimaryBuffer(
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uint32_t start_index, uint32_t end_index) {
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// Adjust pointer base.
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uint32_t ptr = primary_buffer_ptr_ + start_index * 4;
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ptr = (primary_buffer_ptr_ & ~0x1FFFFFFF) | (ptr & 0x1FFFFFFF);
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uint32_t end_ptr = primary_buffer_ptr_ + end_index * 4;
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end_ptr = (primary_buffer_ptr_ & ~0x1FFFFFFF) | (end_ptr & 0x1FFFFFFF);
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XELOGGPU("[%.8X] ExecutePrimaryBuffer(%dw -> %dw)",
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start_index, end_index);
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// Execute commands!
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PacketArgs args;
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args.ptr = ptr;
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args.base_ptr = primary_buffer_ptr_;
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args.max_address = primary_buffer_ptr_ + primary_buffer_size_ * 4;
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args.ptr_mask = (primary_buffer_size_ / 4) - 1;
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uint32_t n = 0;
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while (args.ptr != end_ptr) {
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n += ExecutePacket(args);
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}
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if (end_index > start_index) {
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XEASSERT(n == (end_index - start_index));
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}
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XELOGGPU(" ExecutePrimaryBuffer End");
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}
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void RingBufferWorker::ExecuteIndirectBuffer(uint32_t ptr, uint32_t length) {
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// Adjust pointer base.
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ptr = (primary_buffer_ptr_ & ~0x1FFFFFFF) | (ptr & 0x1FFFFFFF);
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// Tell the driver what to use for translation.
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driver_->set_address_translation(primary_buffer_ptr_ & ~0x1FFFFFFF);
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XELOGGPU("[%.8X] ExecuteIndirectBuffer(%dw)", ptr, length);
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// Execute commands!
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PacketArgs args;
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args.ptr = ptr;
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args.base_ptr = ptr;
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args.max_address = ptr + length * 4;
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args.ptr_mask = 0;
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for (uint32_t n = 0; n < length;) {
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n += ExecutePacket(args);
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XEASSERT(n <= length);
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}
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XELOGGPU(" ExecuteIndirectBuffer End");
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}
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#define LOG_DATA(count) \
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for (uint32_t __m = 0; __m < count; __m++) { \
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XELOGGPU("[%.8X] %.8X", \
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ptr + (n + 1 + __m) * 4, \
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packet_ptr + (1 + __m) * 4, \
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XEGETUINT32BE(packet_base + 1 * 4 + __m * 4)); \
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}
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#define TRANSLATE_ADDR(p) \
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((p & ~0x3) + (primary_buffer_ptr_ & ~0x1FFFFFFF))
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XELOGGPU("[%.8X] CommandList(): executing %dw", ptr, length);
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// Execute commands!
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for (uint32_t n = 0; n < length;) {
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const uint8_t* packet_base = p + ptr + n * 4;
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const uint32_t packet = XEGETUINT32BE(packet_base);
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const uint32_t packet_type = packet >> 30;
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if (packet == 0) {
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n++;
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continue;
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}
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switch (packet_type) {
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case 0x00:
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{
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// Type-0 packet.
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// Write count registers in sequence to the registers starting at
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// (base_index << 2).
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XELOGGPU("[%.8X] Packet(%.8X): set registers:", ptr + n * 4,
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ptr + n * 4, packet);
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uint32_t count = ((packet >> 16) & 0x3FFF) + 1;
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uint32_t base_index = (packet & 0xFFFF);
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for (uint32_t m = 0; m < count; m++) {
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uint32_t reg_data = XEGETUINT32BE(packet_base + 1 * 4 + m * 4);
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const char* reg_name = xenos::GetRegisterName(base_index + m);
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XELOGGPU("[%.8X] %.8X -> %.4X %s",
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ptr + (n + 1 + m) * 4,
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reg_data, base_index + m, reg_name ? reg_name : "");
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// TODO(benvanik): exec write handler (if special).
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if (base_index + m < kXEGpuRegisterCount) {
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regs->values[base_index + m].u32 = reg_data;
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}
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}
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n += 1 + count;
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}
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break;
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case 0x01:
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{
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// Type-1 packet.
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// Contains two registers of data. Type-0 should be more common.
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XELOGGPU("[%.8X] Packet(%.8X): set registers:",
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ptr + n * 4, packet);
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uint32_t reg_index_1 = packet & 0x7FF;
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uint32_t reg_index_2 = (packet >> 11) & 0x7FF;
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uint32_t reg_data_1 = XEGETUINT32BE(packet_base + 1 * 4);
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uint32_t reg_data_2 = XEGETUINT32BE(packet_base + 2 * 4);
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const char* reg_name_1 = xenos::GetRegisterName(reg_index_1);
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const char* reg_name_2 = xenos::GetRegisterName(reg_index_2);
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XELOGGPU("[%.8X] %.8X -> %.4X %s",
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ptr + (n + 1) * 4,
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reg_data_1, reg_index_1, reg_name_1 ? reg_name_1 : "");
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XELOGGPU("[%.8X] %.8X -> %.4X %s",
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ptr + (n + 2) * 4,
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reg_data_2, reg_index_2, reg_name_2 ? reg_name_2 : "");
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// TODO(benvanik): exec write handler (if special).
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if (reg_index_1 < kXEGpuRegisterCount) {
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regs->values[reg_index_1].u32 = reg_data_1;
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}
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if (reg_index_2 < kXEGpuRegisterCount) {
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regs->values[reg_index_2].u32 = reg_data_2;
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}
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n += 1 + 2;
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}
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break;
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case 0x02:
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// Type-2 packet.
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// No-op. Do nothing.
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n++;
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break;
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case 0x03:
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{
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// Type-3 packet.
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uint32_t count = ((packet >> 16) & 0x3FFF) + 1;
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uint32_t opcode = (packet >> 8) & 0x7F;
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// & 1 == predicate, maybe?
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switch (opcode) {
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case PM4_ME_INIT:
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// initialize CP's micro-engine
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XELOGGPU("[%.8X] Packet(%.8X): PM4_ME_INIT",
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ptr + n * 4, packet);
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LOG_DATA(count);
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break;
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case PM4_NOP:
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// skip N 32-bit words to get to the next packet
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// No-op, ignore some data.
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XELOGGPU("[%.8X] Packet(%.8X): PM4_NOP",
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ptr + n * 4, packet);
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LOG_DATA(count);
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break;
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case PM4_INDIRECT_BUFFER:
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// indirect buffer dispatch
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{
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uint32_t list_ptr = XEGETUINT32BE(packet_base + 1 * 4);
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uint32_t list_length = XEGETUINT32BE(packet_base + 2 * 4);
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XELOGGPU("[%.8X] Packet(%.8X): PM4_INDIRECT_BUFFER %.8X (%dw)",
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ptr + n * 4, packet, list_ptr, list_length);
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ExecuteSegment(list_ptr, list_length);
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driver_->set_address_translation(primary_buffer_ptr_ & ~0x1FFFFFFF);
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}
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break;
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case PM4_WAIT_REG_MEM:
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// wait until a register or memory location is a specific value
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XELOGGPU("[%.8X] Packet(%.8X): PM4_WAIT_REG_MEM",
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ptr + n * 4, packet);
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LOG_DATA(count);
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break;
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case PM4_REG_RMW:
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// register read/modify/write
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// ? (used during shader upload and edram setup)
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XELOGGPU("[%.8X] Packet(%.8X): PM4_REG_RMW",
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ptr + n * 4, packet);
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LOG_DATA(count);
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break;
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case PM4_COND_WRITE:
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// conditional write to memory or register
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XELOGGPU("[%.8X] Packet(%.8X): PM4_COND_WRITE",
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ptr + n * 4, packet);
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LOG_DATA(count);
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break;
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case PM4_EVENT_WRITE:
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// generate an event that creates a write to memory when completed
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XELOGGPU("[%.8X] Packet(%.8X): PM4_EVENT_WRITE",
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ptr + n * 4, packet);
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LOG_DATA(count);
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break;
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case PM4_EVENT_WRITE_SHD:
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// generate a VS|PS_done event
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{
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XELOGGPU("[%.8X] Packet(%.8X): PM4_EVENT_WRITE_SHD",
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ptr + n * 4, packet);
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LOG_DATA(count);
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// 3?
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uint32_t d0 = XEGETUINT32BE(packet_base + 1 * 4);
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// ptr
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uint32_t d1 = XEGETUINT32BE(packet_base + 2 * 4);
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// value?
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uint32_t d2 = XEGETUINT32BE(packet_base + 3 * 4);
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XESETUINT32BE(p + TRANSLATE_ADDR(d1), d2);
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}
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break;
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case PM4_DRAW_INDX:
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// initiate fetch of index buffer and draw
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{
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XELOGGPU("[%.8X] Packet(%.8X): PM4_DRAW_INDX",
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ptr + n * 4, packet);
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LOG_DATA(count);
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// d0 = viz query info
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uint32_t d0 = XEGETUINT32BE(packet_base + 1 * 4);
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uint32_t d1 = XEGETUINT32BE(packet_base + 2 * 4);
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uint32_t index_count = d1 >> 16;
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uint32_t prim_type = d1 & 0x3F;
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uint32_t src_sel = (d1 >> 6) & 0x3;
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XEASSERT(src_sel == 0x2); // 'SrcSel=AutoIndex'
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driver_->DrawIndexAuto(
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(XE_GPU_PRIMITIVE_TYPE)prim_type,
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index_count);
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}
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break;
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case PM4_DRAW_INDX_2:
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// draw using supplied indices in packet
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{
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XELOGGPU("[%.8X] Packet(%.8X): PM4_DRAW_INDX_2",
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ptr + n * 4, packet);
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LOG_DATA(count);
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uint32_t d0 = XEGETUINT32BE(packet_base + 1 * 4);
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uint32_t index_count = d0 >> 16;
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uint32_t prim_type = d0 & 0x3F;
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uint32_t src_sel = (d0 >> 6) & 0x3;
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XEASSERT(src_sel == 0x2); // 'SrcSel=AutoIndex'
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driver_->DrawIndexAuto(
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(XE_GPU_PRIMITIVE_TYPE)prim_type,
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index_count);
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}
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break;
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case PM4_IM_LOAD:
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// load sequencer instruction memory (pointer-based)
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{
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XELOGGPU("[%.8X] Packet(%.8X): PM4_IM_LOAD",
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ptr + n * 4, packet);
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LOG_DATA(count);
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uint32_t addr_type = XEGETUINT32BE(packet_base + 1 * 4);
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uint32_t type = addr_type & 0x3;
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uint32_t addr = addr_type & ~0x3;
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uint32_t start_size = XEGETUINT32BE(packet_base + 2 * 4);
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uint32_t start = start_size >> 16;
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uint32_t size = start_size & 0xFFFF; // dwords
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XEASSERT(start == 0);
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driver_->SetShader(
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(XE_GPU_SHADER_TYPE)type,
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TRANSLATE_ADDR(addr),
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start,
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size * 4);
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}
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break;
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case PM4_IM_LOAD_IMMEDIATE:
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// load sequencer instruction memory (code embedded in packet)
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{
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XELOGGPU("[%.8X] Packet(%.8X): PM4_IM_LOAD_IMMEDIATE",
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ptr + n * 4, packet);
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uint32_t type = XEGETUINT32BE(packet_base + 1 * 4);
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uint32_t start_size = XEGETUINT32BE(packet_base + 2 * 4);
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uint32_t start = start_size >> 16;
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uint32_t size = start_size & 0xFFFF; // dwords
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XEASSERT(start == 0);
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LOG_DATA(count);
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driver_->SetShader(
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(XE_GPU_SHADER_TYPE)type,
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ptr + n * 4 + 3 * 4,
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start,
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size * 4);
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}
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break;
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case PM4_INVALIDATE_STATE:
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// selective invalidation of state pointers
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{
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XELOGGPU("[%.8X] Packet(%.8X): PM4_INVALIDATE_STATE",
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ptr + n * 4, packet);
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LOG_DATA(count);
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uint32_t mask = XEGETUINT32BE(packet_base + 1 * 4);
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driver_->InvalidateState(mask);
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}
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break;
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default:
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XELOGGPU("[%.8X] Packet(%.8X): unknown!",
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ptr + n * 4, packet);
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LOG_DATA(count);
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break;
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}
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n += 1 + count;
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}
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break;
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}
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void RingBufferWorker::AdvancePtr(PacketArgs& args, uint32_t n) {
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args.ptr = args.ptr + n * 4;
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if (args.ptr_mask) {
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args.ptr =
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args.base_ptr + (((args.ptr - args.base_ptr) / 4) & args.ptr_mask) * 4;
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}
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}
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#define ADVANCE_PTR(n) AdvancePtr(args, n)
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#define READ_PTR() \
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XEGETUINT32BE(p + args.ptr)
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#define READ_AND_ADVANCE_PTR() \
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XEGETUINT32BE(p + args.ptr); ADVANCE_PTR(1);
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uint32_t RingBufferWorker::ExecutePacket(PacketArgs& args) {
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uint8_t* p = xe_memory_addr(memory_);
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RegisterFile* regs = driver_->register_file();
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uint32_t packet_ptr = args.ptr;
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const uint8_t* packet_base = p + packet_ptr;
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const uint32_t packet = READ_PTR();
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ADVANCE_PTR(1);
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const uint32_t packet_type = packet >> 30;
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if (packet == 0) {
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return 1;
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}
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switch (packet_type) {
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case 0x00:
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{
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// Type-0 packet.
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// Write count registers in sequence to the registers starting at
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// (base_index << 2).
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XELOGGPU("[%.8X] Packet(%.8X): set registers:",
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packet_ptr, packet);
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uint32_t count = ((packet >> 16) & 0x3FFF) + 1;
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uint32_t base_index = (packet & 0xFFFF);
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for (uint32_t m = 0; m < count; m++) {
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uint32_t reg_data = READ_PTR();
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const char* reg_name = xenos::GetRegisterName(base_index + m);
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XELOGGPU("[%.8X] %.8X -> %.4X %s",
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args.ptr,
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reg_data, base_index + m, reg_name ? reg_name : "");
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ADVANCE_PTR(1);
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// TODO(benvanik): exec write handler (if special).
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if (base_index + m < kXEGpuRegisterCount) {
|
||||
regs->values[base_index + m].u32 = reg_data;
|
||||
}
|
||||
}
|
||||
return 1 + count;
|
||||
}
|
||||
break;
|
||||
case 0x01:
|
||||
{
|
||||
// Type-1 packet.
|
||||
// Contains two registers of data. Type-0 should be more common.
|
||||
XELOGGPU("[%.8X] Packet(%.8X): set registers:",
|
||||
packet_ptr, packet);
|
||||
uint32_t reg_index_1 = packet & 0x7FF;
|
||||
uint32_t reg_index_2 = (packet >> 11) & 0x7FF;
|
||||
uint32_t reg_ptr_1 = args.ptr;
|
||||
uint32_t reg_data_1 = READ_AND_ADVANCE_PTR();
|
||||
uint32_t reg_ptr_2 = args.ptr;
|
||||
uint32_t reg_data_2 = READ_AND_ADVANCE_PTR();
|
||||
const char* reg_name_1 = xenos::GetRegisterName(reg_index_1);
|
||||
const char* reg_name_2 = xenos::GetRegisterName(reg_index_2);
|
||||
XELOGGPU("[%.8X] %.8X -> %.4X %s",
|
||||
reg_ptr_1,
|
||||
reg_data_1, reg_index_1, reg_name_1 ? reg_name_1 : "");
|
||||
XELOGGPU("[%.8X] %.8X -> %.4X %s",
|
||||
reg_ptr_2,
|
||||
reg_data_2, reg_index_2, reg_name_2 ? reg_name_2 : "");
|
||||
// TODO(benvanik): exec write handler (if special).
|
||||
if (reg_index_1 < kXEGpuRegisterCount) {
|
||||
regs->values[reg_index_1].u32 = reg_data_1;
|
||||
}
|
||||
if (reg_index_2 < kXEGpuRegisterCount) {
|
||||
regs->values[reg_index_2].u32 = reg_data_2;
|
||||
}
|
||||
return 1 + 2;
|
||||
}
|
||||
break;
|
||||
case 0x02:
|
||||
// Type-2 packet.
|
||||
// No-op. Do nothing.
|
||||
return 1;
|
||||
case 0x03:
|
||||
{
|
||||
// Type-3 packet.
|
||||
uint32_t count = ((packet >> 16) & 0x3FFF) + 1;
|
||||
uint32_t opcode = (packet >> 8) & 0x7F;
|
||||
// & 1 == predicate, maybe?
|
||||
|
||||
switch (opcode) {
|
||||
case PM4_ME_INIT:
|
||||
// initialize CP's micro-engine
|
||||
XELOGGPU("[%.8X] Packet(%.8X): PM4_ME_INIT",
|
||||
packet_ptr, packet);
|
||||
LOG_DATA(count);
|
||||
ADVANCE_PTR(count);
|
||||
break;
|
||||
|
||||
case PM4_NOP:
|
||||
// skip N 32-bit words to get to the next packet
|
||||
// No-op, ignore some data.
|
||||
XELOGGPU("[%.8X] Packet(%.8X): PM4_NOP",
|
||||
packet_ptr, packet);
|
||||
LOG_DATA(count);
|
||||
ADVANCE_PTR(count);
|
||||
break;
|
||||
|
||||
case PM4_INDIRECT_BUFFER:
|
||||
// indirect buffer dispatch
|
||||
{
|
||||
uint32_t list_ptr = READ_AND_ADVANCE_PTR();
|
||||
uint32_t list_length = READ_AND_ADVANCE_PTR();
|
||||
XELOGGPU("[%.8X] Packet(%.8X): PM4_INDIRECT_BUFFER %.8X (%dw)",
|
||||
packet_ptr, packet, list_ptr, list_length);
|
||||
ExecuteIndirectBuffer(list_ptr, list_length);
|
||||
}
|
||||
break;
|
||||
|
||||
case PM4_WAIT_REG_MEM:
|
||||
// wait until a register or memory location is a specific value
|
||||
XELOGGPU("[%.8X] Packet(%.8X): PM4_WAIT_REG_MEM",
|
||||
packet_ptr, packet);
|
||||
LOG_DATA(count);
|
||||
ADVANCE_PTR(count);
|
||||
break;
|
||||
|
||||
case PM4_REG_RMW:
|
||||
// register read/modify/write
|
||||
// ? (used during shader upload and edram setup)
|
||||
XELOGGPU("[%.8X] Packet(%.8X): PM4_REG_RMW",
|
||||
packet_ptr, packet);
|
||||
LOG_DATA(count);
|
||||
ADVANCE_PTR(count);
|
||||
break;
|
||||
|
||||
case PM4_COND_WRITE:
|
||||
// conditional write to memory or register
|
||||
XELOGGPU("[%.8X] Packet(%.8X): PM4_COND_WRITE",
|
||||
packet_ptr, packet);
|
||||
LOG_DATA(count);
|
||||
ADVANCE_PTR(count);
|
||||
break;
|
||||
|
||||
case PM4_EVENT_WRITE:
|
||||
// generate an event that creates a write to memory when completed
|
||||
XELOGGPU("[%.8X] Packet(%.8X): PM4_EVENT_WRITE",
|
||||
packet_ptr, packet);
|
||||
LOG_DATA(count);
|
||||
ADVANCE_PTR(count);
|
||||
break;
|
||||
case PM4_EVENT_WRITE_SHD:
|
||||
// generate a VS|PS_done event
|
||||
{
|
||||
XELOGGPU("[%.8X] Packet(%.8X): PM4_EVENT_WRITE_SHD",
|
||||
packet_ptr, packet);
|
||||
LOG_DATA(count);
|
||||
uint32_t d0 = READ_AND_ADVANCE_PTR(); // 3?
|
||||
uint32_t d1 = READ_AND_ADVANCE_PTR(); // ptr
|
||||
uint32_t d2 = READ_AND_ADVANCE_PTR(); // value?
|
||||
XESETUINT32BE(p + TRANSLATE_ADDR(d1), d2);
|
||||
}
|
||||
break;
|
||||
|
||||
case PM4_DRAW_INDX:
|
||||
// initiate fetch of index buffer and draw
|
||||
{
|
||||
XELOGGPU("[%.8X] Packet(%.8X): PM4_DRAW_INDX",
|
||||
packet_ptr, packet);
|
||||
LOG_DATA(count);
|
||||
// d0 = viz query info
|
||||
uint32_t d0 = READ_AND_ADVANCE_PTR();
|
||||
uint32_t d1 = READ_AND_ADVANCE_PTR();
|
||||
uint32_t index_count = d1 >> 16;
|
||||
uint32_t prim_type = d1 & 0x3F;
|
||||
uint32_t src_sel = (d1 >> 6) & 0x3;
|
||||
XEASSERT(src_sel == 0x2); // 'SrcSel=AutoIndex'
|
||||
driver_->DrawIndexAuto(
|
||||
(XE_GPU_PRIMITIVE_TYPE)prim_type,
|
||||
index_count);
|
||||
}
|
||||
break;
|
||||
case PM4_DRAW_INDX_2:
|
||||
// draw using supplied indices in packet
|
||||
{
|
||||
XELOGGPU("[%.8X] Packet(%.8X): PM4_DRAW_INDX_2",
|
||||
packet_ptr, packet);
|
||||
LOG_DATA(count);
|
||||
uint32_t d0 = READ_AND_ADVANCE_PTR();
|
||||
uint32_t index_count = d0 >> 16;
|
||||
uint32_t prim_type = d0 & 0x3F;
|
||||
uint32_t src_sel = (d0 >> 6) & 0x3;
|
||||
XEASSERT(src_sel == 0x2); // 'SrcSel=AutoIndex'
|
||||
driver_->DrawIndexAuto(
|
||||
(XE_GPU_PRIMITIVE_TYPE)prim_type,
|
||||
index_count);
|
||||
}
|
||||
break;
|
||||
|
||||
case PM4_IM_LOAD:
|
||||
// load sequencer instruction memory (pointer-based)
|
||||
{
|
||||
XELOGGPU("[%.8X] Packet(%.8X): PM4_IM_LOAD",
|
||||
packet_ptr, packet);
|
||||
LOG_DATA(count);
|
||||
uint32_t addr_type = READ_AND_ADVANCE_PTR();
|
||||
uint32_t type = addr_type & 0x3;
|
||||
uint32_t addr = addr_type & ~0x3;
|
||||
uint32_t start_size = READ_AND_ADVANCE_PTR();
|
||||
uint32_t start = start_size >> 16;
|
||||
uint32_t size = start_size & 0xFFFF; // dwords
|
||||
XEASSERT(start == 0);
|
||||
driver_->SetShader(
|
||||
(XE_GPU_SHADER_TYPE)type,
|
||||
TRANSLATE_ADDR(addr),
|
||||
start,
|
||||
size * 4);
|
||||
}
|
||||
break;
|
||||
case PM4_IM_LOAD_IMMEDIATE:
|
||||
// load sequencer instruction memory (code embedded in packet)
|
||||
{
|
||||
XELOGGPU("[%.8X] Packet(%.8X): PM4_IM_LOAD_IMMEDIATE",
|
||||
packet_ptr, packet);
|
||||
LOG_DATA(count);
|
||||
uint32_t type = READ_AND_ADVANCE_PTR();
|
||||
uint32_t start_size = READ_AND_ADVANCE_PTR();
|
||||
uint32_t start = start_size >> 16;
|
||||
uint32_t size = start_size & 0xFFFF; // dwords
|
||||
XEASSERT(start == 0);
|
||||
// TODO(benvanik): figure out if this could wrap.
|
||||
XEASSERT(args.ptr + size * 4 < args.max_address);
|
||||
driver_->SetShader(
|
||||
(XE_GPU_SHADER_TYPE)type,
|
||||
args.ptr,
|
||||
start,
|
||||
size * 4);
|
||||
ADVANCE_PTR(size);
|
||||
}
|
||||
break;
|
||||
|
||||
case PM4_INVALIDATE_STATE:
|
||||
// selective invalidation of state pointers
|
||||
{
|
||||
XELOGGPU("[%.8X] Packet(%.8X): PM4_INVALIDATE_STATE",
|
||||
packet_ptr, packet);
|
||||
LOG_DATA(count);
|
||||
uint32_t mask = READ_AND_ADVANCE_PTR();
|
||||
driver_->InvalidateState(mask);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
XELOGGPU("[%.8X] Packet(%.8X): unknown!",
|
||||
packet_ptr, packet);
|
||||
LOG_DATA(count);
|
||||
ADVANCE_PTR(count);
|
||||
break;
|
||||
}
|
||||
|
||||
return 1 + count;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -35,8 +35,17 @@ public:
|
|||
|
||||
void Pump();
|
||||
|
||||
protected:
|
||||
void ExecuteSegment(uint32_t ptr, uint32_t length);
|
||||
private:
|
||||
typedef struct {
|
||||
uint32_t ptr;
|
||||
uint32_t base_ptr;
|
||||
uint32_t max_address;
|
||||
uint32_t ptr_mask;
|
||||
} PacketArgs;
|
||||
void AdvancePtr(PacketArgs& args, uint32_t n);
|
||||
void ExecutePrimaryBuffer(uint32_t start_index, uint32_t end_index);
|
||||
void ExecuteIndirectBuffer(uint32_t ptr, uint32_t length);
|
||||
uint32_t ExecutePacket(PacketArgs& args);
|
||||
|
||||
protected:
|
||||
xe_memory_ref memory_;
|
||||
|
|
@ -52,6 +61,7 @@ protected:
|
|||
|
||||
HANDLE write_ptr_index_event_;
|
||||
volatile uint32_t write_ptr_index_;
|
||||
volatile uint32_t write_ptr_max_index_;
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue