From 29912f44c0b1d270cca0991d06d02a2f463c4bee Mon Sep 17 00:00:00 2001 From: Ben Vanik Date: Tue, 24 Mar 2015 07:46:18 -0700 Subject: [PATCH] Moving alloy/ into xenia/cpu/ to start simplifying things. --- src/README.md | 1 - src/alloy/README.md | 29 -- src/alloy/alloy-private.h | 24 -- src/alloy/alloy.cc | 35 --- src/alloy/alloy.h | 18 -- src/alloy/frontend/ppc/ppc_context.h | 194 ------------ src/alloy/memory.cc | 76 ----- src/alloy/memory.h | 62 ---- src/alloy/sources.gypi | 37 --- src/alloy/test/test_insert.cc | 87 ------ src/alloy/test/test_shr.cc | 279 ------------------ src/{alloy => xenia/cpu}/backend/assembler.cc | 8 +- src/{alloy => xenia/cpu}/backend/assembler.h | 18 +- src/{alloy => xenia/cpu}/backend/backend.cc | 10 +- src/{alloy => xenia/cpu}/backend/backend.h | 20 +- .../cpu}/backend/machine_info.h | 12 +- src/{alloy => xenia/cpu}/backend/sources.gypi | 0 .../cpu}/backend/x64/sources.gypi | 0 .../cpu}/backend/x64/x64_assembler.cc | 32 +- .../cpu}/backend/x64/x64_assembler.h | 14 +- .../cpu}/backend/x64/x64_backend.cc | 18 +- .../cpu}/backend/x64/x64_backend.h | 16 +- .../cpu}/backend/x64/x64_code_cache.h | 12 +- .../cpu}/backend/x64/x64_code_cache_posix.cc | 15 +- .../cpu}/backend/x64/x64_code_cache_win.cc | 11 +- .../cpu}/backend/x64/x64_emitter.cc | 48 +-- .../cpu}/backend/x64/x64_emitter.h | 20 +- .../cpu}/backend/x64/x64_function.cc | 22 +- .../cpu}/backend/x64/x64_function.h | 16 +- .../cpu}/backend/x64/x64_sequence.inl | 0 .../cpu}/backend/x64/x64_sequences.cc | 24 +- .../cpu}/backend/x64/x64_sequences.h | 18 +- .../cpu}/backend/x64/x64_thunk_emitter.cc | 8 +- .../cpu}/backend/x64/x64_thunk_emitter.h | 16 +- .../cpu}/backend/x64/x64_tracers.cc | 20 +- .../cpu}/backend/x64/x64_tracers.h | 12 +- src/{alloy => xenia/cpu}/compiler/compiler.cc | 16 +- src/{alloy => xenia/cpu}/compiler/compiler.h | 20 +- .../cpu}/compiler/compiler_pass.cc | 10 +- .../cpu}/compiler/compiler_pass.h | 20 +- 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.../cpu}/frontend/ppc/test/instr_vslw.s | 0 .../cpu}/frontend/ppc/test/instr_vspltb.s | 0 .../cpu}/frontend/ppc/test/instr_vsplth.s | 0 .../cpu}/frontend/ppc/test/instr_vspltisb.s | 0 .../cpu}/frontend/ppc/test/instr_vspltish.s | 0 .../cpu}/frontend/ppc/test/instr_vspltisw.s | 0 .../cpu}/frontend/ppc/test/instr_vspltw.s | 0 .../cpu}/frontend/ppc/test/instr_vsubshs.s | 0 .../cpu}/frontend/ppc/test/instr_vsubuhm.s | 0 .../cpu}/frontend/ppc/test/instr_vupkd3d128.s | 0 .../cpu}/frontend/ppc/test/instr_vupkhsh.s | 0 .../cpu}/frontend/ppc/test/instr_vupklsh.s | 0 .../cpu}/frontend/ppc/test/test.gypi | 5 +- .../cpu}/frontend/ppc/test/update.sh | 2 +- .../cpu/frontend/ppc/test/xe-cpu-ppc-test.cc} | 49 +-- .../cpu}/frontend/sources.gypi | 0 src/{alloy => xenia/cpu}/hir/block.cc | 10 +- src/{alloy => xenia/cpu}/hir/block.h | 12 +- src/{alloy => xenia/cpu}/hir/hir_builder.cc | 22 +- src/{alloy => xenia/cpu}/hir/hir_builder.h | 22 +- src/{alloy => xenia/cpu}/hir/instr.cc | 10 +- src/{alloy => xenia/cpu}/hir/instr.h | 22 +- src/{alloy => xenia/cpu}/hir/label.h | 12 +- src/{alloy => xenia/cpu}/hir/opcodes.cc | 10 +- src/{alloy => xenia/cpu}/hir/opcodes.h | 18 +- src/{alloy => xenia/cpu}/hir/opcodes.inl | 0 src/{alloy => xenia/cpu}/hir/sources.gypi | 0 src/{alloy => xenia/cpu}/hir/value.cc | 8 +- src/{alloy => xenia/cpu}/hir/value.h | 16 +- src/xenia/cpu/mmio_handler_mac.cc | 6 +- src/xenia/cpu/processor.cc | 20 +- .../cpu}/runtime/debug_info.cc | 8 +- src/{alloy => xenia/cpu}/runtime/debug_info.h | 12 +- src/{alloy => xenia/cpu}/runtime/debugger.cc | 10 +- src/{alloy => xenia/cpu}/runtime/debugger.h | 12 +- .../cpu}/runtime/entry_table.cc | 9 +- .../cpu}/runtime/entry_table.h | 12 +- src/{alloy => xenia/cpu}/runtime/function.cc | 18 +- src/{alloy => xenia/cpu}/runtime/function.h | 14 +- .../cpu}/runtime/instrument.cc | 14 +- src/{alloy => xenia/cpu}/runtime/instrument.h | 18 +- src/{alloy => xenia/cpu}/runtime/module.cc | 14 +- src/{alloy => xenia/cpu}/runtime/module.h | 16 +- .../cpu}/runtime/raw_module.cc | 8 +- src/{alloy => xenia/cpu}/runtime/raw_module.h | 14 +- src/{alloy => xenia/cpu}/runtime/runtime.cc | 28 +- src/{alloy => xenia/cpu}/runtime/runtime.h | 28 +- src/{alloy => xenia/cpu}/runtime/sources.gypi | 0 .../cpu}/runtime/symbol_info.cc | 8 +- .../cpu}/runtime/symbol_info.h | 12 +- .../cpu}/runtime/test_module.cc | 24 +- .../cpu}/runtime/test_module.h | 20 +- .../cpu}/runtime/thread_state.cc | 10 +- .../cpu}/runtime/thread_state.h | 14 +- src/xenia/cpu/sources.gypi | 8 + src/{alloy => xenia/cpu}/test/test.gypi | 13 +- src/{alloy => xenia/cpu}/test/test_add.cc | 31 +- .../cpu}/test/test_byte_swap.cc | 18 +- src/{alloy => xenia/cpu}/test/test_extract.cc | 49 ++- src/xenia/cpu/test/test_insert.cc | 83 ++++++ .../cpu}/test/test_load_vector_shl_shr.cc | 15 +- src/{alloy => xenia/cpu}/test/test_pack.cc | 19 +- src/{alloy => xenia/cpu}/test/test_permute.cc | 21 +- src/{alloy => xenia/cpu}/test/test_sha.cc | 19 +- src/{alloy => xenia/cpu}/test/test_shl.cc | 19 +- src/xenia/cpu/test/test_shr.cc | 258 ++++++++++++++++ src/{alloy => xenia/cpu}/test/test_swizzle.cc | 17 +- src/{alloy => xenia/cpu}/test/test_unpack.cc | 27 +- .../cpu}/test/test_vector_add.cc | 31 +- .../cpu}/test/test_vector_max.cc | 41 ++- .../cpu}/test/test_vector_min.cc | 23 +- .../cpu}/test/test_vector_rotate_left.cc | 43 ++- .../cpu}/test/test_vector_sha.cc | 50 ++-- .../cpu}/test/test_vector_shl.cc | 50 ++-- .../cpu}/test/test_vector_shr.cc | 50 ++-- src/{alloy => xenia/cpu}/test/util.h | 54 ++-- .../cpu/test/xe-cpu-hir-test.cc} | 14 +- .../cpu/test/xe-cpu-sandbox.cc} | 42 +-- src/xenia/cpu/xenon_runtime.cc | 14 +- src/xenia/cpu/xenon_runtime.h | 7 +- src/xenia/cpu/xenon_thread_state.cc | 13 +- src/xenia/cpu/xenon_thread_state.h | 8 +- src/xenia/cpu/xex_module.cc | 13 +- src/xenia/cpu/xex_module.h | 4 +- src/xenia/kernel/util/shim_utils.h | 7 +- src/xenia/kernel/util/xex2.cc | 2 - src/xenia/memory.cc | 57 +++- src/xenia/memory.h | 33 ++- src/xenia/profiling.cc | 1 - xenia-build.py | 12 +- xenia.gyp | 111 ++----- 519 files changed, 2246 insertions(+), 2296 deletions(-) delete mode 100644 src/alloy/README.md delete mode 100644 src/alloy/alloy-private.h delete mode 100644 src/alloy/alloy.cc delete mode 100644 src/alloy/alloy.h delete mode 100644 src/alloy/frontend/ppc/ppc_context.h delete mode 100644 src/alloy/memory.cc delete mode 100644 src/alloy/memory.h delete mode 100644 src/alloy/sources.gypi delete mode 100644 src/alloy/test/test_insert.cc delete mode 100644 src/alloy/test/test_shr.cc rename src/{alloy => xenia/cpu}/backend/assembler.cc (86%) rename src/{alloy => xenia/cpu}/backend/assembler.h (83%) rename src/{alloy => xenia/cpu}/backend/backend.cc (85%) rename src/{alloy => xenia/cpu}/backend/backend.h (79%) rename src/{alloy => xenia/cpu}/backend/machine_info.h (81%) rename src/{alloy => xenia/cpu}/backend/sources.gypi (100%) rename src/{alloy => xenia/cpu}/backend/x64/sources.gypi (100%) rename src/{alloy => xenia/cpu}/backend/x64/x64_assembler.cc (85%) rename src/{alloy => xenia/cpu}/backend/x64/x64_assembler.h (85%) rename src/{alloy => xenia/cpu}/backend/x64/x64_backend.cc (83%) rename src/{alloy => xenia/cpu}/backend/x64/x64_backend.h (82%) rename src/{alloy => xenia/cpu}/backend/x64/x64_code_cache.h (84%) rename src/{alloy => xenia/cpu}/backend/x64/x64_code_cache_posix.cc (92%) rename src/{alloy => xenia/cpu}/backend/x64/x64_code_cache_win.cc (98%) rename src/{alloy => xenia/cpu}/backend/x64/x64_emitter.cc (97%) rename src/{alloy => xenia/cpu}/backend/x64/x64_emitter.h (94%) rename src/{alloy => xenia/cpu}/backend/x64/x64_function.cc (77%) rename src/{alloy => xenia/cpu}/backend/x64/x64_function.h (80%) rename src/{alloy => xenia/cpu}/backend/x64/x64_sequence.inl (100%) rename src/{alloy => xenia/cpu}/backend/x64/x64_sequences.cc (99%) rename src/{alloy => xenia/cpu}/backend/x64/x64_sequences.h (73%) rename src/{alloy => xenia/cpu}/backend/x64/x64_thunk_emitter.cc (96%) rename src/{alloy => xenia/cpu}/backend/x64/x64_thunk_emitter.h (92%) rename src/{alloy => xenia/cpu}/backend/x64/x64_tracers.cc (96%) rename src/{alloy => xenia/cpu}/backend/x64/x64_tracers.h (94%) rename src/{alloy => xenia/cpu}/compiler/compiler.cc (84%) rename src/{alloy => xenia/cpu}/compiler/compiler.h (79%) rename src/{alloy => xenia/cpu}/compiler/compiler_pass.cc (84%) rename src/{alloy => xenia/cpu}/compiler/compiler_pass.h (75%) rename src/{alloy => xenia/cpu}/compiler/compiler_passes.h (86%) rename src/{alloy => xenia/cpu}/compiler/passes/constant_propagation_pass.cc (97%) rename src/{alloy => xenia/cpu}/compiler/passes/constant_propagation_pass.h (73%) rename src/{alloy => xenia/cpu}/compiler/passes/context_promotion_pass.cc (91%) rename src/{alloy => xenia/cpu}/compiler/passes/context_promotion_pass.h (81%) rename src/{alloy => xenia/cpu}/compiler/passes/control_flow_analysis_pass.cc (85%) rename src/{alloy => xenia/cpu}/compiler/passes/control_flow_analysis_pass.h (72%) rename src/{alloy => xenia/cpu}/compiler/passes/control_flow_simplification_pass.cc (83%) rename src/{alloy => xenia/cpu}/compiler/passes/control_flow_simplification_pass.h (72%) rename src/{alloy => xenia/cpu}/compiler/passes/data_flow_analysis_pass.cc (92%) rename src/{alloy => xenia/cpu}/compiler/passes/data_flow_analysis_pass.h (73%) rename src/{alloy => xenia/cpu}/compiler/passes/dead_code_elimination_pass.cc (96%) rename src/{alloy => xenia/cpu}/compiler/passes/dead_code_elimination_pass.h (73%) rename src/{alloy => xenia/cpu}/compiler/passes/finalization_pass.cc (85%) rename src/{alloy => xenia/cpu}/compiler/passes/finalization_pass.h (73%) rename src/{alloy => xenia/cpu}/compiler/passes/register_allocation_pass.cc (97%) rename src/{alloy => xenia/cpu}/compiler/passes/register_allocation_pass.h (88%) rename src/{alloy => xenia/cpu}/compiler/passes/simplification_pass.cc (95%) rename src/{alloy => xenia/cpu}/compiler/passes/simplification_pass.h (78%) rename src/{alloy => xenia/cpu}/compiler/passes/sources.gypi (100%) rename src/{alloy => xenia/cpu}/compiler/passes/validation_pass.cc (85%) rename src/{alloy => xenia/cpu}/compiler/passes/validation_pass.h (76%) rename src/{alloy => xenia/cpu}/compiler/passes/value_reduction_pass.cc (91%) rename src/{alloy => xenia/cpu}/compiler/passes/value_reduction_pass.h (74%) rename src/{alloy => xenia/cpu}/compiler/sources.gypi (100%) rename src/{alloy => xenia/cpu}/frontend/context_info.cc (87%) rename src/{alloy => xenia/cpu}/frontend/context_info.h (84%) rename src/{alloy => xenia/cpu}/frontend/frontend.cc (83%) rename src/{alloy => xenia/cpu}/frontend/frontend.h (75%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_context.cc (92%) create mode 100644 src/xenia/cpu/frontend/ppc/ppc_context.h rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_disasm.cc (96%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_disasm.h (73%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_emit-private.h (74%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_emit.h (75%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_emit_altivec.cc (99%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_emit_alu.cc (99%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_emit_control.cc (98%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_emit_fpu.cc (96%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_emit_memory.cc (99%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_frontend.cc (82%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_frontend.h (84%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_hir_builder.cc (95%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_hir_builder.h (87%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_instr.cc (97%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_instr.h (98%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_instr_tables.h (99%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_scanner.cc (97%) rename src/{alloy => xenia/cpu}/frontend/ppc/ppc_scanner.h (80%) rename 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(81%) rename src/{alloy => xenia/cpu}/test/test_vector_shl.cc (81%) rename src/{alloy => xenia/cpu}/test/test_vector_shr.cc (81%) rename src/{alloy => xenia/cpu}/test/util.h (78%) rename src/{alloy/test/alloy-test.cc => xenia/cpu/test/xe-cpu-hir-test.cc} (83%) rename src/{alloy/test/alloy-sandbox.cc => xenia/cpu/test/xe-cpu-sandbox.cc} (77%) diff --git a/src/README.md b/src/README.md index 47240caca..fdcfa4e30 100644 --- a/src/README.md +++ b/src/README.md @@ -1,6 +1,5 @@ All code (headers and sources) lives under this path, excluding third_party code. -* alloy: the dynamic recompiler that parses PPC and generates code. * poly: a lightweight cross-platform/compiler compatibility library. * xdb: xenia debugger library and UI. * xenia: emulator code. diff --git a/src/alloy/README.md b/src/alloy/README.md deleted file mode 100644 index 2cbe29fc6..000000000 --- a/src/alloy/README.md +++ /dev/null @@ -1,29 +0,0 @@ -alloy: small dynamic recompiler engine -=== - -Alloy is a transpiler framework that allows for pluggable frontends for decoding -guest machine instructions (such as PPC) and pluggable backends for generating -host code (such as x64). It features an SSA IR designed to model machine -instructions and vector operations and compilation passes that seek to efficiently -optimize previously-optimized code. - -Future versions will cache generated code across runs and enable offline -precompilation. - -Frontends ---- - -Frontends are responsible for translating guest machine instructions into IR. -Information about the guest machine and ABI is used to support efficient CPU -state accesses and debug information. - -* PPC64 with Altivec extenions - -Backends ---- - -A backend takes optimized IR and assembles an implementation-specific result. -The backend is also responsible for executing the code it generates and supporting -debugging features (such as breakpoints). - -* x64: IA-64 with AVX2 code generator diff --git a/src/alloy/alloy-private.h b/src/alloy/alloy-private.h deleted file mode 100644 index e20e04806..000000000 --- a/src/alloy/alloy-private.h +++ /dev/null @@ -1,24 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef ALLOY_ALLOY_PRIVATE_H_ -#define ALLOY_ALLOY_PRIVATE_H_ - -#include - -DECLARE_bool(debug); -DECLARE_bool(always_disasm); - -DECLARE_bool(validate_hir); - -DECLARE_uint64(break_on_instruction); -DECLARE_uint64(break_on_memory); -DECLARE_bool(break_on_debugbreak); - -#endif // ALLOY_ALLOY_PRIVATE_H_ diff --git a/src/alloy/alloy.cc b/src/alloy/alloy.cc deleted file mode 100644 index 3435a4950..000000000 --- a/src/alloy/alloy.cc +++ /dev/null @@ -1,35 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#include "alloy/alloy.h" -#include "alloy/alloy-private.h" - -using namespace alloy; - -#if 0 && DEBUG -#define DEFAULT_DEBUG_FLAG true -#else -#define DEFAULT_DEBUG_FLAG false -#endif - -DEFINE_bool(debug, DEFAULT_DEBUG_FLAG, - "Allow debugging and retain debug information."); -DEFINE_bool( - always_disasm, false, - "Always add debug info to functions, even when no debugger is attached."); - -DEFINE_bool(validate_hir, false, - "Perform validation checks on the HIR during compilation."); - -// Breakpoints: -DEFINE_uint64(break_on_instruction, 0, - "int3 before the given guest address is executed."); -DEFINE_uint64(break_on_memory, 0, - "int3 on read/write to the given memory address."); -DEFINE_bool(break_on_debugbreak, true, "int3 on JITed __debugbreak requests."); diff --git a/src/alloy/alloy.h b/src/alloy/alloy.h deleted file mode 100644 index 4f47028f0..000000000 --- a/src/alloy/alloy.h +++ /dev/null @@ -1,18 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef ALLOY_ALLOY_H_ -#define ALLOY_ALLOY_H_ - -#include "alloy/runtime/function.h" -#include "alloy/runtime/module.h" -#include "alloy/runtime/runtime.h" -#include "alloy/runtime/thread_state.h" - -#endif // ALLOY_ALLOY_H_ diff --git a/src/alloy/frontend/ppc/ppc_context.h b/src/alloy/frontend/ppc/ppc_context.h deleted file mode 100644 index 2945d16a3..000000000 --- a/src/alloy/frontend/ppc/ppc_context.h +++ /dev/null @@ -1,194 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef ALLOY_FRONTEND_PPC_PPC_CONTEXT_H_ -#define ALLOY_FRONTEND_PPC_PPC_CONTEXT_H_ - -#include "poly/poly.h" -#include "poly/vec128.h" - -namespace alloy { namespace runtime { - class Runtime; - class ThreadState; -} } - -namespace alloy { -namespace frontend { -namespace ppc { - -using vec128_t = poly::vec128_t; - -// Map: -// 0-31: GPR -// 32-63: FPR -// 64: LR -// 65: CTR -// 66: XER -// 67: FPSCR -// 68: VSCR -// 69-76: CR0-7 -// 100: invalid -// 128-256: VR - -#pragma pack(push, 4) -typedef struct alignas(64) PPCContext_s { - // Must be stored at 0x0 for now. - // TODO(benvanik): find a nice way to describe this to the JIT. - runtime::ThreadState* thread_state; - // TODO(benvanik): this is getting nasty. Must be here. - uint8_t* membase; - - // Most frequently used registers first. - uint64_t r[32]; // General purpose registers - uint64_t lr; // Link register - uint64_t ctr; // Count register - - // XER register - // Split to make it easier to do individual updates. - uint8_t xer_ca; - uint8_t xer_ov; - uint8_t xer_so; - - // Condition registers - // These are split to make it easier to do DCE on unused stores. - union { - uint32_t value; - struct { - uint8_t cr0_lt; // Negative (LT) - result is negative - uint8_t cr0_gt; // Positive (GT) - result is positive (and not zero) - uint8_t cr0_eq; // Zero (EQ) - result is zero or a stwcx/stdcx completed successfully - uint8_t cr0_so; // Summary Overflow (SO) - copy of XER[SO] - }; - } cr0; - union { - uint32_t value; - struct { - uint8_t cr1_fx; // FP exception summary - copy of FPSCR[FX] - uint8_t cr1_fex; // FP enabled exception summary - copy of FPSCR[FEX] - uint8_t cr1_vx; // FP invalid operation exception summary - copy of FPSCR[VX] - uint8_t cr1_ox; // FP overflow exception - copy of FPSCR[OX] - }; - } cr1; - union { - uint32_t value; - struct { - uint8_t cr2_0; uint8_t cr2_1; uint8_t cr2_2; uint8_t cr2_3; - }; - } cr2; - union { - uint32_t value; - struct { - uint8_t cr3_0; uint8_t cr3_1; uint8_t cr3_2; uint8_t cr3_3; - }; - } cr3; - union { - uint32_t value; - struct { - uint8_t cr4_0; uint8_t cr4_1; uint8_t cr4_2; uint8_t cr4_3; - }; - } cr4; - union { - uint32_t value; - struct { - uint8_t cr5_0; uint8_t cr5_1; uint8_t cr5_2; uint8_t cr5_3; - }; - } cr5; - union { - uint32_t value; - struct { - uint8_t cr6_all_equal; - uint8_t cr6_1; - uint8_t cr6_none_equal; - uint8_t cr6_3; - }; - } cr6; - union { - uint32_t value; - struct { - uint8_t cr7_0; uint8_t cr7_1; uint8_t cr7_2; uint8_t cr7_3; - }; - } cr7; - - union { - uint32_t value; - struct { - uint32_t rn :2; // FP rounding control: 00 = nearest - // 01 = toward zero - // 10 = toward +infinity - // 11 = toward -infinity - uint32_t ni :1; // Floating-point non-IEEE mode - uint32_t xe :1; // IEEE floating-point inexact exception enable - uint32_t ze :1; // IEEE floating-point zero divide exception enable - uint32_t ue :1; // IEEE floating-point underflow exception enable - uint32_t oe :1; // IEEE floating-point overflow exception enable - uint32_t ve :1; // FP invalid op exception enable - uint32_t vxcvi :1; // FP invalid op exception: invalid integer convert -- sticky - uint32_t vxsqrt :1; // FP invalid op exception: invalid sqrt -- sticky - uint32_t vxsoft :1; // FP invalid op exception: software request -- sticky - uint32_t reserved :1; - uint32_t fprf_un :1; // FP result unordered or NaN (FU or ?) - uint32_t fprf_eq :1; // FP result equal or zero (FE or =) - uint32_t fprf_gt :1; // FP result greater than or positive (FG or >) - uint32_t fprf_lt :1; // FP result less than or negative (FL or <) - uint32_t fprf_c :1; // FP result class - uint32_t fi :1; // FP fraction inexact - uint32_t fr :1; // FP fraction rounded - uint32_t vxvc :1; // FP invalid op exception: invalid compare -- sticky - uint32_t vximz :1; // FP invalid op exception: infinity * 0 -- sticky - uint32_t vxzdz :1; // FP invalid op exception: 0 / 0 -- sticky - uint32_t vxidi :1; // FP invalid op exception: infinity / infinity -- sticky - uint32_t vxisi :1; // FP invalid op exception: infinity - infinity -- sticky - uint32_t vxsnan :1; // FP invalid op exception: SNaN -- sticky - uint32_t xx :1; // FP inexact exception -- sticky - uint32_t zx :1; // FP zero divide exception -- sticky - uint32_t ux :1; // FP underflow exception -- sticky - uint32_t ox :1; // FP overflow exception -- sticky - uint32_t vx :1; // FP invalid operation exception summary - uint32_t fex :1; // FP enabled exception summary - uint32_t fx :1; // FP exception summary -- sticky - } bits; - } fpscr; // Floating-point status and control register - - uint8_t vscr_sat; - - double f[32]; // Floating-point registers - vec128_t v[128]; // VMX128 vector registers - - // uint32_t get_fprf() { - // return fpscr.value & 0x000F8000; - // } - // void set_fprf(const uint32_t v) { - // fpscr.value = (fpscr.value & ~0x000F8000) | v; - // } - - // Thread ID assigned to this context. - uint32_t thread_id; - - // Reserve address for load acquire/store release. Shared. - uint64_t* reserve_address; - uint64_t* reserve_value; - - // Used to shuttle data into externs. Contents volatile. - uint64_t scratch; - - // Runtime-specific data pointer. Used on callbacks to get access to the - // current runtime and its data. - runtime::Runtime* runtime; - - void SetRegFromString(const char* name, const char* value); - bool CompareRegWithString(const char* name, const char* value, - char* out_value, size_t out_value_size); -} PPCContext; -#pragma pack(pop) - -} // namespace ppc -} // namespace frontend -} // namespace alloy - -#endif // ALLOY_FRONTEND_PPC_PPC_CONTEXT_H_ diff --git a/src/alloy/memory.cc b/src/alloy/memory.cc deleted file mode 100644 index c5680443b..000000000 --- a/src/alloy/memory.cc +++ /dev/null @@ -1,76 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#include "alloy/memory.h" - -#include "poly/poly.h" - -namespace alloy { - -Memory::Memory() - : membase_(nullptr), - reserve_address_(0), - reserve_value_(0), - trace_base_(0) { - system_page_size_ = poly::page_size(); -} - -Memory::~Memory() = default; - -int Memory::Initialize() { return 0; } - -void Memory::Zero(uint64_t address, size_t size) { - uint8_t* p = membase_ + address; - memset(p, 0, size); -} - -void Memory::Fill(uint64_t address, size_t size, uint8_t value) { - uint8_t* p = membase_ + address; - memset(p, value, size); -} - -void Memory::Copy(uint64_t dest, uint64_t src, size_t size) { - uint8_t* pdest = membase_ + dest; - const uint8_t* psrc = membase_ + src; - memcpy(pdest, psrc, size); -} - -uint64_t Memory::SearchAligned(uint64_t start, uint64_t end, - const uint32_t* values, size_t value_count) { - assert_true(start <= end); - const uint32_t* p = reinterpret_cast(membase_ + start); - const uint32_t* pe = reinterpret_cast(membase_ + end); - while (p != pe) { - if (*p == values[0]) { - const uint32_t* pc = p + 1; - size_t matched = 1; - for (size_t n = 1; n < value_count; n++, pc++) { - if (*pc != values[n]) { - break; - } - matched++; - } - if (matched == value_count) { - return uint64_t(reinterpret_cast(p) - membase_); - } - } - p++; - } - return 0; -} - -SimpleMemory::SimpleMemory(size_t capacity) : memory_(capacity) { - membase_ = reinterpret_cast(memory_.data()); - reserve_address_ = capacity - 8; - reserve_value_ = capacity - 16; -} - -SimpleMemory::~SimpleMemory() = default; - -} // namespace alloy diff --git a/src/alloy/memory.h b/src/alloy/memory.h deleted file mode 100644 index de094f6e3..000000000 --- a/src/alloy/memory.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#ifndef ALLOY_MEMORY_H_ -#define ALLOY_MEMORY_H_ - -#include -#include - -namespace alloy { - -class Memory { - public: - Memory(); - virtual ~Memory(); - - inline uint8_t* membase() const { return membase_; } - inline uint8_t* Translate(uint64_t guest_address) const { - return membase_ + guest_address; - }; - inline uint64_t* reserve_address() { return &reserve_address_; } - inline uint64_t* reserve_value() { return &reserve_value_; } - - uint64_t trace_base() const { return trace_base_; } - void set_trace_base(uint64_t value) { trace_base_ = value; } - - virtual int Initialize(); - - // TODO(benvanik): make poly memory utils for these. - void Zero(uint64_t address, size_t size); - void Fill(uint64_t address, size_t size, uint8_t value); - void Copy(uint64_t dest, uint64_t src, size_t size); - - uint64_t SearchAligned(uint64_t start, uint64_t end, const uint32_t* values, - size_t value_count); - - protected: - size_t system_page_size_; - uint8_t* membase_; - uint64_t reserve_address_; - uint64_t reserve_value_; - uint64_t trace_base_; -}; - -class SimpleMemory : public Memory { - public: - SimpleMemory(size_t capacity); - ~SimpleMemory() override; - - private: - std::vector memory_; -}; - -} // namespace alloy - -#endif // ALLOY_MEMORY_H_ diff --git a/src/alloy/sources.gypi b/src/alloy/sources.gypi deleted file mode 100644 index cea450cc8..000000000 --- a/src/alloy/sources.gypi +++ /dev/null @@ -1,37 +0,0 @@ -# Copyright 2013 Ben Vanik. All Rights Reserved. -{ - 'sources': [ - 'alloy-private.h', - 'alloy.cc', - 'alloy.h', - 'memory.cc', - 'memory.h', - ], - - 'conditions': [ - ['OS == "mac" or OS == "linux"', { - 'sources': [ - ], - }], - ['OS == "linux"', { - 'sources': [ - ], - }], - ['OS == "mac"', { - 'sources': [ - ], - }], - ['OS == "win"', { - 'sources': [ - ], - }], - ], - - 'includes': [ - 'backend/sources.gypi', - 'compiler/sources.gypi', - 'frontend/sources.gypi', - 'hir/sources.gypi', - 'runtime/sources.gypi', - ], -} diff --git a/src/alloy/test/test_insert.cc b/src/alloy/test/test_insert.cc deleted file mode 100644 index 619602b00..000000000 --- a/src/alloy/test/test_insert.cc +++ /dev/null @@ -1,87 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#include "alloy/test/util.h" - -#include - -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; -using namespace poly; - -TEST_CASE("INSERT_INT8", "[instr]") { - for (int i = 0; i < 16; ++i) { - TestFunction test([i](hir::HIRBuilder& b) { - StoreVR(b, 3, b.Insert(LoadVR(b, 4), b.LoadConstant(i), - b.Truncate(LoadGPR(b, 5), INT8_TYPE))); - b.Return(); - }); - test.Run( - [i](PPCContext* ctx) { - ctx->v[4] = - vec128b(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - ctx->r[4] = i; - ctx->r[5] = 100 + i; - }, - [i](PPCContext* ctx) { - auto result = ctx->v[3]; - auto expected = - vec128b(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - expected.i8[i ^ 0x3] = 100 + i; - REQUIRE(result == expected); - }); - } -} - -TEST_CASE("INSERT_INT16", "[instr]") { - for (int i = 0; i < 8; ++i) { - TestFunction test([i](hir::HIRBuilder& b) { - StoreVR(b, 3, b.Insert(LoadVR(b, 4), b.LoadConstant(i), - b.Truncate(LoadGPR(b, 5), INT16_TYPE))); - b.Return(); - }); - test.Run( - [i](PPCContext* ctx) { - ctx->v[4] = vec128s(0, 1, 2, 3, 4, 5, 6, 7); - ctx->r[4] = i; - ctx->r[5] = 100 + i; - }, - [i](PPCContext* ctx) { - auto result = ctx->v[3]; - auto expected = vec128s(0, 1, 2, 3, 4, 5, 6, 7); - expected.i16[i ^ 0x1] = 100 + i; - REQUIRE(result == expected); - }); - } -} - -TEST_CASE("INSERT_INT32", "[instr]") { - for (int i = 0; i < 4; ++i) { - TestFunction test([i](hir::HIRBuilder& b) { - StoreVR(b, 3, b.Insert(LoadVR(b, 4), b.LoadConstant(i), - b.Truncate(LoadGPR(b, 5), INT32_TYPE))); - b.Return(); - }); - test.Run( - [i](PPCContext* ctx) { - ctx->v[4] = vec128i(0, 1, 2, 3); - ctx->r[4] = i; - ctx->r[5] = 100 + i; - }, - [i](PPCContext* ctx) { - auto result = ctx->v[3]; - auto expected = vec128i(0, 1, 2, 3); - expected.i32[i] = 100 + i; - REQUIRE(result == expected); - }); - } -} diff --git a/src/alloy/test/test_shr.cc b/src/alloy/test/test_shr.cc deleted file mode 100644 index bed3cf549..000000000 --- a/src/alloy/test/test_shr.cc +++ /dev/null @@ -1,279 +0,0 @@ -/** - ****************************************************************************** - * Xenia : Xbox 360 Emulator Research Project * - ****************************************************************************** - * Copyright 2014 Ben Vanik. All rights reserved. * - * Released under the BSD license - see LICENSE in the root for more details. * - ****************************************************************************** - */ - -#include "alloy/test/util.h" - -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; -using namespace poly; - -TEST_CASE("SHR_I8", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { - StoreGPR(b, 3, b.ZeroExtend(b.Shr(b.Truncate(LoadGPR(b, 4), INT8_TYPE), - b.Truncate(LoadGPR(b, 5), INT8_TYPE)), - INT64_TYPE)); - b.Return(); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0xF0; - ctx->r[5] = 4; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0x0F); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0xFF; - ctx->r[5] = 0; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0xFF); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0xFF; - ctx->r[5] = 1; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0x7F); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0x80; - ctx->r[5] = 8; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0x7F; - ctx->r[5] = 7; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0); - }); -} - -TEST_CASE("SHR_I16", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { - StoreGPR(b, 3, b.ZeroExtend(b.Shr(b.Truncate(LoadGPR(b, 4), INT16_TYPE), - b.Truncate(LoadGPR(b, 5), INT8_TYPE)), - INT64_TYPE)); - b.Return(); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0xFF00; - ctx->r[5] = 8; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0x00FF); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0xFFFF; - ctx->r[5] = 0; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0xFFFF); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0xFFFE; - ctx->r[5] = 1; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0x7FFF); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0x8000; - ctx->r[5] = 16; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0x7FFF; - ctx->r[5] = 15; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0); - }); -} - -TEST_CASE("SHR_I32", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { - StoreGPR(b, 3, b.ZeroExtend(b.Shr(b.Truncate(LoadGPR(b, 4), INT32_TYPE), - b.Truncate(LoadGPR(b, 5), INT8_TYPE)), - INT64_TYPE)); - b.Return(); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0xFFFF0000; - ctx->r[5] = 16; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0x0000FFFF); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0xFFFFFFFF; - ctx->r[5] = 0; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0xFFFFFFFF); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0xFFFFFFFE; - ctx->r[5] = 1; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0x7FFFFFFF); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0x80000000; - ctx->r[5] = 32; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0x80000000); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0x7FFFFFFF; - ctx->r[5] = 31; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0); - }); -} - -TEST_CASE("SHR_I64", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { - StoreGPR(b, 3, b.Shr(b.Truncate(LoadGPR(b, 4), INT64_TYPE), - b.Truncate(LoadGPR(b, 5), INT8_TYPE))); - b.Return(); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0xFFFFFFFF00000000ull; - ctx->r[5] = 32; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0x00000000FFFFFFFFull); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0xFFFFFFFFFFFFFFFFull; - ctx->r[5] = 0; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0xFFFFFFFFFFFFFFFFull); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0xFFFFFFFFFFFFFFFEull; - ctx->r[5] = 1; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0x7FFFFFFFFFFFFFFFull); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0x8000000000000000ull; - ctx->r[5] = 64; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0x8000000000000000ull); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[4] = 0x7FFFFFFFFFFFFFFFull; - ctx->r[5] = 63; - }, - [](PPCContext* ctx) { - auto result = static_cast(ctx->r[3]); - REQUIRE(result == 0); - }); -} - -TEST_CASE("SHR_V128", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { - StoreVR(b, 3, b.Shr(LoadVR(b, 4), b.Truncate(LoadGPR(b, 1), INT8_TYPE))); - b.Return(); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[1] = 0; - ctx->v[4] = vec128i(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); - }, - [](PPCContext* ctx) { - auto result1 = ctx->v[3]; - REQUIRE(result1 == - vec128i(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF)); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[1] = 1; - ctx->v[4] = vec128i(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); - }, - [](PPCContext* ctx) { - auto result1 = ctx->v[3]; - REQUIRE(result1 == - vec128i(0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF)); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[1] = 2; - ctx->v[4] = vec128i(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); - }, - [](PPCContext* ctx) { - auto result1 = ctx->v[3]; - REQUIRE(result1 == - vec128i(0x3FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF)); - }); - test.Run( - [](PPCContext* ctx) { - ctx->r[1] = 8; - ctx->v[4] = vec128i(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); - }, - [](PPCContext* ctx) { - auto result1 = ctx->v[3]; - REQUIRE(result1 == - vec128i(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF)); - }); -} \ No newline at end of file diff --git a/src/alloy/backend/assembler.cc b/src/xenia/cpu/backend/assembler.cc similarity index 86% rename from src/alloy/backend/assembler.cc rename to src/xenia/cpu/backend/assembler.cc index b045fa615..a6123dfac 100644 --- a/src/alloy/backend/assembler.cc +++ b/src/xenia/cpu/backend/assembler.cc @@ -7,9 +7,10 @@ ****************************************************************************** */ -#include "alloy/backend/assembler.h" +#include "xenia/cpu/backend/assembler.h" -namespace alloy { +namespace xe { +namespace cpu { namespace backend { Assembler::Assembler(Backend* backend) : backend_(backend) {} @@ -21,4 +22,5 @@ int Assembler::Initialize() { return 0; } void Assembler::Reset() {} } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/backend/assembler.h b/src/xenia/cpu/backend/assembler.h similarity index 83% rename from src/alloy/backend/assembler.h rename to src/xenia/cpu/backend/assembler.h index e671b6f38..2655ef3ee 100644 --- a/src/alloy/backend/assembler.h +++ b/src/xenia/cpu/backend/assembler.h @@ -7,12 +7,13 @@ ****************************************************************************** */ -#ifndef ALLOY_BACKEND_ASSEMBLER_H_ -#define ALLOY_BACKEND_ASSEMBLER_H_ +#ifndef XENIA_BACKEND_ASSEMBLER_H_ +#define XENIA_BACKEND_ASSEMBLER_H_ #include -namespace alloy { +namespace xe { +namespace cpu { namespace hir { class HIRBuilder; } // namespace hir @@ -22,9 +23,11 @@ class Function; class FunctionInfo; class Runtime; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -namespace alloy { +namespace xe { +namespace cpu { namespace backend { class Backend; @@ -49,6 +52,7 @@ class Assembler { }; } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_BACKEND_ASSEMBLER_H_ +#endif // XENIA_BACKEND_ASSEMBLER_H_ diff --git a/src/alloy/backend/backend.cc b/src/xenia/cpu/backend/backend.cc similarity index 85% rename from src/alloy/backend/backend.cc rename to src/xenia/cpu/backend/backend.cc index e0b1010ff..041321b73 100644 --- a/src/alloy/backend/backend.cc +++ b/src/xenia/cpu/backend/backend.cc @@ -7,12 +7,13 @@ ****************************************************************************** */ -#include "alloy/backend/backend.h" +#include "xenia/cpu/backend/backend.h" -namespace alloy { +namespace xe { +namespace cpu { namespace backend { -using alloy::runtime::Runtime; +using xe::cpu::runtime::Runtime; Backend::Backend(Runtime* runtime) : runtime_(runtime) { memset(&machine_info_, 0, sizeof(machine_info_)); @@ -27,4 +28,5 @@ void* Backend::AllocThreadData() { return nullptr; } void Backend::FreeThreadData(void* thread_data) {} } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/backend/backend.h b/src/xenia/cpu/backend/backend.h similarity index 79% rename from src/alloy/backend/backend.h rename to src/xenia/cpu/backend/backend.h index ab7756252..268f48dfe 100644 --- a/src/alloy/backend/backend.h +++ b/src/xenia/cpu/backend/backend.h @@ -7,20 +7,23 @@ ****************************************************************************** */ -#ifndef ALLOY_BACKEND_BACKEND_H_ -#define ALLOY_BACKEND_BACKEND_H_ +#ifndef XENIA_BACKEND_BACKEND_H_ +#define XENIA_BACKEND_BACKEND_H_ #include -#include "alloy/backend/machine_info.h" +#include "xenia/cpu/backend/machine_info.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { class Runtime; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -namespace alloy { +namespace xe { +namespace cpu { namespace backend { class Assembler; @@ -46,6 +49,7 @@ class Backend { }; } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_BACKEND_BACKEND_H_ +#endif // XENIA_BACKEND_BACKEND_H_ diff --git a/src/alloy/backend/machine_info.h b/src/xenia/cpu/backend/machine_info.h similarity index 81% rename from src/alloy/backend/machine_info.h rename to src/xenia/cpu/backend/machine_info.h index 709156624..7734b2a48 100644 --- a/src/alloy/backend/machine_info.h +++ b/src/xenia/cpu/backend/machine_info.h @@ -7,12 +7,13 @@ ****************************************************************************** */ -#ifndef ALLOY_BACKEND_MACHINE_INFO_H_ -#define ALLOY_BACKEND_MACHINE_INFO_H_ +#ifndef XENIA_BACKEND_MACHINE_INFO_H_ +#define XENIA_BACKEND_MACHINE_INFO_H_ #include -namespace alloy { +namespace xe { +namespace cpu { namespace backend { struct MachineInfo { @@ -30,6 +31,7 @@ struct MachineInfo { }; } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_BACKEND_MACHINE_INFO_H_ +#endif // XENIA_BACKEND_MACHINE_INFO_H_ diff --git a/src/alloy/backend/sources.gypi b/src/xenia/cpu/backend/sources.gypi similarity index 100% rename from src/alloy/backend/sources.gypi rename to src/xenia/cpu/backend/sources.gypi diff --git a/src/alloy/backend/x64/sources.gypi b/src/xenia/cpu/backend/x64/sources.gypi similarity index 100% rename from src/alloy/backend/x64/sources.gypi rename to src/xenia/cpu/backend/x64/sources.gypi diff --git a/src/alloy/backend/x64/x64_assembler.cc b/src/xenia/cpu/backend/x64/x64_assembler.cc similarity index 85% rename from src/alloy/backend/x64/x64_assembler.cc rename to src/xenia/cpu/backend/x64/x64_assembler.cc index 145191dfb..252c4682d 100644 --- a/src/alloy/backend/x64/x64_assembler.cc +++ b/src/xenia/cpu/backend/x64/x64_assembler.cc @@ -7,14 +7,14 @@ ****************************************************************************** */ -#include "alloy/backend/x64/x64_assembler.h" +#include "xenia/cpu/backend/x64/x64_assembler.h" -#include "alloy/backend/x64/x64_backend.h" -#include "alloy/backend/x64/x64_emitter.h" -#include "alloy/backend/x64/x64_function.h" -#include "alloy/hir/hir_builder.h" -#include "alloy/hir/label.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/backend/x64/x64_backend.h" +#include "xenia/cpu/backend/x64/x64_emitter.h" +#include "xenia/cpu/backend/x64/x64_function.h" +#include "xenia/cpu/hir/hir_builder.h" +#include "xenia/cpu/hir/label.h" +#include "xenia/cpu/runtime/runtime.h" #include "poly/reset_scope.h" #include "xenia/profiling.h" @@ -22,17 +22,18 @@ namespace BE { #include } // namespace BE -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { // TODO(benvanik): remove when enums redefined. -using namespace alloy::runtime; +using namespace xe::cpu::runtime; -using alloy::hir::HIRBuilder; -using alloy::runtime::DebugInfo; -using alloy::runtime::Function; -using alloy::runtime::FunctionInfo; +using xe::cpu::hir::HIRBuilder; +using xe::cpu::runtime::DebugInfo; +using xe::cpu::runtime::Function; +using xe::cpu::runtime::FunctionInfo; X64Assembler::X64Assembler(X64Backend* backend) : Assembler(backend), x64_backend_(backend) {} @@ -64,7 +65,7 @@ int X64Assembler::Assemble(FunctionInfo* symbol_info, HIRBuilder* builder, uint32_t debug_info_flags, std::unique_ptr debug_info, uint32_t trace_flags, Function** out_function) { - SCOPE_profile_cpu_f("alloy"); + SCOPE_profile_cpu_f("cpu"); // Reset when we leave. poly::make_reset_scope(this); @@ -130,4 +131,5 @@ void X64Assembler::DumpMachineCode(DebugInfo* debug_info, void* machine_code, } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/backend/x64/x64_assembler.h b/src/xenia/cpu/backend/x64/x64_assembler.h similarity index 85% rename from src/alloy/backend/x64/x64_assembler.h rename to src/xenia/cpu/backend/x64/x64_assembler.h index fc94df4de..a3362e84e 100644 --- a/src/alloy/backend/x64/x64_assembler.h +++ b/src/xenia/cpu/backend/x64/x64_assembler.h @@ -7,15 +7,16 @@ ****************************************************************************** */ -#ifndef ALLOY_BACKEND_X64_X64_ASSEMBLER_H_ -#define ALLOY_BACKEND_X64_X64_ASSEMBLER_H_ +#ifndef XENIA_BACKEND_X64_X64_ASSEMBLER_H_ +#define XENIA_BACKEND_X64_X64_ASSEMBLER_H_ #include -#include "alloy/backend/assembler.h" +#include "xenia/cpu/backend/assembler.h" #include "poly/string_buffer.h" -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { @@ -51,6 +52,7 @@ class X64Assembler : public Assembler { } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_BACKEND_X64_X64_ASSEMBLER_H_ +#endif // XENIA_BACKEND_X64_X64_ASSEMBLER_H_ diff --git a/src/alloy/backend/x64/x64_backend.cc b/src/xenia/cpu/backend/x64/x64_backend.cc similarity index 83% rename from src/alloy/backend/x64/x64_backend.cc rename to src/xenia/cpu/backend/x64/x64_backend.cc index 892795e9c..4c0b2217b 100644 --- a/src/alloy/backend/x64/x64_backend.cc +++ b/src/xenia/cpu/backend/x64/x64_backend.cc @@ -7,18 +7,19 @@ ****************************************************************************** */ -#include "alloy/backend/x64/x64_backend.h" +#include "xenia/cpu/backend/x64/x64_backend.h" -#include "alloy/backend/x64/x64_assembler.h" -#include "alloy/backend/x64/x64_code_cache.h" -#include "alloy/backend/x64/x64_sequences.h" -#include "alloy/backend/x64/x64_thunk_emitter.h" +#include "xenia/cpu/backend/x64/x64_assembler.h" +#include "xenia/cpu/backend/x64/x64_code_cache.h" +#include "xenia/cpu/backend/x64/x64_sequences.h" +#include "xenia/cpu/backend/x64/x64_thunk_emitter.h" -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { -using alloy::runtime::Runtime; +using xe::cpu::runtime::Runtime; X64Backend::X64Backend(Runtime* runtime) : Backend(runtime), code_cache_(0) {} @@ -62,4 +63,5 @@ std::unique_ptr X64Backend::CreateAssembler() { } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/backend/x64/x64_backend.h b/src/xenia/cpu/backend/x64/x64_backend.h similarity index 82% rename from src/alloy/backend/x64/x64_backend.h rename to src/xenia/cpu/backend/x64/x64_backend.h index b6281ce2c..6eb0973d3 100644 --- a/src/alloy/backend/x64/x64_backend.h +++ b/src/xenia/cpu/backend/x64/x64_backend.h @@ -7,18 +7,19 @@ ****************************************************************************** */ -#ifndef ALLOY_BACKEND_X64_X64_BACKEND_H_ -#define ALLOY_BACKEND_X64_X64_BACKEND_H_ +#ifndef XENIA_BACKEND_X64_X64_BACKEND_H_ +#define XENIA_BACKEND_X64_X64_BACKEND_H_ -#include "alloy/backend/backend.h" +#include "xenia/cpu/backend/backend.h" -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { class X64CodeCache; -#define ALLOY_HAS_X64_BACKEND 1 +#define XENIA_HAS_X64_BACKEND 1 typedef void* (*HostToGuestThunk)(void* target, void* arg0, void* arg1); typedef void* (*GuestToHostThunk)(void* target, void* arg0, void* arg1); @@ -44,6 +45,7 @@ class X64Backend : public Backend { } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_BACKEND_X64_X64_BACKEND_H_ +#endif // XENIA_BACKEND_X64_X64_BACKEND_H_ diff --git a/src/alloy/backend/x64/x64_code_cache.h b/src/xenia/cpu/backend/x64/x64_code_cache.h similarity index 84% rename from src/alloy/backend/x64/x64_code_cache.h rename to src/xenia/cpu/backend/x64/x64_code_cache.h index 014fb8510..84feb6060 100644 --- a/src/alloy/backend/x64/x64_code_cache.h +++ b/src/xenia/cpu/backend/x64/x64_code_cache.h @@ -7,12 +7,13 @@ ****************************************************************************** */ -#ifndef ALLOY_BACKEND_X64_X64_CODE_CACHE_H_ -#define ALLOY_BACKEND_X64_X64_CODE_CACHE_H_ +#ifndef XENIA_BACKEND_X64_X64_CODE_CACHE_H_ +#define XENIA_BACKEND_X64_X64_CODE_CACHE_H_ #include -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { @@ -41,6 +42,7 @@ class X64CodeCache { } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_BACKEND_X64_X64_CODE_CACHE_H_ +#endif // XENIA_BACKEND_X64_X64_CODE_CACHE_H_ diff --git a/src/alloy/backend/x64/x64_code_cache_posix.cc b/src/xenia/cpu/backend/x64/x64_code_cache_posix.cc similarity index 92% rename from src/alloy/backend/x64/x64_code_cache_posix.cc rename to src/xenia/cpu/backend/x64/x64_code_cache_posix.cc index c32990cd6..8c2c92587 100644 --- a/src/alloy/backend/x64/x64_code_cache_posix.cc +++ b/src/xenia/cpu/backend/x64/x64_code_cache_posix.cc @@ -7,15 +7,15 @@ ****************************************************************************** */ -#include +#include "xenia/cpu/backend/x64/x64_code_cache.h" #include -#include -#include -#include +#include "poly/assert.h" +#include "poly/math.h" -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { @@ -49,8 +49,6 @@ int X64CodeCache::Initialize() { return 0; } void* X64CodeCache::PlaceCode(void* machine_code, size_t code_size, size_t stack_size) { - SCOPE_profile_cpu_f("alloy"); - // Always move the code to land on 16b alignment. We do this by rounding up // to 16b so that all offsets are aligned. code_size = poly::round_up(code_size, 16); @@ -96,4 +94,5 @@ X64CodeChunk::~X64CodeChunk() { } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/backend/x64/x64_code_cache_win.cc b/src/xenia/cpu/backend/x64/x64_code_cache_win.cc similarity index 98% rename from src/alloy/backend/x64/x64_code_cache_win.cc rename to src/xenia/cpu/backend/x64/x64_code_cache_win.cc index c8f336de8..ce04f5f86 100644 --- a/src/alloy/backend/x64/x64_code_cache_win.cc +++ b/src/xenia/cpu/backend/x64/x64_code_cache_win.cc @@ -7,12 +7,12 @@ ****************************************************************************** */ -#include "alloy/backend/x64/x64_code_cache.h" +#include "xenia/cpu/backend/x64/x64_code_cache.h" #include "poly/poly.h" -#include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { @@ -59,8 +59,6 @@ int X64CodeCache::Initialize() { return 0; } void* X64CodeCache::PlaceCode(void* machine_code, size_t code_size, size_t stack_size) { - SCOPE_profile_cpu_f("alloy"); - size_t alloc_size = code_size; // Add unwind info into the allocation size. Keep things 16b aligned. @@ -279,4 +277,5 @@ void X64CodeChunk::AddTableEntry(uint8_t* code, size_t code_size, } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/backend/x64/x64_emitter.cc b/src/xenia/cpu/backend/x64/x64_emitter.cc similarity index 97% rename from src/alloy/backend/x64/x64_emitter.cc rename to src/xenia/cpu/backend/x64/x64_emitter.cc index d96192d84..3aa47aa2e 100644 --- a/src/alloy/backend/x64/x64_emitter.cc +++ b/src/xenia/cpu/backend/x64/x64_emitter.cc @@ -7,42 +7,43 @@ ****************************************************************************** */ -#include "alloy/backend/x64/x64_emitter.h" +#include "xenia/cpu/backend/x64/x64_emitter.h" -#include "alloy/alloy-private.h" -#include "alloy/backend/x64/x64_backend.h" -#include "alloy/backend/x64/x64_code_cache.h" -#include "alloy/backend/x64/x64_function.h" -#include "alloy/backend/x64/x64_sequences.h" -#include "alloy/backend/x64/x64_thunk_emitter.h" -#include "alloy/hir/hir_builder.h" -#include "alloy/runtime/debug_info.h" -#include "alloy/runtime/runtime.h" -#include "alloy/runtime/symbol_info.h" -#include "alloy/runtime/thread_state.h" +#include "xenia/cpu/backend/x64/x64_backend.h" +#include "xenia/cpu/backend/x64/x64_code_cache.h" +#include "xenia/cpu/backend/x64/x64_function.h" +#include "xenia/cpu/backend/x64/x64_sequences.h" +#include "xenia/cpu/backend/x64/x64_thunk_emitter.h" +#include "xenia/cpu/cpu-private.h" +#include "xenia/cpu/hir/hir_builder.h" +#include "xenia/cpu/runtime/debug_info.h" +#include "xenia/cpu/runtime/runtime.h" +#include "xenia/cpu/runtime/symbol_info.h" +#include "xenia/cpu/runtime/thread_state.h" #include "poly/vec128.h" #include "xdb/protocol.h" #include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; -using namespace alloy::runtime; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; using poly::vec128b; using poly::vec128f; using poly::vec128i; using namespace Xbyak; -using alloy::hir::HIRBuilder; -using alloy::hir::Instr; -using alloy::runtime::Function; -using alloy::runtime::FunctionInfo; -using alloy::runtime::SourceMapEntry; -using alloy::runtime::ThreadState; +using xe::cpu::hir::HIRBuilder; +using xe::cpu::hir::Instr; +using xe::cpu::runtime::Function; +using xe::cpu::runtime::FunctionInfo; +using xe::cpu::runtime::SourceMapEntry; +using xe::cpu::runtime::ThreadState; static const size_t MAX_CODE_SIZE = 1 * 1024 * 1024; @@ -77,7 +78,7 @@ int X64Emitter::Initialize() { return 0; } int X64Emitter::Emit(HIRBuilder* builder, uint32_t debug_info_flags, runtime::DebugInfo* debug_info, uint32_t trace_flags, void*& out_code_address, size_t& out_code_size) { - SCOPE_profile_cpu_f("alloy"); + SCOPE_profile_cpu_f("cpu"); // Reset. if (debug_info_flags & DEBUG_INFO_SOURCE_MAP) { @@ -937,4 +938,5 @@ Address X64Emitter::StashXmm(int index, const Xmm& r) { } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/backend/x64/x64_emitter.h b/src/xenia/cpu/backend/x64/x64_emitter.h similarity index 94% rename from src/alloy/backend/x64/x64_emitter.h rename to src/xenia/cpu/backend/x64/x64_emitter.h index 1dd16d152..6d3d5dd9a 100644 --- a/src/alloy/backend/x64/x64_emitter.h +++ b/src/xenia/cpu/backend/x64/x64_emitter.h @@ -7,14 +7,15 @@ ****************************************************************************** */ -#ifndef ALLOY_BACKEND_X64_X64_EMITTER_H_ -#define ALLOY_BACKEND_X64_X64_EMITTER_H_ +#ifndef XENIA_BACKEND_X64_X64_EMITTER_H_ +#define XENIA_BACKEND_X64_X64_EMITTER_H_ -#include "alloy/hir/value.h" +#include "xenia/cpu/hir/value.h" #include "poly/arena.h" #include "third_party/xbyak/xbyak/xbyak.h" -namespace alloy { +namespace xe { +namespace cpu { namespace hir { class HIRBuilder; class Instr; @@ -25,9 +26,11 @@ class FunctionInfo; class Runtime; class SymbolInfo; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { @@ -208,6 +211,7 @@ class X64Emitter : public Xbyak::CodeGenerator { } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_BACKEND_X64_X64_EMITTER_H_ +#endif // XENIA_BACKEND_X64_X64_EMITTER_H_ diff --git a/src/alloy/backend/x64/x64_function.cc b/src/xenia/cpu/backend/x64/x64_function.cc similarity index 77% rename from src/alloy/backend/x64/x64_function.cc rename to src/xenia/cpu/backend/x64/x64_function.cc index 96468219d..689dd8a40 100644 --- a/src/alloy/backend/x64/x64_function.cc +++ b/src/xenia/cpu/backend/x64/x64_function.cc @@ -7,20 +7,21 @@ ****************************************************************************** */ -#include "alloy/backend/x64/x64_function.h" +#include "xenia/cpu/backend/x64/x64_function.h" -#include "alloy/backend/x64/x64_backend.h" -#include "alloy/runtime/runtime.h" -#include "alloy/runtime/thread_state.h" +#include "xenia/cpu/backend/x64/x64_backend.h" +#include "xenia/cpu/runtime/runtime.h" +#include "xenia/cpu/runtime/thread_state.h" -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { -using alloy::runtime::Breakpoint; -using alloy::runtime::Function; -using alloy::runtime::FunctionInfo; -using alloy::runtime::ThreadState; +using xe::cpu::runtime::Breakpoint; +using xe::cpu::runtime::Function; +using xe::cpu::runtime::FunctionInfo; +using xe::cpu::runtime::ThreadState; X64Function::X64Function(FunctionInfo* symbol_info) : Function(symbol_info), machine_code_(nullptr), code_size_(0) {} @@ -47,4 +48,5 @@ int X64Function::CallImpl(ThreadState* thread_state, uint64_t return_address) { } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/backend/x64/x64_function.h b/src/xenia/cpu/backend/x64/x64_function.h similarity index 80% rename from src/alloy/backend/x64/x64_function.h rename to src/xenia/cpu/backend/x64/x64_function.h index b78689364..d6692fc75 100644 --- a/src/alloy/backend/x64/x64_function.h +++ b/src/xenia/cpu/backend/x64/x64_function.h @@ -7,13 +7,14 @@ ****************************************************************************** */ -#ifndef ALLOY_BACKEND_X64_X64_FUNCTION_H_ -#define ALLOY_BACKEND_X64_X64_FUNCTION_H_ +#ifndef XENIA_BACKEND_X64_X64_FUNCTION_H_ +#define XENIA_BACKEND_X64_X64_FUNCTION_H_ -#include "alloy/runtime/function.h" -#include "alloy/runtime/symbol_info.h" +#include "xenia/cpu/runtime/function.h" +#include "xenia/cpu/runtime/symbol_info.h" -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { @@ -40,6 +41,7 @@ class X64Function : public runtime::Function { } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_BACKEND_X64_X64_FUNCTION_H_ +#endif // XENIA_BACKEND_X64_X64_FUNCTION_H_ diff --git a/src/alloy/backend/x64/x64_sequence.inl b/src/xenia/cpu/backend/x64/x64_sequence.inl similarity index 100% rename from src/alloy/backend/x64/x64_sequence.inl rename to src/xenia/cpu/backend/x64/x64_sequence.inl diff --git a/src/alloy/backend/x64/x64_sequences.cc b/src/xenia/cpu/backend/x64/x64_sequences.cc similarity index 99% rename from src/alloy/backend/x64/x64_sequences.cc rename to src/xenia/cpu/backend/x64/x64_sequences.cc index f213658be..e5297b910 100644 --- a/src/alloy/backend/x64/x64_sequences.cc +++ b/src/xenia/cpu/backend/x64/x64_sequences.cc @@ -8,7 +8,7 @@ */ // A note about vectors: -// Alloy represents vectors as xyzw pairs, with indices 0123. +// Xenia represents vectors as xyzw pairs, with indices 0123. // XMM registers are xyzw pairs with indices 3210, making them more like wzyx. // This makes things somewhat confusing. It'd be nice to just shuffle the // registers around on load/store, however certain operations require that @@ -22,22 +22,23 @@ // load into xmm register: // [0F 0E 0D 0C] [0B 0A 09 08] [07 06 05 04] [03 02 01 00] (w, z, y, x) -#include "alloy/backend/x64/x64_sequences.h" +#include "xenia/cpu/backend/x64/x64_sequences.h" -#include "alloy/backend/x64/x64_emitter.h" -#include "alloy/backend/x64/x64_tracers.h" -#include "alloy/hir/hir_builder.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/backend/x64/x64_emitter.h" +#include "xenia/cpu/backend/x64/x64_tracers.h" +#include "xenia/cpu/hir/hir_builder.h" +#include "xenia/cpu/runtime/runtime.h" -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { using namespace Xbyak; // TODO(benvanik): direct usings. -using namespace alloy::hir; -using namespace alloy::runtime; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; using poly::vec128b; @@ -45,7 +46,7 @@ typedef bool (*SequenceSelectFn)(X64Emitter&, const Instr*, const Instr**); std::unordered_multimap sequence_table; // Utilities/types used only in this file: -#include "alloy/backend/x64/x64_sequence.inl" +#include "xenia/cpu/backend/x64/x64_sequence.inl" // Selects the right byte/word/etc from a vector. We need to flip logical // indices (0,1,2,3,4,5,6,7,...) = (3,2,1,0,7,6,5,4,...) @@ -5882,4 +5883,5 @@ bool SelectSequence(X64Emitter& e, const Instr* i, const Instr** new_tail) { } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/backend/x64/x64_sequences.h b/src/xenia/cpu/backend/x64/x64_sequences.h similarity index 73% rename from src/alloy/backend/x64/x64_sequences.h rename to src/xenia/cpu/backend/x64/x64_sequences.h index 2e77112fa..fa50fedf5 100644 --- a/src/alloy/backend/x64/x64_sequences.h +++ b/src/xenia/cpu/backend/x64/x64_sequences.h @@ -7,16 +7,19 @@ ****************************************************************************** */ -#ifndef ALLOY_BACKEND_X64_X64_SEQUENCES_H_ -#define ALLOY_BACKEND_X64_X64_SEQUENCES_H_ +#ifndef XENIA_BACKEND_X64_X64_SEQUENCES_H_ +#define XENIA_BACKEND_X64_X64_SEQUENCES_H_ -namespace alloy { +namespace xe { +namespace cpu { namespace hir { class Instr; } // namespace hir -} // namespace alloy +} // namespace cpu +} // namespace xe -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { @@ -28,6 +31,7 @@ bool SelectSequence(X64Emitter& e, const hir::Instr* i, } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_BACKEND_X64_X64_SEQUENCES_H_ +#endif // XENIA_BACKEND_X64_X64_SEQUENCES_H_ diff --git a/src/alloy/backend/x64/x64_thunk_emitter.cc b/src/xenia/cpu/backend/x64/x64_thunk_emitter.cc similarity index 96% rename from src/alloy/backend/x64/x64_thunk_emitter.cc rename to src/xenia/cpu/backend/x64/x64_thunk_emitter.cc index 054e41c02..55ab32506 100644 --- a/src/alloy/backend/x64/x64_thunk_emitter.cc +++ b/src/xenia/cpu/backend/x64/x64_thunk_emitter.cc @@ -7,11 +7,12 @@ ****************************************************************************** */ -#include "alloy/backend/x64/x64_thunk_emitter.h" +#include "xenia/cpu/backend/x64/x64_thunk_emitter.h" #include "third_party/xbyak/xbyak/xbyak.h" -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { @@ -142,4 +143,5 @@ GuestToHostThunk X64ThunkEmitter::EmitGuestToHostThunk() { } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/backend/x64/x64_thunk_emitter.h b/src/xenia/cpu/backend/x64/x64_thunk_emitter.h similarity index 92% rename from src/alloy/backend/x64/x64_thunk_emitter.h rename to src/xenia/cpu/backend/x64/x64_thunk_emitter.h index e8a0d4903..9b792575c 100644 --- a/src/alloy/backend/x64/x64_thunk_emitter.h +++ b/src/xenia/cpu/backend/x64/x64_thunk_emitter.h @@ -7,13 +7,14 @@ ****************************************************************************** */ -#ifndef ALLOY_BACKEND_X64_X64_THUNK_EMITTER_H_ -#define ALLOY_BACKEND_X64_X64_THUNK_EMITTER_H_ +#ifndef XENIA_BACKEND_X64_X64_THUNK_EMITTER_H_ +#define XENIA_BACKEND_X64_X64_THUNK_EMITTER_H_ -#include "alloy/backend/x64/x64_backend.h" -#include "alloy/backend/x64/x64_emitter.h" +#include "xenia/cpu/backend/x64/x64_backend.h" +#include "xenia/cpu/backend/x64/x64_emitter.h" -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { @@ -136,6 +137,7 @@ class X64ThunkEmitter : public X64Emitter { } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_BACKEND_X64_X64_THUNK_EMITTER_H_ +#endif // XENIA_BACKEND_X64_X64_THUNK_EMITTER_H_ diff --git a/src/alloy/backend/x64/x64_tracers.cc b/src/xenia/cpu/backend/x64/x64_tracers.cc similarity index 96% rename from src/alloy/backend/x64/x64_tracers.cc rename to src/xenia/cpu/backend/x64/x64_tracers.cc index aa51892fe..059d5d65f 100644 --- a/src/alloy/backend/x64/x64_tracers.cc +++ b/src/xenia/cpu/backend/x64/x64_tracers.cc @@ -7,17 +7,18 @@ ****************************************************************************** */ -#include "alloy/backend/x64/x64_tracers.h" +#include "xenia/cpu/backend/x64/x64_tracers.h" -#include "alloy/backend/x64/x64_emitter.h" -#include "alloy/runtime/runtime.h" -#include "alloy/runtime/thread_state.h" +#include "xenia/cpu/backend/x64/x64_emitter.h" +#include "xenia/cpu/runtime/runtime.h" +#include "xenia/cpu/runtime/thread_state.h" -using namespace alloy; -using namespace alloy::backend::x64; -using namespace alloy::runtime; +using namespace xe; +using namespace xe::cpu::backend::x64; +using namespace xe::cpu::runtime; -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { @@ -197,4 +198,5 @@ void TraceMemoryStoreV128(void* raw_context, uint32_t address, __m128 value) { } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/backend/x64/x64_tracers.h b/src/xenia/cpu/backend/x64/x64_tracers.h similarity index 94% rename from src/alloy/backend/x64/x64_tracers.h rename to src/xenia/cpu/backend/x64/x64_tracers.h index 8015f8a69..1642f7920 100644 --- a/src/alloy/backend/x64/x64_tracers.h +++ b/src/xenia/cpu/backend/x64/x64_tracers.h @@ -7,13 +7,14 @@ ****************************************************************************** */ -#ifndef ALLOY_BACKEND_X64_X64_TRACERS_H_ -#define ALLOY_BACKEND_X64_X64_TRACERS_H_ +#ifndef XENIA_BACKEND_X64_X64_TRACERS_H_ +#define XENIA_BACKEND_X64_X64_TRACERS_H_ #include #include -namespace alloy { +namespace xe { +namespace cpu { namespace backend { namespace x64 { class X64Emitter; @@ -65,6 +66,7 @@ void TraceMemoryStoreV128(void* raw_context, uint32_t address, __m128 value); } // namespace x64 } // namespace backend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_BACKEND_X64_X64_TRACERS_H_ +#endif // XENIA_BACKEND_X64_X64_TRACERS_H_ diff --git a/src/alloy/compiler/compiler.cc b/src/xenia/cpu/compiler/compiler.cc similarity index 84% rename from src/alloy/compiler/compiler.cc rename to src/xenia/cpu/compiler/compiler.cc index fc03d8de4..2308de4a8 100644 --- a/src/alloy/compiler/compiler.cc +++ b/src/xenia/cpu/compiler/compiler.cc @@ -7,16 +7,17 @@ ****************************************************************************** */ -#include "alloy/compiler/compiler.h" +#include "xenia/cpu/compiler/compiler.h" -#include "alloy/compiler/compiler_pass.h" +#include "xenia/cpu/compiler/compiler_pass.h" #include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { -using alloy::hir::HIRBuilder; -using alloy::runtime::Runtime; +using xe::cpu::hir::HIRBuilder; +using xe::cpu::runtime::Runtime; Compiler::Compiler(Runtime* runtime) : runtime_(runtime) {} @@ -30,8 +31,6 @@ void Compiler::AddPass(std::unique_ptr pass) { void Compiler::Reset() {} int Compiler::Compile(HIRBuilder* builder) { - SCOPE_profile_cpu_f("alloy"); - // TODO(benvanik): sophisticated stuff. Run passes in parallel, run until they // stop changing things, etc. for (size_t i = 0; i < passes_.size(); ++i) { @@ -46,4 +45,5 @@ int Compiler::Compile(HIRBuilder* builder) { } } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/compiler/compiler.h b/src/xenia/cpu/compiler/compiler.h similarity index 79% rename from src/alloy/compiler/compiler.h rename to src/xenia/cpu/compiler/compiler.h index b0f2d2367..e7973a00f 100644 --- a/src/alloy/compiler/compiler.h +++ b/src/xenia/cpu/compiler/compiler.h @@ -7,22 +7,25 @@ ****************************************************************************** */ -#ifndef ALLOY_COMPILER_COMPILER_H_ -#define ALLOY_COMPILER_COMPILER_H_ +#ifndef XENIA_COMPILER_COMPILER_H_ +#define XENIA_COMPILER_COMPILER_H_ #include #include -#include "alloy/hir/hir_builder.h" +#include "xenia/cpu/hir/hir_builder.h" #include "poly/arena.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { class Runtime; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { class CompilerPass; @@ -49,6 +52,7 @@ class Compiler { }; } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_COMPILER_COMPILER_H_ +#endif // XENIA_COMPILER_COMPILER_H_ diff --git a/src/alloy/compiler/compiler_pass.cc b/src/xenia/cpu/compiler/compiler_pass.cc similarity index 84% rename from src/alloy/compiler/compiler_pass.cc rename to src/xenia/cpu/compiler/compiler_pass.cc index c616129f2..ec80973d4 100644 --- a/src/alloy/compiler/compiler_pass.cc +++ b/src/xenia/cpu/compiler/compiler_pass.cc @@ -7,11 +7,12 @@ ****************************************************************************** */ -#include "alloy/compiler/compiler_pass.h" +#include "xenia/cpu/compiler/compiler_pass.h" -#include "alloy/compiler/compiler.h" +#include "xenia/cpu/compiler/compiler.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { CompilerPass::CompilerPass() : runtime_(0), compiler_(0) {} @@ -29,4 +30,5 @@ poly::Arena* CompilerPass::scratch_arena() const { } } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/compiler/compiler_pass.h b/src/xenia/cpu/compiler/compiler_pass.h similarity index 75% rename from src/alloy/compiler/compiler_pass.h rename to src/xenia/cpu/compiler/compiler_pass.h index a3ff2a11e..975cc9595 100644 --- a/src/alloy/compiler/compiler_pass.h +++ b/src/xenia/cpu/compiler/compiler_pass.h @@ -7,19 +7,22 @@ ****************************************************************************** */ -#ifndef ALLOY_COMPILER_COMPILER_PASS_H_ -#define ALLOY_COMPILER_COMPILER_PASS_H_ +#ifndef XENIA_COMPILER_COMPILER_PASS_H_ +#define XENIA_COMPILER_COMPILER_PASS_H_ -#include "alloy/hir/hir_builder.h" +#include "xenia/cpu/hir/hir_builder.h" #include "poly/arena.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { class Runtime; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { class Compiler; @@ -42,6 +45,7 @@ class CompilerPass { }; } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_COMPILER_COMPILER_PASS_H_ +#endif // XENIA_COMPILER_COMPILER_PASS_H_ diff --git a/src/alloy/compiler/compiler_passes.h b/src/xenia/cpu/compiler/compiler_passes.h similarity index 86% rename from src/alloy/compiler/compiler_passes.h rename to src/xenia/cpu/compiler/compiler_passes.h index 83cd1b924..dfd714bf7 100644 --- a/src/alloy/compiler/compiler_passes.h +++ b/src/xenia/cpu/compiler/compiler_passes.h @@ -7,21 +7,21 @@ ****************************************************************************** */ -#ifndef ALLOY_COMPILER_COMPILER_PASSES_H_ -#define ALLOY_COMPILER_COMPILER_PASSES_H_ +#ifndef XENIA_COMPILER_COMPILER_PASSES_H_ +#define XENIA_COMPILER_COMPILER_PASSES_H_ -#include "alloy/compiler/passes/constant_propagation_pass.h" -#include "alloy/compiler/passes/context_promotion_pass.h" -#include "alloy/compiler/passes/control_flow_analysis_pass.h" -#include "alloy/compiler/passes/control_flow_simplification_pass.h" -#include "alloy/compiler/passes/data_flow_analysis_pass.h" -#include "alloy/compiler/passes/dead_code_elimination_pass.h" -//#include "alloy/compiler/passes/dead_store_elimination_pass.h" -#include "alloy/compiler/passes/finalization_pass.h" -#include "alloy/compiler/passes/register_allocation_pass.h" -#include "alloy/compiler/passes/simplification_pass.h" -#include "alloy/compiler/passes/validation_pass.h" -#include "alloy/compiler/passes/value_reduction_pass.h" +#include "xenia/cpu/compiler/passes/constant_propagation_pass.h" +#include "xenia/cpu/compiler/passes/context_promotion_pass.h" +#include "xenia/cpu/compiler/passes/control_flow_analysis_pass.h" +#include "xenia/cpu/compiler/passes/control_flow_simplification_pass.h" +#include "xenia/cpu/compiler/passes/data_flow_analysis_pass.h" +#include "xenia/cpu/compiler/passes/dead_code_elimination_pass.h" +//#include "xenia/cpu/compiler/passes/dead_store_elimination_pass.h" +#include "xenia/cpu/compiler/passes/finalization_pass.h" +#include "xenia/cpu/compiler/passes/register_allocation_pass.h" +#include "xenia/cpu/compiler/passes/simplification_pass.h" +#include "xenia/cpu/compiler/passes/validation_pass.h" +#include "xenia/cpu/compiler/passes/value_reduction_pass.h" // TODO: // - mark_use/mark_set @@ -176,4 +176,4 @@ // reg0 = load_local +123 <-- load inserted // reg0 = mul reg0, reg1 -#endif // ALLOY_COMPILER_COMPILER_PASSES_H_ +#endif // XENIA_COMPILER_COMPILER_PASSES_H_ diff --git a/src/alloy/compiler/passes/constant_propagation_pass.cc b/src/xenia/cpu/compiler/passes/constant_propagation_pass.cc similarity index 97% rename from src/alloy/compiler/passes/constant_propagation_pass.cc rename to src/xenia/cpu/compiler/passes/constant_propagation_pass.cc index 29d1b1451..16f4e3b85 100644 --- a/src/alloy/compiler/passes/constant_propagation_pass.cc +++ b/src/xenia/cpu/compiler/passes/constant_propagation_pass.cc @@ -7,30 +7,29 @@ ****************************************************************************** */ -#include "alloy/compiler/passes/constant_propagation_pass.h" +#include "xenia/cpu/compiler/passes/constant_propagation_pass.h" -#include "alloy/runtime/function.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/runtime/function.h" +#include "xenia/cpu/runtime/runtime.h" #include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::hir::HIRBuilder; -using alloy::hir::TypeName; -using alloy::hir::Value; +using xe::cpu::hir::HIRBuilder; +using xe::cpu::hir::TypeName; +using xe::cpu::hir::Value; ConstantPropagationPass::ConstantPropagationPass() : CompilerPass() {} ConstantPropagationPass::~ConstantPropagationPass() {} int ConstantPropagationPass::Run(HIRBuilder* builder) { - SCOPE_profile_cpu_f("alloy"); - // Once ContextPromotion has run there will likely be a whole slew of // constants that can be pushed through the function. // Example: @@ -302,7 +301,8 @@ int ConstantPropagationPass::Run(HIRBuilder* builder) { break; // TODO(benvanik): ADD_CARRY (w/ ARITHMETIC_SET_CARRY) case OPCODE_ADD_CARRY: - if (i->src1.value->IsConstantZero() && i->src2.value->IsConstantZero()) { + if (i->src1.value->IsConstantZero() && + i->src2.value->IsConstantZero()) { Value* ca = i->src3.value; // If carry is set find the DID_CARRY and fix it. if (!!(i->flags & ARITHMETIC_SET_CARRY)) { @@ -485,4 +485,5 @@ void ConstantPropagationPass::PropagateCarry(Value* v, bool did_carry) { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/compiler/passes/constant_propagation_pass.h b/src/xenia/cpu/compiler/passes/constant_propagation_pass.h similarity index 73% rename from src/alloy/compiler/passes/constant_propagation_pass.h rename to src/xenia/cpu/compiler/passes/constant_propagation_pass.h index 7f5d4da96..bd8926a1f 100644 --- a/src/alloy/compiler/passes/constant_propagation_pass.h +++ b/src/xenia/cpu/compiler/passes/constant_propagation_pass.h @@ -7,12 +7,13 @@ ****************************************************************************** */ -#ifndef ALLOY_COMPILER_PASSES_CONSTANT_PROPAGATION_PASS_H_ -#define ALLOY_COMPILER_PASSES_CONSTANT_PROPAGATION_PASS_H_ +#ifndef XENIA_COMPILER_PASSES_CONSTANT_PROPAGATION_PASS_H_ +#define XENIA_COMPILER_PASSES_CONSTANT_PROPAGATION_PASS_H_ -#include "alloy/compiler/compiler_pass.h" +#include "xenia/cpu/compiler/compiler_pass.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { @@ -29,6 +30,7 @@ class ConstantPropagationPass : public CompilerPass { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_COMPILER_PASSES_CONSTANT_PROPAGATION_PASS_H_ +#endif // XENIA_COMPILER_PASSES_CONSTANT_PROPAGATION_PASS_H_ diff --git a/src/alloy/compiler/passes/context_promotion_pass.cc b/src/xenia/cpu/compiler/passes/context_promotion_pass.cc similarity index 91% rename from src/alloy/compiler/passes/context_promotion_pass.cc rename to src/xenia/cpu/compiler/passes/context_promotion_pass.cc index 6b630b7ca..a675da8d7 100644 --- a/src/alloy/compiler/passes/context_promotion_pass.cc +++ b/src/xenia/cpu/compiler/passes/context_promotion_pass.cc @@ -7,29 +7,30 @@ ****************************************************************************** */ -#include "alloy/compiler/passes/context_promotion_pass.h" +#include "xenia/cpu/compiler/passes/context_promotion_pass.h" #include -#include "alloy/compiler/compiler.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/compiler/compiler.h" +#include "xenia/cpu/runtime/runtime.h" #include "xenia/profiling.h" DEFINE_bool(store_all_context_values, false, "Don't strip dead context stores to aid in debugging."); -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::frontend::ContextInfo; -using alloy::hir::Block; -using alloy::hir::HIRBuilder; -using alloy::hir::Instr; -using alloy::hir::Value; +using xe::cpu::frontend::ContextInfo; +using xe::cpu::hir::Block; +using xe::cpu::hir::HIRBuilder; +using xe::cpu::hir::Instr; +using xe::cpu::hir::Value; ContextPromotionPass::ContextPromotionPass() : CompilerPass() {} @@ -49,8 +50,6 @@ int ContextPromotionPass::Initialize(Compiler* compiler) { } int ContextPromotionPass::Run(HIRBuilder* builder) { - SCOPE_profile_cpu_f("alloy"); - // Like mem2reg, but because context memory is unaliasable it's easier to // check and convert LoadContext/StoreContext into value operations. // Example of load->value promotion: @@ -147,4 +146,5 @@ void ContextPromotionPass::RemoveDeadStoresBlock(Block* block) { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/compiler/passes/context_promotion_pass.h b/src/xenia/cpu/compiler/passes/context_promotion_pass.h similarity index 81% rename from src/alloy/compiler/passes/context_promotion_pass.h rename to src/xenia/cpu/compiler/passes/context_promotion_pass.h index 07b192598..875da9464 100644 --- a/src/alloy/compiler/passes/context_promotion_pass.h +++ b/src/xenia/cpu/compiler/passes/context_promotion_pass.h @@ -7,10 +7,10 @@ ****************************************************************************** */ -#ifndef ALLOY_COMPILER_PASSES_CONTEXT_PROMOTION_PASS_H_ -#define ALLOY_COMPILER_PASSES_CONTEXT_PROMOTION_PASS_H_ +#ifndef XENIA_COMPILER_PASSES_CONTEXT_PROMOTION_PASS_H_ +#define XENIA_COMPILER_PASSES_CONTEXT_PROMOTION_PASS_H_ -#include "alloy/compiler/compiler_pass.h" +#include "xenia/cpu/compiler/compiler_pass.h" #if XE_COMPILER_MSVC #pragma warning(push) @@ -23,7 +23,8 @@ #include #endif // XE_COMPILER_MSVC -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { @@ -47,6 +48,7 @@ class ContextPromotionPass : public CompilerPass { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_COMPILER_PASSES_CONTEXT_PROMOTION_PASS_H_ +#endif // XENIA_COMPILER_PASSES_CONTEXT_PROMOTION_PASS_H_ diff --git a/src/alloy/compiler/passes/control_flow_analysis_pass.cc b/src/xenia/cpu/compiler/passes/control_flow_analysis_pass.cc similarity index 85% rename from src/alloy/compiler/passes/control_flow_analysis_pass.cc rename to src/xenia/cpu/compiler/passes/control_flow_analysis_pass.cc index 3fd72c49b..335498883 100644 --- a/src/alloy/compiler/passes/control_flow_analysis_pass.cc +++ b/src/xenia/cpu/compiler/passes/control_flow_analysis_pass.cc @@ -7,30 +7,29 @@ ****************************************************************************** */ -#include "alloy/compiler/passes/control_flow_analysis_pass.h" +#include "xenia/cpu/compiler/passes/control_flow_analysis_pass.h" -#include "alloy/backend/backend.h" -#include "alloy/compiler/compiler.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/backend/backend.h" +#include "xenia/cpu/compiler/compiler.h" +#include "xenia/cpu/runtime/runtime.h" #include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::hir::Edge; -using alloy::hir::HIRBuilder; +using xe::cpu::hir::Edge; +using xe::cpu::hir::HIRBuilder; ControlFlowAnalysisPass::ControlFlowAnalysisPass() : CompilerPass() {} ControlFlowAnalysisPass::~ControlFlowAnalysisPass() {} int ControlFlowAnalysisPass::Run(HIRBuilder* builder) { - SCOPE_profile_cpu_f("alloy"); - // Reset edges for all blocks. Needed to be re-runnable. // Note that this wastes a bunch of arena memory, so we shouldn't // re-run too often. @@ -77,4 +76,5 @@ int ControlFlowAnalysisPass::Run(HIRBuilder* builder) { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/compiler/passes/control_flow_analysis_pass.h b/src/xenia/cpu/compiler/passes/control_flow_analysis_pass.h similarity index 72% rename from src/alloy/compiler/passes/control_flow_analysis_pass.h rename to src/xenia/cpu/compiler/passes/control_flow_analysis_pass.h index 7354f0be5..1f51c80e0 100644 --- a/src/alloy/compiler/passes/control_flow_analysis_pass.h +++ b/src/xenia/cpu/compiler/passes/control_flow_analysis_pass.h @@ -7,12 +7,13 @@ ****************************************************************************** */ -#ifndef ALLOY_COMPILER_PASSES_CONTROL_FLOW_ANALYSIS_PASS_H_ -#define ALLOY_COMPILER_PASSES_CONTROL_FLOW_ANALYSIS_PASS_H_ +#ifndef XENIA_COMPILER_PASSES_CONTROL_FLOW_ANALYSIS_PASS_H_ +#define XENIA_COMPILER_PASSES_CONTROL_FLOW_ANALYSIS_PASS_H_ -#include "alloy/compiler/compiler_pass.h" +#include "xenia/cpu/compiler/compiler_pass.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { @@ -28,6 +29,7 @@ class ControlFlowAnalysisPass : public CompilerPass { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_COMPILER_PASSES_CONTROL_FLOW_ANALYSIS_PASS_H_ +#endif // XENIA_COMPILER_PASSES_CONTROL_FLOW_ANALYSIS_PASS_H_ diff --git a/src/alloy/compiler/passes/control_flow_simplification_pass.cc b/src/xenia/cpu/compiler/passes/control_flow_simplification_pass.cc similarity index 83% rename from src/alloy/compiler/passes/control_flow_simplification_pass.cc rename to src/xenia/cpu/compiler/passes/control_flow_simplification_pass.cc index 89764b456..2a4520dd4 100644 --- a/src/alloy/compiler/passes/control_flow_simplification_pass.cc +++ b/src/xenia/cpu/compiler/passes/control_flow_simplification_pass.cc @@ -7,22 +7,23 @@ ****************************************************************************** */ -#include "alloy/compiler/passes/control_flow_simplification_pass.h" +#include "xenia/cpu/compiler/passes/control_flow_simplification_pass.h" -#include "alloy/backend/backend.h" -#include "alloy/compiler/compiler.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/backend/backend.h" +#include "xenia/cpu/compiler/compiler.h" +#include "xenia/cpu/runtime/runtime.h" #include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::hir::Edge; -using alloy::hir::HIRBuilder; +using xe::cpu::hir::Edge; +using xe::cpu::hir::HIRBuilder; ControlFlowSimplificationPass::ControlFlowSimplificationPass() : CompilerPass() {} @@ -30,8 +31,6 @@ ControlFlowSimplificationPass::ControlFlowSimplificationPass() ControlFlowSimplificationPass::~ControlFlowSimplificationPass() {} int ControlFlowSimplificationPass::Run(HIRBuilder* builder) { - SCOPE_profile_cpu_f("alloy"); - // Walk backwards and merge blocks if possible. bool merged_any = false; auto block = builder->last_block(); @@ -58,4 +57,5 @@ int ControlFlowSimplificationPass::Run(HIRBuilder* builder) { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/compiler/passes/control_flow_simplification_pass.h b/src/xenia/cpu/compiler/passes/control_flow_simplification_pass.h similarity index 72% rename from src/alloy/compiler/passes/control_flow_simplification_pass.h rename to src/xenia/cpu/compiler/passes/control_flow_simplification_pass.h index 4c79ac57d..204803f23 100644 --- a/src/alloy/compiler/passes/control_flow_simplification_pass.h +++ b/src/xenia/cpu/compiler/passes/control_flow_simplification_pass.h @@ -7,12 +7,13 @@ ****************************************************************************** */ -#ifndef ALLOY_COMPILER_PASSES_CONTROL_FLOW_SIMPLIFICATION_PASS_H_ -#define ALLOY_COMPILER_PASSES_CONTROL_FLOW_SIMPLIFICATION_PASS_H_ +#ifndef XENIA_COMPILER_PASSES_CONTROL_FLOW_SIMPLIFICATION_PASS_H_ +#define XENIA_COMPILER_PASSES_CONTROL_FLOW_SIMPLIFICATION_PASS_H_ -#include "alloy/compiler/compiler_pass.h" +#include "xenia/cpu/compiler/compiler_pass.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { @@ -28,6 +29,7 @@ class ControlFlowSimplificationPass : public CompilerPass { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_COMPILER_PASSES_CONTROL_FLOW_SIMPLIFICATION_PASS_H_ +#endif // XENIA_COMPILER_PASSES_CONTROL_FLOW_SIMPLIFICATION_PASS_H_ diff --git a/src/alloy/compiler/passes/data_flow_analysis_pass.cc b/src/xenia/cpu/compiler/passes/data_flow_analysis_pass.cc similarity index 92% rename from src/alloy/compiler/passes/data_flow_analysis_pass.cc rename to src/xenia/cpu/compiler/passes/data_flow_analysis_pass.cc index 8decd65f8..63f5d7f6d 100644 --- a/src/alloy/compiler/passes/data_flow_analysis_pass.cc +++ b/src/xenia/cpu/compiler/passes/data_flow_analysis_pass.cc @@ -7,11 +7,11 @@ ****************************************************************************** */ -#include "alloy/compiler/passes/data_flow_analysis_pass.h" +#include "xenia/cpu/compiler/passes/data_flow_analysis_pass.h" -#include "alloy/backend/backend.h" -#include "alloy/compiler/compiler.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/backend/backend.h" +#include "xenia/cpu/compiler/compiler.h" +#include "xenia/cpu/runtime/runtime.h" #include "xenia/profiling.h" #if XE_COMPILER_MSVC @@ -24,24 +24,23 @@ #include #endif // XE_COMPILER_MSVC -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::hir::HIRBuilder; -using alloy::hir::OpcodeSignatureType; -using alloy::hir::Value; +using xe::cpu::hir::HIRBuilder; +using xe::cpu::hir::OpcodeSignatureType; +using xe::cpu::hir::Value; DataFlowAnalysisPass::DataFlowAnalysisPass() : CompilerPass() {} DataFlowAnalysisPass::~DataFlowAnalysisPass() {} int DataFlowAnalysisPass::Run(HIRBuilder* builder) { - SCOPE_profile_cpu_f("alloy"); - // Linearize blocks so that we can detect cycles and propagate dependencies. uint32_t block_count = LinearizeBlocks(builder); @@ -94,10 +93,10 @@ void DataFlowAnalysisPass::AnalyzeFlow(HIRBuilder* builder, auto instr = block->instr_head; while (instr) { uint32_t signature = instr->opcode->signature; -#define SET_INCOMING_VALUE(v) \ - if (v->def && v->def->block != block) { \ - incoming_values.set(v->ordinal); \ - } \ +#define SET_INCOMING_VALUE(v) \ + if (v->def && v->def->block != block) { \ + incoming_values.set(v->ordinal); \ + } \ assert_true(v->ordinal < max_value_estimate); \ value_map[v->ordinal] = v; if (GET_OPCODE_SIG_TYPE_SRC1(signature) == OPCODE_SIG_TYPE_V) { @@ -208,4 +207,5 @@ void DataFlowAnalysisPass::AnalyzeFlow(HIRBuilder* builder, } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/compiler/passes/data_flow_analysis_pass.h b/src/xenia/cpu/compiler/passes/data_flow_analysis_pass.h similarity index 73% rename from src/alloy/compiler/passes/data_flow_analysis_pass.h rename to src/xenia/cpu/compiler/passes/data_flow_analysis_pass.h index 41ce04952..45cac7f92 100644 --- a/src/alloy/compiler/passes/data_flow_analysis_pass.h +++ b/src/xenia/cpu/compiler/passes/data_flow_analysis_pass.h @@ -7,33 +7,31 @@ ****************************************************************************** */ -#ifndef ALLOY_COMPILER_PASSES_DATA_FLOW_ANALYSIS_PASS_H_ -#define ALLOY_COMPILER_PASSES_DATA_FLOW_ANALYSIS_PASS_H_ +#ifndef XENIA_COMPILER_PASSES_DATA_FLOW_ANALYSIS_PASS_H_ +#define XENIA_COMPILER_PASSES_DATA_FLOW_ANALYSIS_PASS_H_ -#include "alloy/compiler/compiler_pass.h" +#include "xenia/cpu/compiler/compiler_pass.h" - -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { - class DataFlowAnalysisPass : public CompilerPass { -public: + public: DataFlowAnalysisPass(); ~DataFlowAnalysisPass() override; int Run(hir::HIRBuilder* builder) override; -private: + private: uint32_t LinearizeBlocks(hir::HIRBuilder* builder); void AnalyzeFlow(hir::HIRBuilder* builder, uint32_t block_count); }; - } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe - -#endif // ALLOY_COMPILER_PASSES_DATA_FLOW_ANALYSIS_PASS_H_ +#endif // XENIA_COMPILER_PASSES_DATA_FLOW_ANALYSIS_PASS_H_ diff --git a/src/alloy/compiler/passes/dead_code_elimination_pass.cc b/src/xenia/cpu/compiler/passes/dead_code_elimination_pass.cc similarity index 96% rename from src/alloy/compiler/passes/dead_code_elimination_pass.cc rename to src/xenia/cpu/compiler/passes/dead_code_elimination_pass.cc index 3d36ce411..c480e0e8e 100644 --- a/src/alloy/compiler/passes/dead_code_elimination_pass.cc +++ b/src/xenia/cpu/compiler/passes/dead_code_elimination_pass.cc @@ -7,28 +7,27 @@ ****************************************************************************** */ -#include "alloy/compiler/passes/dead_code_elimination_pass.h" +#include "xenia/cpu/compiler/passes/dead_code_elimination_pass.h" #include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::hir::HIRBuilder; -using alloy::hir::Instr; -using alloy::hir::Value; +using xe::cpu::hir::HIRBuilder; +using xe::cpu::hir::Instr; +using xe::cpu::hir::Value; DeadCodeEliminationPass::DeadCodeEliminationPass() : CompilerPass() {} DeadCodeEliminationPass::~DeadCodeEliminationPass() {} int DeadCodeEliminationPass::Run(HIRBuilder* builder) { - SCOPE_profile_cpu_f("alloy"); - // ContextPromotion/DSE will likely leave around a lot of dead statements. // Code generated for comparison/testing produces many unused statements and // with proper use analysis it should be possible to remove most of them: @@ -215,4 +214,5 @@ bool DeadCodeEliminationPass::CheckLocalUse(Instr* i) { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/compiler/passes/dead_code_elimination_pass.h b/src/xenia/cpu/compiler/passes/dead_code_elimination_pass.h similarity index 73% rename from src/alloy/compiler/passes/dead_code_elimination_pass.h rename to src/xenia/cpu/compiler/passes/dead_code_elimination_pass.h index 3350fb573..945ca56e7 100644 --- a/src/alloy/compiler/passes/dead_code_elimination_pass.h +++ b/src/xenia/cpu/compiler/passes/dead_code_elimination_pass.h @@ -7,34 +7,32 @@ ****************************************************************************** */ -#ifndef ALLOY_COMPILER_PASSES_DEAD_CODE_ELIMINATION_PASS_H_ -#define ALLOY_COMPILER_PASSES_DEAD_CODE_ELIMINATION_PASS_H_ +#ifndef XENIA_COMPILER_PASSES_DEAD_CODE_ELIMINATION_PASS_H_ +#define XENIA_COMPILER_PASSES_DEAD_CODE_ELIMINATION_PASS_H_ -#include "alloy/compiler/compiler_pass.h" +#include "xenia/cpu/compiler/compiler_pass.h" - -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { - class DeadCodeEliminationPass : public CompilerPass { -public: + public: DeadCodeEliminationPass(); ~DeadCodeEliminationPass() override; int Run(hir::HIRBuilder* builder) override; -private: + private: void MakeNopRecursive(hir::Instr* i); void ReplaceAssignment(hir::Instr* i); bool CheckLocalUse(hir::Instr* i); }; - } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe - -#endif // ALLOY_COMPILER_PASSES_DEAD_CODE_ELIMINATION_PASS_H_ +#endif // XENIA_COMPILER_PASSES_DEAD_CODE_ELIMINATION_PASS_H_ diff --git a/src/alloy/compiler/passes/finalization_pass.cc b/src/xenia/cpu/compiler/passes/finalization_pass.cc similarity index 85% rename from src/alloy/compiler/passes/finalization_pass.cc rename to src/xenia/cpu/compiler/passes/finalization_pass.cc index 0c3b96392..e585089bb 100644 --- a/src/alloy/compiler/passes/finalization_pass.cc +++ b/src/xenia/cpu/compiler/passes/finalization_pass.cc @@ -7,29 +7,28 @@ ****************************************************************************** */ -#include "alloy/compiler/passes/finalization_pass.h" +#include "xenia/cpu/compiler/passes/finalization_pass.h" -#include "alloy/backend/backend.h" -#include "alloy/compiler/compiler.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/backend/backend.h" +#include "xenia/cpu/compiler/compiler.h" +#include "xenia/cpu/runtime/runtime.h" #include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::hir::HIRBuilder; +using xe::cpu::hir::HIRBuilder; FinalizationPass::FinalizationPass() : CompilerPass() {} FinalizationPass::~FinalizationPass() {} int FinalizationPass::Run(HIRBuilder* builder) { - SCOPE_profile_cpu_f("alloy"); - // Process the HIR and prepare it for lowering. // After this is done the HIR should be ready for emitting. @@ -71,4 +70,5 @@ int FinalizationPass::Run(HIRBuilder* builder) { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/compiler/passes/finalization_pass.h b/src/xenia/cpu/compiler/passes/finalization_pass.h similarity index 73% rename from src/alloy/compiler/passes/finalization_pass.h rename to src/xenia/cpu/compiler/passes/finalization_pass.h index 1e5ca2b99..3baf2e9eb 100644 --- a/src/alloy/compiler/passes/finalization_pass.h +++ b/src/xenia/cpu/compiler/passes/finalization_pass.h @@ -7,12 +7,13 @@ ****************************************************************************** */ -#ifndef ALLOY_COMPILER_PASSES_FINALIZATION_PASS_H_ -#define ALLOY_COMPILER_PASSES_FINALIZATION_PASS_H_ +#ifndef XENIA_COMPILER_PASSES_FINALIZATION_PASS_H_ +#define XENIA_COMPILER_PASSES_FINALIZATION_PASS_H_ -#include "alloy/compiler/compiler_pass.h" +#include "xenia/cpu/compiler/compiler_pass.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { @@ -28,6 +29,7 @@ class FinalizationPass : public CompilerPass { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_COMPILER_PASSES_FINALIZATION_PASS_H_ +#endif // XENIA_COMPILER_PASSES_FINALIZATION_PASS_H_ diff --git a/src/alloy/compiler/passes/register_allocation_pass.cc b/src/xenia/cpu/compiler/passes/register_allocation_pass.cc similarity index 97% rename from src/alloy/compiler/passes/register_allocation_pass.cc rename to src/xenia/cpu/compiler/passes/register_allocation_pass.cc index 3a1ce56c5..3800174a2 100644 --- a/src/alloy/compiler/passes/register_allocation_pass.cc +++ b/src/xenia/cpu/compiler/passes/register_allocation_pass.cc @@ -7,26 +7,27 @@ ****************************************************************************** */ -#include "alloy/compiler/passes/register_allocation_pass.h" +#include "xenia/cpu/compiler/passes/register_allocation_pass.h" #include #include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::backend::MachineInfo; -using alloy::hir::HIRBuilder; -using alloy::hir::Instr; -using alloy::hir::OpcodeSignatureType; -using alloy::hir::RegAssignment; -using alloy::hir::TypeName; -using alloy::hir::Value; +using xe::cpu::backend::MachineInfo; +using xe::cpu::hir::HIRBuilder; +using xe::cpu::hir::Instr; +using xe::cpu::hir::OpcodeSignatureType; +using xe::cpu::hir::RegAssignment; +using xe::cpu::hir::TypeName; +using xe::cpu::hir::Value; #define ASSERT_NO_CYCLES 0 @@ -66,8 +67,6 @@ RegisterAllocationPass::~RegisterAllocationPass() { } int RegisterAllocationPass::Run(HIRBuilder* builder) { - SCOPE_profile_cpu_f("alloy"); - // Simple per-block allocator that operates on SSA form. // Registers do not move across blocks, though this could be // optimized with some intra-block analysis (dominators/etc). @@ -561,4 +560,5 @@ void RegisterAllocationPass::SortUsageList(Value* value) { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/compiler/passes/register_allocation_pass.h b/src/xenia/cpu/compiler/passes/register_allocation_pass.h similarity index 88% rename from src/alloy/compiler/passes/register_allocation_pass.h rename to src/xenia/cpu/compiler/passes/register_allocation_pass.h index c57a4da60..ae6e40f50 100644 --- a/src/alloy/compiler/passes/register_allocation_pass.h +++ b/src/xenia/cpu/compiler/passes/register_allocation_pass.h @@ -7,17 +7,18 @@ ****************************************************************************** */ -#ifndef ALLOY_COMPILER_PASSES_REGISTER_ALLOCATION_PASS_H_ -#define ALLOY_COMPILER_PASSES_REGISTER_ALLOCATION_PASS_H_ +#ifndef XENIA_COMPILER_PASSES_REGISTER_ALLOCATION_PASS_H_ +#define XENIA_COMPILER_PASSES_REGISTER_ALLOCATION_PASS_H_ #include #include #include -#include "alloy/backend/machine_info.h" -#include "alloy/compiler/compiler_pass.h" +#include "xenia/cpu/backend/machine_info.h" +#include "xenia/cpu/compiler/compiler_pass.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { @@ -80,6 +81,7 @@ class RegisterAllocationPass : public CompilerPass { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_COMPILER_PASSES_REGISTER_ALLOCATION_PASS_H_ +#endif // XENIA_COMPILER_PASSES_REGISTER_ALLOCATION_PASS_H_ diff --git a/src/alloy/compiler/passes/simplification_pass.cc b/src/xenia/cpu/compiler/passes/simplification_pass.cc similarity index 95% rename from src/alloy/compiler/passes/simplification_pass.cc rename to src/xenia/cpu/compiler/passes/simplification_pass.cc index cbd2ee39a..03965b678 100644 --- a/src/alloy/compiler/passes/simplification_pass.cc +++ b/src/xenia/cpu/compiler/passes/simplification_pass.cc @@ -7,28 +7,27 @@ ****************************************************************************** */ -#include "alloy/compiler/passes/simplification_pass.h" +#include "xenia/cpu/compiler/passes/simplification_pass.h" #include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::hir::HIRBuilder; -using alloy::hir::Instr; -using alloy::hir::Value; +using xe::cpu::hir::HIRBuilder; +using xe::cpu::hir::Instr; +using xe::cpu::hir::Value; SimplificationPass::SimplificationPass() : CompilerPass() {} SimplificationPass::~SimplificationPass() {} int SimplificationPass::Run(HIRBuilder* builder) { - SCOPE_profile_cpu_f("alloy"); - EliminateConversions(builder); SimplifyAssignments(builder); return 0; @@ -170,4 +169,5 @@ Value* SimplificationPass::CheckValue(Value* value) { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/compiler/passes/simplification_pass.h b/src/xenia/cpu/compiler/passes/simplification_pass.h similarity index 78% rename from src/alloy/compiler/passes/simplification_pass.h rename to src/xenia/cpu/compiler/passes/simplification_pass.h index 769a355fd..c4fd102c6 100644 --- a/src/alloy/compiler/passes/simplification_pass.h +++ b/src/xenia/cpu/compiler/passes/simplification_pass.h @@ -7,12 +7,13 @@ ****************************************************************************** */ -#ifndef ALLOY_COMPILER_PASSES_SIMPLIFICATION_PASS_H_ -#define ALLOY_COMPILER_PASSES_SIMPLIFICATION_PASS_H_ +#ifndef XENIA_COMPILER_PASSES_SIMPLIFICATION_PASS_H_ +#define XENIA_COMPILER_PASSES_SIMPLIFICATION_PASS_H_ -#include "alloy/compiler/compiler_pass.h" +#include "xenia/cpu/compiler/compiler_pass.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { @@ -34,6 +35,7 @@ class SimplificationPass : public CompilerPass { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_COMPILER_PASSES_SIMPLIFICATION_PASS_H_ +#endif // XENIA_COMPILER_PASSES_SIMPLIFICATION_PASS_H_ diff --git a/src/alloy/compiler/passes/sources.gypi b/src/xenia/cpu/compiler/passes/sources.gypi similarity index 100% rename from src/alloy/compiler/passes/sources.gypi rename to src/xenia/cpu/compiler/passes/sources.gypi diff --git a/src/alloy/compiler/passes/validation_pass.cc b/src/xenia/cpu/compiler/passes/validation_pass.cc similarity index 85% rename from src/alloy/compiler/passes/validation_pass.cc rename to src/xenia/cpu/compiler/passes/validation_pass.cc index f4650fdf0..a3d1cd7b0 100644 --- a/src/alloy/compiler/passes/validation_pass.cc +++ b/src/xenia/cpu/compiler/passes/validation_pass.cc @@ -7,33 +7,32 @@ ****************************************************************************** */ -#include "alloy/compiler/passes/validation_pass.h" +#include "xenia/cpu/compiler/passes/validation_pass.h" -#include "alloy/backend/backend.h" -#include "alloy/compiler/compiler.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/backend/backend.h" +#include "xenia/cpu/compiler/compiler.h" +#include "xenia/cpu/runtime/runtime.h" #include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::hir::Block; -using alloy::hir::HIRBuilder; -using alloy::hir::Instr; -using alloy::hir::OpcodeSignatureType; -using alloy::hir::Value; +using xe::cpu::hir::Block; +using xe::cpu::hir::HIRBuilder; +using xe::cpu::hir::Instr; +using xe::cpu::hir::OpcodeSignatureType; +using xe::cpu::hir::Value; ValidationPass::ValidationPass() : CompilerPass() {} ValidationPass::~ValidationPass() {} int ValidationPass::Run(HIRBuilder* builder) { - SCOPE_profile_cpu_f("alloy"); - #if 0 StringBuffer str; builder->Dump(&str); @@ -115,4 +114,5 @@ int ValidationPass::ValidateValue(Block* block, Instr* instr, Value* value) { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/compiler/passes/validation_pass.h b/src/xenia/cpu/compiler/passes/validation_pass.h similarity index 76% rename from src/alloy/compiler/passes/validation_pass.h rename to src/xenia/cpu/compiler/passes/validation_pass.h index 974e1da50..55e3e7cff 100644 --- a/src/alloy/compiler/passes/validation_pass.h +++ b/src/xenia/cpu/compiler/passes/validation_pass.h @@ -7,12 +7,13 @@ ****************************************************************************** */ -#ifndef ALLOY_COMPILER_PASSES_VALIDATION_PASS_H_ -#define ALLOY_COMPILER_PASSES_VALIDATION_PASS_H_ +#ifndef XENIA_COMPILER_PASSES_VALIDATION_PASS_H_ +#define XENIA_COMPILER_PASSES_VALIDATION_PASS_H_ -#include "alloy/compiler/compiler_pass.h" +#include "xenia/cpu/compiler/compiler_pass.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { @@ -30,6 +31,7 @@ class ValidationPass : public CompilerPass { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_COMPILER_PASSES_VALIDATION_PASS_H_ +#endif // XENIA_COMPILER_PASSES_VALIDATION_PASS_H_ diff --git a/src/alloy/compiler/passes/value_reduction_pass.cc b/src/xenia/cpu/compiler/passes/value_reduction_pass.cc similarity index 91% rename from src/alloy/compiler/passes/value_reduction_pass.cc rename to src/xenia/cpu/compiler/passes/value_reduction_pass.cc index 46ade7351..9f4e479e7 100644 --- a/src/alloy/compiler/passes/value_reduction_pass.cc +++ b/src/xenia/cpu/compiler/passes/value_reduction_pass.cc @@ -7,11 +7,11 @@ ****************************************************************************** */ -#include "alloy/compiler/passes/value_reduction_pass.h" +#include "xenia/cpu/compiler/passes/value_reduction_pass.h" -#include "alloy/backend/backend.h" -#include "alloy/compiler/compiler.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/backend/backend.h" +#include "xenia/cpu/compiler/compiler.h" +#include "xenia/cpu/runtime/runtime.h" #include "xenia/profiling.h" #if XE_COMPILER_MSVC @@ -24,16 +24,17 @@ #include #endif // XE_COMPILER_MSVC -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::hir::HIRBuilder; -using alloy::hir::OpcodeInfo; -using alloy::hir::Value; +using xe::cpu::hir::HIRBuilder; +using xe::cpu::hir::OpcodeInfo; +using xe::cpu::hir::Value; ValueReductionPass::ValueReductionPass() : CompilerPass() {} @@ -57,8 +58,6 @@ void ValueReductionPass::ComputeLastUse(Value* value) { } int ValueReductionPass::Run(HIRBuilder* builder) { - SCOPE_profile_cpu_f("alloy"); - // Walk each block and reuse variable ordinals as much as possible. llvm::BitVector ordinals(builder->max_value_ordinal()); @@ -144,4 +143,5 @@ int ValueReductionPass::Run(HIRBuilder* builder) { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/compiler/passes/value_reduction_pass.h b/src/xenia/cpu/compiler/passes/value_reduction_pass.h similarity index 74% rename from src/alloy/compiler/passes/value_reduction_pass.h rename to src/xenia/cpu/compiler/passes/value_reduction_pass.h index 430c02c18..d2ef47d3b 100644 --- a/src/alloy/compiler/passes/value_reduction_pass.h +++ b/src/xenia/cpu/compiler/passes/value_reduction_pass.h @@ -7,12 +7,13 @@ ****************************************************************************** */ -#ifndef ALLOY_COMPILER_PASSES_VALUE_REDUCTION_PASS_H_ -#define ALLOY_COMPILER_PASSES_VALUE_REDUCTION_PASS_H_ +#ifndef XENIA_COMPILER_PASSES_VALUE_REDUCTION_PASS_H_ +#define XENIA_COMPILER_PASSES_VALUE_REDUCTION_PASS_H_ -#include "alloy/compiler/compiler_pass.h" +#include "xenia/cpu/compiler/compiler_pass.h" -namespace alloy { +namespace xe { +namespace cpu { namespace compiler { namespace passes { @@ -29,6 +30,7 @@ class ValueReductionPass : public CompilerPass { } // namespace passes } // namespace compiler -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_COMPILER_PASSES_VALUE_REDUCTION_PASS_H_ +#endif // XENIA_COMPILER_PASSES_VALUE_REDUCTION_PASS_H_ diff --git a/src/alloy/compiler/sources.gypi b/src/xenia/cpu/compiler/sources.gypi similarity index 100% rename from src/alloy/compiler/sources.gypi rename to src/xenia/cpu/compiler/sources.gypi diff --git a/src/xenia/cpu/cpu-private.h b/src/xenia/cpu/cpu-private.h index 0c2c33313..b2a5dfa64 100644 --- a/src/xenia/cpu/cpu-private.h +++ b/src/xenia/cpu/cpu-private.h @@ -22,4 +22,13 @@ DECLARE_string(load_module_map); DECLARE_string(dump_path); DECLARE_bool(dump_module_map); +DECLARE_bool(debug); +DECLARE_bool(always_disasm); + +DECLARE_bool(validate_hir); + +DECLARE_uint64(break_on_instruction); +DECLARE_uint64(break_on_memory); +DECLARE_bool(break_on_debugbreak); + #endif // XENIA_CPU_PRIVATE_H_ diff --git a/src/xenia/cpu/cpu.cc b/src/xenia/cpu/cpu.cc index dbc6cc34b..c9643ca44 100644 --- a/src/xenia/cpu/cpu.cc +++ b/src/xenia/cpu/cpu.cc @@ -28,3 +28,25 @@ DEFINE_string(dump_path, "build/", DEFINE_bool(dump_module_bitcode, true, "Writes the module bitcode both before and after optimizations."); DEFINE_bool(dump_module_map, true, "Dumps the module symbol database."); + +#if 0 && DEBUG +#define DEFAULT_DEBUG_FLAG true +#else +#define DEFAULT_DEBUG_FLAG false +#endif + +DEFINE_bool(debug, DEFAULT_DEBUG_FLAG, + "Allow debugging and retain debug information."); +DEFINE_bool( + always_disasm, false, + "Always add debug info to functions, even when no debugger is attached."); + +DEFINE_bool(validate_hir, false, + "Perform validation checks on the HIR during compilation."); + +// Breakpoints: +DEFINE_uint64(break_on_instruction, 0, + "int3 before the given guest address is executed."); +DEFINE_uint64(break_on_memory, 0, + "int3 on read/write to the given memory address."); +DEFINE_bool(break_on_debugbreak, true, "int3 on JITed __debugbreak requests."); diff --git a/src/xenia/cpu/cpu.h b/src/xenia/cpu/cpu.h index 15a3d4a53..19b7fc983 100644 --- a/src/xenia/cpu/cpu.h +++ b/src/xenia/cpu/cpu.h @@ -11,6 +11,10 @@ #define XENIA_CPU_CPU_H_ #include "xenia/cpu/processor.h" +#include "xenia/cpu/runtime/function.h" +#include "xenia/cpu/runtime/module.h" +#include "xenia/cpu/runtime/runtime.h" +#include "xenia/cpu/runtime/thread_state.h" #include "xenia/cpu/xenon_runtime.h" #include "xenia/cpu/xenon_thread_state.h" #include "xenia/cpu/xex_module.h" diff --git a/src/alloy/frontend/context_info.cc b/src/xenia/cpu/frontend/context_info.cc similarity index 87% rename from src/alloy/frontend/context_info.cc rename to src/xenia/cpu/frontend/context_info.cc index 7917ff33f..d1e782e72 100644 --- a/src/alloy/frontend/context_info.cc +++ b/src/xenia/cpu/frontend/context_info.cc @@ -7,9 +7,10 @@ ****************************************************************************** */ -#include "alloy/frontend/context_info.h" +#include "xenia/cpu/frontend/context_info.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { ContextInfo::ContextInfo(size_t size, uintptr_t thread_state_offset, @@ -21,4 +22,5 @@ ContextInfo::ContextInfo(size_t size, uintptr_t thread_state_offset, ContextInfo::~ContextInfo() {} } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/frontend/context_info.h b/src/xenia/cpu/frontend/context_info.h similarity index 84% rename from src/alloy/frontend/context_info.h rename to src/xenia/cpu/frontend/context_info.h index 68cf52e18..48ce4b0a4 100644 --- a/src/alloy/frontend/context_info.h +++ b/src/xenia/cpu/frontend/context_info.h @@ -7,13 +7,14 @@ ****************************************************************************** */ -#ifndef ALLOY_FRONTEND_CONTEXT_INFO_H_ -#define ALLOY_FRONTEND_CONTEXT_INFO_H_ +#ifndef XENIA_FRONTEND_CONTEXT_INFO_H_ +#define XENIA_FRONTEND_CONTEXT_INFO_H_ #include #include -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { class ContextInfo { @@ -34,6 +35,7 @@ class ContextInfo { }; } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_FRONTEND_CONTEXT_INFO_H_ +#endif // XENIA_FRONTEND_CONTEXT_INFO_H_ diff --git a/src/alloy/frontend/frontend.cc b/src/xenia/cpu/frontend/frontend.cc similarity index 83% rename from src/alloy/frontend/frontend.cc rename to src/xenia/cpu/frontend/frontend.cc index c762a6225..c5a46e7b2 100644 --- a/src/alloy/frontend/frontend.cc +++ b/src/xenia/cpu/frontend/frontend.cc @@ -7,11 +7,12 @@ ****************************************************************************** */ -#include "alloy/frontend/frontend.h" +#include "xenia/cpu/frontend/frontend.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/runtime/runtime.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { Frontend::Frontend(runtime::Runtime* runtime) : runtime_(runtime) {} @@ -23,4 +24,5 @@ Memory* Frontend::memory() const { return runtime_->memory(); } int Frontend::Initialize() { return 0; } } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/frontend/frontend.h b/src/xenia/cpu/frontend/frontend.h similarity index 75% rename from src/alloy/frontend/frontend.h rename to src/xenia/cpu/frontend/frontend.h index 5e8d4b346..efa398951 100644 --- a/src/alloy/frontend/frontend.h +++ b/src/xenia/cpu/frontend/frontend.h @@ -7,23 +7,26 @@ ****************************************************************************** */ -#ifndef ALLOY_FRONTEND_FRONTEND_H_ -#define ALLOY_FRONTEND_FRONTEND_H_ +#ifndef XENIA_FRONTEND_FRONTEND_H_ +#define XENIA_FRONTEND_FRONTEND_H_ #include -#include "alloy/frontend/context_info.h" -#include "alloy/memory.h" -#include "alloy/runtime/function.h" -#include "alloy/runtime/symbol_info.h" +#include "xenia/cpu/frontend/context_info.h" +#include "xenia/memory.h" +#include "xenia/cpu/runtime/function.h" +#include "xenia/cpu/runtime/symbol_info.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { class Runtime; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { class Frontend { @@ -48,6 +51,7 @@ class Frontend { }; } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_FRONTEND_FRONTEND_H_ +#endif // XENIA_FRONTEND_FRONTEND_H_ diff --git a/src/alloy/frontend/ppc/ppc_context.cc b/src/xenia/cpu/frontend/ppc/ppc_context.cc similarity index 92% rename from src/alloy/frontend/ppc/ppc_context.cc rename to src/xenia/cpu/frontend/ppc/ppc_context.cc index f7a05715e..1b8950a3d 100644 --- a/src/alloy/frontend/ppc/ppc_context.cc +++ b/src/xenia/cpu/frontend/ppc/ppc_context.cc @@ -7,11 +7,12 @@ ****************************************************************************** */ -#include "alloy/frontend/ppc/ppc_context.h" +#include "xenia/cpu/frontend/ppc/ppc_context.h" #include -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { @@ -19,9 +20,7 @@ uint64_t ParseInt64(const char* value) { return std::strtoull(value, nullptr, 0); } -double ParseFloat64(const char* value) { - return std::strtod(value, nullptr); -} +double ParseFloat64(const char* value) { return std::strtod(value, nullptr); } vec128_t ParseVec128(const char* value) { vec128_t v; @@ -85,4 +84,5 @@ bool PPCContext::CompareRegWithString(const char* name, const char* value, } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/xenia/cpu/frontend/ppc/ppc_context.h b/src/xenia/cpu/frontend/ppc/ppc_context.h new file mode 100644 index 000000000..ea9beccb8 --- /dev/null +++ b/src/xenia/cpu/frontend/ppc/ppc_context.h @@ -0,0 +1,227 @@ +/** + ****************************************************************************** + * Xenia : Xbox 360 Emulator Research Project * + ****************************************************************************** + * Copyright 2013 Ben Vanik. All rights reserved. * + * Released under the BSD license - see LICENSE in the root for more details. * + ****************************************************************************** + */ + +#ifndef XENIA_FRONTEND_PPC_PPC_CONTEXT_H_ +#define XENIA_FRONTEND_PPC_PPC_CONTEXT_H_ + +#include "poly/poly.h" +#include "poly/vec128.h" + +namespace xe { +namespace cpu { +namespace runtime { +class Runtime; +class ThreadState; +} // namespace runtime +} // namespace cpu +} // namespace xe + +namespace xe { +namespace cpu { +namespace frontend { +namespace ppc { + +using vec128_t = poly::vec128_t; + +// Map: +// 0-31: GPR +// 32-63: FPR +// 64: LR +// 65: CTR +// 66: XER +// 67: FPSCR +// 68: VSCR +// 69-76: CR0-7 +// 100: invalid +// 128-256: VR + +#pragma pack(push, 4) +typedef struct alignas(64) PPCContext_s { + // Must be stored at 0x0 for now. + // TODO(benvanik): find a nice way to describe this to the JIT. + runtime::ThreadState* thread_state; + // TODO(benvanik): this is getting nasty. Must be here. + uint8_t* membase; + + // Most frequently used registers first. + uint64_t r[32]; // General purpose registers + uint64_t lr; // Link register + uint64_t ctr; // Count register + + // XER register + // Split to make it easier to do individual updates. + uint8_t xer_ca; + uint8_t xer_ov; + uint8_t xer_so; + + // Condition registers + // These are split to make it easier to do DCE on unused stores. + union { + uint32_t value; + struct { + uint8_t cr0_lt; // Negative (LT) - result is negative + uint8_t cr0_gt; // Positive (GT) - result is positive (and not zero) + uint8_t cr0_eq; // Zero (EQ) - result is zero or a stwcx/stdcx completed + // successfully + uint8_t cr0_so; // Summary Overflow (SO) - copy of XER[SO] + }; + } cr0; + union { + uint32_t value; + struct { + uint8_t cr1_fx; // FP exception summary - copy of FPSCR[FX] + uint8_t cr1_fex; // FP enabled exception summary - copy of FPSCR[FEX] + uint8_t + cr1_vx; // FP invalid operation exception summary - copy of FPSCR[VX] + uint8_t cr1_ox; // FP overflow exception - copy of FPSCR[OX] + }; + } cr1; + union { + uint32_t value; + struct { + uint8_t cr2_0; + uint8_t cr2_1; + uint8_t cr2_2; + uint8_t cr2_3; + }; + } cr2; + union { + uint32_t value; + struct { + uint8_t cr3_0; + uint8_t cr3_1; + uint8_t cr3_2; + uint8_t cr3_3; + }; + } cr3; + union { + uint32_t value; + struct { + uint8_t cr4_0; + uint8_t cr4_1; + uint8_t cr4_2; + uint8_t cr4_3; + }; + } cr4; + union { + uint32_t value; + struct { + uint8_t cr5_0; + uint8_t cr5_1; + uint8_t cr5_2; + uint8_t cr5_3; + }; + } cr5; + union { + uint32_t value; + struct { + uint8_t cr6_all_equal; + uint8_t cr6_1; + uint8_t cr6_none_equal; + uint8_t cr6_3; + }; + } cr6; + union { + uint32_t value; + struct { + uint8_t cr7_0; + uint8_t cr7_1; + uint8_t cr7_2; + uint8_t cr7_3; + }; + } cr7; + + union { + uint32_t value; + struct { + uint32_t rn : 2; // FP rounding control: 00 = nearest + // 01 = toward zero + // 10 = toward +infinity + // 11 = toward -infinity + uint32_t ni : 1; // Floating-point non-IEEE mode + uint32_t xe : 1; // IEEE floating-point inexact exception enable + uint32_t ze : 1; // IEEE floating-point zero divide exception enable + uint32_t ue : 1; // IEEE floating-point underflow exception enable + uint32_t oe : 1; // IEEE floating-point overflow exception enable + uint32_t ve : 1; // FP invalid op exception enable + uint32_t vxcvi : 1; // FP invalid op exception: invalid integer convert + // -- sticky + uint32_t vxsqrt : 1; // FP invalid op exception: invalid sqrt -- sticky + uint32_t vxsoft : 1; // FP invalid op exception: software request + // -- sticky + uint32_t reserved : 1; + uint32_t fprf_un : 1; // FP result unordered or NaN (FU or ?) + uint32_t fprf_eq : 1; // FP result equal or zero (FE or =) + uint32_t fprf_gt : 1; // FP result greater than or positive (FG or >) + uint32_t fprf_lt : 1; // FP result less than or negative (FL or <) + uint32_t fprf_c : 1; // FP result class + uint32_t fi : 1; // FP fraction inexact + uint32_t fr : 1; // FP fraction rounded + uint32_t vxvc : 1; // FP invalid op exception: invalid compare -- + // sticky + uint32_t vximz : 1; // FP invalid op exception: infinity * 0 -- sticky + uint32_t vxzdz : 1; // FP invalid op exception: 0 / 0 -- sticky + uint32_t vxidi : 1; // FP invalid op exception: infinity / infinity + // -- sticky + uint32_t vxisi : 1; // FP invalid op exception: infinity - infinity + // -- sticky + uint32_t vxsnan : 1; // FP invalid op exception: SNaN -- sticky + uint32_t + xx : 1; // FP inexact exception -- sticky + uint32_t + zx : 1; // FP zero divide exception -- sticky + uint32_t + ux : 1; // FP underflow exception -- sticky + uint32_t + ox : 1; // FP overflow exception -- sticky + uint32_t vx : 1; // FP invalid operation exception summary + uint32_t fex : 1; // FP enabled exception summary + uint32_t + fx : 1; // FP exception summary -- sticky + } bits; + } fpscr; // Floating-point status and control register + + uint8_t vscr_sat; + + double f[32]; // Floating-point registers + vec128_t v[128]; // VMX128 vector registers + + // uint32_t get_fprf() { + // return fpscr.value & 0x000F8000; + // } + // void set_fprf(const uint32_t v) { + // fpscr.value = (fpscr.value & ~0x000F8000) | v; + // } + + // Thread ID assigned to this context. + uint32_t thread_id; + + // Reserve address for load acquire/store release. Shared. + uint64_t* reserve_address; + uint64_t* reserve_value; + + // Used to shuttle data into externs. Contents volatile. + uint64_t scratch; + + // Runtime-specific data pointer. Used on callbacks to get access to the + // current runtime and its data. + runtime::Runtime* runtime; + + void SetRegFromString(const char* name, const char* value); + bool CompareRegWithString(const char* name, const char* value, + char* out_value, size_t out_value_size); +} PPCContext; +#pragma pack(pop) + +} // namespace ppc +} // namespace frontend +} // namespace cpu +} // namespace xe + +#endif // XENIA_FRONTEND_PPC_PPC_CONTEXT_H_ diff --git a/src/alloy/frontend/ppc/ppc_disasm.cc b/src/xenia/cpu/frontend/ppc/ppc_disasm.cc similarity index 96% rename from src/alloy/frontend/ppc/ppc_disasm.cc rename to src/xenia/cpu/frontend/ppc/ppc_disasm.cc index 42b919499..5bb74ea8e 100644 --- a/src/alloy/frontend/ppc/ppc_disasm.cc +++ b/src/xenia/cpu/frontend/ppc/ppc_disasm.cc @@ -7,12 +7,13 @@ ****************************************************************************** */ -#include "alloy/frontend/ppc/ppc_disasm.h" +#include "xenia/cpu/frontend/ppc/ppc_disasm.h" #include "poly/poly.h" #include "poly/string_buffer.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { @@ -62,41 +63,41 @@ void Disasm_X_FRT_RA0_RB(InstrData& i, poly::StringBuffer* str) { } void Disasm_D_RT_RA_I(InstrData& i, poly::StringBuffer* str) { str->Append("%-8s r%d, r%d, %d", i.type->name, i.D.RT, i.D.RA, - (int32_t)(int16_t)XEEXTS16(i.D.DS)); + (int32_t)(int16_t) XEEXTS16(i.D.DS)); } void Disasm_D_RT_RA0_I(InstrData& i, poly::StringBuffer* str) { if (i.D.RA) { str->Append("%-8s r%d, r%d, %d", i.type->name, i.D.RT, i.D.RA, - (int32_t)(int16_t)XEEXTS16(i.D.DS)); + (int32_t)(int16_t) XEEXTS16(i.D.DS)); } else { str->Append("%-8s r%d, 0, %d", i.type->name, i.D.RT, - (int32_t)(int16_t)XEEXTS16(i.D.DS)); + (int32_t)(int16_t) XEEXTS16(i.D.DS)); } } void Disasm_D_FRT_RA_I(InstrData& i, poly::StringBuffer* str) { str->Append("%-8s f%d, r%d, %d", i.type->name, i.D.RT, i.D.RA, - (int32_t)(int16_t)XEEXTS16(i.D.DS)); + (int32_t)(int16_t) XEEXTS16(i.D.DS)); } void Disasm_D_FRT_RA0_I(InstrData& i, poly::StringBuffer* str) { if (i.D.RA) { str->Append("%-8s f%d, r%d, %d", i.type->name, i.D.RT, i.D.RA, - (int32_t)(int16_t)XEEXTS16(i.D.DS)); + (int32_t)(int16_t) XEEXTS16(i.D.DS)); } else { str->Append("%-8s f%d, 0, %d", i.type->name, i.D.RT, - (int32_t)(int16_t)XEEXTS16(i.D.DS)); + (int32_t)(int16_t) XEEXTS16(i.D.DS)); } } void Disasm_DS_RT_RA_I(InstrData& i, poly::StringBuffer* str) { str->Append("%-8s r%d, r%d, %d", i.type->name, i.DS.RT, i.DS.RA, - (int32_t)(int16_t)XEEXTS16(i.DS.DS << 2)); + (int32_t)(int16_t) XEEXTS16(i.DS.DS << 2)); } void Disasm_DS_RT_RA0_I(InstrData& i, poly::StringBuffer* str) { if (i.DS.RA) { str->Append("%-8s r%d, r%d, %d", i.type->name, i.DS.RT, i.DS.RA, - (int32_t)(int16_t)XEEXTS16(i.DS.DS << 2)); + (int32_t)(int16_t) XEEXTS16(i.DS.DS << 2)); } else { str->Append("%-8s r%d, 0, %d", i.type->name, i.DS.RT, - (int32_t)(int16_t)XEEXTS16(i.DS.DS << 2)); + (int32_t)(int16_t) XEEXTS16(i.DS.DS << 2)); } } void Disasm_D_RA(InstrData& i, poly::StringBuffer* str) { @@ -500,4 +501,5 @@ int DisasmPPC(InstrData& i, poly::StringBuffer* str) { } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/frontend/ppc/ppc_disasm.h b/src/xenia/cpu/frontend/ppc/ppc_disasm.h similarity index 73% rename from src/alloy/frontend/ppc/ppc_disasm.h rename to src/xenia/cpu/frontend/ppc/ppc_disasm.h index a43dbf4fa..2fef833f1 100644 --- a/src/alloy/frontend/ppc/ppc_disasm.h +++ b/src/xenia/cpu/frontend/ppc/ppc_disasm.h @@ -7,13 +7,14 @@ ****************************************************************************** */ -#ifndef ALLOY_FRONTEND_PPC_PPC_DISASM_H_ -#define ALLOY_FRONTEND_PPC_PPC_DISASM_H_ +#ifndef XENIA_FRONTEND_PPC_PPC_DISASM_H_ +#define XENIA_FRONTEND_PPC_PPC_DISASM_H_ -#include "alloy/frontend/ppc/ppc_instr.h" +#include "xenia/cpu/frontend/ppc/ppc_instr.h" #include "poly/string_buffer.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { @@ -21,6 +22,7 @@ int DisasmPPC(InstrData& i, poly::StringBuffer* str); } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_FRONTEND_PPC_PPC_DISASM_H_ +#endif // XENIA_FRONTEND_PPC_PPC_DISASM_H_ diff --git a/src/alloy/frontend/ppc/ppc_emit-private.h b/src/xenia/cpu/frontend/ppc/ppc_emit-private.h similarity index 74% rename from src/alloy/frontend/ppc/ppc_emit-private.h rename to src/xenia/cpu/frontend/ppc/ppc_emit-private.h index 3b095dc13..58dbb0505 100644 --- a/src/alloy/frontend/ppc/ppc_emit-private.h +++ b/src/xenia/cpu/frontend/ppc/ppc_emit-private.h @@ -7,13 +7,14 @@ ****************************************************************************** */ -#ifndef ALLOY_FRONTEND_PPC_PPC_EMIT_PRIVATE_H_ -#define ALLOY_FRONTEND_PPC_PPC_EMIT_PRIVATE_H_ +#ifndef XENIA_FRONTEND_PPC_PPC_EMIT_PRIVATE_H_ +#define XENIA_FRONTEND_PPC_PPC_EMIT_PRIVATE_H_ -#include "alloy/frontend/ppc/ppc_emit.h" -#include "alloy/frontend/ppc/ppc_instr.h" +#include "xenia/cpu/frontend/ppc/ppc_emit.h" +#include "xenia/cpu/frontend/ppc/ppc_instr.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { @@ -28,6 +29,7 @@ namespace ppc { } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_FRONTEND_PPC_PPC_EMIT_PRIVATE_H_ +#endif // XENIA_FRONTEND_PPC_PPC_EMIT_PRIVATE_H_ diff --git a/src/alloy/frontend/ppc/ppc_emit.h b/src/xenia/cpu/frontend/ppc/ppc_emit.h similarity index 75% rename from src/alloy/frontend/ppc/ppc_emit.h rename to src/xenia/cpu/frontend/ppc/ppc_emit.h index 18aa6959f..5ae2e40ca 100644 --- a/src/alloy/frontend/ppc/ppc_emit.h +++ b/src/xenia/cpu/frontend/ppc/ppc_emit.h @@ -7,12 +7,13 @@ ****************************************************************************** */ -#ifndef ALLOY_FRONTEND_PPC_PPC_EMIT_H_ -#define ALLOY_FRONTEND_PPC_PPC_EMIT_H_ +#ifndef XENIA_FRONTEND_PPC_PPC_EMIT_H_ +#define XENIA_FRONTEND_PPC_PPC_EMIT_H_ -#include "alloy/frontend/ppc/ppc_instr.h" +#include "xenia/cpu/frontend/ppc/ppc_instr.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { @@ -24,6 +25,7 @@ void RegisterEmitCategoryMemory(); } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_FRONTEND_PPC_PPC_EMIT_H_ +#endif // XENIA_FRONTEND_PPC_PPC_EMIT_H_ diff --git a/src/alloy/frontend/ppc/ppc_emit_altivec.cc b/src/xenia/cpu/frontend/ppc/ppc_emit_altivec.cc similarity index 99% rename from src/alloy/frontend/ppc/ppc_emit_altivec.cc rename to src/xenia/cpu/frontend/ppc/ppc_emit_altivec.cc index 81c8444e2..10e0b694c 100644 --- a/src/alloy/frontend/ppc/ppc_emit_altivec.cc +++ b/src/xenia/cpu/frontend/ppc/ppc_emit_altivec.cc @@ -7,23 +7,24 @@ ****************************************************************************** */ -#include "alloy/frontend/ppc/ppc_emit-private.h" +#include "xenia/cpu/frontend/ppc/ppc_emit-private.h" -#include "alloy/frontend/ppc/ppc_context.h" -#include "alloy/frontend/ppc/ppc_hir_builder.h" +#include "xenia/cpu/frontend/ppc/ppc_context.h" +#include "xenia/cpu/frontend/ppc/ppc_hir_builder.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; using poly::vec128b; using poly::vec128f; using poly::vec128i; using poly::vec128s; -using alloy::hir::Value; +using xe::cpu::hir::Value; Value* CalculateEA_0(PPCHIRBuilder& f, uint32_t ra, uint32_t rb); @@ -1462,8 +1463,8 @@ XEEMITTER(vsldoi128, VX128_5(4, 16), VX128_5)(PPCHIRBuilder& f, InstrData& i) { int InstrEmit_vslo_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { // (VD) <- (VA) << (VB.b[F] & 0x78) (by octet) // TODO(benvanik): flag for shift-by-octet as optimization. - Value* sh = - f.And(f.Extract(f.LoadVR(vb), 15, INT8_TYPE), f.LoadConstant(int8_t(0x78))); + Value* sh = f.And(f.Extract(f.LoadVR(vb), 15, INT8_TYPE), + f.LoadConstant(int8_t(0x78))); Value* v = f.Permute(f.LoadVectorShl(sh), f.LoadVR(va), f.LoadZero(VEC128_TYPE), INT8_TYPE); f.StoreVR(vd, v); @@ -1761,7 +1762,8 @@ XEEMITTER(vpkpx, 0x1000030E, VX)(PPCHIRBuilder& f, InstrData& i) { return 1; } -int InstrEmit_vpkshss_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { +int InstrEmit_vpkshss_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, + uint32_t vb) { // Vector Pack Signed Halfword Signed Saturate // Convert VA and VB from signed words to signed saturated bytes then // concat: @@ -1781,7 +1783,8 @@ XEEMITTER(vpkshss128, VX128(5, 512), VX128)(PPCHIRBuilder& f, InstrData& i) { return InstrEmit_vpkshss_(f, VX128_VD128, VX128_VA128, VX128_VB128); } -int InstrEmit_vpkswss_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { +int InstrEmit_vpkswss_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, + uint32_t vb) { // Vector Pack Signed Word Signed Saturate // Convert VA and VB from signed int words to signed saturated shorts then // concat: @@ -1801,7 +1804,8 @@ XEEMITTER(vpkswss128, VX128(5, 640), VX128)(PPCHIRBuilder& f, InstrData& i) { return InstrEmit_vpkswss_(f, VX128_VD128, VX128_VA128, VX128_VB128); } -int InstrEmit_vpkswus_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { +int InstrEmit_vpkswus_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, + uint32_t vb) { // Vector Pack Signed Word Unsigned Saturate // Convert VA and VB from signed int words to unsigned saturated shorts then // concat: @@ -1821,7 +1825,8 @@ XEEMITTER(vpkswus128, VX128(5, 704), VX128)(PPCHIRBuilder& f, InstrData& i) { return InstrEmit_vpkswus_(f, VX128_VD128, VX128_VA128, VX128_VB128); } -int InstrEmit_vpkuhum_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { +int InstrEmit_vpkuhum_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, + uint32_t vb) { // Vector Pack Unsigned Halfword Unsigned Modulo // Convert VA and VB from unsigned shorts to unsigned bytes then concat: // for each i in VA + VB: @@ -1840,7 +1845,8 @@ XEEMITTER(vpkuhum128, VX128(5, 768), VX128)(PPCHIRBuilder& f, InstrData& i) { return InstrEmit_vpkuhum_(f, VX128_VD128, VX128_VA128, VX128_VB128); } -int InstrEmit_vpkuhus_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { +int InstrEmit_vpkuhus_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, + uint32_t vb) { // Vector Pack Unsigned Halfword Unsigned Saturate // Convert VA and VB from unsigned shorts to unsigned saturated bytes then // concat: @@ -1860,7 +1866,8 @@ XEEMITTER(vpkuhus128, VX128(5, 832), VX128)(PPCHIRBuilder& f, InstrData& i) { return InstrEmit_vpkuhus_(f, VX128_VD128, VX128_VA128, VX128_VB128); } -int InstrEmit_vpkshus_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { +int InstrEmit_vpkshus_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, + uint32_t vb) { // Vector Pack Signed Halfword Unsigned Saturate // Convert VA and VB from signed shorts to unsigned saturated bytes then // concat: @@ -1880,7 +1887,8 @@ XEEMITTER(vpkshus128, VX128(5, 576), VX128)(PPCHIRBuilder& f, InstrData& i) { return InstrEmit_vpkshus_(f, VX128_VD128, VX128_VA128, VX128_VB128); } -int InstrEmit_vpkuwum_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { +int InstrEmit_vpkuwum_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, + uint32_t vb) { // Vector Pack Unsigned Word Unsigned Modulo // Concat low shorts from VA + VB: // for each i in VA + VB: @@ -1899,7 +1907,8 @@ XEEMITTER(vpkuwum128, VX128(5, 896), VX128)(PPCHIRBuilder& f, InstrData& i) { return InstrEmit_vpkuwum_(f, VX128_VD128, VX128_VA128, VX128_VB128); } -int InstrEmit_vpkuwus_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { +int InstrEmit_vpkuwus_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, + uint32_t vb) { // Vector Pack Unsigned Word Unsigned Saturate // Convert VA and VB from unsigned int words to unsigned saturated shorts then // concat: @@ -1989,7 +1998,8 @@ XEEMITTER(vupkhsb128, VX128(6, 896), VX128)(PPCHIRBuilder& f, InstrData& i) { int InstrEmit_vupklsb_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) { // Vector Unpack Low Signed Byte // bytes 8-15 expanded to halfwords 0-7 and sign extended - Value* v = f.Unpack(f.LoadVR(vb), PACK_TYPE_TO_LO | PACK_TYPE_8_IN_16 | + Value* v = + f.Unpack(f.LoadVR(vb), PACK_TYPE_TO_LO | PACK_TYPE_8_IN_16 | PACK_TYPE_IN_SIGNED | PACK_TYPE_OUT_SIGNED); f.StoreVR(vd, v); return 0; @@ -2400,4 +2410,5 @@ void RegisterEmitCategoryAltivec() { } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/frontend/ppc/ppc_emit_alu.cc b/src/xenia/cpu/frontend/ppc/ppc_emit_alu.cc similarity index 99% rename from src/alloy/frontend/ppc/ppc_emit_alu.cc rename to src/xenia/cpu/frontend/ppc/ppc_emit_alu.cc index 3a3e95472..fbf519650 100644 --- a/src/alloy/frontend/ppc/ppc_emit_alu.cc +++ b/src/xenia/cpu/frontend/ppc/ppc_emit_alu.cc @@ -7,19 +7,20 @@ ****************************************************************************** */ -#include "alloy/frontend/ppc/ppc_emit-private.h" +#include "xenia/cpu/frontend/ppc/ppc_emit-private.h" -#include "alloy/frontend/ppc/ppc_context.h" -#include "alloy/frontend/ppc/ppc_hir_builder.h" +#include "xenia/cpu/frontend/ppc/ppc_context.h" +#include "xenia/cpu/frontend/ppc/ppc_hir_builder.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::hir::Value; +using xe::cpu::hir::Value; // Integer arithmetic (A-3) @@ -1271,4 +1272,5 @@ void RegisterEmitCategoryALU() { } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/frontend/ppc/ppc_emit_control.cc b/src/xenia/cpu/frontend/ppc/ppc_emit_control.cc similarity index 98% rename from src/alloy/frontend/ppc/ppc_emit_control.cc rename to src/xenia/cpu/frontend/ppc/ppc_emit_control.cc index 7e3c0ebff..18c1cfcbf 100644 --- a/src/alloy/frontend/ppc/ppc_emit_control.cc +++ b/src/xenia/cpu/frontend/ppc/ppc_emit_control.cc @@ -7,20 +7,21 @@ ****************************************************************************** */ -#include "alloy/frontend/ppc/ppc_emit-private.h" +#include "xenia/cpu/frontend/ppc/ppc_emit-private.h" -#include "alloy/frontend/ppc/ppc_context.h" -#include "alloy/frontend/ppc/ppc_hir_builder.h" +#include "xenia/cpu/frontend/ppc/ppc_context.h" +#include "xenia/cpu/frontend/ppc/ppc_hir_builder.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::hir::Label; -using alloy::hir::Value; +using xe::cpu::hir::Label; +using xe::cpu::hir::Value; int InstrEmit_branch(PPCHIRBuilder& f, const char* src, uint64_t cia, Value* nia, bool lk, Value* cond = NULL, @@ -749,4 +750,5 @@ void RegisterEmitCategoryControl() { } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/frontend/ppc/ppc_emit_fpu.cc b/src/xenia/cpu/frontend/ppc/ppc_emit_fpu.cc similarity index 96% rename from src/alloy/frontend/ppc/ppc_emit_fpu.cc rename to src/xenia/cpu/frontend/ppc/ppc_emit_fpu.cc index cc3eeeb28..e29499e82 100644 --- a/src/alloy/frontend/ppc/ppc_emit_fpu.cc +++ b/src/xenia/cpu/frontend/ppc/ppc_emit_fpu.cc @@ -7,20 +7,21 @@ ****************************************************************************** */ -#include "alloy/frontend/ppc/ppc_emit-private.h" +#include "xenia/cpu/frontend/ppc/ppc_emit-private.h" -#include "alloy/frontend/ppc/ppc_context.h" -#include "alloy/frontend/ppc/ppc_hir_builder.h" +#include "xenia/cpu/frontend/ppc/ppc_context.h" +#include "xenia/cpu/frontend/ppc/ppc_hir_builder.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::hir::RoundMode; -using alloy::hir::Value; +using xe::cpu::hir::RoundMode; +using xe::cpu::hir::Value; // Good source of information: // http://mamedev.org/source/src/emu/cpu/powerpc/ppc_ops.c @@ -257,7 +258,7 @@ XEEMITTER(fmsubsx, 0xEC000038, A)(PPCHIRBuilder& f, InstrData& i) { XEEMITTER(fnmaddx, 0xFC00003E, A)(PPCHIRBuilder& f, InstrData& i) { // frD <- -([frA x frC] + frB) Value* v = f.Neg( - f.MulAdd(f.LoadFPR(i.A.FRA), f.LoadFPR(i.A.FRC), f.LoadFPR(i.A.FRB))); + f.MulAdd(f.LoadFPR(i.A.FRA), f.LoadFPR(i.A.FRC), f.LoadFPR(i.A.FRB))); f.StoreFPR(i.A.FRT, v); // f.UpdateFPRF(v); if (i.A.Rc) { @@ -271,7 +272,7 @@ XEEMITTER(fnmaddx, 0xFC00003E, A)(PPCHIRBuilder& f, InstrData& i) { XEEMITTER(fnmaddsx, 0xEC00003E, A)(PPCHIRBuilder& f, InstrData& i) { // frD <- -([frA x frC] + frB) Value* v = f.Neg( - f.MulAdd(f.LoadFPR(i.A.FRA), f.LoadFPR(i.A.FRC), f.LoadFPR(i.A.FRB))); + f.MulAdd(f.LoadFPR(i.A.FRA), f.LoadFPR(i.A.FRC), f.LoadFPR(i.A.FRB))); v = f.Convert(f.Convert(v, FLOAT32_TYPE), FLOAT64_TYPE); f.StoreFPR(i.A.FRT, v); // f.UpdateFPRF(v); @@ -554,4 +555,5 @@ void RegisterEmitCategoryFPU() { } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/frontend/ppc/ppc_emit_memory.cc b/src/xenia/cpu/frontend/ppc/ppc_emit_memory.cc similarity index 99% rename from src/alloy/frontend/ppc/ppc_emit_memory.cc rename to src/xenia/cpu/frontend/ppc/ppc_emit_memory.cc index 49a28f085..6cd688a3f 100644 --- a/src/alloy/frontend/ppc/ppc_emit_memory.cc +++ b/src/xenia/cpu/frontend/ppc/ppc_emit_memory.cc @@ -7,19 +7,20 @@ ****************************************************************************** */ -#include "alloy/frontend/ppc/ppc_emit-private.h" +#include "xenia/cpu/frontend/ppc/ppc_emit-private.h" -#include "alloy/frontend/ppc/ppc_context.h" -#include "alloy/frontend/ppc/ppc_hir_builder.h" +#include "xenia/cpu/frontend/ppc/ppc_context.h" +#include "xenia/cpu/frontend/ppc/ppc_hir_builder.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::hir::Value; +using xe::cpu::hir::Value; #define TRUNCATE_ADDRESSES 0 @@ -1083,4 +1084,5 @@ void RegisterEmitCategoryMemory() { } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/frontend/ppc/ppc_frontend.cc b/src/xenia/cpu/frontend/ppc/ppc_frontend.cc similarity index 82% rename from src/alloy/frontend/ppc/ppc_frontend.cc rename to src/xenia/cpu/frontend/ppc/ppc_frontend.cc index 44dd08101..9a5436c63 100644 --- a/src/alloy/frontend/ppc/ppc_frontend.cc +++ b/src/xenia/cpu/frontend/ppc/ppc_frontend.cc @@ -7,21 +7,22 @@ ****************************************************************************** */ -#include "alloy/frontend/ppc/ppc_frontend.h" +#include "xenia/cpu/frontend/ppc/ppc_frontend.h" -#include "alloy/frontend/ppc/ppc_context.h" -#include "alloy/frontend/ppc/ppc_disasm.h" -#include "alloy/frontend/ppc/ppc_emit.h" -#include "alloy/frontend/ppc/ppc_translator.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/frontend/ppc/ppc_context.h" +#include "xenia/cpu/frontend/ppc/ppc_disasm.h" +#include "xenia/cpu/frontend/ppc/ppc_emit.h" +#include "xenia/cpu/frontend/ppc/ppc_translator.h" +#include "xenia/cpu/runtime/runtime.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { -using alloy::runtime::Function; -using alloy::runtime::FunctionInfo; -using alloy::runtime::Runtime; +using xe::cpu::runtime::Function; +using xe::cpu::runtime::FunctionInfo; +using xe::cpu::runtime::Runtime; void InitializeIfNeeded(); void CleanupOnShutdown(); @@ -103,16 +104,16 @@ int PPCFrontend::DeclareFunction(FunctionInfo* symbol_info) { } int PPCFrontend::DefineFunction(FunctionInfo* symbol_info, - uint32_t debug_info_flags, - uint32_t trace_flags, + uint32_t debug_info_flags, uint32_t trace_flags, Function** out_function) { PPCTranslator* translator = translator_pool_.Allocate(this); - int result = - translator->Translate(symbol_info, debug_info_flags, trace_flags, out_function); + int result = translator->Translate(symbol_info, debug_info_flags, trace_flags, + out_function); translator_pool_.Release(translator); return result; } } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/frontend/ppc/ppc_frontend.h b/src/xenia/cpu/frontend/ppc/ppc_frontend.h similarity index 84% rename from src/alloy/frontend/ppc/ppc_frontend.h rename to src/xenia/cpu/frontend/ppc/ppc_frontend.h index 99b9a8ae1..876c03920 100644 --- a/src/alloy/frontend/ppc/ppc_frontend.h +++ b/src/xenia/cpu/frontend/ppc/ppc_frontend.h @@ -7,15 +7,16 @@ ****************************************************************************** */ -#ifndef ALLOY_FRONTEND_PPC_PPC_FRONTEND_H_ -#define ALLOY_FRONTEND_PPC_PPC_FRONTEND_H_ +#ifndef XENIA_FRONTEND_PPC_PPC_FRONTEND_H_ +#define XENIA_FRONTEND_PPC_PPC_FRONTEND_H_ #include -#include "alloy/frontend/frontend.h" +#include "xenia/cpu/frontend/frontend.h" #include "poly/type_pool.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { @@ -49,6 +50,7 @@ class PPCFrontend : public Frontend { } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_FRONTEND_PPC_PPC_FRONTEND_H_ +#endif // XENIA_FRONTEND_PPC_PPC_FRONTEND_H_ diff --git a/src/alloy/frontend/ppc/ppc_hir_builder.cc b/src/xenia/cpu/frontend/ppc/ppc_hir_builder.cc similarity index 95% rename from src/alloy/frontend/ppc/ppc_hir_builder.cc rename to src/xenia/cpu/frontend/ppc/ppc_hir_builder.cc index b8a81d76d..d9f5cdab9 100644 --- a/src/alloy/frontend/ppc/ppc_hir_builder.cc +++ b/src/xenia/cpu/frontend/ppc/ppc_hir_builder.cc @@ -7,29 +7,30 @@ ****************************************************************************** */ -#include "alloy/frontend/ppc/ppc_hir_builder.h" +#include "xenia/cpu/frontend/ppc/ppc_hir_builder.h" -#include "alloy/alloy-private.h" -#include "alloy/frontend/ppc/ppc_context.h" -#include "alloy/frontend/ppc/ppc_disasm.h" -#include "alloy/frontend/ppc/ppc_frontend.h" -#include "alloy/frontend/ppc/ppc_instr.h" -#include "alloy/hir/label.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/cpu-private.h" +#include "xenia/cpu/frontend/ppc/ppc_context.h" +#include "xenia/cpu/frontend/ppc/ppc_disasm.h" +#include "xenia/cpu/frontend/ppc/ppc_frontend.h" +#include "xenia/cpu/frontend/ppc/ppc_instr.h" +#include "xenia/cpu/hir/label.h" +#include "xenia/cpu/runtime/runtime.h" #include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { // TODO(benvanik): remove when enums redefined. -using namespace alloy::hir; +using namespace xe::cpu::hir; -using alloy::hir::Label; -using alloy::hir::TypeName; -using alloy::hir::Value; -using alloy::runtime::Runtime; -using alloy::runtime::FunctionInfo; +using xe::cpu::hir::Label; +using xe::cpu::hir::TypeName; +using xe::cpu::hir::Value; +using xe::cpu::runtime::Runtime; +using xe::cpu::runtime::FunctionInfo; PPCHIRBuilder::PPCHIRBuilder(PPCFrontend* frontend) : HIRBuilder(), frontend_(frontend), comment_buffer_(4096) {} @@ -45,7 +46,7 @@ void PPCHIRBuilder::Reset() { } int PPCHIRBuilder::Emit(FunctionInfo* symbol_info, uint32_t flags) { - SCOPE_profile_cpu_f("alloy"); + SCOPE_profile_cpu_f("cpu"); Memory* memory = frontend_->memory(); const uint8_t* p = memory->membase(); @@ -464,9 +465,8 @@ Value* PPCHIRBuilder::LoadAcquire(Value* address, TypeName type, Truncate(address, INT32_TYPE)); Value* value = Load(address, type, load_flags); // Save the value so that we can compare it later in StoreRelease. - AtomicExchange( - LoadContext(offsetof(PPCContext, reserve_value), INT64_TYPE), - value); + AtomicExchange(LoadContext(offsetof(PPCContext, reserve_value), INT64_TYPE), + value); return value; } @@ -494,4 +494,5 @@ Value* PPCHIRBuilder::StoreRelease(Value* address, Value* value, } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/frontend/ppc/ppc_hir_builder.h b/src/xenia/cpu/frontend/ppc/ppc_hir_builder.h similarity index 87% rename from src/alloy/frontend/ppc/ppc_hir_builder.h rename to src/xenia/cpu/frontend/ppc/ppc_hir_builder.h index 440f8d2d9..86587e394 100644 --- a/src/alloy/frontend/ppc/ppc_hir_builder.h +++ b/src/xenia/cpu/frontend/ppc/ppc_hir_builder.h @@ -7,24 +7,25 @@ ****************************************************************************** */ -#ifndef ALLOY_FRONTEND_PPC_PPC_HIR_BUILDER_H_ -#define ALLOY_FRONTEND_PPC_PPC_HIR_BUILDER_H_ +#ifndef XENIA_FRONTEND_PPC_PPC_HIR_BUILDER_H_ +#define XENIA_FRONTEND_PPC_PPC_HIR_BUILDER_H_ -#include "alloy/hir/hir_builder.h" -#include "alloy/runtime/function.h" -#include "alloy/runtime/symbol_info.h" +#include "xenia/cpu/hir/hir_builder.h" +#include "xenia/cpu/runtime/function.h" +#include "xenia/cpu/runtime/symbol_info.h" #include "poly/string_buffer.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { class PPCFrontend; class PPCHIRBuilder : public hir::HIRBuilder { - using Instr = alloy::hir::Instr; - using Label = alloy::hir::Label; - using Value = alloy::hir::Value; + using Instr = xe::cpu::hir::Instr; + using Label = xe::cpu::hir::Label; + using Value = xe::cpu::hir::Value; public: PPCHIRBuilder(PPCFrontend* frontend); @@ -113,6 +114,7 @@ class PPCHIRBuilder : public hir::HIRBuilder { } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_FRONTEND_PPC_PPC_HIR_BUILDER_H_ +#endif // XENIA_FRONTEND_PPC_PPC_HIR_BUILDER_H_ diff --git a/src/alloy/frontend/ppc/ppc_instr.cc b/src/xenia/cpu/frontend/ppc/ppc_instr.cc similarity index 97% rename from src/alloy/frontend/ppc/ppc_instr.cc rename to src/xenia/cpu/frontend/ppc/ppc_instr.cc index 9c03171a2..8eba143fb 100644 --- a/src/alloy/frontend/ppc/ppc_instr.cc +++ b/src/xenia/cpu/frontend/ppc/ppc_instr.cc @@ -7,16 +7,17 @@ ****************************************************************************** */ -#include "alloy/frontend/ppc/ppc_instr.h" +#include "xenia/cpu/frontend/ppc/ppc_instr.h" #include #include -#include "alloy/frontend/ppc/ppc_instr_tables.h" +#include "xenia/cpu/frontend/ppc/ppc_instr_tables.h" #include "poly/poly.h" #include "poly/string_buffer.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { @@ -75,14 +76,14 @@ void InstrOperand::Dump(std::string& out_str) { switch (imm.width) { case 1: if (imm.is_signed) { - snprintf(buffer, max_count, "%d", (int32_t)(int8_t)imm.value); + snprintf(buffer, max_count, "%d", (int32_t)(int8_t) imm.value); } else { snprintf(buffer, max_count, "0x%.2X", (uint8_t)imm.value); } break; case 2: if (imm.is_signed) { - snprintf(buffer, max_count, "%d", (int32_t)(int16_t)imm.value); + snprintf(buffer, max_count, "%d", (int32_t)(int16_t) imm.value); } else { snprintf(buffer, max_count, "0x%.4X", (uint16_t)imm.value); } @@ -403,4 +404,5 @@ int RegisterInstrEmit(uint32_t code, InstrEmitFn emit) { } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/frontend/ppc/ppc_instr.h b/src/xenia/cpu/frontend/ppc/ppc_instr.h similarity index 98% rename from src/alloy/frontend/ppc/ppc_instr.h rename to src/xenia/cpu/frontend/ppc/ppc_instr.h index 6f5ce2a12..d4d0ee846 100644 --- a/src/alloy/frontend/ppc/ppc_instr.h +++ b/src/xenia/cpu/frontend/ppc/ppc_instr.h @@ -7,8 +7,8 @@ ****************************************************************************** */ -#ifndef ALLOY_FRONTEND_PPC_PPC_INSTR_H_ -#define ALLOY_FRONTEND_PPC_PPC_INSTR_H_ +#ifndef XENIA_FRONTEND_PPC_PPC_INSTR_H_ +#define XENIA_FRONTEND_PPC_PPC_INSTR_H_ #include #include @@ -16,7 +16,8 @@ #include "poly/string_buffer.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { @@ -59,7 +60,7 @@ typedef enum { kXEPPCInstrFormatXDSS = 26, } xe_ppc_instr_format_e; -typedef enum : uint32_t { +enum xe_ppc_instr_mask_e : uint32_t { kXEPPCInstrMaskVXR = 0xFC0003FF, kXEPPCInstrMaskVXA = 0xFC00003F, kXEPPCInstrMaskVX128 = 0xFC0003D0, @@ -70,7 +71,7 @@ typedef enum : uint32_t { kXEPPCInstrMaskVX128_5 = 0xFC000010, kXEPPCInstrMaskVX128_P = 0xFC000630, kXEPPCInstrMaskVX128_R = 0xFC000390, -} xe_ppc_instr_mask_e; +}; typedef enum { kXEPPCInstrTypeGeneral = (1 << 0), @@ -570,6 +571,7 @@ int RegisterInstrEmit(uint32_t code, InstrEmitFn emit); } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_FRONTEND_PPC_PPC_INSTR_H_ +#endif // XENIA_FRONTEND_PPC_PPC_INSTR_H_ diff --git a/src/alloy/frontend/ppc/ppc_instr_tables.h b/src/xenia/cpu/frontend/ppc/ppc_instr_tables.h similarity index 99% rename from src/alloy/frontend/ppc/ppc_instr_tables.h rename to src/xenia/cpu/frontend/ppc/ppc_instr_tables.h index 6349e0b38..e891e3670 100644 --- a/src/alloy/frontend/ppc/ppc_instr_tables.h +++ b/src/xenia/cpu/frontend/ppc/ppc_instr_tables.h @@ -7,16 +7,17 @@ ****************************************************************************** */ -#ifndef ALLOY_FRONTEND_PPC_PPC_INSTR_TABLES_H_ -#define ALLOY_FRONTEND_PPC_PPC_INSTR_TABLES_H_ +#ifndef XENIA_FRONTEND_PPC_PPC_INSTR_TABLES_H_ +#define XENIA_FRONTEND_PPC_PPC_INSTR_TABLES_H_ #include -#include "alloy/frontend/ppc/ppc_instr.h" +#include "xenia/cpu/frontend/ppc/ppc_instr.h" #include "poly/poly.h" #include "poly/string_buffer.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { @@ -1095,6 +1096,7 @@ static InstrType instr_table_scan[] = { } // namespace tables } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_FRONTEND_PPC_PPC_INSTR_TABLES_H_ +#endif // XENIA_FRONTEND_PPC_PPC_INSTR_TABLES_H_ diff --git a/src/alloy/frontend/ppc/ppc_scanner.cc b/src/xenia/cpu/frontend/ppc/ppc_scanner.cc similarity index 97% rename from src/alloy/frontend/ppc/ppc_scanner.cc rename to src/xenia/cpu/frontend/ppc/ppc_scanner.cc index c45521c3d..07488a317 100644 --- a/src/alloy/frontend/ppc/ppc_scanner.cc +++ b/src/xenia/cpu/frontend/ppc/ppc_scanner.cc @@ -7,14 +7,14 @@ ****************************************************************************** */ -#include "alloy/frontend/ppc/ppc_scanner.h" +#include "xenia/cpu/frontend/ppc/ppc_scanner.h" #include #include -#include "alloy/frontend/ppc/ppc_frontend.h" -#include "alloy/frontend/ppc/ppc_instr.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/frontend/ppc/ppc_frontend.h" +#include "xenia/cpu/frontend/ppc/ppc_instr.h" +#include "xenia/cpu/runtime/runtime.h" #include "poly/logging.h" #include "poly/memory.h" #include "xenia/profiling.h" @@ -25,11 +25,12 @@ #define LOGPPC(fmt, ...) POLY_EMPTY_MACRO #endif -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { -using alloy::runtime::FunctionInfo; +using xe::cpu::runtime::FunctionInfo; PPCScanner::PPCScanner(PPCFrontend* frontend) : frontend_(frontend) {} @@ -44,8 +45,6 @@ bool PPCScanner::IsRestGprLr(uint64_t address) { } int PPCScanner::FindExtents(FunctionInfo* symbol_info) { - SCOPE_profile_cpu_f("alloy"); - // This is a simple basic block analyizer. It walks the start address to the // end address looking for branches. Each span of instructions between // branches is considered a basic block. When the last blr (that has no @@ -284,8 +283,6 @@ int PPCScanner::FindExtents(FunctionInfo* symbol_info) { } std::vector PPCScanner::FindBlocks(FunctionInfo* symbol_info) { - SCOPE_profile_cpu_f("alloy"); - Memory* memory = frontend_->memory(); const uint8_t* p = memory->membase(); @@ -364,4 +361,5 @@ std::vector PPCScanner::FindBlocks(FunctionInfo* symbol_info) { } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/frontend/ppc/ppc_scanner.h b/src/xenia/cpu/frontend/ppc/ppc_scanner.h similarity index 80% rename from src/alloy/frontend/ppc/ppc_scanner.h rename to src/xenia/cpu/frontend/ppc/ppc_scanner.h index 556c4df96..a64a014ad 100644 --- a/src/alloy/frontend/ppc/ppc_scanner.h +++ b/src/xenia/cpu/frontend/ppc/ppc_scanner.h @@ -7,14 +7,15 @@ ****************************************************************************** */ -#ifndef ALLOY_FRONTEND_PPC_PPC_SCANNER_H_ -#define ALLOY_FRONTEND_PPC_PPC_SCANNER_H_ +#ifndef XENIA_FRONTEND_PPC_PPC_SCANNER_H_ +#define XENIA_FRONTEND_PPC_PPC_SCANNER_H_ #include -#include "alloy/runtime/symbol_info.h" +#include "xenia/cpu/runtime/symbol_info.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { @@ -43,6 +44,7 @@ class PPCScanner { } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_FRONTEND_PPC_PPC_SCANNER_H_ +#endif // XENIA_FRONTEND_PPC_PPC_SCANNER_H_ diff --git a/src/alloy/frontend/ppc/ppc_translator.cc b/src/xenia/cpu/frontend/ppc/ppc_translator.cc similarity index 90% rename from src/alloy/frontend/ppc/ppc_translator.cc rename to src/xenia/cpu/frontend/ppc/ppc_translator.cc index 4a6f2d1bd..345f35555 100644 --- a/src/alloy/frontend/ppc/ppc_translator.cc +++ b/src/xenia/cpu/frontend/ppc/ppc_translator.cc @@ -7,31 +7,32 @@ ****************************************************************************** */ -#include "alloy/frontend/ppc/ppc_translator.h" +#include "xenia/cpu/frontend/ppc/ppc_translator.h" -#include "alloy/alloy-private.h" -#include "alloy/compiler/compiler_passes.h" -#include "alloy/frontend/ppc/ppc_disasm.h" -#include "alloy/frontend/ppc/ppc_frontend.h" -#include "alloy/frontend/ppc/ppc_hir_builder.h" -#include "alloy/frontend/ppc/ppc_instr.h" -#include "alloy/frontend/ppc/ppc_scanner.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/compiler/compiler_passes.h" +#include "xenia/cpu/cpu-private.h" +#include "xenia/cpu/frontend/ppc/ppc_disasm.h" +#include "xenia/cpu/frontend/ppc/ppc_frontend.h" +#include "xenia/cpu/frontend/ppc/ppc_hir_builder.h" +#include "xenia/cpu/frontend/ppc/ppc_instr.h" +#include "xenia/cpu/frontend/ppc/ppc_scanner.h" +#include "xenia/cpu/runtime/runtime.h" #include "poly/reset_scope.h" #include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { // TODO(benvanik): remove when enums redefined. -using namespace alloy::runtime; +using namespace xe::cpu::runtime; -using alloy::backend::Backend; -using alloy::compiler::Compiler; -using alloy::runtime::Function; -using alloy::runtime::FunctionInfo; -namespace passes = alloy::compiler::passes; +using xe::cpu::backend::Backend; +using xe::cpu::compiler::Compiler; +using xe::cpu::runtime::Function; +using xe::cpu::runtime::FunctionInfo; +namespace passes = xe::cpu::compiler::passes; PPCTranslator::PPCTranslator(PPCFrontend* frontend) : frontend_(frontend) { Backend* backend = frontend->runtime()->backend(); @@ -88,7 +89,7 @@ PPCTranslator::~PPCTranslator() = default; int PPCTranslator::Translate(FunctionInfo* symbol_info, uint32_t debug_info_flags, uint32_t trace_flags, Function** out_function) { - SCOPE_profile_cpu_f("alloy"); + SCOPE_profile_cpu_f("cpu"); // Reset() all caching when we leave. poly::make_reset_scope(builder_); @@ -125,7 +126,7 @@ int PPCTranslator::Translate(FunctionInfo* symbol_info, } if (false) { - alloy::frontend::ppc::DumpAllInstrCounts(); + xe::cpu::frontend::ppc::DumpAllInstrCounts(); } // Emit function. @@ -211,4 +212,5 @@ void PPCTranslator::DumpSource(runtime::FunctionInfo* symbol_info, } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/frontend/ppc/ppc_translator.h b/src/xenia/cpu/frontend/ppc/ppc_translator.h similarity index 79% rename from src/alloy/frontend/ppc/ppc_translator.h rename to src/xenia/cpu/frontend/ppc/ppc_translator.h index 0258939c5..e8bfa8218 100644 --- a/src/alloy/frontend/ppc/ppc_translator.h +++ b/src/xenia/cpu/frontend/ppc/ppc_translator.h @@ -7,17 +7,18 @@ ****************************************************************************** */ -#ifndef ALLOY_FRONTEND_PPC_PPC_TRANSLATOR_H_ -#define ALLOY_FRONTEND_PPC_PPC_TRANSLATOR_H_ +#ifndef XENIA_FRONTEND_PPC_PPC_TRANSLATOR_H_ +#define XENIA_FRONTEND_PPC_PPC_TRANSLATOR_H_ #include -#include "alloy/backend/assembler.h" -#include "alloy/compiler/compiler.h" -#include "alloy/runtime/symbol_info.h" +#include "xenia/cpu/backend/assembler.h" +#include "xenia/cpu/compiler/compiler.h" +#include "xenia/cpu/runtime/symbol_info.h" #include "poly/string_buffer.h" -namespace alloy { +namespace xe { +namespace cpu { namespace frontend { namespace ppc { @@ -49,6 +50,7 @@ class PPCTranslator { } // namespace ppc } // namespace frontend -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_FRONTEND_PPC_PPC_TRANSLATOR_H_ +#endif // XENIA_FRONTEND_PPC_PPC_TRANSLATOR_H_ diff --git a/src/alloy/frontend/ppc/sources.gypi b/src/xenia/cpu/frontend/ppc/sources.gypi similarity index 100% rename from src/alloy/frontend/ppc/sources.gypi rename to src/xenia/cpu/frontend/ppc/sources.gypi diff --git a/src/alloy/frontend/ppc/test/README.md b/src/xenia/cpu/frontend/ppc/test/README.md similarity index 100% rename from src/alloy/frontend/ppc/test/README.md rename to src/xenia/cpu/frontend/ppc/test/README.md diff --git a/src/alloy/frontend/ppc/test/bin/instr_add.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_add.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_add.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_add.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_add.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_add.dis similarity index 72% rename from src/alloy/frontend/ppc/test/bin/instr_add.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_add.dis index 58963620a..edb6347bc 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_add.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_add.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_add.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_add.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_add.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_add.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_add.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_add.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_addc.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_addc.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_addc.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_addc.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_addc.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_addc.dis similarity index 89% rename from src/alloy/frontend/ppc/test/bin/instr_addc.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_addc.dis index c113fd618..87d699b0f 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_addc.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_addc.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_addc.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_addc.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_addc.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_addc.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_addc.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_addc.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_adde.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_adde.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_adde.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_adde.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_adde.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_adde.dis similarity index 95% rename from src/alloy/frontend/ppc/test/bin/instr_adde.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_adde.dis index 6df59b52f..b8b472c03 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_adde.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_adde.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_adde.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_adde.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_adde.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_adde.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_adde.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_adde.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_addic.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_addic.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_addic.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_addic.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_addic.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_addic.dis similarity index 77% rename from src/alloy/frontend/ppc/test/bin/instr_addic.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_addic.dis index 62eb33ef7..89398bf12 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_addic.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_addic.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_addic.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_addic.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_addic.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_addic.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_addic.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_addic.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_addme.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_addme.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_addme.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_addme.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_addme.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_addme.dis similarity index 94% rename from src/alloy/frontend/ppc/test/bin/instr_addme.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_addme.dis index 766dffc5e..2c428c6a5 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_addme.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_addme.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_addme.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_addme.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_addme.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_addme.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_addme.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_addme.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_addze.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_addze.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_addze.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_addze.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_addze.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_addze.dis similarity index 94% rename from src/alloy/frontend/ppc/test/bin/instr_addze.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_addze.dis index 2209d366d..9abe262b3 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_addze.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_addze.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_addze.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_addze.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_addze.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_addze.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_addze.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_addze.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_cntlzd.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_cntlzd.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_cntlzd.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_cntlzd.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_cntlzd.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_cntlzd.dis similarity index 82% rename from src/alloy/frontend/ppc/test/bin/instr_cntlzd.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_cntlzd.dis index f8797e0b1..a88c70f14 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_cntlzd.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_cntlzd.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_cntlzd.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_cntlzd.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_cntlzd.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_cntlzd.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_cntlzd.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_cntlzd.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_cntlzw.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_cntlzw.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_cntlzw.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_cntlzw.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_cntlzw.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_cntlzw.dis similarity index 82% rename from src/alloy/frontend/ppc/test/bin/instr_cntlzw.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_cntlzw.dis index 842693b66..53f45a573 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_cntlzw.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_cntlzw.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_cntlzw.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_cntlzw.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_cntlzw.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_cntlzw.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_cntlzw.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_cntlzw.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_divd.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_divd.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_divd.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_divd.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_divd.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_divd.dis similarity index 89% rename from src/alloy/frontend/ppc/test/bin/instr_divd.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_divd.dis index 5b622f6c1..c2dc23d56 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_divd.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_divd.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_divd.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_divd.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_divd.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_divd.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_divd.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_divd.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_divdu.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_divdu.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_divdu.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_divdu.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_divdu.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_divdu.dis similarity index 90% rename from src/alloy/frontend/ppc/test/bin/instr_divdu.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_divdu.dis index cf260bc48..fb8ff3e88 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_divdu.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_divdu.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_divdu.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_divdu.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_divdu.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_divdu.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_divdu.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_divdu.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_divw.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_divw.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_divw.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_divw.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_divw.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_divw.dis similarity index 92% rename from src/alloy/frontend/ppc/test/bin/instr_divw.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_divw.dis index f4574cf52..93d6f8a0b 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_divw.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_divw.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_divw.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_divw.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_divw.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_divw.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_divw.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_divw.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_divwu.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_divwu.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_divwu.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_divwu.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_divwu.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_divwu.dis similarity index 92% rename from src/alloy/frontend/ppc/test/bin/instr_divwu.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_divwu.dis index 3e5ca892b..6a9c22a0e 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_divwu.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_divwu.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_divwu.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_divwu.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_divwu.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_divwu.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_divwu.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_divwu.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_eqv.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_eqv.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_eqv.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_eqv.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_eqv.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_eqv.dis similarity index 87% rename from src/alloy/frontend/ppc/test/bin/instr_eqv.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_eqv.dis index 4a30e0b5b..c85336360 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_eqv.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_eqv.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_eqv.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_eqv.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_eqv.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_eqv.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_eqv.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_eqv.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_fabs.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_fabs.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_fabs.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_fabs.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_fabs.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_fabs.dis similarity index 78% rename from src/alloy/frontend/ppc/test/bin/instr_fabs.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_fabs.dis index b18e88a5c..f440b2968 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_fabs.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_fabs.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_fabs.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_fabs.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_fabs.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_fabs.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_fabs.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_fabs.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_fsel.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_fsel.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_fsel.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_fsel.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_fsel.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_fsel.dis similarity index 79% rename from src/alloy/frontend/ppc/test/bin/instr_fsel.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_fsel.dis index b2ac1fd55..ff6d87cfb 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_fsel.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_fsel.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_fsel.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_fsel.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_fsel.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_fsel.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_fsel.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_fsel.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvexx.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvexx.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_lvexx.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_lvexx.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvexx.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvexx.dis similarity index 87% rename from src/alloy/frontend/ppc/test/bin/instr_lvexx.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_lvexx.dis index eb1faecc1..e7f263a6d 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_lvexx.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvexx.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_lvexx.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_lvexx.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvexx.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvexx.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_lvexx.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_lvexx.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvl.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvl.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_lvl.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_lvl.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvl.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvl.dis similarity index 59% rename from src/alloy/frontend/ppc/test/bin/instr_lvl.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_lvl.dis index 754f83d1a..358b5f8ce 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_lvl.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvl.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_lvl.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_lvl.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvl.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvl.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_lvl.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_lvl.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvr.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvr.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_lvr.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_lvr.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvr.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvr.dis similarity index 59% rename from src/alloy/frontend/ppc/test/bin/instr_lvr.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_lvr.dis index 41b6065df..fcdaec821 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_lvr.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvr.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_lvr.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_lvr.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvr.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvr.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_lvr.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_lvr.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvsl.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvsl.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_lvsl.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_lvsl.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvsl.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvsl.dis similarity index 78% rename from src/alloy/frontend/ppc/test/bin/instr_lvsl.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_lvsl.dis index 809e14bb3..298d4443a 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_lvsl.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvsl.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_lvsl.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_lvsl.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvsl.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvsl.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_lvsl.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_lvsl.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvsr.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvsr.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_lvsr.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_lvsr.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvsr.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvsr.dis similarity index 78% rename from src/alloy/frontend/ppc/test/bin/instr_lvsr.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_lvsr.dis index 5a7853740..298c614fd 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_lvsr.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvsr.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_lvsr.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_lvsr.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvsr.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_lvsr.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_lvsr.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_lvsr.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhd.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhd.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_mulhd.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulhd.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhd.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhd.dis similarity index 85% rename from src/alloy/frontend/ppc/test/bin/instr_mulhd.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulhd.dis index 8011360e9..436b1a8d2 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_mulhd.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhd.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_mulhd.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_mulhd.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhd.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhd.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_mulhd.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulhd.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhdu.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhdu.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_mulhdu.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulhdu.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhdu.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhdu.dis similarity index 85% rename from src/alloy/frontend/ppc/test/bin/instr_mulhdu.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulhdu.dis index 6f89b2ffb..2f9180b92 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_mulhdu.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhdu.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_mulhdu.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_mulhdu.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhdu.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhdu.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_mulhdu.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulhdu.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhw.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhw.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_mulhw.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulhw.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhw.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhw.dis similarity index 87% rename from src/alloy/frontend/ppc/test/bin/instr_mulhw.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulhw.dis index 451f1efe5..cd8508dff 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_mulhw.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhw.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_mulhw.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_mulhw.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhw.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhw.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_mulhw.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulhw.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhwu.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhwu.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_mulhwu.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulhwu.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhwu.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhwu.dis similarity index 87% rename from src/alloy/frontend/ppc/test/bin/instr_mulhwu.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulhwu.dis index 1be6b924f..e8d0c3e0e 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_mulhwu.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhwu.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_mulhwu.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_mulhwu.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhwu.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulhwu.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_mulhwu.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulhwu.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulld.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulld.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_mulld.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulld.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulld.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulld.dis similarity index 90% rename from src/alloy/frontend/ppc/test/bin/instr_mulld.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulld.dis index 68c20c90b..54dffd70d 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_mulld.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulld.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_mulld.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_mulld.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulld.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulld.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_mulld.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulld.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulli.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulli.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_mulli.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulli.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulli.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulli.dis similarity index 90% rename from src/alloy/frontend/ppc/test/bin/instr_mulli.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulli.dis index bca53580e..5a2b0500d 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_mulli.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulli.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_mulli.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_mulli.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulli.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_mulli.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_mulli.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mulli.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_mullw.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_mullw.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_mullw.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mullw.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_mullw.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_mullw.dis similarity index 92% rename from src/alloy/frontend/ppc/test/bin/instr_mullw.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mullw.dis index 4e295346c..44bf4c4c6 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_mullw.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_mullw.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_mullw.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_mullw.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_mullw.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_mullw.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_mullw.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_mullw.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_neg.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_neg.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_neg.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_neg.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_neg.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_neg.dis similarity index 78% rename from src/alloy/frontend/ppc/test/bin/instr_neg.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_neg.dis index b7a5234ed..d0466abcd 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_neg.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_neg.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_neg.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_neg.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_neg.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_neg.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_neg.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_neg.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_nor.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_nor.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_nor.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_nor.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_nor.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_nor.dis similarity index 76% rename from src/alloy/frontend/ppc/test/bin/instr_nor.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_nor.dis index d1342e34a..d132762c6 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_nor.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_nor.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_nor.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_nor.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_nor.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_nor.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_nor.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_nor.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_ori.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_ori.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_ori.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_ori.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_ori.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_ori.dis similarity index 72% rename from src/alloy/frontend/ppc/test/bin/instr_ori.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_ori.dis index c947e25ad..724c48110 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_ori.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_ori.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_ori.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_ori.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_ori.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_ori.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_ori.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_ori.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicl.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_rldicl.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_rldicl.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_rldicl.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicl.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_rldicl.dis similarity index 94% rename from src/alloy/frontend/ppc/test/bin/instr_rldicl.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_rldicl.dis index 9933b7437..78e51f198 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_rldicl.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_rldicl.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_rldicl.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_rldicl.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicl.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_rldicl.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_rldicl.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_rldicl.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicr.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_rldicr.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_rldicr.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_rldicr.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicr.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_rldicr.dis similarity index 94% rename from src/alloy/frontend/ppc/test/bin/instr_rldicr.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_rldicr.dis index 1be1d4db4..c4e024f2d 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_rldicr.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_rldicr.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_rldicr.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_rldicr.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicr.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_rldicr.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_rldicr.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_rldicr.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_rlwimi.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_rlwimi.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_rlwimi.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_rlwimi.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_rlwimi.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_rlwimi.dis similarity index 59% rename from src/alloy/frontend/ppc/test/bin/instr_rlwimi.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_rlwimi.dis index 59c25b491..4d06c9b15 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_rlwimi.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_rlwimi.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_rlwimi.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_rlwimi.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_rlwimi.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_rlwimi.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_rlwimi.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_rlwimi.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_rlwinm.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_rlwinm.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_rlwinm.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_rlwinm.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_rlwinm.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_rlwinm.dis similarity index 92% rename from src/alloy/frontend/ppc/test/bin/instr_rlwinm.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_rlwinm.dis index f7214a092..117e3cbbb 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_rlwinm.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_rlwinm.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_rlwinm.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_rlwinm.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_rlwinm.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_rlwinm.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_rlwinm.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_rlwinm.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_rlwnm.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_rlwnm.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_rlwnm.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_rlwnm.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_rlwnm.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_rlwnm.dis similarity index 92% rename from src/alloy/frontend/ppc/test/bin/instr_rlwnm.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_rlwnm.dis index 84eb6d939..ff39d3374 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_rlwnm.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_rlwnm.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_rlwnm.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_rlwnm.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_rlwnm.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_rlwnm.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_rlwnm.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_rlwnm.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_sld.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_sld.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_sld.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_sld.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_sld.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_sld.dis similarity index 89% rename from src/alloy/frontend/ppc/test/bin/instr_sld.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_sld.dis index 602090951..9c45d277d 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_sld.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_sld.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_sld.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_sld.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_sld.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_sld.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_sld.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_sld.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_slw.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_slw.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_slw.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_slw.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_slw.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_slw.dis similarity index 91% rename from src/alloy/frontend/ppc/test/bin/instr_slw.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_slw.dis index 654fa9779..89c526003 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_slw.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_slw.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_slw.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_slw.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_slw.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_slw.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_slw.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_slw.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_srad.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_srad.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_srad.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_srad.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_srad.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_srad.dis similarity index 91% rename from src/alloy/frontend/ppc/test/bin/instr_srad.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_srad.dis index ab9b64ac8..47e6c61f6 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_srad.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_srad.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_srad.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_srad.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_srad.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_srad.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_srad.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_srad.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_sradi.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_sradi.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_sradi.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_sradi.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_sradi.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_sradi.dis similarity index 88% rename from src/alloy/frontend/ppc/test/bin/instr_sradi.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_sradi.dis index 65b0f03da..386bc9188 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_sradi.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_sradi.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_sradi.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_sradi.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_sradi.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_sradi.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_sradi.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_sradi.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_sraw.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_sraw.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_sraw.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_sraw.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_sraw.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_sraw.dis similarity index 93% rename from src/alloy/frontend/ppc/test/bin/instr_sraw.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_sraw.dis index fe1d65547..74d6ae0d8 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_sraw.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_sraw.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_sraw.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_sraw.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_sraw.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_sraw.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_sraw.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_sraw.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_srawi.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_srawi.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_srawi.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_srawi.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_srawi.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_srawi.dis similarity index 88% rename from src/alloy/frontend/ppc/test/bin/instr_srawi.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_srawi.dis index 13e05e784..69c8e3907 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_srawi.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_srawi.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_srawi.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_srawi.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_srawi.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_srawi.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_srawi.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_srawi.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_srd.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_srd.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_srd.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_srd.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_srd.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_srd.dis similarity index 89% rename from src/alloy/frontend/ppc/test/bin/instr_srd.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_srd.dis index fc717de5a..0a45b4cf5 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_srd.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_srd.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_srd.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_srd.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_srd.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_srd.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_srd.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_srd.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_srw.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_srw.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_srw.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_srw.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_srw.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_srw.dis similarity index 91% rename from src/alloy/frontend/ppc/test/bin/instr_srw.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_srw.dis index c2e8559c6..70b5dc722 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_srw.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_srw.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_srw.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_srw.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_srw.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_srw.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_srw.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_srw.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_stvew.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_stvew.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_stvew.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_stvew.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_stvew.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_stvew.dis similarity index 82% rename from src/alloy/frontend/ppc/test/bin/instr_stvew.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_stvew.dis index a5c4cac0b..18dba2a35 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_stvew.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_stvew.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_stvew.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_stvew.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_stvew.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_stvew.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_stvew.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_stvew.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_stvl.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_stvl.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_stvl.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_stvl.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_stvl.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_stvl.dis similarity index 72% rename from src/alloy/frontend/ppc/test/bin/instr_stvl.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_stvl.dis index 0339edc32..878d30754 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_stvl.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_stvl.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_stvl.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_stvl.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_stvl.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_stvl.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_stvl.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_stvl.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_stvr.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_stvr.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_stvr.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_stvr.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_stvr.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_stvr.dis similarity index 72% rename from src/alloy/frontend/ppc/test/bin/instr_stvr.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_stvr.dis index 4c9224966..daf9a7d7f 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_stvr.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_stvr.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_stvr.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_stvr.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_stvr.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_stvr.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_stvr.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_stvr.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_subf.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_subf.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_subf.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subf.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_subf.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_subf.dis similarity index 85% rename from src/alloy/frontend/ppc/test/bin/instr_subf.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subf.dis index 79d03d3c6..e80e84e63 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_subf.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_subf.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_subf.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_subf.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_subf.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_subf.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_subf.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subf.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfc.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfc.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_subfc.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subfc.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfc.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfc.dis similarity index 89% rename from src/alloy/frontend/ppc/test/bin/instr_subfc.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subfc.dis index cf77ab4c8..dd4a4d975 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_subfc.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfc.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_subfc.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_subfc.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfc.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfc.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_subfc.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subfc.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfe.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfe.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_subfe.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subfe.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfe.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfe.dis similarity index 89% rename from src/alloy/frontend/ppc/test/bin/instr_subfe.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subfe.dis index fe4f2cbca..b65aa5de6 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_subfe.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfe.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_subfe.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_subfe.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfe.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfe.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_subfe.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subfe.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfic.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfic.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_subfic.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subfic.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfic.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfic.dis similarity index 90% rename from src/alloy/frontend/ppc/test/bin/instr_subfic.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subfic.dis index 17920075a..4ea667e38 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_subfic.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfic.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_subfic.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_subfic.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfic.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfic.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_subfic.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subfic.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfme.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfme.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_subfme.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subfme.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfme.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfme.dis similarity index 95% rename from src/alloy/frontend/ppc/test/bin/instr_subfme.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subfme.dis index f21dd43b5..7e5fc4daf 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_subfme.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfme.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_subfme.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_subfme.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfme.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfme.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_subfme.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subfme.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfze.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfze.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_subfze.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subfze.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfze.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfze.dis similarity index 95% rename from src/alloy/frontend/ppc/test/bin/instr_subfze.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subfze.dis index df4aa687d..fda14ee42 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_subfze.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfze.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_subfze.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_subfze.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfze.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_subfze.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_subfze.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_subfze.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vaddshs.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vaddshs.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vaddshs.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vaddshs.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vaddshs.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vaddshs.dis similarity index 59% rename from src/alloy/frontend/ppc/test/bin/instr_vaddshs.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vaddshs.dis index 62ebbba4c..4663a0442 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vaddshs.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vaddshs.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vaddshs.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vaddshs.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vaddshs.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vaddshs.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vaddshs.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vaddshs.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vadduhm.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vadduhm.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vadduhm.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vadduhm.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vadduhm.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vadduhm.dis similarity index 59% rename from src/alloy/frontend/ppc/test/bin/instr_vadduhm.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vadduhm.dis index 696588275..f60ca05e9 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vadduhm.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vadduhm.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vadduhm.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vadduhm.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vadduhm.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vadduhm.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vadduhm.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vadduhm.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vcfsx.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vcfsx.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vcfsx.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vcfsx.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vcfsx.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vcfsx.dis similarity index 78% rename from src/alloy/frontend/ppc/test/bin/instr_vcfsx.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vcfsx.dis index 4a48e6f4b..441d0b8a4 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vcfsx.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vcfsx.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vcfsx.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vcfsx.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vcfsx.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vcfsx.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vcfsx.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vcfsx.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vcmpxxfp.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vcmpxxfp.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vcmpxxfp.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vcmpxxfp.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vcmpxxfp.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vcmpxxfp.dis similarity index 82% rename from src/alloy/frontend/ppc/test/bin/instr_vcmpxxfp.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vcmpxxfp.dis index cd34b261f..d6233f6d7 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vcmpxxfp.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vcmpxxfp.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vcmpxxfp.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vcmpxxfp.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vcmpxxfp.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vcmpxxfp.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vcmpxxfp.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vcmpxxfp.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vctsxs.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vctsxs.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vctsxs.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vctsxs.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vctsxs.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vctsxs.dis similarity index 85% rename from src/alloy/frontend/ppc/test/bin/instr_vctsxs.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vctsxs.dis index 9416bbc42..9d2c9873a 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vctsxs.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vctsxs.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vctsxs.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vctsxs.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vctsxs.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vctsxs.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vctsxs.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vctsxs.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrghb.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghb.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vmrghb.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghb.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrghb.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghb.dis similarity index 59% rename from src/alloy/frontend/ppc/test/bin/instr_vmrghb.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghb.dis index cad3a1fec..826ceb2ce 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vmrghb.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghb.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vmrghb.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vmrghb.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrghb.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghb.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vmrghb.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghb.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrghh.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghh.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vmrghh.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghh.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrghh.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghh.dis similarity index 59% rename from src/alloy/frontend/ppc/test/bin/instr_vmrghh.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghh.dis index a1c0db44f..49afcbe4b 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vmrghh.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghh.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vmrghh.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vmrghh.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrghh.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghh.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vmrghh.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghh.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrghw.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghw.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vmrghw.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghw.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrghw.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghw.dis similarity index 59% rename from src/alloy/frontend/ppc/test/bin/instr_vmrghw.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghw.dis index 836fa3ecc..f683f053d 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vmrghw.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghw.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vmrghw.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vmrghw.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrghw.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghw.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vmrghw.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrghw.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrglb.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglb.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vmrglb.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglb.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrglb.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglb.dis similarity index 59% rename from src/alloy/frontend/ppc/test/bin/instr_vmrglb.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglb.dis index 0f0eb6667..f98764104 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vmrglb.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglb.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vmrglb.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vmrglb.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrglb.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglb.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vmrglb.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglb.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrglh.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglh.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vmrglh.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglh.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrglh.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglh.dis similarity index 59% rename from src/alloy/frontend/ppc/test/bin/instr_vmrglh.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglh.dis index af22d8548..320a2992d 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vmrglh.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglh.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vmrglh.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vmrglh.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrglh.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglh.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vmrglh.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglh.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrglw.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglw.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vmrglw.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglw.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrglw.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglw.dis similarity index 59% rename from src/alloy/frontend/ppc/test/bin/instr_vmrglw.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglw.dis index 148d0d08a..a5ffbbe60 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vmrglw.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglw.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vmrglw.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vmrglw.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vmrglw.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglw.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vmrglw.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vmrglw.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vperm.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vperm.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vperm.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vperm.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vperm.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vperm.dis similarity index 83% rename from src/alloy/frontend/ppc/test/bin/instr_vperm.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vperm.dis index 353683ccb..498de6fd1 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vperm.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vperm.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vperm.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vperm.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vperm.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vperm.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vperm.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vperm.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vpermwi128.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpermwi128.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vpermwi128.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vpermwi128.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vpermwi128.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpermwi128.dis similarity index 83% rename from src/alloy/frontend/ppc/test/bin/instr_vpermwi128.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vpermwi128.dis index a805aa45d..aad887857 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vpermwi128.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpermwi128.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vpermwi128.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vpermwi128.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vpermwi128.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpermwi128.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vpermwi128.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vpermwi128.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpkd3d128.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vpkd3d128.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpkd3d128.dis similarity index 96% rename from src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vpkd3d128.dis index 9f616af8d..fa39a1d69 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpkd3d128.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vpkd3d128.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vpkd3d128.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpkd3d128.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vpkd3d128.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vpkshss.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpkshss.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vpkshss.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vpkshss.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vpkshss.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpkshss.dis similarity index 71% rename from src/alloy/frontend/ppc/test/bin/instr_vpkshss.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vpkshss.dis index 580c9f973..405c7e9fb 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vpkshss.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpkshss.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vpkshss.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vpkshss.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vpkshss.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpkshss.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vpkshss.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vpkshss.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vpkswss.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpkswss.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vpkswss.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vpkswss.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vpkswss.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpkswss.dis similarity index 71% rename from src/alloy/frontend/ppc/test/bin/instr_vpkswss.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vpkswss.dis index fb1339cc4..b3c4adff1 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vpkswss.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpkswss.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vpkswss.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vpkswss.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vpkswss.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vpkswss.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vpkswss.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vpkswss.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vrfin.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vrfin.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vrfin.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vrfin.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vrfin.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vrfin.dis similarity index 71% rename from src/alloy/frontend/ppc/test/bin/instr_vrfin.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vrfin.dis index 3d7f0a2cd..effd2b8cd 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vrfin.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vrfin.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vrfin.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vrfin.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vrfin.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vrfin.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vrfin.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vrfin.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vrlimi128.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vrlimi128.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vrlimi128.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vrlimi128.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vrlimi128.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vrlimi128.dis similarity index 91% rename from src/alloy/frontend/ppc/test/bin/instr_vrlimi128.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vrlimi128.dis index ddf889e37..d906f0676 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vrlimi128.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vrlimi128.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vrlimi128.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vrlimi128.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vrlimi128.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vrlimi128.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vrlimi128.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vrlimi128.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsel.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsel.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vsel.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vsel.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsel.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsel.dis similarity index 79% rename from src/alloy/frontend/ppc/test/bin/instr_vsel.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vsel.dis index 60fb62fce..2b192debe 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vsel.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsel.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vsel.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vsel.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsel.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsel.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vsel.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vsel.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vslb.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vslb.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vslb.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vslb.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vslb.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vslb.dis similarity index 85% rename from src/alloy/frontend/ppc/test/bin/instr_vslb.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vslb.dis index 0b18bd296..0ccd162a0 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vslb.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vslb.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vslb.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vslb.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vslb.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vslb.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vslb.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vslb.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsldoi.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsldoi.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vsldoi.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vsldoi.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsldoi.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsldoi.dis similarity index 78% rename from src/alloy/frontend/ppc/test/bin/instr_vsldoi.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vsldoi.dis index cc5a2b16a..770e7a0af 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vsldoi.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsldoi.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vsldoi.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vsldoi.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsldoi.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsldoi.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vsldoi.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vsldoi.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vslh.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vslh.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vslh.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vslh.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vslh.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vslh.dis similarity index 87% rename from src/alloy/frontend/ppc/test/bin/instr_vslh.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vslh.dis index 45b8e7e75..ac0904b6c 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vslh.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vslh.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vslh.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vslh.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vslh.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vslh.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vslh.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vslh.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vslw.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vslw.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vslw.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vslw.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vslw.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vslw.dis similarity index 87% rename from src/alloy/frontend/ppc/test/bin/instr_vslw.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vslw.dis index 711653586..3fa611b71 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vslw.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vslw.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vslw.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vslw.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vslw.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vslw.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vslw.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vslw.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltb.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltb.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vspltb.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vspltb.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltb.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltb.dis similarity index 78% rename from src/alloy/frontend/ppc/test/bin/instr_vspltb.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vspltb.dis index 600912aec..0d971e500 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vspltb.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltb.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vspltb.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vspltb.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltb.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltb.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vspltb.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vspltb.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsplth.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsplth.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vsplth.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vsplth.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsplth.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsplth.dis similarity index 78% rename from src/alloy/frontend/ppc/test/bin/instr_vsplth.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vsplth.dis index 4512df243..6981aa708 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vsplth.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsplth.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vsplth.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vsplth.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsplth.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsplth.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vsplth.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vsplth.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltisb.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltisb.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vspltisb.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vspltisb.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltisb.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltisb.dis similarity index 82% rename from src/alloy/frontend/ppc/test/bin/instr_vspltisb.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vspltisb.dis index 8378aca3e..c227f5416 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vspltisb.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltisb.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vspltisb.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vspltisb.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltisb.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltisb.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vspltisb.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vspltisb.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltish.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltish.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vspltish.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vspltish.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltish.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltish.dis similarity index 82% rename from src/alloy/frontend/ppc/test/bin/instr_vspltish.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vspltish.dis index 7eb39018e..19b7dd6fd 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vspltish.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltish.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vspltish.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vspltish.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltish.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltish.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vspltish.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vspltish.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltisw.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltisw.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vspltisw.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vspltisw.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltisw.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltisw.dis similarity index 82% rename from src/alloy/frontend/ppc/test/bin/instr_vspltisw.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vspltisw.dis index 740a94ea9..513ab4200 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vspltisw.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltisw.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vspltisw.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vspltisw.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltisw.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltisw.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vspltisw.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vspltisw.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltw.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltw.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vspltw.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vspltw.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltw.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltw.dis similarity index 78% rename from src/alloy/frontend/ppc/test/bin/instr_vspltw.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vspltw.dis index 147037bae..a6f7f1faa 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vspltw.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltw.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vspltw.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vspltw.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltw.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vspltw.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vspltw.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vspltw.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsubshs.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsubshs.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vsubshs.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vsubshs.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsubshs.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsubshs.dis similarity index 59% rename from src/alloy/frontend/ppc/test/bin/instr_vsubshs.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vsubshs.dis index dc1333a0f..a8035a881 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vsubshs.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsubshs.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vsubshs.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vsubshs.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsubshs.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsubshs.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vsubshs.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vsubshs.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsubuhm.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsubuhm.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vsubuhm.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vsubuhm.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsubuhm.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsubuhm.dis similarity index 59% rename from src/alloy/frontend/ppc/test/bin/instr_vsubuhm.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vsubuhm.dis index af6831d44..0decabb50 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vsubuhm.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsubuhm.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vsubuhm.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vsubuhm.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsubuhm.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vsubuhm.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vsubuhm.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vsubuhm.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vupkd3d128.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vupkd3d128.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vupkd3d128.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vupkd3d128.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vupkd3d128.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vupkd3d128.dis similarity index 88% rename from src/alloy/frontend/ppc/test/bin/instr_vupkd3d128.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vupkd3d128.dis index 8f6225d63..a5dd0c4a4 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vupkd3d128.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vupkd3d128.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vupkd3d128.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vupkd3d128.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vupkd3d128.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vupkd3d128.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vupkd3d128.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vupkd3d128.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vupkhsh.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vupkhsh.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vupkhsh.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vupkhsh.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vupkhsh.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vupkhsh.dis similarity index 71% rename from src/alloy/frontend/ppc/test/bin/instr_vupkhsh.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vupkhsh.dis index 045a34f5e..efb206cb5 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vupkhsh.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vupkhsh.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vupkhsh.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vupkhsh.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vupkhsh.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vupkhsh.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vupkhsh.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vupkhsh.map diff --git a/src/alloy/frontend/ppc/test/bin/instr_vupklsh.bin b/src/xenia/cpu/frontend/ppc/test/bin/instr_vupklsh.bin similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vupklsh.bin rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vupklsh.bin diff --git a/src/alloy/frontend/ppc/test/bin/instr_vupklsh.dis b/src/xenia/cpu/frontend/ppc/test/bin/instr_vupklsh.dis similarity index 71% rename from src/alloy/frontend/ppc/test/bin/instr_vupklsh.dis rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vupklsh.dis index 1d7f0a4c5..c247dc0f3 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_vupklsh.dis +++ b/src/xenia/cpu/frontend/ppc/test/bin/instr_vupklsh.dis @@ -1,5 +1,5 @@ -/vagrant/src/alloy/frontend/ppc/test/bin//instr_vupklsh.o: file format elf64-powerpc +/vagrant/src/xenia/cpu/frontend/ppc/test/bin//instr_vupklsh.o: file format elf64-powerpc Disassembly of section .text: diff --git a/src/alloy/frontend/ppc/test/bin/instr_vupklsh.map b/src/xenia/cpu/frontend/ppc/test/bin/instr_vupklsh.map similarity index 100% rename from src/alloy/frontend/ppc/test/bin/instr_vupklsh.map rename to src/xenia/cpu/frontend/ppc/test/bin/instr_vupklsh.map diff --git a/src/alloy/frontend/ppc/test/instr_add.s b/src/xenia/cpu/frontend/ppc/test/instr_add.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_add.s rename to src/xenia/cpu/frontend/ppc/test/instr_add.s diff --git a/src/alloy/frontend/ppc/test/instr_addc.s b/src/xenia/cpu/frontend/ppc/test/instr_addc.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_addc.s rename to src/xenia/cpu/frontend/ppc/test/instr_addc.s diff --git a/src/alloy/frontend/ppc/test/instr_adde.s b/src/xenia/cpu/frontend/ppc/test/instr_adde.s similarity index 100% rename from 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b/src/xenia/cpu/frontend/ppc/test/instr_vmrghb.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vmrghb.s rename to src/xenia/cpu/frontend/ppc/test/instr_vmrghb.s diff --git a/src/alloy/frontend/ppc/test/instr_vmrghh.s b/src/xenia/cpu/frontend/ppc/test/instr_vmrghh.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vmrghh.s rename to src/xenia/cpu/frontend/ppc/test/instr_vmrghh.s diff --git a/src/alloy/frontend/ppc/test/instr_vmrghw.s b/src/xenia/cpu/frontend/ppc/test/instr_vmrghw.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vmrghw.s rename to src/xenia/cpu/frontend/ppc/test/instr_vmrghw.s diff --git a/src/alloy/frontend/ppc/test/instr_vmrglb.s b/src/xenia/cpu/frontend/ppc/test/instr_vmrglb.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vmrglb.s rename to src/xenia/cpu/frontend/ppc/test/instr_vmrglb.s diff --git a/src/alloy/frontend/ppc/test/instr_vmrglh.s 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b/src/xenia/cpu/frontend/ppc/test/instr_vpkd3d128.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vpkd3d128.s rename to src/xenia/cpu/frontend/ppc/test/instr_vpkd3d128.s diff --git a/src/alloy/frontend/ppc/test/instr_vpkshss.s b/src/xenia/cpu/frontend/ppc/test/instr_vpkshss.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vpkshss.s rename to src/xenia/cpu/frontend/ppc/test/instr_vpkshss.s diff --git a/src/alloy/frontend/ppc/test/instr_vpkswss.s b/src/xenia/cpu/frontend/ppc/test/instr_vpkswss.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vpkswss.s rename to src/xenia/cpu/frontend/ppc/test/instr_vpkswss.s diff --git a/src/alloy/frontend/ppc/test/instr_vrfin.s b/src/xenia/cpu/frontend/ppc/test/instr_vrfin.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vrfin.s rename to src/xenia/cpu/frontend/ppc/test/instr_vrfin.s diff --git a/src/alloy/frontend/ppc/test/instr_vrlimi128.s b/src/xenia/cpu/frontend/ppc/test/instr_vrlimi128.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vrlimi128.s rename to src/xenia/cpu/frontend/ppc/test/instr_vrlimi128.s diff --git a/src/alloy/frontend/ppc/test/instr_vsel.s b/src/xenia/cpu/frontend/ppc/test/instr_vsel.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vsel.s rename to src/xenia/cpu/frontend/ppc/test/instr_vsel.s diff --git a/src/alloy/frontend/ppc/test/instr_vslb.s b/src/xenia/cpu/frontend/ppc/test/instr_vslb.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vslb.s rename to src/xenia/cpu/frontend/ppc/test/instr_vslb.s diff --git a/src/alloy/frontend/ppc/test/instr_vsldoi.s b/src/xenia/cpu/frontend/ppc/test/instr_vsldoi.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vsldoi.s rename to src/xenia/cpu/frontend/ppc/test/instr_vsldoi.s diff --git a/src/alloy/frontend/ppc/test/instr_vslh.s b/src/xenia/cpu/frontend/ppc/test/instr_vslh.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vslh.s rename to src/xenia/cpu/frontend/ppc/test/instr_vslh.s diff --git a/src/alloy/frontend/ppc/test/instr_vslw.s b/src/xenia/cpu/frontend/ppc/test/instr_vslw.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vslw.s rename to src/xenia/cpu/frontend/ppc/test/instr_vslw.s diff --git a/src/alloy/frontend/ppc/test/instr_vspltb.s b/src/xenia/cpu/frontend/ppc/test/instr_vspltb.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vspltb.s rename to src/xenia/cpu/frontend/ppc/test/instr_vspltb.s diff --git a/src/alloy/frontend/ppc/test/instr_vsplth.s b/src/xenia/cpu/frontend/ppc/test/instr_vsplth.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vsplth.s rename to src/xenia/cpu/frontend/ppc/test/instr_vsplth.s diff --git a/src/alloy/frontend/ppc/test/instr_vspltisb.s b/src/xenia/cpu/frontend/ppc/test/instr_vspltisb.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vspltisb.s rename to src/xenia/cpu/frontend/ppc/test/instr_vspltisb.s diff --git a/src/alloy/frontend/ppc/test/instr_vspltish.s b/src/xenia/cpu/frontend/ppc/test/instr_vspltish.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vspltish.s rename to src/xenia/cpu/frontend/ppc/test/instr_vspltish.s diff --git a/src/alloy/frontend/ppc/test/instr_vspltisw.s b/src/xenia/cpu/frontend/ppc/test/instr_vspltisw.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vspltisw.s rename to src/xenia/cpu/frontend/ppc/test/instr_vspltisw.s diff --git a/src/alloy/frontend/ppc/test/instr_vspltw.s b/src/xenia/cpu/frontend/ppc/test/instr_vspltw.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vspltw.s rename to src/xenia/cpu/frontend/ppc/test/instr_vspltw.s diff --git a/src/alloy/frontend/ppc/test/instr_vsubshs.s b/src/xenia/cpu/frontend/ppc/test/instr_vsubshs.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vsubshs.s rename to src/xenia/cpu/frontend/ppc/test/instr_vsubshs.s diff --git a/src/alloy/frontend/ppc/test/instr_vsubuhm.s b/src/xenia/cpu/frontend/ppc/test/instr_vsubuhm.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vsubuhm.s rename to src/xenia/cpu/frontend/ppc/test/instr_vsubuhm.s diff --git a/src/alloy/frontend/ppc/test/instr_vupkd3d128.s b/src/xenia/cpu/frontend/ppc/test/instr_vupkd3d128.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vupkd3d128.s rename to src/xenia/cpu/frontend/ppc/test/instr_vupkd3d128.s diff --git a/src/alloy/frontend/ppc/test/instr_vupkhsh.s b/src/xenia/cpu/frontend/ppc/test/instr_vupkhsh.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vupkhsh.s rename to src/xenia/cpu/frontend/ppc/test/instr_vupkhsh.s diff --git a/src/alloy/frontend/ppc/test/instr_vupklsh.s b/src/xenia/cpu/frontend/ppc/test/instr_vupklsh.s similarity index 100% rename from src/alloy/frontend/ppc/test/instr_vupklsh.s rename to src/xenia/cpu/frontend/ppc/test/instr_vupklsh.s diff --git a/src/alloy/frontend/ppc/test/test.gypi b/src/xenia/cpu/frontend/ppc/test/test.gypi similarity index 79% rename from src/alloy/frontend/ppc/test/test.gypi rename to src/xenia/cpu/frontend/ppc/test/test.gypi index f37d59eaf..5fb138813 100644 --- a/src/alloy/frontend/ppc/test/test.gypi +++ b/src/xenia/cpu/frontend/ppc/test/test.gypi @@ -2,7 +2,7 @@ { 'targets': [ { - 'target_name': 'alloy-ppc-test', + 'target_name': 'xe-cpu-ppc-test', 'type': 'executable', 'msvs_settings': { @@ -12,7 +12,6 @@ }, 'dependencies': [ - 'liballoy', 'libxenia', ], @@ -21,7 +20,7 @@ ], 'sources': [ - 'alloy-ppc-test.cc', + 'xe-cpu-ppc-test.cc', ], }, ], diff --git a/src/alloy/frontend/ppc/test/update.sh b/src/xenia/cpu/frontend/ppc/test/update.sh similarity index 93% rename from src/alloy/frontend/ppc/test/update.sh rename to src/xenia/cpu/frontend/ppc/test/update.sh index 95d2ff9de..8f3bd7b40 100644 --- a/src/alloy/frontend/ppc/test/update.sh +++ b/src/xenia/cpu/frontend/ppc/test/update.sh @@ -3,7 +3,7 @@ set -e THIS_SCRIPT_DIR=$( cd "$( dirname "$0" )" && pwd ) -BINUTILS=$THIS_SCRIPT_DIR/../../../../../third_party/binutils/bin/ +BINUTILS=$THIS_SCRIPT_DIR/../../../../../../third_party/binutils/bin/ PPC_AS=$BINUTILS/powerpc-none-elf-as PPC_LD=$BINUTILS/powerpc-none-elf-ld PPC_OBJDUMP=$BINUTILS/powerpc-none-elf-objdump diff --git a/src/alloy/frontend/ppc/test/alloy-ppc-test.cc b/src/xenia/cpu/frontend/ppc/test/xe-cpu-ppc-test.cc similarity index 92% rename from src/alloy/frontend/ppc/test/alloy-ppc-test.cc rename to src/xenia/cpu/frontend/ppc/test/xe-cpu-ppc-test.cc index cecfb46b0..4a3b50f31 100644 --- a/src/alloy/frontend/ppc/test/alloy-ppc-test.cc +++ b/src/xenia/cpu/frontend/ppc/test/xe-cpu-ppc-test.cc @@ -7,11 +7,11 @@ ****************************************************************************** */ -#include "alloy/alloy.h" -#include "alloy/backend/x64/x64_backend.h" -#include "alloy/frontend/ppc/ppc_context.h" -#include "alloy/frontend/ppc/ppc_frontend.h" -#include "alloy/runtime/raw_module.h" +#include "xenia/cpu/cpu.h" +#include "xenia/cpu/backend/x64/x64_backend.h" +#include "xenia/cpu/frontend/ppc/ppc_context.h" +#include "xenia/cpu/frontend/ppc/ppc_frontend.h" +#include "xenia/cpu/runtime/raw_module.h" #include "poly/main.h" #include "poly/poly.h" @@ -20,26 +20,27 @@ #endif // !WIN32 #include -DEFINE_string(test_path, "src/alloy/frontend/ppc/test/", +DEFINE_string(test_path, "src/xenia/cpu/frontend/ppc/test/", "Directory scanned for test files."); -DEFINE_string(test_bin_path, "src/alloy/frontend/ppc/test/bin/", +DEFINE_string(test_bin_path, "src/xenia/cpu/frontend/ppc/test/bin/", "Directory with binary outputs of the test files."); -namespace alloy { +namespace xe { +namespace cpu { namespace test { -using alloy::frontend::ppc::PPCContext; -using alloy::runtime::Runtime; +using xe::cpu::frontend::ppc::PPCContext; +using xe::cpu::runtime::Runtime; typedef std::vector> AnnotationList; const uint32_t START_ADDRESS = 0x100000; -class ThreadState : public alloy::runtime::ThreadState { +class ThreadState : public xe::cpu::runtime::ThreadState { public: ThreadState(Runtime* runtime, uint32_t thread_id, uint64_t stack_address, size_t stack_size, uint64_t thread_state_address) - : alloy::runtime::ThreadState(runtime, thread_id), + : xe::cpu::runtime::ThreadState(runtime, thread_id), stack_address_(stack_address), stack_size_(stack_size), thread_state_address_(thread_state_address) { @@ -121,7 +122,8 @@ class TestSuite { std::vector test_cases; private: - std::wstring ReplaceExtension(const std::wstring& path, const std::wstring& new_extension) { + std::wstring ReplaceExtension(const std::wstring& path, + const std::wstring& new_extension) { std::wstring result = path; auto last_dot = result.find_last_of('.'); result.replace(result.begin() + last_dot, result.end(), new_extension); @@ -219,11 +221,12 @@ class TestRunner { public: TestRunner() { memory_size = 64 * 1024 * 1024; - memory.reset(new SimpleMemory(memory_size)); + memory.reset(new Memory()); + memory->Initialize(); runtime.reset(new Runtime(memory.get())); auto frontend = - std::make_unique(runtime.get()); + std::make_unique(runtime.get()); runtime->Initialize(std::move(frontend), nullptr); } @@ -235,7 +238,7 @@ class TestRunner { bool Setup(TestSuite& suite) { // Load the binary module. - auto module = std::make_unique(runtime.get()); + auto module = std::make_unique(runtime.get()); if (module->LoadFile(START_ADDRESS, suite.bin_file_path)) { PLOGE("Unable to load test binary %ls", suite.bin_file_path.c_str()); return false; @@ -260,7 +263,7 @@ class TestRunner { } // Execute test. - alloy::runtime::Function* fn; + xe::cpu::runtime::Function* fn; runtime->ResolveFunction(test_case.address, &fn); if (!fn) { PLOGE("Entry function not found"); @@ -297,7 +300,7 @@ class TestRunner { if (!*c) { break; } - char ccs[3] = { c[0], c[1], 0 }; + char ccs[3] = {c[0], c[1], 0}; c += 2; uint32_t b = std::strtoul(ccs, nullptr, 16); *p = static_cast(b); @@ -420,7 +423,8 @@ bool RunTests(const std::wstring& test_name) { int failed_count = 0; int passed_count = 0; - auto test_path_root = poly::fix_path_separators(poly::to_wstring(FLAGS_test_path)); + auto test_path_root = + poly::fix_path_separators(poly::to_wstring(FLAGS_test_path)); std::vector test_files; if (!DiscoverTests(test_path_root, test_files)) { return false; @@ -490,7 +494,8 @@ int main(std::vector& args) { } } // namespace test -} // namespace alloy +} // namespace cpu +} // namespace xe -DEFINE_ENTRY_POINT(L"alloy-ppc-test", L"alloy-ppc-test [test name]", - alloy::test::main); +DEFINE_ENTRY_POINT(L"xe-cpu-ppc-test", L"xe-cpu-ppc-test [test name]", + xe::cpu::test::main); diff --git a/src/alloy/frontend/sources.gypi b/src/xenia/cpu/frontend/sources.gypi similarity index 100% rename from src/alloy/frontend/sources.gypi rename to src/xenia/cpu/frontend/sources.gypi diff --git a/src/alloy/hir/block.cc b/src/xenia/cpu/hir/block.cc similarity index 87% rename from src/alloy/hir/block.cc rename to src/xenia/cpu/hir/block.cc index 41d9b5078..7233f21cd 100644 --- a/src/alloy/hir/block.cc +++ b/src/xenia/cpu/hir/block.cc @@ -7,11 +7,12 @@ ****************************************************************************** */ -#include "alloy/hir/block.h" +#include "xenia/cpu/hir/block.h" -#include "alloy/hir/instr.h" +#include "xenia/cpu/hir/instr.h" -namespace alloy { +namespace xe { +namespace cpu { namespace hir { void Block::AssertNoCycles() { @@ -38,4 +39,5 @@ void Block::AssertNoCycles() { } } // namespace hir -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/hir/block.h b/src/xenia/cpu/hir/block.h similarity index 88% rename from src/alloy/hir/block.h rename to src/xenia/cpu/hir/block.h index 83ec23f06..dcd745600 100644 --- a/src/alloy/hir/block.h +++ b/src/xenia/cpu/hir/block.h @@ -7,8 +7,8 @@ ****************************************************************************** */ -#ifndef ALLOY_HIR_BLOCK_H_ -#define ALLOY_HIR_BLOCK_H_ +#ifndef XENIA_HIR_BLOCK_H_ +#define XENIA_HIR_BLOCK_H_ #include "poly/arena.h" @@ -16,7 +16,8 @@ namespace llvm { class BitVector; } // namespace llvm -namespace alloy { +namespace xe { +namespace cpu { namespace hir { class Block; @@ -66,6 +67,7 @@ class Block { }; } // namespace hir -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_HIR_BLOCK_H_ +#endif // XENIA_HIR_BLOCK_H_ diff --git a/src/alloy/hir/hir_builder.cc b/src/xenia/cpu/hir/hir_builder.cc similarity index 99% rename from src/alloy/hir/hir_builder.cc rename to src/xenia/cpu/hir/hir_builder.cc index 96c7fe526..2ef6f3279 100644 --- a/src/alloy/hir/hir_builder.cc +++ b/src/xenia/cpu/hir/hir_builder.cc @@ -7,18 +7,19 @@ ****************************************************************************** */ -#include "alloy/hir/hir_builder.h" +#include "xenia/cpu/hir/hir_builder.h" -#include "alloy/hir/block.h" -#include "alloy/hir/instr.h" -#include "alloy/hir/label.h" -#include "alloy/runtime/symbol_info.h" +#include "xenia/cpu/hir/block.h" +#include "xenia/cpu/hir/instr.h" +#include "xenia/cpu/hir/label.h" +#include "xenia/cpu/runtime/symbol_info.h" #include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace hir { -using alloy::runtime::FunctionInfo; +using xe::cpu::runtime::FunctionInfo; #define ASSERT_ADDRESS_TYPE(value) #define ASSERT_INTEGER_TYPE(value) @@ -52,8 +53,6 @@ void HIRBuilder::Reset() { } int HIRBuilder::Finalize() { - SCOPE_profile_cpu_f("alloy"); - // Scan blocks in order and add fallthrough branches. These are needed for // analysis passes to work. We may have also added blocks out of order and // need to ensure they fall through in the right order. @@ -158,8 +157,6 @@ void HIRBuilder::DumpOp(poly::StringBuffer* str, OpcodeSignatureType sig_type, } void HIRBuilder::Dump(poly::StringBuffer* str) { - SCOPE_profile_cpu_f("alloy"); - if (attributes_) { str->Append("; attributes = %.8X\n", attributes_); } @@ -1980,4 +1977,5 @@ Value* HIRBuilder::AtomicSub(Value* address, Value* value) { } } // namespace hir -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/hir/hir_builder.h b/src/xenia/cpu/hir/hir_builder.h similarity index 96% rename from src/alloy/hir/hir_builder.h rename to src/xenia/cpu/hir/hir_builder.h index 97da4aaa5..d30adcedf 100644 --- a/src/alloy/hir/hir_builder.h +++ b/src/xenia/cpu/hir/hir_builder.h @@ -7,20 +7,21 @@ ****************************************************************************** */ -#ifndef ALLOY_HIR_HIR_BUILDER_H_ -#define ALLOY_HIR_HIR_BUILDER_H_ +#ifndef XENIA_HIR_HIR_BUILDER_H_ +#define XENIA_HIR_HIR_BUILDER_H_ #include -#include "alloy/hir/block.h" -#include "alloy/hir/instr.h" -#include "alloy/hir/label.h" -#include "alloy/hir/opcodes.h" -#include "alloy/hir/value.h" +#include "xenia/cpu/hir/block.h" +#include "xenia/cpu/hir/instr.h" +#include "xenia/cpu/hir/label.h" +#include "xenia/cpu/hir/opcodes.h" +#include "xenia/cpu/hir/value.h" #include "poly/arena.h" #include "poly/string_buffer.h" -namespace alloy { +namespace xe { +namespace cpu { namespace hir { enum FunctionAttributes { @@ -260,6 +261,7 @@ class HIRBuilder { }; } // namespace hir -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_HIR_HIR_BUILDER_H_ +#endif // XENIA_HIR_HIR_BUILDER_H_ diff --git a/src/alloy/hir/instr.cc b/src/xenia/cpu/hir/instr.cc similarity index 94% rename from src/alloy/hir/instr.cc rename to src/xenia/cpu/hir/instr.cc index fccd93479..796e54f06 100644 --- a/src/alloy/hir/instr.cc +++ b/src/xenia/cpu/hir/instr.cc @@ -7,11 +7,12 @@ ****************************************************************************** */ -#include "alloy/hir/instr.h" +#include "xenia/cpu/hir/instr.h" -#include "alloy/hir/block.h" +#include "xenia/cpu/hir/block.h" -namespace alloy { +namespace xe { +namespace cpu { namespace hir { void Instr::set_src1(Value* value) { @@ -115,4 +116,5 @@ void Instr::Remove() { } } // namespace hir -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/hir/instr.h b/src/xenia/cpu/hir/instr.h similarity index 80% rename from src/alloy/hir/instr.h rename to src/xenia/cpu/hir/instr.h index df676afba..bee06ebe5 100644 --- a/src/alloy/hir/instr.h +++ b/src/xenia/cpu/hir/instr.h @@ -7,19 +7,22 @@ ****************************************************************************** */ -#ifndef ALLOY_HIR_INSTR_H_ -#define ALLOY_HIR_INSTR_H_ +#ifndef XENIA_HIR_INSTR_H_ +#define XENIA_HIR_INSTR_H_ -#include "alloy/hir/opcodes.h" -#include "alloy/hir/value.h" +#include "xenia/cpu/hir/opcodes.h" +#include "xenia/cpu/hir/value.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { class FunctionInfo; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -namespace alloy { +namespace xe { +namespace cpu { namespace hir { class Block; @@ -61,6 +64,7 @@ class Instr { }; } // namespace hir -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_HIR_INSTR_H_ +#endif // XENIA_HIR_INSTR_H_ diff --git a/src/alloy/hir/label.h b/src/xenia/cpu/hir/label.h similarity index 81% rename from src/alloy/hir/label.h rename to src/xenia/cpu/hir/label.h index bea95e7fc..fa86ff535 100644 --- a/src/alloy/hir/label.h +++ b/src/xenia/cpu/hir/label.h @@ -7,10 +7,11 @@ ****************************************************************************** */ -#ifndef ALLOY_HIR_LABEL_H_ -#define ALLOY_HIR_LABEL_H_ +#ifndef XENIA_HIR_LABEL_H_ +#define XENIA_HIR_LABEL_H_ -namespace alloy { +namespace xe { +namespace cpu { namespace hir { class Block; @@ -28,6 +29,7 @@ class Label { }; } // namespace hir -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_HIR_LABEL_H_ +#endif // XENIA_HIR_LABEL_H_ diff --git a/src/alloy/hir/opcodes.cc b/src/xenia/cpu/hir/opcodes.cc similarity index 83% rename from src/alloy/hir/opcodes.cc rename to src/xenia/cpu/hir/opcodes.cc index f7349887f..bbfe0cebe 100644 --- a/src/alloy/hir/opcodes.cc +++ b/src/xenia/cpu/hir/opcodes.cc @@ -7,17 +7,19 @@ ****************************************************************************** */ -#include "alloy/hir/opcodes.h" +#include "xenia/cpu/hir/opcodes.h" -namespace alloy { +namespace xe { +namespace cpu { namespace hir { #define DEFINE_OPCODE(num, name, sig, flags) \ const OpcodeInfo num##_info = { \ flags, sig, name, num, \ }; -#include "alloy/hir/opcodes.inl" +#include "xenia/cpu/hir/opcodes.inl" #undef DEFINE_OPCODE } // namespace hir -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/hir/opcodes.h b/src/xenia/cpu/hir/opcodes.h similarity index 96% rename from src/alloy/hir/opcodes.h rename to src/xenia/cpu/hir/opcodes.h index e14069ed0..108a99fc5 100644 --- a/src/alloy/hir/opcodes.h +++ b/src/xenia/cpu/hir/opcodes.h @@ -7,12 +7,13 @@ ****************************************************************************** */ -#ifndef ALLOY_HIR_OPCODES_H_ -#define ALLOY_HIR_OPCODES_H_ +#ifndef XENIA_HIR_OPCODES_H_ +#define XENIA_HIR_OPCODES_H_ #include -namespace alloy { +namespace xe { +namespace cpu { namespace hir { enum CallFlags { @@ -93,9 +94,7 @@ enum PackType : uint16_t { inline bool IsPackToHi(uint32_t flags) { return (flags & PACK_TYPE_TO_HI) == PACK_TYPE_TO_HI; } -inline bool IsPackToLo(uint32_t flags) { - return !IsPackToHi(flags); -} +inline bool IsPackToLo(uint32_t flags) { return !IsPackToHi(flags); } inline bool IsPackInUnsigned(uint32_t flags) { return (flags & PACK_TYPE_IN_UNSIGNED) == PACK_TYPE_IN_UNSIGNED; } @@ -286,10 +285,11 @@ typedef struct { } OpcodeInfo; #define DEFINE_OPCODE(num, name, sig, flags) extern const OpcodeInfo num##_info; -#include "alloy/hir/opcodes.inl" +#include "xenia/cpu/hir/opcodes.inl" #undef DEFINE_OPCODE } // namespace hir -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_HIR_OPCODES_H_ +#endif // XENIA_HIR_OPCODES_H_ diff --git a/src/alloy/hir/opcodes.inl b/src/xenia/cpu/hir/opcodes.inl similarity index 100% rename from src/alloy/hir/opcodes.inl rename to src/xenia/cpu/hir/opcodes.inl diff --git a/src/alloy/hir/sources.gypi b/src/xenia/cpu/hir/sources.gypi similarity index 100% rename from src/alloy/hir/sources.gypi rename to src/xenia/cpu/hir/sources.gypi diff --git a/src/alloy/hir/value.cc b/src/xenia/cpu/hir/value.cc similarity index 99% rename from src/alloy/hir/value.cc rename to src/xenia/cpu/hir/value.cc index 6c443e575..719967e20 100644 --- a/src/alloy/hir/value.cc +++ b/src/xenia/cpu/hir/value.cc @@ -7,11 +7,12 @@ ****************************************************************************** */ -#include "alloy/hir/value.h" +#include "xenia/cpu/hir/value.h" #include -namespace alloy { +namespace xe { +namespace cpu { namespace hir { Value::Use* Value::AddUse(poly::Arena* arena, Instr* instr) { @@ -618,4 +619,5 @@ bool Value::Compare(Opcode opcode, Value* other) { } } // namespace hir -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/hir/value.h b/src/xenia/cpu/hir/value.h similarity index 98% rename from src/alloy/hir/value.h rename to src/xenia/cpu/hir/value.h index 634bb61c1..a3e4c95f9 100644 --- a/src/alloy/hir/value.h +++ b/src/xenia/cpu/hir/value.h @@ -7,16 +7,17 @@ ****************************************************************************** */ -#ifndef ALLOY_HIR_VALUE_H_ -#define ALLOY_HIR_VALUE_H_ +#ifndef XENIA_HIR_VALUE_H_ +#define XENIA_HIR_VALUE_H_ -#include "alloy/backend/machine_info.h" -#include "alloy/hir/opcodes.h" +#include "xenia/cpu/backend/machine_info.h" +#include "xenia/cpu/hir/opcodes.h" #include "poly/arena.h" #include "poly/poly.h" #include "poly/vec128.h" -namespace alloy { +namespace xe { +namespace cpu { namespace hir { class Instr; @@ -404,6 +405,7 @@ class Value { }; } // namespace hir -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_HIR_VALUE_H_ +#endif // XENIA_HIR_VALUE_H_ diff --git a/src/xenia/cpu/mmio_handler_mac.cc b/src/xenia/cpu/mmio_handler_mac.cc index 9e540ffa2..3c9794fb3 100644 --- a/src/xenia/cpu/mmio_handler_mac.cc +++ b/src/xenia/cpu/mmio_handler_mac.cc @@ -7,15 +7,15 @@ ****************************************************************************** */ -#include +#include "xenia/cpu/mmio_handler.h" #include #include #include -#include -#include +#include "poly/poly.h" +#include "xenia/logging.h" // Mach internal function, not defined in any header. // http://web.mit.edu/darwin/src/modules/xnu/osfmk/man/exc_server.html diff --git a/src/xenia/cpu/processor.cc b/src/xenia/cpu/processor.cc index 2777297d0..8c29701c6 100644 --- a/src/xenia/cpu/processor.cc +++ b/src/xenia/cpu/processor.cc @@ -9,19 +9,17 @@ #include "xenia/cpu/processor.h" -#include "xenia/export_resolver.h" #include "xenia/cpu/cpu-private.h" #include "xenia/cpu/xenon_runtime.h" #include "xenia/cpu/xex_module.h" +#include "xenia/export_resolver.h" -using namespace alloy; -using namespace alloy::backend; -using namespace alloy::frontend::ppc; -using namespace alloy::runtime; -using namespace xe; -using namespace xe::cpu; +namespace xe { +namespace cpu { + +using namespace xe::cpu::backend; +using namespace xe::cpu::runtime; -namespace { void InitializeIfNeeded(); void CleanupOnShutdown(); @@ -42,7 +40,6 @@ void InitializeIfNeeded() { } void CleanupOnShutdown() {} -} Processor::Processor(xe::Memory* memory, ExportResolver* export_resolver) : export_resolver_(export_resolver), @@ -90,7 +87,7 @@ int Processor::Setup() { } std::unique_ptr backend; - // backend.reset(new alloy::backend::x64::X64Backend(runtime)); + // backend.reset(new xe::cpu::backend::x64::X64Backend(runtime)); int result = runtime_->Initialize(std::move(backend)); if (result) { return result; @@ -171,3 +168,6 @@ uint64_t Processor::ExecuteInterrupt(uint32_t cpu, uint64_t address, return result; } + +} // namespace cpu +} // namespace xe diff --git a/src/alloy/runtime/debug_info.cc b/src/xenia/cpu/runtime/debug_info.cc similarity index 95% rename from src/alloy/runtime/debug_info.cc rename to src/xenia/cpu/runtime/debug_info.cc index 5cb9bf0a6..ef5355e8e 100644 --- a/src/alloy/runtime/debug_info.cc +++ b/src/xenia/cpu/runtime/debug_info.cc @@ -7,11 +7,12 @@ ****************************************************************************** */ -#include "alloy/runtime/debug_info.h" +#include "xenia/cpu/runtime/debug_info.h" #include -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { DebugInfo::DebugInfo() @@ -72,4 +73,5 @@ SourceMapEntry* DebugInfo::LookupCodeOffset(uint64_t offset) { } } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/runtime/debug_info.h b/src/xenia/cpu/runtime/debug_info.h similarity index 92% rename from src/alloy/runtime/debug_info.h rename to src/xenia/cpu/runtime/debug_info.h index 4540deecf..207559fce 100644 --- a/src/alloy/runtime/debug_info.h +++ b/src/xenia/cpu/runtime/debug_info.h @@ -7,13 +7,14 @@ ****************************************************************************** */ -#ifndef ALLOY_RUNTIME_DEBUG_INFO_H_ -#define ALLOY_RUNTIME_DEBUG_INFO_H_ +#ifndef XENIA_RUNTIME_DEBUG_INFO_H_ +#define XENIA_RUNTIME_DEBUG_INFO_H_ #include #include -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { enum DebugInfoFlags { @@ -72,6 +73,7 @@ class DebugInfo { }; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_RUNTIME_DEBUG_INFO_H_ +#endif // XENIA_RUNTIME_DEBUG_INFO_H_ diff --git a/src/alloy/runtime/debugger.cc b/src/xenia/cpu/runtime/debugger.cc similarity index 97% rename from src/alloy/runtime/debugger.cc rename to src/xenia/cpu/runtime/debugger.cc index 2ef43f231..b465fd9dc 100644 --- a/src/alloy/runtime/debugger.cc +++ b/src/xenia/cpu/runtime/debugger.cc @@ -7,13 +7,14 @@ ****************************************************************************** */ -#include "alloy/runtime/debugger.h" +#include "xenia/cpu/runtime/debugger.h" #include -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/runtime/runtime.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { Breakpoint::Breakpoint(Type type, uint64_t address) @@ -195,4 +196,5 @@ void Debugger::OnBreakpointHit(ThreadState* thread_state, } } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/runtime/debugger.h b/src/xenia/cpu/runtime/debugger.h similarity index 94% rename from src/alloy/runtime/debugger.h rename to src/xenia/cpu/runtime/debugger.h index a10eaddf0..fe76eaccd 100644 --- a/src/alloy/runtime/debugger.h +++ b/src/xenia/cpu/runtime/debugger.h @@ -7,8 +7,8 @@ ****************************************************************************** */ -#ifndef ALLOY_RUNTIME_DEBUGGER_H_ -#define ALLOY_RUNTIME_DEBUGGER_H_ +#ifndef XENIA_RUNTIME_DEBUGGER_H_ +#define XENIA_RUNTIME_DEBUGGER_H_ #include #include @@ -17,7 +17,8 @@ #include "poly/delegate.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { class Debugger; @@ -117,6 +118,7 @@ class Debugger { }; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_RUNTIME_DEBUGGER_H_ +#endif // XENIA_RUNTIME_DEBUGGER_H_ diff --git a/src/alloy/runtime/entry_table.cc b/src/xenia/cpu/runtime/entry_table.cc similarity index 95% rename from src/alloy/runtime/entry_table.cc rename to src/xenia/cpu/runtime/entry_table.cc index 3cbc015f6..d23c277fa 100644 --- a/src/alloy/runtime/entry_table.cc +++ b/src/xenia/cpu/runtime/entry_table.cc @@ -7,12 +7,13 @@ ****************************************************************************** */ -#include "alloy/runtime/entry_table.h" +#include "xenia/cpu/runtime/entry_table.h" #include "poly/poly.h" #include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { EntryTable::EntryTable() = default; @@ -74,7 +75,6 @@ Entry::Status EntryTable::GetOrCreate(uint64_t address, Entry** out_entry) { } std::vector EntryTable::FindWithAddress(uint64_t address) { - SCOPE_profile_cpu_f("alloy"); std::lock_guard guard(lock_); std::vector fns; for (auto& it : map_) { @@ -89,4 +89,5 @@ std::vector EntryTable::FindWithAddress(uint64_t address) { } } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/runtime/entry_table.h b/src/xenia/cpu/runtime/entry_table.h similarity index 86% rename from src/alloy/runtime/entry_table.h rename to src/xenia/cpu/runtime/entry_table.h index fb70c4847..f371ffb00 100644 --- a/src/alloy/runtime/entry_table.h +++ b/src/xenia/cpu/runtime/entry_table.h @@ -7,14 +7,15 @@ ****************************************************************************** */ -#ifndef ALLOY_RUNTIME_ENTRY_TABLE_H_ -#define ALLOY_RUNTIME_ENTRY_TABLE_H_ +#ifndef XENIA_RUNTIME_ENTRY_TABLE_H_ +#define XENIA_RUNTIME_ENTRY_TABLE_H_ #include #include #include -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { class Function; @@ -50,6 +51,7 @@ class EntryTable { }; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_RUNTIME_ENTRY_TABLE_H_ +#endif // XENIA_RUNTIME_ENTRY_TABLE_H_ diff --git a/src/alloy/runtime/function.cc b/src/xenia/cpu/runtime/function.cc similarity index 92% rename from src/alloy/runtime/function.cc rename to src/xenia/cpu/runtime/function.cc index 41141f218..9eb64f34f 100644 --- a/src/alloy/runtime/function.cc +++ b/src/xenia/cpu/runtime/function.cc @@ -7,15 +7,16 @@ ****************************************************************************** */ -#include "alloy/runtime/function.h" +#include "xenia/cpu/runtime/function.h" -#include "alloy/runtime/debugger.h" -#include "alloy/runtime/symbol_info.h" -#include "alloy/runtime/thread_state.h" +#include "xenia/cpu/runtime/debugger.h" +#include "xenia/cpu/runtime/symbol_info.h" +#include "xenia/cpu/runtime/thread_state.h" #include "poly/logging.h" #include "xdb/protocol.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { Function::Function(FunctionInfo* symbol_info) @@ -66,7 +67,7 @@ Breakpoint* Function::FindBreakpoint(uint64_t address) { } int Function::Call(ThreadState* thread_state, uint64_t return_address) { - //SCOPE_profile_cpu_f("alloy"); + // SCOPE_profile_cpu_f("cpu"); ThreadState* original_thread_state = ThreadState::Get(); if (original_thread_state != thread_state) { @@ -105,7 +106,7 @@ int Function::Call(ThreadState* thread_state, uint64_t return_address) { if (trace_base && true) { auto ev = xdb::protocol::UserCallEvent::Append(trace_base); ev->type = xdb::protocol::EventType::USER_CALL; - ev->call_type = 0; // ? + ev->call_type = 0; // ? ev->thread_id = thread_state->thread_id(); ev->address = static_cast(symbol_info_->address()); } @@ -126,4 +127,5 @@ int Function::Call(ThreadState* thread_state, uint64_t return_address) { } } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/runtime/function.h b/src/xenia/cpu/runtime/function.h similarity index 88% rename from src/alloy/runtime/function.h rename to src/xenia/cpu/runtime/function.h index 6400cc4aa..37090c69c 100644 --- a/src/alloy/runtime/function.h +++ b/src/xenia/cpu/runtime/function.h @@ -7,16 +7,17 @@ ****************************************************************************** */ -#ifndef ALLOY_RUNTIME_FUNCTION_H_ -#define ALLOY_RUNTIME_FUNCTION_H_ +#ifndef XENIA_RUNTIME_FUNCTION_H_ +#define XENIA_RUNTIME_FUNCTION_H_ #include #include #include -#include "alloy/runtime/debug_info.h" +#include "xenia/cpu/runtime/debug_info.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { class Breakpoint; @@ -58,6 +59,7 @@ class Function { }; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_RUNTIME_FUNCTION_H_ +#endif // XENIA_RUNTIME_FUNCTION_H_ diff --git a/src/alloy/runtime/instrument.cc b/src/xenia/cpu/runtime/instrument.cc similarity index 92% rename from src/alloy/runtime/instrument.cc rename to src/xenia/cpu/runtime/instrument.cc index 939348997..eaeddac34 100644 --- a/src/alloy/runtime/instrument.cc +++ b/src/xenia/cpu/runtime/instrument.cc @@ -7,13 +7,14 @@ ****************************************************************************** */ -#include "alloy/runtime/instrument.h" +#include "xenia/cpu/runtime/instrument.h" -#include "alloy/memory.h" -#include "alloy/runtime/function.h" -#include "alloy/runtime/runtime.h" +#include "xenia/memory.h" +#include "xenia/cpu/runtime/function.h" +#include "xenia/cpu/runtime/runtime.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { Instrument::Instrument(Runtime* runtime) @@ -109,4 +110,5 @@ void MemoryInstrument::Access(ThreadState* thread_state, uint64_t address, } } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/runtime/instrument.h b/src/xenia/cpu/runtime/instrument.h similarity index 93% rename from src/alloy/runtime/instrument.h rename to src/xenia/cpu/runtime/instrument.h index 6ef8ce3a6..e400c7e35 100644 --- a/src/alloy/runtime/instrument.h +++ b/src/xenia/cpu/runtime/instrument.h @@ -7,16 +7,19 @@ ****************************************************************************** */ -#ifndef ALLOY_RUNTIME_INSTRUMENT_H_ -#define ALLOY_RUNTIME_INSTRUMENT_H_ +#ifndef XENIA_RUNTIME_INSTRUMENT_H_ +#define XENIA_RUNTIME_INSTRUMENT_H_ #include -namespace alloy { +namespace xe { +namespace cpu { class Memory; -} // namespace alloy +} // namespace cpu +} // namespace xe -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { class Function; @@ -139,6 +142,7 @@ class MemoryInstrument : public Instrument { // // get proc address? } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_RUNTIME_INSTRUMENT_H_ +#endif // XENIA_RUNTIME_INSTRUMENT_H_ diff --git a/src/alloy/runtime/module.cc b/src/xenia/cpu/runtime/module.cc similarity index 97% rename from src/alloy/runtime/module.cc rename to src/xenia/cpu/runtime/module.cc index 3d9dbd0b6..8ff6f6124 100644 --- a/src/alloy/runtime/module.cc +++ b/src/xenia/cpu/runtime/module.cc @@ -7,16 +7,17 @@ ****************************************************************************** */ -#include "alloy/runtime/module.h" +#include "xenia/cpu/runtime/module.h" #include #include -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/runtime/runtime.h" #include "poly/poly.h" #include "xenia/profiling.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { Module::Module(Runtime* runtime) @@ -150,7 +151,7 @@ SymbolInfo::Status Module::DefineVariable(VariableInfo* symbol_info) { } void Module::ForEachFunction(std::function callback) { - SCOPE_profile_cpu_f("alloy"); + SCOPE_profile_cpu_f("cpu"); std::lock_guard guard(lock_); for (auto& symbol_info : list_) { if (symbol_info->type() == SymbolInfo::TYPE_FUNCTION) { @@ -162,7 +163,7 @@ void Module::ForEachFunction(std::function callback) { void Module::ForEachFunction(size_t since, size_t& version, std::function callback) { - SCOPE_profile_cpu_f("alloy"); + SCOPE_profile_cpu_f("cpu"); std::lock_guard guard(lock_); size_t count = list_.size(); version = count; @@ -247,4 +248,5 @@ int Module::ReadMap(const char* file_name) { } } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/runtime/module.h b/src/xenia/cpu/runtime/module.h similarity index 89% rename from src/alloy/runtime/module.h rename to src/xenia/cpu/runtime/module.h index 671743bdf..8ecefc988 100644 --- a/src/alloy/runtime/module.h +++ b/src/xenia/cpu/runtime/module.h @@ -7,8 +7,8 @@ ****************************************************************************** */ -#ifndef ALLOY_RUNTIME_MODULE_H_ -#define ALLOY_RUNTIME_MODULE_H_ +#ifndef XENIA_RUNTIME_MODULE_H_ +#define XENIA_RUNTIME_MODULE_H_ #include #include @@ -16,10 +16,11 @@ #include #include -#include "alloy/memory.h" -#include "alloy/runtime/symbol_info.h" +#include "xenia/memory.h" +#include "xenia/cpu/runtime/symbol_info.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { class Function; @@ -68,6 +69,7 @@ class Module { }; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_RUNTIME_MODULE_H_ +#endif // XENIA_RUNTIME_MODULE_H_ diff --git a/src/alloy/runtime/raw_module.cc b/src/xenia/cpu/runtime/raw_module.cc similarity index 93% rename from src/alloy/runtime/raw_module.cc rename to src/xenia/cpu/runtime/raw_module.cc index 9eaed2ba4..02fbc1d9a 100644 --- a/src/alloy/runtime/raw_module.cc +++ b/src/xenia/cpu/runtime/raw_module.cc @@ -7,12 +7,13 @@ ****************************************************************************** */ -#include "alloy/runtime/raw_module.h" +#include "xenia/cpu/runtime/raw_module.h" #include "poly/platform.h" #include "poly/string.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { RawModule::RawModule(Runtime* runtime) @@ -57,4 +58,5 @@ bool RawModule::ContainsAddress(uint64_t address) { } } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/runtime/raw_module.h b/src/xenia/cpu/runtime/raw_module.h similarity index 81% rename from src/alloy/runtime/raw_module.h rename to src/xenia/cpu/runtime/raw_module.h index af9eb6aed..9cc402872 100644 --- a/src/alloy/runtime/raw_module.h +++ b/src/xenia/cpu/runtime/raw_module.h @@ -7,14 +7,15 @@ ****************************************************************************** */ -#ifndef ALLOY_RUNTIME_RAW_MODULE_H_ -#define ALLOY_RUNTIME_RAW_MODULE_H_ +#ifndef XENIA_RUNTIME_RAW_MODULE_H_ +#define XENIA_RUNTIME_RAW_MODULE_H_ #include -#include "alloy/runtime/module.h" +#include "xenia/cpu/runtime/module.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { class RawModule : public Module { @@ -36,6 +37,7 @@ class RawModule : public Module { }; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_RUNTIME_RAW_MODULE_H_ +#endif // XENIA_RUNTIME_RAW_MODULE_H_ diff --git a/src/alloy/runtime/runtime.cc b/src/xenia/cpu/runtime/runtime.cc similarity index 93% rename from src/alloy/runtime/runtime.cc rename to src/xenia/cpu/runtime/runtime.cc index 0b4fa0b0f..3d6ec62f3 100644 --- a/src/alloy/runtime/runtime.cc +++ b/src/xenia/cpu/runtime/runtime.cc @@ -7,24 +7,25 @@ ****************************************************************************** */ -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/runtime/runtime.h" #include -#include "alloy/runtime/module.h" +#include "xenia/cpu/runtime/module.h" #include "poly/poly.h" #include "xdb/protocol.h" // TODO(benvanik): based on compiler support -#include "alloy/backend/x64/x64_backend.h" +#include "xenia/cpu/backend/x64/x64_backend.h" DEFINE_string(runtime_backend, "any", "Runtime backend [any, x64]."); -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { -using alloy::backend::Backend; -using alloy::frontend::Frontend; +using xe::cpu::backend::Backend; +using xe::cpu::frontend::Frontend; class BuiltinModule : public Module { public: @@ -74,17 +75,17 @@ int Runtime::Initialize(std::unique_ptr frontend, } if (!backend) { -#if defined(ALLOY_HAS_X64_BACKEND) && ALLOY_HAS_X64_BACKEND +#if defined(XENIA_HAS_X64_BACKEND) && XENIA_HAS_X64_BACKEND if (FLAGS_runtime_backend == "x64") { - backend.reset(new alloy::backend::x64::X64Backend(this)); + backend.reset(new xe::cpu::backend::x64::X64Backend(this)); } -#endif // ALLOY_HAS_X64_BACKEND +#endif // XENIA_HAS_X64_BACKEND if (FLAGS_runtime_backend == "any") { -#if defined(ALLOY_HAS_X64_BACKEND) && ALLOY_HAS_X64_BACKEND +#if defined(XENIA_HAS_X64_BACKEND) && XENIA_HAS_X64_BACKEND if (!backend) { - backend.reset(new alloy::backend::x64::X64Backend(this)); + backend.reset(new xe::cpu::backend::x64::X64Backend(this)); } -#endif // ALLOY_HAS_X64_BACKEND +#endif // XENIA_HAS_X64_BACKEND } } @@ -280,4 +281,5 @@ int Runtime::DemandFunction(FunctionInfo* symbol_info, } } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/runtime/runtime.h b/src/xenia/cpu/runtime/runtime.h similarity index 83% rename from src/alloy/runtime/runtime.h rename to src/xenia/cpu/runtime/runtime.h index cc572ac70..7a33e8c90 100644 --- a/src/alloy/runtime/runtime.h +++ b/src/xenia/cpu/runtime/runtime.h @@ -7,23 +7,24 @@ ****************************************************************************** */ -#ifndef ALLOY_RUNTIME_RUNTIME_H_ -#define ALLOY_RUNTIME_RUNTIME_H_ +#ifndef XENIA_RUNTIME_RUNTIME_H_ +#define XENIA_RUNTIME_RUNTIME_H_ #include #include #include -#include "alloy/backend/backend.h" -#include "alloy/frontend/frontend.h" -#include "alloy/memory.h" -#include "alloy/runtime/debugger.h" -#include "alloy/runtime/entry_table.h" -#include "alloy/runtime/module.h" -#include "alloy/runtime/symbol_info.h" -#include "alloy/runtime/thread_state.h" +#include "xenia/cpu/backend/backend.h" +#include "xenia/cpu/frontend/frontend.h" +#include "xenia/memory.h" +#include "xenia/cpu/runtime/debugger.h" +#include "xenia/cpu/runtime/entry_table.h" +#include "xenia/cpu/runtime/module.h" +#include "xenia/cpu/runtime/symbol_info.h" +#include "xenia/cpu/runtime/thread_state.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { class Runtime { @@ -81,6 +82,7 @@ class Runtime { }; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_RUNTIME_RUNTIME_H_ +#endif // XENIA_RUNTIME_RUNTIME_H_ diff --git a/src/alloy/runtime/sources.gypi b/src/xenia/cpu/runtime/sources.gypi similarity index 100% rename from src/alloy/runtime/sources.gypi rename to src/xenia/cpu/runtime/sources.gypi diff --git a/src/alloy/runtime/symbol_info.cc b/src/xenia/cpu/runtime/symbol_info.cc similarity index 92% rename from src/alloy/runtime/symbol_info.cc rename to src/xenia/cpu/runtime/symbol_info.cc index 968534f4b..33e9e566b 100644 --- a/src/alloy/runtime/symbol_info.cc +++ b/src/xenia/cpu/runtime/symbol_info.cc @@ -7,9 +7,10 @@ ****************************************************************************** */ -#include "alloy/runtime/symbol_info.h" +#include "xenia/cpu/runtime/symbol_info.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { SymbolInfo::SymbolInfo(Type type, Module* module, uint64_t address) @@ -44,4 +45,5 @@ VariableInfo::VariableInfo(Module* module, uint64_t address) VariableInfo::~VariableInfo() = default; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/runtime/symbol_info.h b/src/xenia/cpu/runtime/symbol_info.h similarity index 93% rename from src/alloy/runtime/symbol_info.h rename to src/xenia/cpu/runtime/symbol_info.h index 0f71323c1..fdb96192e 100644 --- a/src/alloy/runtime/symbol_info.h +++ b/src/xenia/cpu/runtime/symbol_info.h @@ -7,13 +7,14 @@ ****************************************************************************** */ -#ifndef ALLOY_RUNTIME_SYMBOL_INFO_H_ -#define ALLOY_RUNTIME_SYMBOL_INFO_H_ +#ifndef XENIA_RUNTIME_SYMBOL_INFO_H_ +#define XENIA_RUNTIME_SYMBOL_INFO_H_ #include #include -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { class Function; @@ -104,6 +105,7 @@ class VariableInfo : public SymbolInfo { }; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_RUNTIME_SYMBOL_INFO_H_ +#endif // XENIA_RUNTIME_SYMBOL_INFO_H_ diff --git a/src/alloy/runtime/test_module.cc b/src/xenia/cpu/runtime/test_module.cc similarity index 89% rename from src/alloy/runtime/test_module.cc rename to src/xenia/cpu/runtime/test_module.cc index 8793e448d..40835ecdb 100644 --- a/src/alloy/runtime/test_module.cc +++ b/src/xenia/cpu/runtime/test_module.cc @@ -7,23 +7,24 @@ ****************************************************************************** */ -#include "alloy/runtime/test_module.h" +#include "xenia/cpu/runtime/test_module.h" -#include "alloy/compiler/compiler_passes.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/compiler/compiler_passes.h" +#include "xenia/cpu/runtime/runtime.h" #include "poly/platform.h" #include "poly/reset_scope.h" #include "poly/string.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { -using alloy::backend::Backend; -using alloy::compiler::Compiler; -using alloy::hir::HIRBuilder; -using alloy::runtime::Function; -using alloy::runtime::FunctionInfo; -namespace passes = alloy::compiler::passes; +using xe::cpu::backend::Backend; +using xe::cpu::compiler::Compiler; +using xe::cpu::hir::HIRBuilder; +using xe::cpu::runtime::Function; +using xe::cpu::runtime::FunctionInfo; +namespace passes = xe::cpu::compiler::passes; TestModule::TestModule(Runtime* runtime, const std::string& name, std::function contains_address, @@ -100,4 +101,5 @@ SymbolInfo::Status TestModule::DeclareFunction(uint64_t address, } } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/runtime/test_module.h b/src/xenia/cpu/runtime/test_module.h similarity index 80% rename from src/alloy/runtime/test_module.h rename to src/xenia/cpu/runtime/test_module.h index fc78bd2c0..65669df85 100644 --- a/src/alloy/runtime/test_module.h +++ b/src/xenia/cpu/runtime/test_module.h @@ -7,19 +7,20 @@ ****************************************************************************** */ -#ifndef ALLOY_RUNTIME_TEST_MODULE_H_ -#define ALLOY_RUNTIME_TEST_MODULE_H_ +#ifndef XENIA_RUNTIME_TEST_MODULE_H_ +#define XENIA_RUNTIME_TEST_MODULE_H_ #include #include #include -#include "alloy/backend/assembler.h" -#include "alloy/compiler/compiler.h" -#include "alloy/hir/hir_builder.h" -#include "alloy/runtime/module.h" +#include "xenia/cpu/backend/assembler.h" +#include "xenia/cpu/compiler/compiler.h" +#include "xenia/cpu/hir/hir_builder.h" +#include "xenia/cpu/runtime/module.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { class TestModule : public Module { @@ -47,6 +48,7 @@ class TestModule : public Module { }; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_RUNTIME_TEST_MODULE_H_ +#endif // XENIA_RUNTIME_TEST_MODULE_H_ diff --git a/src/alloy/runtime/thread_state.cc b/src/xenia/cpu/runtime/thread_state.cc similarity index 91% rename from src/alloy/runtime/thread_state.cc rename to src/xenia/cpu/runtime/thread_state.cc index 2c8e28a45..0e515c28f 100644 --- a/src/alloy/runtime/thread_state.cc +++ b/src/xenia/cpu/runtime/thread_state.cc @@ -7,12 +7,13 @@ ****************************************************************************** */ -#include "alloy/runtime/thread_state.h" +#include "xenia/cpu/runtime/thread_state.h" -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/runtime/runtime.h" #include "poly/poly.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { thread_local ThreadState* thread_state_ = nullptr; @@ -51,4 +52,5 @@ ThreadState* ThreadState::Get() { return thread_state_; } uint32_t ThreadState::GetThreadID() { return thread_state_->thread_id_; } } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe diff --git a/src/alloy/runtime/thread_state.h b/src/xenia/cpu/runtime/thread_state.h similarity index 87% rename from src/alloy/runtime/thread_state.h rename to src/xenia/cpu/runtime/thread_state.h index 9e91ff5d7..cd8e9b6f7 100644 --- a/src/alloy/runtime/thread_state.h +++ b/src/xenia/cpu/runtime/thread_state.h @@ -7,14 +7,15 @@ ****************************************************************************** */ -#ifndef ALLOY_RUNTIME_THREAD_STATE_H_ -#define ALLOY_RUNTIME_THREAD_STATE_H_ +#ifndef XENIA_RUNTIME_THREAD_STATE_H_ +#define XENIA_RUNTIME_THREAD_STATE_H_ #include -#include "alloy/memory.h" +#include "xenia/memory.h" -namespace alloy { +namespace xe { +namespace cpu { namespace runtime { class Runtime; @@ -50,6 +51,7 @@ class ThreadState { }; } // namespace runtime -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_RUNTIME_THREAD_STATE_H_ +#endif // XENIA_RUNTIME_THREAD_STATE_H_ diff --git a/src/xenia/cpu/sources.gypi b/src/xenia/cpu/sources.gypi index c519655de..9d9daa4f5 100644 --- a/src/xenia/cpu/sources.gypi +++ b/src/xenia/cpu/sources.gypi @@ -36,4 +36,12 @@ ], }], ], + + 'includes': [ + 'backend/sources.gypi', + 'compiler/sources.gypi', + 'frontend/sources.gypi', + 'hir/sources.gypi', + 'runtime/sources.gypi', + ], } diff --git a/src/alloy/test/test.gypi b/src/xenia/cpu/test/test.gypi similarity index 93% rename from src/alloy/test/test.gypi rename to src/xenia/cpu/test/test.gypi index 0b8a9cb0e..9c894bfd2 100644 --- a/src/alloy/test/test.gypi +++ b/src/xenia/cpu/test/test.gypi @@ -2,7 +2,7 @@ { 'targets': [ { - 'target_name': 'alloy-sandbox', + 'target_name': 'xe-cpu-sandbox', 'type': 'executable', 'msvs_settings': { @@ -12,7 +12,6 @@ }, 'dependencies': [ - 'liballoy', 'libxenia', ], @@ -21,14 +20,14 @@ ], 'sources': [ - 'alloy-sandbox.cc', + 'xe-cpu-sandbox.cc', ], }, ], 'targets': [ { - 'target_name': 'alloy-test', + 'target_name': 'xe-cpu-hir-test', 'type': 'executable', 'msvs_settings': { @@ -38,7 +37,6 @@ }, 'dependencies': [ - 'liballoy', 'libxenia', ], @@ -47,7 +45,9 @@ ], 'sources': [ - 'alloy-test.cc', + 'xe-cpu-hir-test.cc', + 'util.h', + #'test_abs.cc', 'test_add.cc', #'test_add_carry.cc', @@ -111,7 +111,6 @@ #'test_vector_sub.cc', #'test_xor.cc', #'test_zero_extend.cc', - 'util.h', ], }, ], diff --git a/src/alloy/test/test_add.cc b/src/xenia/cpu/test/test_add.cc similarity index 96% rename from src/alloy/test/test_add.cc rename to src/xenia/cpu/test/test_add.cc index 21c5649b1..ff7b86be9 100644 --- a/src/alloy/test/test_add.cc +++ b/src/xenia/cpu/test/test_add.cc @@ -7,18 +7,17 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" #include -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; TEST_CASE("ADD_I8", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreGPR(b, 3, b.ZeroExtend(b.Add(b.Truncate(LoadGPR(b, 4), INT8_TYPE), b.Truncate(LoadGPR(b, 5), INT8_TYPE)), INT64_TYPE)); @@ -83,7 +82,7 @@ TEST_CASE("ADD_I8", "[instr]") { } TEST_CASE("ADD_I8_CARRY", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { auto v = b.Add(b.Truncate(LoadGPR(b, 4), INT8_TYPE), b.Truncate(LoadGPR(b, 5), INT8_TYPE), ARITHMETIC_SET_CARRY); StoreGPR(b, 3, b.ZeroExtend(b.DidCarry(v), INT64_TYPE)); @@ -124,7 +123,7 @@ TEST_CASE("ADD_I8_CARRY", "[instr]") { } TEST_CASE("ADD_I16", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreGPR(b, 3, b.ZeroExtend(b.Add(b.Truncate(LoadGPR(b, 4), INT16_TYPE), b.Truncate(LoadGPR(b, 5), INT16_TYPE)), INT64_TYPE)); @@ -189,7 +188,7 @@ TEST_CASE("ADD_I16", "[instr]") { } TEST_CASE("ADD_I16_CARRY", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { auto v = b.Add(b.Truncate(LoadGPR(b, 4), INT16_TYPE), b.Truncate(LoadGPR(b, 5), INT16_TYPE), ARITHMETIC_SET_CARRY); StoreGPR(b, 3, b.ZeroExtend(b.DidCarry(v), INT64_TYPE)); @@ -230,7 +229,7 @@ TEST_CASE("ADD_I16_CARRY", "[instr]") { } TEST_CASE("ADD_I32", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreGPR(b, 3, b.ZeroExtend(b.Add(b.Truncate(LoadGPR(b, 4), INT32_TYPE), b.Truncate(LoadGPR(b, 5), INT32_TYPE)), INT64_TYPE)); @@ -295,7 +294,7 @@ TEST_CASE("ADD_I32", "[instr]") { } TEST_CASE("ADD_I32_CARRY", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { auto v = b.Add(b.Truncate(LoadGPR(b, 4), INT32_TYPE), b.Truncate(LoadGPR(b, 5), INT32_TYPE), ARITHMETIC_SET_CARRY); StoreGPR(b, 3, b.ZeroExtend(b.DidCarry(v), INT64_TYPE)); @@ -336,7 +335,7 @@ TEST_CASE("ADD_I32_CARRY", "[instr]") { } TEST_CASE("ADD_I64", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreGPR(b, 3, b.Add(LoadGPR(b, 4), LoadGPR(b, 5))); b.Return(); }); @@ -399,7 +398,7 @@ TEST_CASE("ADD_I64", "[instr]") { } TEST_CASE("ADD_I64_CARRY", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { auto v = b.Add(b.Truncate(LoadGPR(b, 4), INT64_TYPE), b.Truncate(LoadGPR(b, 5), INT64_TYPE), ARITHMETIC_SET_CARRY); StoreGPR(b, 3, b.ZeroExtend(b.DidCarry(v), INT64_TYPE)); @@ -440,7 +439,7 @@ TEST_CASE("ADD_I64_CARRY", "[instr]") { } TEST_CASE("ADD_F32", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreFPR(b, 3, b.Convert(b.Add(b.Convert(LoadFPR(b, 4), FLOAT32_TYPE), b.Convert(LoadFPR(b, 5), FLOAT32_TYPE)), FLOAT64_TYPE)); @@ -497,7 +496,7 @@ TEST_CASE("ADD_F32", "[instr]") { } TEST_CASE("ADD_F64", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreFPR(b, 3, b.Add(LoadFPR(b, 4), LoadFPR(b, 5))); b.Return(); }); diff --git a/src/alloy/test/test_byte_swap.cc b/src/xenia/cpu/test/test_byte_swap.cc similarity index 83% rename from src/alloy/test/test_byte_swap.cc rename to src/xenia/cpu/test/test_byte_swap.cc index 9ea221f48..44db4eae0 100644 --- a/src/alloy/test/test_byte_swap.cc +++ b/src/xenia/cpu/test/test_byte_swap.cc @@ -7,17 +7,16 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; using namespace poly; TEST_CASE("BYTE_SWAP_V128", "[instr]") { - TestFunction([](hir::HIRBuilder& b) { + TestFunction([](HIRBuilder& b) { StoreVR(b, 3, b.ByteSwap(LoadVR(b, 4))); b.Return(); }).Run([](PPCContext* ctx) { @@ -29,7 +28,7 @@ TEST_CASE("BYTE_SWAP_V128", "[instr]") { REQUIRE(result == vec128b(3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12)); }); - TestFunction([](hir::HIRBuilder& b) { + TestFunction([](HIRBuilder& b) { StoreVR(b, 3, b.ByteSwap(LoadVR(b, 4))); b.Return(); }).Run([](PPCContext* ctx) { @@ -38,6 +37,7 @@ TEST_CASE("BYTE_SWAP_V128", "[instr]") { }, [](PPCContext* ctx) { auto result = ctx->v[3]; - REQUIRE(result == vec128i(0x0F10130C, 0x0B0C0D0E, 0x0000000A, 0x00000000)); + REQUIRE(result == vec128i(0x0F10130C, 0x0B0C0D0E, + 0x0000000A, 0x00000000)); }); } diff --git a/src/alloy/test/test_extract.cc b/src/xenia/cpu/test/test_extract.cc similarity index 80% rename from src/alloy/test/test_extract.cc rename to src/xenia/cpu/test/test_extract.cc index 2e289709a..f40e030b3 100644 --- a/src/alloy/test/test_extract.cc +++ b/src/xenia/cpu/test/test_extract.cc @@ -7,19 +7,18 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" #include -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; using namespace poly; TEST_CASE("EXTRACT_INT8", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreGPR(b, 3, b.ZeroExtend(b.Extract(LoadVR(b, 4), b.Truncate(LoadGPR(b, 4), INT8_TYPE), INT8_TYPE), @@ -41,27 +40,27 @@ TEST_CASE("EXTRACT_INT8", "[instr]") { TEST_CASE("EXTRACT_INT8_CONSTANT", "[instr]") { for (int i = 0; i < 16; ++i) { - TestFunction([i](hir::HIRBuilder& b) { - StoreGPR(b, 3, - b.ZeroExtend( - b.Extract(LoadVR(b, 4), + TestFunction( + [i](HIRBuilder& b) { + StoreGPR(b, 3, + b.ZeroExtend(b.Extract(LoadVR(b, 4), b.LoadConstant(int8_t(i)), INT8_TYPE), INT64_TYPE)); - b.Return(); - }).Run([i](PPCContext* ctx) { - ctx->r[4] = i; - ctx->v[4] = vec128b(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, - 11, 12, 13, 14, 15); - }, - [i](PPCContext* ctx) { - auto result = ctx->r[3]; - REQUIRE(result == i); - }); + b.Return(); + }).Run([i](PPCContext* ctx) { + ctx->r[4] = i; + ctx->v[4] = vec128b(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15); + }, + [i](PPCContext* ctx) { + auto result = ctx->r[3]; + REQUIRE(result == i); + }); } } TEST_CASE("EXTRACT_INT16", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreGPR(b, 3, b.ZeroExtend(b.Extract(LoadVR(b, 4), b.Truncate(LoadGPR(b, 4), INT8_TYPE), INT16_TYPE), @@ -83,7 +82,7 @@ TEST_CASE("EXTRACT_INT16", "[instr]") { TEST_CASE("EXTRACT_INT16_CONSTANT", "[instr]") { for (int i = 0; i < 8; ++i) { - TestFunction([i](hir::HIRBuilder& b) { + TestFunction([i](HIRBuilder& b) { StoreGPR(b, 3, b.ZeroExtend(b.Extract(LoadVR(b, 4), b.LoadConstant(int8_t(i)), @@ -102,7 +101,7 @@ TEST_CASE("EXTRACT_INT16_CONSTANT", "[instr]") { } TEST_CASE("EXTRACT_INT32", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreGPR(b, 3, b.ZeroExtend(b.Extract(LoadVR(b, 4), b.Truncate(LoadGPR(b, 4), INT8_TYPE), INT32_TYPE), @@ -123,7 +122,7 @@ TEST_CASE("EXTRACT_INT32", "[instr]") { TEST_CASE("EXTRACT_INT32_CONSTANT", "[instr]") { for (int i = 0; i < 4; ++i) { - TestFunction([i](hir::HIRBuilder& b) { + TestFunction([i](HIRBuilder& b) { StoreGPR(b, 3, b.ZeroExtend(b.Extract(LoadVR(b, 4), b.LoadConstant(int8_t(i)), diff --git a/src/xenia/cpu/test/test_insert.cc b/src/xenia/cpu/test/test_insert.cc new file mode 100644 index 000000000..0372db977 --- /dev/null +++ b/src/xenia/cpu/test/test_insert.cc @@ -0,0 +1,83 @@ +/** + ****************************************************************************** + * Xenia : Xbox 360 Emulator Research Project * + ****************************************************************************** + * Copyright 2014 Ben Vanik. All rights reserved. * + * Released under the BSD license - see LICENSE in the root for more details. * + ****************************************************************************** + */ + +#include "xenia/cpu/test/util.h" + +#include + +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; +using namespace poly; + +TEST_CASE("INSERT_INT8", "[instr]") { + for (int i = 0; i < 16; ++i) { + TestFunction test([i](HIRBuilder& b) { + StoreVR(b, 3, b.Insert(LoadVR(b, 4), b.LoadConstant(i), + b.Truncate(LoadGPR(b, 5), INT8_TYPE))); + b.Return(); + }); + test.Run([i](PPCContext* ctx) { + ctx->v[4] = vec128b(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, + 14, 15); + ctx->r[4] = i; + ctx->r[5] = 100 + i; + }, + [i](PPCContext* ctx) { + auto result = ctx->v[3]; + auto expected = vec128b(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15); + expected.i8[i ^ 0x3] = 100 + i; + REQUIRE(result == expected); + }); + } +} + +TEST_CASE("INSERT_INT16", "[instr]") { + for (int i = 0; i < 8; ++i) { + TestFunction test([i](HIRBuilder& b) { + StoreVR(b, 3, b.Insert(LoadVR(b, 4), b.LoadConstant(i), + b.Truncate(LoadGPR(b, 5), INT16_TYPE))); + b.Return(); + }); + test.Run([i](PPCContext* ctx) { + ctx->v[4] = vec128s(0, 1, 2, 3, 4, 5, 6, 7); + ctx->r[4] = i; + ctx->r[5] = 100 + i; + }, + [i](PPCContext* ctx) { + auto result = ctx->v[3]; + auto expected = vec128s(0, 1, 2, 3, 4, 5, 6, 7); + expected.i16[i ^ 0x1] = 100 + i; + REQUIRE(result == expected); + }); + } +} + +TEST_CASE("INSERT_INT32", "[instr]") { + for (int i = 0; i < 4; ++i) { + TestFunction test([i](HIRBuilder& b) { + StoreVR(b, 3, b.Insert(LoadVR(b, 4), b.LoadConstant(i), + b.Truncate(LoadGPR(b, 5), INT32_TYPE))); + b.Return(); + }); + test.Run([i](PPCContext* ctx) { + ctx->v[4] = vec128i(0, 1, 2, 3); + ctx->r[4] = i; + ctx->r[5] = 100 + i; + }, + [i](PPCContext* ctx) { + auto result = ctx->v[3]; + auto expected = vec128i(0, 1, 2, 3); + expected.i32[i] = 100 + i; + REQUIRE(result == expected); + }); + } +} diff --git a/src/alloy/test/test_load_vector_shl_shr.cc b/src/xenia/cpu/test/test_load_vector_shl_shr.cc similarity index 91% rename from src/alloy/test/test_load_vector_shl_shr.cc rename to src/xenia/cpu/test/test_load_vector_shl_shr.cc index 678144afb..cfcd1e62b 100644 --- a/src/alloy/test/test_load_vector_shl_shr.cc +++ b/src/xenia/cpu/test/test_load_vector_shl_shr.cc @@ -7,17 +7,16 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; using namespace poly; TEST_CASE("LOAD_VECTOR_SHL", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.LoadVectorShl(b.Truncate(LoadGPR(b, 4), INT8_TYPE))); b.Return(); }); @@ -48,7 +47,7 @@ TEST_CASE("LOAD_VECTOR_SHL", "[instr]") { } TEST_CASE("LOAD_VECTOR_SHR", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.LoadVectorShr(b.Truncate(LoadGPR(b, 4), INT8_TYPE))); b.Return(); }); diff --git a/src/alloy/test/test_pack.cc b/src/xenia/cpu/test/test_pack.cc similarity index 90% rename from src/alloy/test/test_pack.cc rename to src/xenia/cpu/test/test_pack.cc index 2d7b6fab7..5f93447c2 100644 --- a/src/alloy/test/test_pack.cc +++ b/src/xenia/cpu/test/test_pack.cc @@ -7,17 +7,16 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; using namespace poly; TEST_CASE("PACK_D3DCOLOR", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.Pack(LoadVR(b, 4), PACK_TYPE_D3DCOLOR)); b.Return(); }); @@ -37,7 +36,7 @@ TEST_CASE("PACK_D3DCOLOR", "[instr]") { } TEST_CASE("PACK_FLOAT16_2", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.Pack(LoadVR(b, 4), PACK_TYPE_FLOAT16_2)); b.Return(); }); @@ -65,7 +64,7 @@ TEST_CASE("PACK_FLOAT16_2", "[instr]") { } TEST_CASE("PACK_FLOAT16_4", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.Pack(LoadVR(b, 4), PACK_TYPE_FLOAT16_4)); b.Return(); }); @@ -86,7 +85,7 @@ TEST_CASE("PACK_FLOAT16_4", "[instr]") { } TEST_CASE("PACK_SHORT_2", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.Pack(LoadVR(b, 4), PACK_TYPE_SHORT_2)); b.Return(); }); diff --git a/src/alloy/test/test_permute.cc b/src/xenia/cpu/test/test_permute.cc similarity index 93% rename from src/alloy/test/test_permute.cc rename to src/xenia/cpu/test/test_permute.cc index 3432b0817..1d82cc457 100644 --- a/src/alloy/test/test_permute.cc +++ b/src/xenia/cpu/test/test_permute.cc @@ -7,19 +7,18 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; using namespace poly; TEST_CASE("PERMUTE_V128_BY_INT32_CONSTANT", "[instr]") { { uint32_t mask = PERMUTE_MASK(0, 0, 0, 1, 0, 2, 0, 3); - TestFunction([mask](hir::HIRBuilder& b) { + TestFunction([mask](HIRBuilder& b) { StoreVR(b, 3, b.Permute(b.LoadConstant(mask), LoadVR(b, 4), LoadVR(b, 5), INT32_TYPE)); b.Return(); @@ -34,7 +33,7 @@ TEST_CASE("PERMUTE_V128_BY_INT32_CONSTANT", "[instr]") { } { uint32_t mask = PERMUTE_MASK(1, 0, 1, 1, 1, 2, 1, 3); - TestFunction([mask](hir::HIRBuilder& b) { + TestFunction([mask](HIRBuilder& b) { StoreVR(b, 3, b.Permute(b.LoadConstant(mask), LoadVR(b, 4), LoadVR(b, 5), INT32_TYPE)); b.Return(); @@ -49,7 +48,7 @@ TEST_CASE("PERMUTE_V128_BY_INT32_CONSTANT", "[instr]") { } { uint32_t mask = PERMUTE_MASK(0, 3, 0, 2, 0, 1, 0, 0); - TestFunction([mask](hir::HIRBuilder& b) { + TestFunction([mask](HIRBuilder& b) { StoreVR(b, 3, b.Permute(b.LoadConstant(mask), LoadVR(b, 4), LoadVR(b, 5), INT32_TYPE)); b.Return(); @@ -64,7 +63,7 @@ TEST_CASE("PERMUTE_V128_BY_INT32_CONSTANT", "[instr]") { } { uint32_t mask = PERMUTE_MASK(1, 3, 1, 2, 1, 1, 1, 0); - TestFunction([mask](hir::HIRBuilder& b) { + TestFunction([mask](HIRBuilder& b) { StoreVR(b, 3, b.Permute(b.LoadConstant(mask), LoadVR(b, 4), LoadVR(b, 5), INT32_TYPE)); b.Return(); @@ -80,7 +79,7 @@ TEST_CASE("PERMUTE_V128_BY_INT32_CONSTANT", "[instr]") { } TEST_CASE("PERMUTE_V128_BY_V128", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.Permute(LoadVR(b, 3), LoadVR(b, 4), LoadVR(b, 5), INT8_TYPE)); b.Return(); diff --git a/src/alloy/test/test_sha.cc b/src/xenia/cpu/test/test_sha.cc similarity index 94% rename from src/alloy/test/test_sha.cc rename to src/xenia/cpu/test/test_sha.cc index 9ed155afd..a9368b2f8 100644 --- a/src/alloy/test/test_sha.cc +++ b/src/xenia/cpu/test/test_sha.cc @@ -7,16 +7,15 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; TEST_CASE("SHA_I8", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreGPR(b, 3, b.ZeroExtend(b.Sha(b.Truncate(LoadGPR(b, 4), INT8_TYPE), b.Truncate(LoadGPR(b, 5), INT8_TYPE)), INT64_TYPE)); @@ -65,7 +64,7 @@ TEST_CASE("SHA_I8", "[instr]") { } TEST_CASE("SHA_I16", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreGPR(b, 3, b.ZeroExtend(b.Sha(b.Truncate(LoadGPR(b, 4), INT16_TYPE), b.Truncate(LoadGPR(b, 5), INT8_TYPE)), INT64_TYPE)); @@ -114,7 +113,7 @@ TEST_CASE("SHA_I16", "[instr]") { } TEST_CASE("SHA_I32", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreGPR(b, 3, b.ZeroExtend(b.Sha(b.Truncate(LoadGPR(b, 4), INT32_TYPE), b.Truncate(LoadGPR(b, 5), INT8_TYPE)), INT64_TYPE)); @@ -163,7 +162,7 @@ TEST_CASE("SHA_I32", "[instr]") { } TEST_CASE("SHA_I64", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreGPR(b, 3, b.Sha(b.Truncate(LoadGPR(b, 4), INT64_TYPE), b.Truncate(LoadGPR(b, 5), INT8_TYPE))); b.Return(); diff --git a/src/alloy/test/test_shl.cc b/src/xenia/cpu/test/test_shl.cc similarity index 94% rename from src/alloy/test/test_shl.cc rename to src/xenia/cpu/test/test_shl.cc index 31dc1d772..d12d054b3 100644 --- a/src/alloy/test/test_shl.cc +++ b/src/xenia/cpu/test/test_shl.cc @@ -7,16 +7,15 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; TEST_CASE("SHL_I8", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreGPR(b, 3, b.ZeroExtend(b.Shl(b.Truncate(LoadGPR(b, 4), INT8_TYPE), b.Truncate(LoadGPR(b, 5), INT8_TYPE)), INT64_TYPE)); @@ -65,7 +64,7 @@ TEST_CASE("SHL_I8", "[instr]") { } TEST_CASE("SHL_I16", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreGPR(b, 3, b.ZeroExtend(b.Shl(b.Truncate(LoadGPR(b, 4), INT16_TYPE), b.Truncate(LoadGPR(b, 5), INT8_TYPE)), INT64_TYPE)); @@ -114,7 +113,7 @@ TEST_CASE("SHL_I16", "[instr]") { } TEST_CASE("SHL_I32", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreGPR(b, 3, b.ZeroExtend(b.Shl(b.Truncate(LoadGPR(b, 4), INT32_TYPE), b.Truncate(LoadGPR(b, 5), INT8_TYPE)), INT64_TYPE)); @@ -163,7 +162,7 @@ TEST_CASE("SHL_I32", "[instr]") { } TEST_CASE("SHL_I64", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreGPR(b, 3, b.Shl(b.Truncate(LoadGPR(b, 4), INT64_TYPE), b.Truncate(LoadGPR(b, 5), INT8_TYPE))); b.Return(); diff --git a/src/xenia/cpu/test/test_shr.cc b/src/xenia/cpu/test/test_shr.cc new file mode 100644 index 000000000..703ee9b73 --- /dev/null +++ b/src/xenia/cpu/test/test_shr.cc @@ -0,0 +1,258 @@ +/** + ****************************************************************************** + * Xenia : Xbox 360 Emulator Research Project * + ****************************************************************************** + * Copyright 2014 Ben Vanik. All rights reserved. * + * Released under the BSD license - see LICENSE in the root for more details. * + ****************************************************************************** + */ + +#include "xenia/cpu/test/util.h" + +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; +using namespace poly; + +TEST_CASE("SHR_I8", "[instr]") { + TestFunction test([](HIRBuilder& b) { + StoreGPR(b, 3, b.ZeroExtend(b.Shr(b.Truncate(LoadGPR(b, 4), INT8_TYPE), + b.Truncate(LoadGPR(b, 5), INT8_TYPE)), + INT64_TYPE)); + b.Return(); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0xF0; + ctx->r[5] = 4; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0x0F); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0xFF; + ctx->r[5] = 0; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0xFF); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0xFF; + ctx->r[5] = 1; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0x7F); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0x80; + ctx->r[5] = 8; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0x7F; + ctx->r[5] = 7; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0); + }); +} + +TEST_CASE("SHR_I16", "[instr]") { + TestFunction test([](HIRBuilder& b) { + StoreGPR(b, 3, b.ZeroExtend(b.Shr(b.Truncate(LoadGPR(b, 4), INT16_TYPE), + b.Truncate(LoadGPR(b, 5), INT8_TYPE)), + INT64_TYPE)); + b.Return(); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0xFF00; + ctx->r[5] = 8; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0x00FF); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0xFFFF; + ctx->r[5] = 0; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0xFFFF); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0xFFFE; + ctx->r[5] = 1; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0x7FFF); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0x8000; + ctx->r[5] = 16; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0x7FFF; + ctx->r[5] = 15; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0); + }); +} + +TEST_CASE("SHR_I32", "[instr]") { + TestFunction test([](HIRBuilder& b) { + StoreGPR(b, 3, b.ZeroExtend(b.Shr(b.Truncate(LoadGPR(b, 4), INT32_TYPE), + b.Truncate(LoadGPR(b, 5), INT8_TYPE)), + INT64_TYPE)); + b.Return(); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0xFFFF0000; + ctx->r[5] = 16; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0x0000FFFF); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0xFFFFFFFF; + ctx->r[5] = 0; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0xFFFFFFFF); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0xFFFFFFFE; + ctx->r[5] = 1; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0x7FFFFFFF); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0x80000000; + ctx->r[5] = 32; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0x80000000); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0x7FFFFFFF; + ctx->r[5] = 31; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0); + }); +} + +TEST_CASE("SHR_I64", "[instr]") { + TestFunction test([](HIRBuilder& b) { + StoreGPR(b, 3, b.Shr(b.Truncate(LoadGPR(b, 4), INT64_TYPE), + b.Truncate(LoadGPR(b, 5), INT8_TYPE))); + b.Return(); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0xFFFFFFFF00000000ull; + ctx->r[5] = 32; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0x00000000FFFFFFFFull); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0xFFFFFFFFFFFFFFFFull; + ctx->r[5] = 0; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0xFFFFFFFFFFFFFFFFull); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0xFFFFFFFFFFFFFFFEull; + ctx->r[5] = 1; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0x7FFFFFFFFFFFFFFFull); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0x8000000000000000ull; + ctx->r[5] = 64; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0x8000000000000000ull); + }); + test.Run([](PPCContext* ctx) { + ctx->r[4] = 0x7FFFFFFFFFFFFFFFull; + ctx->r[5] = 63; + }, + [](PPCContext* ctx) { + auto result = static_cast(ctx->r[3]); + REQUIRE(result == 0); + }); +} + +TEST_CASE("SHR_V128", "[instr]") { + TestFunction test([](HIRBuilder& b) { + StoreVR(b, 3, b.Shr(LoadVR(b, 4), b.Truncate(LoadGPR(b, 1), INT8_TYPE))); + b.Return(); + }); + test.Run([](PPCContext* ctx) { + ctx->r[1] = 0; + ctx->v[4] = + vec128i(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); + }, + [](PPCContext* ctx) { + auto result1 = ctx->v[3]; + REQUIRE(result1 == + vec128i(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF)); + }); + test.Run([](PPCContext* ctx) { + ctx->r[1] = 1; + ctx->v[4] = + vec128i(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); + }, + [](PPCContext* ctx) { + auto result1 = ctx->v[3]; + REQUIRE(result1 == + vec128i(0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF)); + }); + test.Run([](PPCContext* ctx) { + ctx->r[1] = 2; + ctx->v[4] = + vec128i(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); + }, + [](PPCContext* ctx) { + auto result1 = ctx->v[3]; + REQUIRE(result1 == + vec128i(0x3FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF)); + }); + test.Run([](PPCContext* ctx) { + ctx->r[1] = 8; + ctx->v[4] = + vec128i(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); + }, + [](PPCContext* ctx) { + auto result1 = ctx->v[3]; + REQUIRE(result1 == + vec128i(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF)); + }); +} diff --git a/src/alloy/test/test_swizzle.cc b/src/xenia/cpu/test/test_swizzle.cc similarity index 85% rename from src/alloy/test/test_swizzle.cc rename to src/xenia/cpu/test/test_swizzle.cc index 341fcc9ae..0c17e0177 100644 --- a/src/alloy/test/test_swizzle.cc +++ b/src/xenia/cpu/test/test_swizzle.cc @@ -7,17 +7,16 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; using namespace poly; TEST_CASE("SWIZZLE_V128", "[instr]") { - TestFunction([](hir::HIRBuilder& b) { + TestFunction([](HIRBuilder& b) { StoreVR(b, 3, b.Swizzle(LoadVR(b, 4), INT32_TYPE, SWIZZLE_MASK(0, 1, 2, 3))); b.Return(); @@ -26,7 +25,7 @@ TEST_CASE("SWIZZLE_V128", "[instr]") { auto result = ctx->v[3]; REQUIRE(result == vec128i(0, 1, 2, 3)); }); - TestFunction([](hir::HIRBuilder& b) { + TestFunction([](HIRBuilder& b) { StoreVR(b, 3, b.Swizzle(LoadVR(b, 4), INT32_TYPE, SWIZZLE_MASK(3, 2, 1, 0))); b.Return(); @@ -35,7 +34,7 @@ TEST_CASE("SWIZZLE_V128", "[instr]") { auto result = ctx->v[3]; REQUIRE(result == vec128i(3, 2, 1, 0)); }); - TestFunction([](hir::HIRBuilder& b) { + TestFunction([](HIRBuilder& b) { StoreVR(b, 3, b.Swizzle(LoadVR(b, 4), INT32_TYPE, SWIZZLE_MASK(1, 1, 2, 2))); b.Return(); diff --git a/src/alloy/test/test_unpack.cc b/src/xenia/cpu/test/test_unpack.cc similarity index 90% rename from src/alloy/test/test_unpack.cc rename to src/xenia/cpu/test/test_unpack.cc index 5a8de821b..3794063d3 100644 --- a/src/alloy/test/test_unpack.cc +++ b/src/xenia/cpu/test/test_unpack.cc @@ -7,17 +7,16 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; using namespace poly; TEST_CASE("UNPACK_D3DCOLOR", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.Unpack(LoadVR(b, 4), PACK_TYPE_D3DCOLOR)); b.Return(); }); @@ -41,7 +40,7 @@ TEST_CASE("UNPACK_D3DCOLOR", "[instr]") { } TEST_CASE("UNPACK_FLOAT16_2", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.Unpack(LoadVR(b, 4), PACK_TYPE_FLOAT16_2)); b.Return(); }); @@ -65,7 +64,7 @@ TEST_CASE("UNPACK_FLOAT16_2", "[instr]") { } TEST_CASE("UNPACK_FLOAT16_4", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.Unpack(LoadVR(b, 4), PACK_TYPE_FLOAT16_4)); b.Return(); }); @@ -85,7 +84,7 @@ TEST_CASE("UNPACK_FLOAT16_4", "[instr]") { } TEST_CASE("UNPACK_SHORT_2", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.Unpack(LoadVR(b, 4), PACK_TYPE_SHORT_2)); b.Return(); }); @@ -115,7 +114,7 @@ TEST_CASE("UNPACK_SHORT_2", "[instr]") { } // TEST_CASE("UNPACK_S8_IN_16_LO", "[instr]") { -// TestFunction test([](hir::HIRBuilder& b) { +// TestFunction test([](HIRBuilder& b) { // StoreVR(b, 3, b.Unpack(LoadVR(b, 4), PACK_TYPE_S8_IN_16_LO)); // b.Return(); // }); @@ -127,7 +126,7 @@ TEST_CASE("UNPACK_SHORT_2", "[instr]") { //} // // TEST_CASE("UNPACK_S8_IN_16_HI", "[instr]") { -// TestFunction test([](hir::HIRBuilder& b) { +// TestFunction test([](HIRBuilder& b) { // StoreVR(b, 3, b.Unpack(LoadVR(b, 4), PACK_TYPE_S8_IN_16_HI)); // b.Return(); // }); @@ -139,7 +138,7 @@ TEST_CASE("UNPACK_SHORT_2", "[instr]") { //} // // TEST_CASE("UNPACK_S16_IN_32_LO", "[instr]") { -// TestFunction test([](hir::HIRBuilder& b) { +// TestFunction test([](HIRBuilder& b) { // StoreVR(b, 3, b.Unpack(LoadVR(b, 4), PACK_TYPE_S16_IN_32_LO)); // b.Return(); // }); @@ -151,7 +150,7 @@ TEST_CASE("UNPACK_SHORT_2", "[instr]") { //} // // TEST_CASE("UNPACK_S16_IN_32_HI", "[instr]") { -// TestFunction test([](hir::HIRBuilder& b) { +// TestFunction test([](HIRBuilder& b) { // StoreVR(b, 3, b.Unpack(LoadVR(b, 4), PACK_TYPE_S16_IN_32_HI)); // b.Return(); // }); diff --git a/src/alloy/test/test_vector_add.cc b/src/xenia/cpu/test/test_vector_add.cc similarity index 93% rename from src/alloy/test/test_vector_add.cc rename to src/xenia/cpu/test/test_vector_add.cc index 5ff7095ce..4c89d774b 100644 --- a/src/alloy/test/test_vector_add.cc +++ b/src/xenia/cpu/test/test_vector_add.cc @@ -7,19 +7,18 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" #include -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; using namespace poly; TEST_CASE("VECTOR_ADD_I8", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), INT8_TYPE)); b.Return(); }); @@ -45,7 +44,7 @@ TEST_CASE("VECTOR_ADD_I8", "[instr]") { } TEST_CASE("VECTOR_ADD_I8_SAT_SIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), INT8_TYPE, ARITHMETIC_SATURATE)); b.Return(); @@ -69,7 +68,7 @@ TEST_CASE("VECTOR_ADD_I8_SAT_SIGNED", "[instr]") { } TEST_CASE("VECTOR_ADD_I8_SAT_UNSIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), INT8_TYPE, ARITHMETIC_SATURATE | ARITHMETIC_UNSIGNED)); b.Return(); @@ -85,7 +84,7 @@ TEST_CASE("VECTOR_ADD_I8_SAT_UNSIGNED", "[instr]") { } TEST_CASE("VECTOR_ADD_I16", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), INT16_TYPE)); b.Return(); }); @@ -116,7 +115,7 @@ TEST_CASE("VECTOR_ADD_I16", "[instr]") { } TEST_CASE("VECTOR_ADD_I16_SAT_SIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), INT16_TYPE, ARITHMETIC_SATURATE)); b.Return(); @@ -140,7 +139,7 @@ TEST_CASE("VECTOR_ADD_I16_SAT_SIGNED", "[instr]") { } TEST_CASE("VECTOR_ADD_I16_SAT_UNSIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), INT16_TYPE, ARITHMETIC_SATURATE | ARITHMETIC_UNSIGNED)); b.Return(); @@ -156,7 +155,7 @@ TEST_CASE("VECTOR_ADD_I16_SAT_UNSIGNED", "[instr]") { } TEST_CASE("VECTOR_ADD_I32", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), INT32_TYPE)); b.Return(); }); @@ -187,7 +186,7 @@ TEST_CASE("VECTOR_ADD_I32", "[instr]") { } TEST_CASE("VECTOR_ADD_I32_SAT_SIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), INT32_TYPE, ARITHMETIC_SATURATE)); b.Return(); @@ -219,7 +218,7 @@ TEST_CASE("VECTOR_ADD_I32_SAT_SIGNED", "[instr]") { } TEST_CASE("VECTOR_ADD_I32_SAT_UNSIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), INT32_TYPE, ARITHMETIC_SATURATE | ARITHMETIC_UNSIGNED)); b.Return(); @@ -243,7 +242,7 @@ TEST_CASE("VECTOR_ADD_I32_SAT_UNSIGNED", "[instr]") { } TEST_CASE("VECTOR_ADD_F32", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), FLOAT32_TYPE)); b.Return(); }); diff --git a/src/alloy/test/test_vector_max.cc b/src/xenia/cpu/test/test_vector_max.cc similarity index 81% rename from src/alloy/test/test_vector_max.cc rename to src/xenia/cpu/test/test_vector_max.cc index 2aa4cda2e..fa1dbcc28 100644 --- a/src/alloy/test/test_vector_max.cc +++ b/src/xenia/cpu/test/test_vector_max.cc @@ -7,19 +7,18 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" #include -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; using namespace poly; TEST_CASE("VECTOR_MAX_I8_SIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorMax(LoadVR(b, 4), LoadVR(b, 5), INT8_TYPE)); b.Return(); }); @@ -37,7 +36,7 @@ TEST_CASE("VECTOR_MAX_I8_SIGNED", "[instr]") { } TEST_CASE("VECTOR_MAX_I8_UNSIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorMax(LoadVR(b, 4), LoadVR(b, 5), INT8_TYPE, ARITHMETIC_UNSIGNED)); b.Return(); @@ -56,7 +55,7 @@ TEST_CASE("VECTOR_MAX_I8_UNSIGNED", "[instr]") { } TEST_CASE("VECTOR_MAX_I16_SIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorMax(LoadVR(b, 4), LoadVR(b, 5), INT16_TYPE)); b.Return(); }); @@ -71,24 +70,24 @@ TEST_CASE("VECTOR_MAX_I16_SIGNED", "[instr]") { } TEST_CASE("VECTOR_MAX_I16_UNSIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorMax(LoadVR(b, 4), LoadVR(b, 5), INT16_TYPE, ARITHMETIC_UNSIGNED)); b.Return(); }); - test.Run([](PPCContext* ctx) { - ctx->v[4] = vec128s(0, 1, 2, 3, 4, 5, -6000, 7); - ctx->v[5] = vec128s(-1000, 1, -2000, 3, 4, USHRT_MAX, 6, 0); - }, - [](PPCContext* ctx) { - auto result = ctx->v[3]; - REQUIRE(result == - vec128s(-1000, 1, -2000, 3, 4, USHRT_MAX, -6000, 7)); - }); + test.Run( + [](PPCContext* ctx) { + ctx->v[4] = vec128s(0, 1, 2, 3, 4, 5, -6000, 7); + ctx->v[5] = vec128s(-1000, 1, -2000, 3, 4, USHRT_MAX, 6, 0); + }, + [](PPCContext* ctx) { + auto result = ctx->v[3]; + REQUIRE(result == vec128s(-1000, 1, -2000, 3, 4, USHRT_MAX, -6000, 7)); + }); } TEST_CASE("VECTOR_MAX_I32_SIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorMax(LoadVR(b, 4), LoadVR(b, 5), INT32_TYPE)); b.Return(); }); @@ -103,7 +102,7 @@ TEST_CASE("VECTOR_MAX_I32_SIGNED", "[instr]") { } TEST_CASE("VECTOR_MAX_I32_UNSIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorMax(LoadVR(b, 4), LoadVR(b, 5), INT32_TYPE, ARITHMETIC_UNSIGNED)); b.Return(); diff --git a/src/alloy/test/test_vector_min.cc b/src/xenia/cpu/test/test_vector_min.cc similarity index 89% rename from src/alloy/test/test_vector_min.cc rename to src/xenia/cpu/test/test_vector_min.cc index 31cf3c18f..caab12d6b 100644 --- a/src/alloy/test/test_vector_min.cc +++ b/src/xenia/cpu/test/test_vector_min.cc @@ -7,19 +7,18 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" #include -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; using namespace poly; TEST_CASE("VECTOR_MIN_I8_SIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorMin(LoadVR(b, 4), LoadVR(b, 5), INT8_TYPE)); b.Return(); }); @@ -37,7 +36,7 @@ TEST_CASE("VECTOR_MIN_I8_SIGNED", "[instr]") { } TEST_CASE("VECTOR_MIN_I8_UNSIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorMin(LoadVR(b, 4), LoadVR(b, 5), INT8_TYPE, ARITHMETIC_UNSIGNED)); b.Return(); @@ -56,7 +55,7 @@ TEST_CASE("VECTOR_MIN_I8_UNSIGNED", "[instr]") { } TEST_CASE("VECTOR_MIN_I16_SIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorMin(LoadVR(b, 4), LoadVR(b, 5), INT16_TYPE)); b.Return(); }); @@ -71,7 +70,7 @@ TEST_CASE("VECTOR_MIN_I16_SIGNED", "[instr]") { } TEST_CASE("VECTOR_MIN_I16_UNSIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorMin(LoadVR(b, 4), LoadVR(b, 5), INT16_TYPE, ARITHMETIC_UNSIGNED)); b.Return(); @@ -87,7 +86,7 @@ TEST_CASE("VECTOR_MIN_I16_UNSIGNED", "[instr]") { } TEST_CASE("VECTOR_MIN_I32_SIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorMin(LoadVR(b, 4), LoadVR(b, 5), INT32_TYPE)); b.Return(); }); @@ -102,7 +101,7 @@ TEST_CASE("VECTOR_MIN_I32_SIGNED", "[instr]") { } TEST_CASE("VECTOR_MIN_I32_UNSIGNED", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorMin(LoadVR(b, 4), LoadVR(b, 5), INT32_TYPE, ARITHMETIC_UNSIGNED)); b.Return(); diff --git a/src/alloy/test/test_vector_rotate_left.cc b/src/xenia/cpu/test/test_vector_rotate_left.cc similarity index 67% rename from src/alloy/test/test_vector_rotate_left.cc rename to src/xenia/cpu/test/test_vector_rotate_left.cc index 80ba706c3..96a71997f 100644 --- a/src/alloy/test/test_vector_rotate_left.cc +++ b/src/xenia/cpu/test/test_vector_rotate_left.cc @@ -8,37 +8,36 @@ */ #include "third_party/xbyak/xbyak/xbyak_bin2hex.h" -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; using namespace poly; TEST_CASE("VECTOR_ROTATE_LEFT_I8", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorRotateLeft(LoadVR(b, 4), LoadVR(b, 5), INT8_TYPE)); b.Return(); }); - test.Run([](PPCContext* ctx) { - ctx->v[4] = vec128b(B00000001); - ctx->v[5] = - vec128b(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - }, - [](PPCContext* ctx) { - auto result = ctx->v[3]; - REQUIRE(result == - vec128b(B00000001, B00000010, B00000100, B00001000, - B00010000, B00100000, B01000000, B10000000, - B00000001, B00000010, B00000100, B00001000, - B00010000, B00100000, B01000000, B10000000)); - }); + test.Run( + [](PPCContext* ctx) { + ctx->v[4] = vec128b(B00000001); + ctx->v[5] = + vec128b(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); + }, + [](PPCContext* ctx) { + auto result = ctx->v[3]; + REQUIRE(result == vec128b(B00000001, B00000010, B00000100, B00001000, + B00010000, B00100000, B01000000, B10000000, + B00000001, B00000010, B00000100, B00001000, + B00010000, B00100000, B01000000, B10000000)); + }); } TEST_CASE("VECTOR_ROTATE_LEFT_I16", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorRotateLeft(LoadVR(b, 4), LoadVR(b, 5), INT16_TYPE)); b.Return(); }); @@ -55,7 +54,7 @@ TEST_CASE("VECTOR_ROTATE_LEFT_I16", "[instr]") { } TEST_CASE("VECTOR_ROTATE_LEFT_I32", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorRotateLeft(LoadVR(b, 4), LoadVR(b, 5), INT32_TYPE)); b.Return(); }); diff --git a/src/alloy/test/test_vector_sha.cc b/src/xenia/cpu/test/test_vector_sha.cc similarity index 81% rename from src/alloy/test/test_vector_sha.cc rename to src/xenia/cpu/test/test_vector_sha.cc index 97c7fa2ea..5506ee775 100644 --- a/src/alloy/test/test_vector_sha.cc +++ b/src/xenia/cpu/test/test_vector_sha.cc @@ -7,17 +7,16 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; using namespace poly; TEST_CASE("VECTOR_SHA_I8", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorSha(LoadVR(b, 4), LoadVR(b, 5), INT8_TYPE)); b.Return(); }); @@ -37,7 +36,7 @@ TEST_CASE("VECTOR_SHA_I8", "[instr]") { } TEST_CASE("VECTOR_SHA_I8_CONSTANT", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorSha(LoadVR(b, 4), b.LoadConstant(vec128b( 0, 1, 2, 8, 4, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)), @@ -58,7 +57,7 @@ TEST_CASE("VECTOR_SHA_I8_CONSTANT", "[instr]") { } TEST_CASE("VECTOR_SHA_I16", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorSha(LoadVR(b, 4), LoadVR(b, 5), INT16_TYPE)); b.Return(); }); @@ -75,7 +74,7 @@ TEST_CASE("VECTOR_SHA_I16", "[instr]") { } TEST_CASE("VECTOR_SHA_I16_CONSTANT", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorSha(LoadVR(b, 4), b.LoadConstant(vec128s( 0, 1, 8, 15, 15, 8, 1, 16)), INT16_TYPE)); @@ -93,7 +92,7 @@ TEST_CASE("VECTOR_SHA_I16_CONSTANT", "[instr]") { } TEST_CASE("VECTOR_SHA_I32", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorSha(LoadVR(b, 4), LoadVR(b, 5), INT32_TYPE)); b.Return(); }); @@ -120,7 +119,7 @@ TEST_CASE("VECTOR_SHA_I32", "[instr]") { } TEST_CASE("VECTOR_SHA_I32_CONSTANT", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorSha(LoadVR(b, 4), b.LoadConstant(vec128i(0, 1, 16, 31)), INT32_TYPE)); @@ -129,18 +128,17 @@ TEST_CASE("VECTOR_SHA_I32_CONSTANT", "[instr]") { INT32_TYPE)); b.Return(); }); - test.Run([](PPCContext* ctx) { - ctx->v[4] = - vec128i(0x7FFFFFFE, 0x7FFFFFFE, 0x7FFFFFFE, 0x7FFFFFFF); - ctx->v[5] = - vec128i(0x80000000, 0xFFFFFFFF, 0x00000001, 0x12345678); - }, - [](PPCContext* ctx) { - auto result1 = ctx->v[3]; - REQUIRE(result1 == - vec128i(0x7FFFFFFE, 0x3FFFFFFF, 0x00007FFF, 0x00000000)); - auto result2 = ctx->v[4]; - REQUIRE(result2 == - vec128i(0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x12345678)); - }); + test.Run( + [](PPCContext* ctx) { + ctx->v[4] = vec128i(0x7FFFFFFE, 0x7FFFFFFE, 0x7FFFFFFE, 0x7FFFFFFF); + ctx->v[5] = vec128i(0x80000000, 0xFFFFFFFF, 0x00000001, 0x12345678); + }, + [](PPCContext* ctx) { + auto result1 = ctx->v[3]; + REQUIRE(result1 == + vec128i(0x7FFFFFFE, 0x3FFFFFFF, 0x00007FFF, 0x00000000)); + auto result2 = ctx->v[4]; + REQUIRE(result2 == + vec128i(0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x12345678)); + }); } diff --git a/src/alloy/test/test_vector_shl.cc b/src/xenia/cpu/test/test_vector_shl.cc similarity index 81% rename from src/alloy/test/test_vector_shl.cc rename to src/xenia/cpu/test/test_vector_shl.cc index bdb0f3b9d..9c80023cf 100644 --- a/src/alloy/test/test_vector_shl.cc +++ b/src/xenia/cpu/test/test_vector_shl.cc @@ -7,17 +7,16 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; using namespace poly; TEST_CASE("VECTOR_SHL_I8", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorShl(LoadVR(b, 4), LoadVR(b, 5), INT8_TYPE)); b.Return(); }); @@ -37,7 +36,7 @@ TEST_CASE("VECTOR_SHL_I8", "[instr]") { } TEST_CASE("VECTOR_SHL_I8_CONSTANT", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorShl(LoadVR(b, 4), b.LoadConstant(vec128b( 0, 1, 2, 8, 4, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)), @@ -58,7 +57,7 @@ TEST_CASE("VECTOR_SHL_I8_CONSTANT", "[instr]") { } TEST_CASE("VECTOR_SHL_I16", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorShl(LoadVR(b, 4), LoadVR(b, 5), INT16_TYPE)); b.Return(); }); @@ -75,7 +74,7 @@ TEST_CASE("VECTOR_SHL_I16", "[instr]") { } TEST_CASE("VECTOR_SHL_I16_CONSTANT", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorShl(LoadVR(b, 4), b.LoadConstant(vec128s( 0, 1, 8, 15, 15, 8, 1, 16)), INT16_TYPE)); @@ -93,7 +92,7 @@ TEST_CASE("VECTOR_SHL_I16_CONSTANT", "[instr]") { } TEST_CASE("VECTOR_SHL_I32", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorShl(LoadVR(b, 4), LoadVR(b, 5), INT32_TYPE)); b.Return(); }); @@ -120,7 +119,7 @@ TEST_CASE("VECTOR_SHL_I32", "[instr]") { } TEST_CASE("VECTOR_SHL_I32_CONSTANT", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorShl(LoadVR(b, 4), b.LoadConstant(vec128i(0, 1, 16, 31)), INT32_TYPE)); @@ -129,18 +128,17 @@ TEST_CASE("VECTOR_SHL_I32_CONSTANT", "[instr]") { INT32_TYPE)); b.Return(); }); - test.Run([](PPCContext* ctx) { - ctx->v[4] = - vec128i(0x7FFFFFFE, 0x7FFFFFFE, 0x7FFFFFFE, 0x7FFFFFFF); - ctx->v[5] = - vec128i(0x80000000, 0xFFFFFFFF, 0x00000001, 0x12345678); - }, - [](PPCContext* ctx) { - auto result1 = ctx->v[3]; - REQUIRE(result1 == - vec128i(0x7FFFFFFE, 0xFFFFFFFC, 0xFFFE0000, 0x80000000)); - auto result2 = ctx->v[4]; - REQUIRE(result2 == - vec128i(0x00000000, 0xFFFF0000, 0x00000002, 0x12345678)); - }); + test.Run( + [](PPCContext* ctx) { + ctx->v[4] = vec128i(0x7FFFFFFE, 0x7FFFFFFE, 0x7FFFFFFE, 0x7FFFFFFF); + ctx->v[5] = vec128i(0x80000000, 0xFFFFFFFF, 0x00000001, 0x12345678); + }, + [](PPCContext* ctx) { + auto result1 = ctx->v[3]; + REQUIRE(result1 == + vec128i(0x7FFFFFFE, 0xFFFFFFFC, 0xFFFE0000, 0x80000000)); + auto result2 = ctx->v[4]; + REQUIRE(result2 == + vec128i(0x00000000, 0xFFFF0000, 0x00000002, 0x12345678)); + }); } diff --git a/src/alloy/test/test_vector_shr.cc b/src/xenia/cpu/test/test_vector_shr.cc similarity index 81% rename from src/alloy/test/test_vector_shr.cc rename to src/xenia/cpu/test/test_vector_shr.cc index e0666e830..6a5cb0223 100644 --- a/src/alloy/test/test_vector_shr.cc +++ b/src/xenia/cpu/test/test_vector_shr.cc @@ -7,17 +7,16 @@ ****************************************************************************** */ -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" -using namespace alloy; -using namespace alloy::hir; -using namespace alloy::runtime; -using namespace alloy::test; -using alloy::frontend::ppc::PPCContext; +using namespace xe::cpu::hir; +using namespace xe::cpu::runtime; +using namespace xe::cpu::test; +using xe::cpu::frontend::ppc::PPCContext; using namespace poly; TEST_CASE("VECTOR_SHR_I8", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorShr(LoadVR(b, 4), LoadVR(b, 5), INT8_TYPE)); b.Return(); }); @@ -37,7 +36,7 @@ TEST_CASE("VECTOR_SHR_I8", "[instr]") { } TEST_CASE("VECTOR_SHR_I8_CONSTANT", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorShr(LoadVR(b, 4), b.LoadConstant(vec128b( 0, 1, 2, 8, 4, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)), @@ -58,7 +57,7 @@ TEST_CASE("VECTOR_SHR_I8_CONSTANT", "[instr]") { } TEST_CASE("VECTOR_SHR_I16", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorShr(LoadVR(b, 4), LoadVR(b, 5), INT16_TYPE)); b.Return(); }); @@ -75,7 +74,7 @@ TEST_CASE("VECTOR_SHR_I16", "[instr]") { } TEST_CASE("VECTOR_SHR_I16_CONSTANT", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorShr(LoadVR(b, 4), b.LoadConstant(vec128s( 0, 1, 8, 15, 15, 8, 1, 16)), INT16_TYPE)); @@ -93,7 +92,7 @@ TEST_CASE("VECTOR_SHR_I16_CONSTANT", "[instr]") { } TEST_CASE("VECTOR_SHR_I32", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorShr(LoadVR(b, 4), LoadVR(b, 5), INT32_TYPE)); b.Return(); }); @@ -120,7 +119,7 @@ TEST_CASE("VECTOR_SHR_I32", "[instr]") { } TEST_CASE("VECTOR_SHR_I32_CONSTANT", "[instr]") { - TestFunction test([](hir::HIRBuilder& b) { + TestFunction test([](HIRBuilder& b) { StoreVR(b, 3, b.VectorShr(LoadVR(b, 4), b.LoadConstant(vec128i(0, 1, 16, 31)), INT32_TYPE)); @@ -129,18 +128,17 @@ TEST_CASE("VECTOR_SHR_I32_CONSTANT", "[instr]") { INT32_TYPE)); b.Return(); }); - test.Run([](PPCContext* ctx) { - ctx->v[4] = - vec128i(0x7FFFFFFE, 0x7FFFFFFE, 0x7FFFFFFE, 0x7FFFFFFF); - ctx->v[5] = - vec128i(0x80000000, 0xFFFFFFFF, 0x00000001, 0x12345678); - }, - [](PPCContext* ctx) { - auto result1 = ctx->v[3]; - REQUIRE(result1 == - vec128i(0x7FFFFFFE, 0x3FFFFFFF, 0x00007FFF, 0x00000000)); - auto result2 = ctx->v[4]; - REQUIRE(result2 == - vec128i(0x00000001, 0x0000FFFF, 0x00000000, 0x12345678)); - }); + test.Run( + [](PPCContext* ctx) { + ctx->v[4] = vec128i(0x7FFFFFFE, 0x7FFFFFFE, 0x7FFFFFFE, 0x7FFFFFFF); + ctx->v[5] = vec128i(0x80000000, 0xFFFFFFFF, 0x00000001, 0x12345678); + }, + [](PPCContext* ctx) { + auto result1 = ctx->v[3]; + REQUIRE(result1 == + vec128i(0x7FFFFFFE, 0x3FFFFFFF, 0x00007FFF, 0x00000000)); + auto result2 = ctx->v[4]; + REQUIRE(result2 == + vec128i(0x00000001, 0x0000FFFF, 0x00000000, 0x12345678)); + }); } diff --git a/src/alloy/test/util.h b/src/xenia/cpu/test/util.h similarity index 78% rename from src/alloy/test/util.h rename to src/xenia/cpu/test/util.h index 46267e498..0ba9f83ed 100644 --- a/src/alloy/test/util.h +++ b/src/xenia/cpu/test/util.h @@ -7,33 +7,34 @@ ****************************************************************************** */ -#ifndef ALLOY_TEST_UTIL_H_ -#define ALLOY_TEST_UTIL_H_ +#ifndef XENIA_TEST_UTIL_H_ +#define XENIA_TEST_UTIL_H_ -#include "alloy/alloy.h" -#include "alloy/backend/x64/x64_backend.h" -#include "alloy/frontend/ppc/ppc_context.h" -#include "alloy/frontend/ppc/ppc_frontend.h" -#include "alloy/hir/hir_builder.h" -#include "alloy/runtime/test_module.h" +#include "xenia/cpu/backend/x64/x64_backend.h" +#include "xenia/cpu/cpu.h" +#include "xenia/cpu/frontend/ppc/ppc_context.h" +#include "xenia/cpu/frontend/ppc/ppc_frontend.h" +#include "xenia/cpu/hir/hir_builder.h" +#include "xenia/cpu/runtime/test_module.h" #include "poly/main.h" #include "poly/poly.h" #include "third_party/catch/single_include/catch.hpp" -#define ALLOY_TEST_X64 1 +#define XENIA_TEST_X64 1 -namespace alloy { +namespace xe { +namespace cpu { namespace test { -using alloy::frontend::ppc::PPCContext; -using alloy::runtime::Runtime; +using xe::cpu::frontend::ppc::PPCContext; +using xe::cpu::runtime::Runtime; -class ThreadState : public alloy::runtime::ThreadState { +class ThreadState : public xe::cpu::runtime::ThreadState { public: ThreadState(Runtime* runtime, uint32_t thread_id, uint64_t stack_address, size_t stack_size, uint64_t thread_state_address) - : alloy::runtime::ThreadState(runtime, thread_id), + : xe::cpu::runtime::ThreadState(runtime, thread_id), stack_address_(stack_address), stack_size_(stack_size), thread_state_address_(thread_state_address) { @@ -82,22 +83,23 @@ class TestFunction { public: TestFunction(std::function generator) { memory_size = 16 * 1024 * 1024; - memory.reset(new SimpleMemory(memory_size)); + memory.reset(new Memory()); + memory->Initialize(); -#if ALLOY_TEST_X64 +#if XENIA_TEST_X64 { auto runtime = std::make_unique(memory.get()); auto frontend = - std::make_unique(runtime.get()); + std::make_unique(runtime.get()); auto backend = - std::make_unique(runtime.get()); + std::make_unique(runtime.get()); runtime->Initialize(std::move(frontend), std::move(backend)); runtimes.emplace_back(std::move(runtime)); } -#endif // ALLOY_TEST_X64 +#endif // XENIA_TEST_X64 for (auto& runtime : runtimes) { - auto module = std::make_unique( + auto module = std::make_unique( runtime.get(), "Test", [](uint64_t address) { return address == 0x1000; }, [generator](hir::HIRBuilder& b) { @@ -118,14 +120,15 @@ class TestFunction { for (auto& runtime : runtimes) { memory->Zero(0, memory_size); - alloy::runtime::Function* fn; + xe::cpu::runtime::Function* fn; runtime->ResolveFunction(0x1000, &fn); uint64_t stack_size = 64 * 1024; uint64_t stack_address = memory_size - stack_size; uint64_t thread_state_address = stack_address - 0x1000; - auto thread_state = std::make_unique( - runtime.get(), 0x100, stack_address, stack_size, thread_state_address); + auto thread_state = + std::make_unique(runtime.get(), 0x100, stack_address, + stack_size, thread_state_address); auto ctx = thread_state->context(); ctx->lr = 0xBEBEBEBE; @@ -164,6 +167,7 @@ inline void StoreVR(hir::HIRBuilder& b, int reg, hir::Value* value) { } } // namespace test -} // namespace alloy +} // namespace cpu +} // namespace xe -#endif // ALLOY_TEST_UTIL_H_ +#endif // XENIA_TEST_UTIL_H_ diff --git a/src/alloy/test/alloy-test.cc b/src/xenia/cpu/test/xe-cpu-hir-test.cc similarity index 83% rename from src/alloy/test/alloy-test.cc rename to src/xenia/cpu/test/xe-cpu-hir-test.cc index 6c493ce05..4695ba64e 100644 --- a/src/alloy/test/alloy-test.cc +++ b/src/xenia/cpu/test/xe-cpu-hir-test.cc @@ -10,13 +10,14 @@ #define CATCH_CONFIG_RUNNER #include "third_party/catch/single_include/catch.hpp" -#include "alloy/test/util.h" +#include "xenia/cpu/test/util.h" -namespace alloy { +namespace xe { +namespace cpu { namespace test { -using alloy::frontend::ppc::PPCContext; -using alloy::runtime::Runtime; +using xe::cpu::frontend::ppc::PPCContext; +using xe::cpu::runtime::Runtime; int main(std::vector& args) { std::vector narrow_args; @@ -39,6 +40,7 @@ int main(std::vector& args) { } } // namespace test -} // namespace alloy +} // namespace cpu +} // namespace xe -DEFINE_ENTRY_POINT(L"alloy-test", L"?", alloy::test::main); +DEFINE_ENTRY_POINT(L"xe-cpu-hir-test", L"?", xe::cpu::test::main); diff --git a/src/alloy/test/alloy-sandbox.cc b/src/xenia/cpu/test/xe-cpu-sandbox.cc similarity index 77% rename from src/alloy/test/alloy-sandbox.cc rename to src/xenia/cpu/test/xe-cpu-sandbox.cc index 8d519cf1b..d1640e967 100644 --- a/src/alloy/test/alloy-sandbox.cc +++ b/src/xenia/cpu/test/xe-cpu-sandbox.cc @@ -7,27 +7,28 @@ ****************************************************************************** */ -#include -#include -#include -#include -#include -#include -#include +#include "xenia/cpu/cpu.h" +#include "xenia/cpu/backend/x64/x64_backend.h" +#include "xenia/cpu/frontend/ppc/ppc_context.h" +#include "xenia/cpu/frontend/ppc/ppc_frontend.h" +#include "xenia/cpu/runtime/raw_module.h" +#include "poly/main.h" +#include "poly/poly.h" #include -namespace alloy { +namespace xe { +namespace cpu { namespace sandbox { -using alloy::frontend::ppc::PPCContext; -using alloy::runtime::Runtime; +using xe::cpu::frontend::ppc::PPCContext; +using xe::cpu::runtime::Runtime; -class ThreadState : public alloy::runtime::ThreadState { +class ThreadState : public xe::cpu::runtime::ThreadState { public: ThreadState(Runtime* runtime, uint32_t thread_id, uint64_t stack_address, size_t stack_size, uint64_t thread_state_address) - : alloy::runtime::ThreadState(runtime, thread_id), + : xe::cpu::runtime::ThreadState(runtime, thread_id), stack_address_(stack_address), stack_size_(stack_size), thread_state_address_(thread_state_address) { @@ -84,15 +85,15 @@ int main(std::vector& args) { auto runtime = std::make_unique(memory.get()); auto frontend = - std::make_unique(runtime.get()); - std::unique_ptr backend; + std::make_unique(runtime.get()); + std::unique_ptr backend; // backend = - // std::make_unique(runtime.get()); + // std::make_unique(runtime.get()); // backend = - // std::make_unique(runtime.get()); + // std::make_unique(runtime.get()); runtime->Initialize(std::move(frontend), std::move(backend)); - auto module = std::make_unique(runtime.get()); + auto module = std::make_unique(runtime.get()); module->LoadFile(0x00001000, L"test\\codegen\\instr_add.bin"); runtime->AddModule(std::move(module)); @@ -103,7 +104,7 @@ int main(std::vector& args) { auto thread_state = std::make_unique( runtime.get(), 100, stack_address, stack_size, thread_state_address); - alloy::runtime::Function* fn; + xe::cpu::runtime::Function* fn; runtime->ResolveFunction(0x1000, &fn); auto ctx = thread_state->context(); ctx->lr = 0xBEBEBEBE; @@ -126,6 +127,7 @@ int main(std::vector& args) { } } // namespace sandbox -} // namespace alloy +} // namespace cpu +} // namespace xe -DEFINE_ENTRY_POINT(L"alloy-sandbox", L"?", alloy::sandbox::main); +DEFINE_ENTRY_POINT(L"xe-cpu-sandbox", L"?", xe::cpu::sandbox::main); diff --git a/src/xenia/cpu/xenon_runtime.cc b/src/xenia/cpu/xenon_runtime.cc index 2b9ffb306..566198f1c 100644 --- a/src/xenia/cpu/xenon_runtime.cc +++ b/src/xenia/cpu/xenon_runtime.cc @@ -9,11 +9,11 @@ #include "xenia/cpu/xenon_runtime.h" -#include "alloy/frontend/ppc/ppc_frontend.h" +#include "xenia/cpu/frontend/ppc/ppc_frontend.h" #include "xenia/cpu/xenon_thread_state.h" -using namespace xe; -using namespace xe::cpu; +namespace xe { +namespace cpu { XenonRuntime::XenonRuntime(Memory* memory, ExportResolver* export_resolver, uint32_t debug_info_flags, uint32_t trace_flags) @@ -22,8 +22,9 @@ XenonRuntime::XenonRuntime(Memory* memory, ExportResolver* export_resolver, XenonRuntime::~XenonRuntime() = default; -int XenonRuntime::Initialize(std::unique_ptr backend) { - auto frontend = std::make_unique(this); +int XenonRuntime::Initialize( + std::unique_ptr backend) { + auto frontend = std::make_unique(this); // TODO(benvanik): set options/etc. int result = Runtime::Initialize(std::move(frontend), std::move(backend)); @@ -33,3 +34,6 @@ int XenonRuntime::Initialize(std::unique_ptr backend) { return result; } + +} // namespace cpu +} // namespace xe diff --git a/src/xenia/cpu/xenon_runtime.h b/src/xenia/cpu/xenon_runtime.h index 3aae4f0e2..b8b279e6b 100644 --- a/src/xenia/cpu/xenon_runtime.h +++ b/src/xenia/cpu/xenon_runtime.h @@ -10,7 +10,7 @@ #ifndef XENIA_CPU_XENON_RUNTIME_H_ #define XENIA_CPU_XENON_RUNTIME_H_ -#include "alloy/runtime/runtime.h" +#include "xenia/cpu/runtime/runtime.h" #include "xenia/common.h" #include "xenia/cpu/xenon_thread_state.h" #include "xenia/export_resolver.h" @@ -21,7 +21,7 @@ namespace cpu { class XenonThreadState; -class XenonRuntime : public alloy::runtime::Runtime { +class XenonRuntime : public xe::cpu::runtime::Runtime { public: XenonRuntime(Memory* memory, ExportResolver* export_resolver, uint32_t debug_info_flags, uint32_t trace_flags); @@ -29,7 +29,8 @@ class XenonRuntime : public alloy::runtime::Runtime { ExportResolver* export_resolver() const { return export_resolver_; } - virtual int Initialize(std::unique_ptr backend = 0); + virtual int Initialize( + std::unique_ptr backend = 0); private: ExportResolver* export_resolver_; diff --git a/src/xenia/cpu/xenon_thread_state.cc b/src/xenia/cpu/xenon_thread_state.cc index ce3083cae..636418c48 100644 --- a/src/xenia/cpu/xenon_thread_state.cc +++ b/src/xenia/cpu/xenon_thread_state.cc @@ -12,11 +12,11 @@ #include "xdb/protocol.h" #include "xenia/cpu/xenon_runtime.h" -using namespace alloy; -using namespace alloy::frontend; -using namespace alloy::frontend::ppc; -using namespace alloy::runtime; -using namespace xe::cpu; +namespace xe { +namespace cpu { + +using namespace xe::cpu::frontend; +using namespace xe::cpu::runtime; XenonThreadState::XenonThreadState(XenonRuntime* runtime, uint32_t thread_id, size_t stack_size, @@ -83,3 +83,6 @@ void XenonThreadState::WriteRegisters(xdb::protocol::Registers* registers) { memcpy(registers->fpr, context_->f, sizeof(context_->f)); memcpy(registers->vr, context_->v, sizeof(context_->v)); } + +} // namespace cpu +} // namespace xe diff --git a/src/xenia/cpu/xenon_thread_state.h b/src/xenia/cpu/xenon_thread_state.h index 926ea04d1..693143577 100644 --- a/src/xenia/cpu/xenon_thread_state.h +++ b/src/xenia/cpu/xenon_thread_state.h @@ -10,8 +10,8 @@ #ifndef XENIA_CPU_XENON_THREAD_STATE_H_ #define XENIA_CPU_XENON_THREAD_STATE_H_ -#include "alloy/frontend/ppc/ppc_context.h" -#include "alloy/runtime/thread_state.h" +#include "xenia/cpu/frontend/ppc/ppc_context.h" +#include "xenia/cpu/runtime/thread_state.h" #include "xenia/common.h" #include "xenia/memory.h" @@ -26,9 +26,9 @@ namespace cpu { class XenonRuntime; -using PPCContext = alloy::frontend::ppc::PPCContext; +using PPCContext = xe::cpu::frontend::ppc::PPCContext; -class XenonThreadState : public alloy::runtime::ThreadState { +class XenonThreadState : public xe::cpu::runtime::ThreadState { public: XenonThreadState(XenonRuntime* runtime, uint32_t thread_id, size_t stack_size, uint64_t thread_state_address); diff --git a/src/xenia/cpu/xex_module.cc b/src/xenia/cpu/xex_module.cc index 1f4940573..f65a68af1 100644 --- a/src/xenia/cpu/xex_module.cc +++ b/src/xenia/cpu/xex_module.cc @@ -16,16 +16,14 @@ #include "xenia/cpu/xenon_runtime.h" #include "xenia/export_resolver.h" -using namespace alloy; -using namespace alloy::runtime; -using namespace xe::cpu; +namespace xe { +namespace cpu { +using namespace xe::cpu::runtime; -namespace { void UndefinedImport(PPCContext* ppc_state, void* arg0, void* arg1) { XELOGE("call to undefined kernel import"); } -} XexModule::XexModule(XenonRuntime* runtime) : Module(runtime), @@ -171,7 +169,7 @@ int XexModule::SetupLibraryImports(const xe_xex2_import_library_t* library) { // Real consoles rewrite this with some code that sets r11. // If we did that we'd still have to put a thunk somewhere and do the // dynamic lookup. Instead, we rewrite it to use syscalls, as they - // aren't used on the 360. Alloy backends can either take the syscall + // aren't used on the 360. CPU backends can either take the syscall // or do something smarter. // sc // blr @@ -531,3 +529,6 @@ int XexModule::FindSaveRest() { return 0; } + +} // namespace cpu +} // namespace xe diff --git a/src/xenia/cpu/xex_module.h b/src/xenia/cpu/xex_module.h index 222b25841..7d9ddb6ca 100644 --- a/src/xenia/cpu/xex_module.h +++ b/src/xenia/cpu/xex_module.h @@ -12,7 +12,7 @@ #include -#include "alloy/runtime/module.h" +#include "xenia/cpu/runtime/module.h" #include "xenia/common.h" #include "xenia/kernel/util/xex2.h" @@ -21,7 +21,7 @@ namespace cpu { class XenonRuntime; -class XexModule : public alloy::runtime::Module { +class XexModule : public xe::cpu::runtime::Module { public: XexModule(XenonRuntime* runtime); virtual ~XexModule(); diff --git a/src/xenia/kernel/util/shim_utils.h b/src/xenia/kernel/util/shim_utils.h index 6b3f6bdd5..6b8805994 100644 --- a/src/xenia/kernel/util/shim_utils.h +++ b/src/xenia/kernel/util/shim_utils.h @@ -10,16 +10,14 @@ #ifndef XENIA_KERNEL_UTIL_SHIM_UTILS_H_ #define XENIA_KERNEL_UTIL_SHIM_UTILS_H_ -#include "alloy/frontend/ppc/ppc_context.h" +#include "xenia/cpu/frontend/ppc/ppc_context.h" #include "xenia/common.h" #include "xenia/export_resolver.h" - namespace xe { namespace kernel { -using PPCContext = alloy::frontend::ppc::PPCContext; - +using PPCContext = xe::cpu::frontend::ppc::PPCContext; #define SHIM_CALL void _cdecl #define SHIM_SET_MAPPING(library_name, export_name, shim_data) \ @@ -62,5 +60,4 @@ using PPCContext = alloy::frontend::ppc::PPCContext; } // namespace kernel } // namespace xe - #endif // XENIA_KERNEL_UTIL_SHIM_UTILS_H_ diff --git a/src/xenia/kernel/util/xex2.cc b/src/xenia/kernel/util/xex2.cc index a5d62435c..e28015ccd 100644 --- a/src/xenia/kernel/util/xex2.cc +++ b/src/xenia/kernel/util/xex2.cc @@ -21,8 +21,6 @@ #include "third_party/mspack/mspack.h" #include "third_party/pe/pe_image.h" -// using namespace alloy; - // TODO(benvanik): remove. #define XEEXPECTZERO(expr) \ if ((expr) != 0) { \ diff --git a/src/xenia/memory.cc b/src/xenia/memory.cc index 74865ebfd..8ebe37e70 100644 --- a/src/xenia/memory.cc +++ b/src/xenia/memory.cc @@ -9,10 +9,11 @@ #include "xenia/memory.h" +#include + #include #include -#include #include "poly/math.h" #include "xenia/cpu/mmio_handler.h" @@ -114,7 +115,14 @@ class xe::MemoryHeap { }; uint32_t MemoryHeap::next_heap_id_ = 1; -Memory::Memory() : mapping_(0), mapping_base_(nullptr) { +Memory::Memory() + : membase_(nullptr), + reserve_address_(0), + reserve_value_(0), + trace_base_(0), + mapping_(0), + mapping_base_(nullptr) { + system_page_size_ = poly::page_size(); virtual_heap_ = new MemoryHeap(this, false); physical_heap_ = new MemoryHeap(this, true); } @@ -142,11 +150,6 @@ Memory::~Memory() { } int Memory::Initialize() { - int result = alloy::Memory::Initialize(); - if (result) { - return result; - } - // Create main page file-backed mapping. This is all reserved but // uncommitted (so it shouldn't expand page file). #if XE_PLATFORM_WIN32 @@ -263,6 +266,46 @@ void Memory::UnmapViews() { } } +void Memory::Zero(uint64_t address, size_t size) { + uint8_t* p = membase_ + address; + memset(p, 0, size); +} + +void Memory::Fill(uint64_t address, size_t size, uint8_t value) { + uint8_t* p = membase_ + address; + memset(p, value, size); +} + +void Memory::Copy(uint64_t dest, uint64_t src, size_t size) { + uint8_t* pdest = membase_ + dest; + const uint8_t* psrc = membase_ + src; + memcpy(pdest, psrc, size); +} + +uint64_t Memory::SearchAligned(uint64_t start, uint64_t end, + const uint32_t* values, size_t value_count) { + assert_true(start <= end); + const uint32_t* p = reinterpret_cast(membase_ + start); + const uint32_t* pe = reinterpret_cast(membase_ + end); + while (p != pe) { + if (*p == values[0]) { + const uint32_t* pc = p + 1; + size_t matched = 1; + for (size_t n = 1; n < value_count; n++, pc++) { + if (*pc != values[n]) { + break; + } + matched++; + } + if (matched == value_count) { + return uint64_t(reinterpret_cast(p) - membase_); + } + } + p++; + } + return 0; +} + bool Memory::AddMappedRange(uint64_t address, uint64_t mask, uint64_t size, void* context, cpu::MMIOReadCallback read_callback, cpu::MMIOWriteCallback write_callback) { diff --git a/src/xenia/memory.h b/src/xenia/memory.h index 868b4f293..86e6b6a81 100644 --- a/src/xenia/memory.h +++ b/src/xenia/memory.h @@ -10,9 +10,11 @@ #ifndef XENIA_MEMORY_H_ #define XENIA_MEMORY_H_ +#include #include +#include -#include "alloy/memory.h" +#include "xenia/memory.h" #include "xenia/common.h" #include "xenia/cpu/mmio_handler.h" @@ -42,12 +44,29 @@ struct AllocationInfo { uint32_t type; // TBD }; -class Memory : public alloy::Memory { +class Memory { public: Memory(); - ~Memory() override; + ~Memory(); - int Initialize() override; + int Initialize(); + + inline uint8_t* membase() const { return membase_; } + inline uint8_t* Translate(uint64_t guest_address) const { + return membase_ + guest_address; + }; + inline uint64_t* reserve_address() { return &reserve_address_; } + inline uint64_t* reserve_value() { return &reserve_value_; } + + uint64_t trace_base() const { return trace_base_; } + void set_trace_base(uint64_t value) { trace_base_ = value; } + + // TODO(benvanik): make poly memory utils for these. + void Zero(uint64_t address, size_t size); + void Fill(uint64_t address, size_t size, uint8_t value); + void Copy(uint64_t dest, uint64_t src, size_t size); + uint64_t SearchAligned(uint64_t start, uint64_t end, const uint32_t* values, + size_t value_count); bool AddMappedRange(uint64_t address, uint64_t mask, uint64_t size, void* context, cpu::MMIOReadCallback read_callback, @@ -73,6 +92,12 @@ class Memory : public alloy::Memory { void UnmapViews(); private: + size_t system_page_size_; + uint8_t* membase_; + uint64_t reserve_address_; + uint64_t reserve_value_; + uint64_t trace_base_; + HANDLE mapping_; uint8_t* mapping_base_; union { diff --git a/src/xenia/profiling.cc b/src/xenia/profiling.cc index 3b93c7478..c2c537e9c 100644 --- a/src/xenia/profiling.cc +++ b/src/xenia/profiling.cc @@ -36,7 +36,6 @@ std::unique_ptr Profiler::display_ = nullptr; void Profiler::Initialize() { // Custom groups. MicroProfileSetEnableAllGroups(false); - MicroProfileForceEnableGroup("alloy", MicroProfileTokenTypeCpu); MicroProfileForceEnableGroup("apu", MicroProfileTokenTypeCpu); MicroProfileForceEnableGroup("cpu", MicroProfileTokenTypeCpu); MicroProfileForceEnableGroup("gpu", MicroProfileTokenTypeCpu); diff --git a/xenia-build.py b/xenia-build.py index e9d17b9ca..be0ab29e7 100644 --- a/xenia-build.py +++ b/xenia-build.py @@ -452,9 +452,9 @@ class TestCommand(Command): print('Testing...') print('') - # Run base alloy tests. - print('Launching alloy-test runner...') - result = shell_call('"build/xenia/Debug/alloy-test"') + # Run base CPU tests. + print('Launching xe-cpu-hir-test runner...') + result = shell_call('"build/xenia/Debug/xe-cpu-hir-test"') print('') if result != 0: return result @@ -465,14 +465,14 @@ class TestCommand(Command): print('WARNING: test files not updated!'); else: print('Updating test files...') - result = shell_call('./src/alloy/frontend/ppc/test/update.sh') + result = shell_call('./src/xenia/cpu/frontend/ppc/test/update.sh') print('') if result != 0: return result # Start the test runner. - print('Launching alloy-ppc-test runner...') - result = shell_call('"build/xenia/Debug/alloy-ppc-test"') + print('Launching xe-cpu-ppc-test runner...') + result = shell_call('"build/xenia/Debug/xe-cpu-ppc-test"') print('') if result != 0: return result diff --git a/xenia.gyp b/xenia.gyp index f8f1bd17a..77fcbc488 100644 --- a/xenia.gyp +++ b/xenia.gyp @@ -1,8 +1,8 @@ # Copyright 2013 Ben Vanik. All Rights Reserved. { 'includes': [ - 'src/alloy/frontend/ppc/test/test.gypi', - 'src/alloy/test/test.gypi', + 'src/xenia/cpu/frontend/ppc/test/test.gypi', + 'src/xenia/cpu/test/test.gypi', 'tools/tools.gypi', 'third_party/beaengine.gypi', 'third_party/gflags.gypi', @@ -283,108 +283,24 @@ ], }, - { - 'target_name': 'liballoy', - 'product_name': 'liballoy', - 'type': 'static_library', - - 'dependencies': [ - 'beaengine', - 'gflags', - 'llvm', - 'libpoly', - ], - - 'conditions': [ - ['OS == "mac"', { - 'xcode_settings': { - 'OTHER_CFLAGS': [ - '-fno-operator-names', - ], - }, - }], - ['OS == "linux"', { - 'cflags': [ - '-fno-operator-names', - ], - }], - ], - - 'export_dependent_settings': [ - 'beaengine', - 'gflags', - 'llvm', - 'libpoly', - ], - - 'direct_dependent_settings': { - 'include_dirs': [ - 'src/', - ], - - 'target_conditions': [ - ['_type=="shared_library"', { - 'cflags': [ - ], - }], - ['_type=="executable"', { - 'conditions': [ - ['OS == "win"', { - 'libraries': [ - 'kernel32', - 'user32', - 'ole32', - 'ntdll', - 'advapi32', - ], - }], - ['OS == "mac"', { - 'xcode_settings': { - 'OTHER_LDFLAGS': [ - ], - }, - }], - ['OS == "linux"', { - 'libraries': [ - '-lpthread', - '-ldl', - ], - }], - ], - }], - ], - }, - - 'cflags': [ - ], - - 'include_dirs': [ - '.', - 'src/', - '<(INTERMEDIATE_DIR)', - ], - - 'includes': [ - 'src/alloy/sources.gypi', - ], - }, - { 'target_name': 'libxenia', 'product_name': 'libxenia', 'type': 'static_library', 'dependencies': [ + 'beaengine', 'gflags', 'glew', - 'liballoy', + 'llvm', 'libpoly', 'xxhash', ], 'export_dependent_settings': [ + 'beaengine', 'gflags', 'glew', - 'liballoy', + 'llvm', 'libpoly', 'xxhash', ], @@ -436,6 +352,21 @@ ], }, + 'conditions': [ + ['OS == "mac"', { + 'xcode_settings': { + 'OTHER_CFLAGS': [ + '-fno-operator-names', + ], + }, + }], + ['OS == "linux"', { + 'cflags': [ + '-fno-operator-names', + ], + }], + ], + 'cflags': [ ],