diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfe.bin b/src/alloy/frontend/ppc/test/bin/instr_subfe.bin
index ffec5570e..f3025563f 100644
Binary files a/src/alloy/frontend/ppc/test/bin/instr_subfe.bin and b/src/alloy/frontend/ppc/test/bin/instr_subfe.bin differ
diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfe.dis b/src/alloy/frontend/ppc/test/bin/instr_subfe.dis
index c0ec805d3..99f1f248e 100644
--- a/src/alloy/frontend/ppc/test/bin/instr_subfe.dis
+++ b/src/alloy/frontend/ppc/test/bin/instr_subfe.dis
@@ -7,3 +7,19 @@ Disassembly of section .text:
 0000000000100000 <test_subfe>:
   100000:	7c 6a 59 10 	subfe   r3,r10,r11
   100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_subfe_2>:
+  100008:	7c 6a 59 10 	subfe   r3,r10,r11
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_subfe_3>:
+  100010:	7c 6a 59 10 	subfe   r3,r10,r11
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_subfe_4>:
+  100018:	7c 6a 59 10 	subfe   r3,r10,r11
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_subfe_5>:
+  100020:	7c 6a 59 10 	subfe   r3,r10,r11
+  100024:	4e 80 00 20 	blr
diff --git a/src/alloy/frontend/ppc/test/bin/instr_subfe.map b/src/alloy/frontend/ppc/test/bin/instr_subfe.map
index 0295d5687..296212367 100644
--- a/src/alloy/frontend/ppc/test/bin/instr_subfe.map
+++ b/src/alloy/frontend/ppc/test/bin/instr_subfe.map
@@ -1 +1,5 @@
 0000000000000000 t test_subfe
+0000000000000008 t test_subfe_2
+0000000000000010 t test_subfe_3
+0000000000000018 t test_subfe_4
+0000000000000020 t test_subfe_5
diff --git a/src/alloy/frontend/ppc/test/instr_subfe.s b/src/alloy/frontend/ppc/test/instr_subfe.s
index 32a7e9703..2280ea3a1 100644
--- a/src/alloy/frontend/ppc/test/instr_subfe.s
+++ b/src/alloy/frontend/ppc/test/instr_subfe.s
@@ -1,10 +1,44 @@
 test_subfe:
   #_ REGISTER_IN r10 0x00000000000103BF
   #_ REGISTER_IN r11 0x00000000000103C0
-
   subfe r3, r10, r11
-
   blr
   #_ REGISTER_OUT r10 0x00000000000103BF
   #_ REGISTER_OUT r11 0x00000000000103C0
-  #_ REGISTER_OUT r3 0x1
+  #_ REGISTER_OUT r3 0x0
+
+test_subfe_2:
+  #_ REGISTER_IN r10 0
+  #_ REGISTER_IN r11 0
+  subfe r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 0
+
+test_subfe_3:
+  #_ REGISTER_IN r10 1
+  #_ REGISTER_IN r11 0
+  subfe r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 1
+  #_ REGISTER_OUT r11 0
+  #_ REGISTER_OUT r3 -1
+
+test_subfe_4:
+  #_ REGISTER_IN r10 0
+  #_ REGISTER_IN r11 1
+  subfe r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 0
+  #_ REGISTER_OUT r11 1
+  #_ REGISTER_OUT r3 0
+
+test_subfe_5:
+  #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF
+  subfe r3, r10, r11
+  blr
+  #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r3 0x0