Update a few Xenos enums/structs
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Dr. Chat
parent
5875b79cc4
commit
284aa14a67
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@ -73,6 +73,13 @@ enum class AnisoFilter : uint32_t {
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kUseFetchConst = 7,
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};
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enum class BorderColor : uint32_t {
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k_AGBR_Black = 0,
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k_AGBR_White = 1,
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k_ACBYCR_BLACK = 2,
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k_ACBCRY_BLACK = 3,
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};
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enum class TextureDimension : uint32_t {
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k1D = 0,
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k2D = 1,
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@ -381,21 +388,25 @@ XEPACKEDUNION(xe_gpu_vertex_fetch_t, {
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// XE_GPU_REG_SHADER_CONSTANT_FETCH_*
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XEPACKEDUNION(xe_gpu_texture_fetch_t, {
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t type : 2; // dword_0
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uint32_t sign_x : 2;
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uint32_t sign_y : 2;
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uint32_t sign_z : 2;
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uint32_t sign_w : 2;
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uint32_t clamp_x : 3;
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uint32_t clamp_y : 3;
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uint32_t clamp_z : 3;
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uint32_t unk0 : 3;
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uint32_t pitch : 9;
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uint32_t tiled : 1;
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uint32_t type : 2; // +0 dword_0
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uint32_t sign_x : 2; // +2
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uint32_t sign_y : 2; // +4
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uint32_t sign_z : 2; // +6
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uint32_t sign_w : 2; // +8
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uint32_t clamp_x : 3; // +10
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uint32_t clamp_y : 3; // +13
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uint32_t clamp_z : 3; // +16
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uint32_t unused_0 : 3; // +19
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uint32_t pitch : 9; // +22 byte_pitch >> 5
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uint32_t tiled : 1; // +31
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uint32_t format : 6; // dword_1
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uint32_t endianness : 2;
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uint32_t unk1 : 4;
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uint32_t request_size : 2;
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uint32_t stacked : 1;
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uint32_t clamp_policy : 1; // d3d/opengl
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uint32_t address : 20;
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union { // dword_2
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struct {
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uint32_t width : 24;
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@ -417,22 +428,34 @@ XEPACKEDUNION(xe_gpu_texture_fetch_t, {
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uint32_t depth : 10;
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} size_3d;
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};
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uint32_t unk3_0 : 1; // dword_3
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uint32_t swizzle : 12; // xyzw, 3b each (XE_GPU_SWIZZLE)
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uint32_t unk3_1 : 6;
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uint32_t mag_filter : 2;
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uint32_t min_filter : 2;
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uint32_t mip_filter : 2;
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uint32_t aniso_filter : 3;
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uint32_t unk3_2 : 3;
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uint32_t border : 1;
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uint32_t unk4_0 : 2; // dword_4
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uint32_t mip_min_level : 4;
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uint32_t mip_max_level : 4;
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uint32_t unk4_1 : 22;
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uint32_t unk5 : 9; // dword_5
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uint32_t dimension : 2;
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uint32_t unk5b : 21;
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uint32_t num_format : 1; // +0 dword_3 frac/int
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uint32_t swizzle : 12; // +1 xyzw, 3b each (XE_GPU_SWIZZLE)
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int32_t exp_adjust : 6; // +13
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uint32_t mag_filter : 2; // +19
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uint32_t min_filter : 2; // +21
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uint32_t mip_filter : 2; // +23
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uint32_t aniso_filter : 3; // +25
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uint32_t unused_3 : 3; // +28
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uint32_t border_size : 1; // +31
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uint32_t vol_mag_filter : 1; // +0 dword_4
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uint32_t vol_min_filter : 1; // +1
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uint32_t mip_min_level : 4; // +2
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uint32_t mip_max_level : 4; // +6
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uint32_t mag_aniso_walk : 1; // +10
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uint32_t min_aniso_walk : 1; // +11
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int32_t lod_bias : 10; // +12
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int32_t grad_exp_adjust_h : 5; // +22
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int32_t grad_exp_adjust_v : 5; // +27
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uint32_t border_color : 2; // +0 dword_5
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uint32_t force_bcw_max : 1; // +2
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uint32_t tri_clamp : 2; // +3
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int32_t aniso_bias : 4; // +5
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uint32_t dimension : 2; // +9
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uint32_t packed_mips : 1; // +11
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uint32_t mip_address : 20; // +12
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});
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t dword_0;
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@ -475,43 +498,30 @@ XEPACKEDUNION(xe_gpu_fetch_group_t, {
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// Enum of event values used for VGT_EVENT_INITIATOR
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enum Event {
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SAMPLE_STREAMOUTSTATS1 = (1 << 0),
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SAMPLE_STREAMOUTSTATS2 = (2 << 0),
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SAMPLE_STREAMOUTSTATS3 = (3 << 0),
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CACHE_FLUSH_TS = (4 << 0),
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CACHE_FLUSH = (6 << 0),
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CS_PARTIAL_FLUSH = (7 << 0),
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VGT_STREAMOUT_RESET = (10 << 0),
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END_OF_PIPE_INCR_DE = (11 << 0),
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END_OF_PIPE_IB_END = (12 << 0),
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RST_PIX_CNT = (13 << 0),
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VS_PARTIAL_FLUSH = (15 << 0),
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PS_PARTIAL_FLUSH = (16 << 0),
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CACHE_FLUSH_AND_INV_TS_EVENT = (20 << 0),
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ZPASS_DONE = (21 << 0),
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CACHE_FLUSH_AND_INV_EVENT = (22 << 0),
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PERFCOUNTER_START = (23 << 0),
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PERFCOUNTER_STOP = (24 << 0),
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PIPELINESTAT_START = (25 << 0),
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PIPELINESTAT_STOP = (26 << 0),
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PERFCOUNTER_SAMPLE = (27 << 0),
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SAMPLE_PIPELINESTAT = (30 << 0),
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SAMPLE_STREAMOUTSTATS = (32 << 0),
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RESET_VTX_CNT = (33 << 0),
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VGT_FLUSH = (36 << 0),
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BOTTOM_OF_PIPE_TS = (40 << 0),
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DB_CACHE_FLUSH_AND_INV = (42 << 0),
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FLUSH_AND_INV_DB_DATA_TS = (43 << 0),
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FLUSH_AND_INV_DB_META = (44 << 0),
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FLUSH_AND_INV_CB_DATA_TS = (45 << 0),
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FLUSH_AND_INV_CB_META = (46 << 0),
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CS_DONE = (47 << 0),
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PS_DONE = (48 << 0),
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FLUSH_AND_INV_CB_PIXEL_DATA = (49 << 0),
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THREAD_TRACE_START = (51 << 0),
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THREAD_TRACE_STOP = (52 << 0),
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THREAD_TRACE_FLUSH = (54 << 0),
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THREAD_TRACE_FINISH = (55 << 0),
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VS_DEALLOC = 0,
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PS_DEALLOC = 1,
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VS_DONE_TS = 2,
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PS_DONE_TS = 3,
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CACHE_FLUSH_TS = 4,
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CONTEXT_DONE = 5,
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CACHE_FLUSH = 6,
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VIZQUERY_START = 7,
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VIZQUERY_END = 8,
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SC_WAIT_WC = 9,
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MPASS_PS_CP_REFETCH = 10,
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MPASS_PS_RST_START = 11,
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MPASS_PS_INCR_START = 12,
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RST_PIX_CNT = 13,
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RST_VTX_CNT = 14,
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TILE_FLUSH = 15,
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CACHE_FLUSH_AND_INV_TS_EVENT = 20,
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ZPASS_DONE = 21,
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CACHE_FLUSH_AND_INV_EVENT = 22,
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PERFCOUNTER_START = 23,
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PERFCOUNTER_STOP = 24,
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SCREEN_EXT_INIT = 25,
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SCREEN_EXT_RPT = 26,
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VS_FETCH_DONE_TS = 27,
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};
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// Opcodes (IT_OPCODE) for Type-3 commands in the ringbuffer.
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