[Vulkan] Track render target state with the pipeline cache
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516c113423
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26100c586f
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@ -791,6 +791,22 @@ bool PipelineCache::SetShadowRegister(float* dest, uint32_t register_name) {
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return true;
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return true;
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}
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}
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bool PipelineCache::SetShadowRegisterArray(uint32_t* dest, uint32_t num,
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uint32_t register_name) {
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bool dirty = false;
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for (uint32_t i = 0; i < num; i++) {
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uint32_t value = register_file_->values[register_name + i].u32;
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if (dest[i] == value) {
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continue;
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}
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dest[i] = value;
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dirty |= true;
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}
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return dirty;
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}
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PipelineCache::UpdateStatus PipelineCache::UpdateState(
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PipelineCache::UpdateStatus PipelineCache::UpdateState(
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VulkanShader* vertex_shader, VulkanShader* pixel_shader,
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VulkanShader* vertex_shader, VulkanShader* pixel_shader,
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PrimitiveType primitive_type) {
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PrimitiveType primitive_type) {
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@ -810,6 +826,8 @@ PipelineCache::UpdateStatus PipelineCache::UpdateState(
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}
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}
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UpdateStatus status;
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UpdateStatus status;
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status = UpdateRenderTargetState();
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CHECK_UPDATE_STATUS(status, mismatch, "Unable to update render target state");
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status = UpdateShaderStages(vertex_shader, pixel_shader, primitive_type);
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status = UpdateShaderStages(vertex_shader, pixel_shader, primitive_type);
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CHECK_UPDATE_STATUS(status, mismatch, "Unable to update shader stages");
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CHECK_UPDATE_STATUS(status, mismatch, "Unable to update shader stages");
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status = UpdateVertexInputState(vertex_shader);
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status = UpdateVertexInputState(vertex_shader);
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@ -831,6 +849,45 @@ PipelineCache::UpdateStatus PipelineCache::UpdateState(
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return mismatch ? UpdateStatus::kMismatch : UpdateStatus::kCompatible;
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return mismatch ? UpdateStatus::kMismatch : UpdateStatus::kCompatible;
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}
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}
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PipelineCache::UpdateStatus PipelineCache::UpdateRenderTargetState() {
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auto& regs = update_render_targets_regs_;
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bool dirty = false;
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// Check the render target formats
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struct {
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reg::RB_COLOR_INFO rb_color_info;
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reg::RB_DEPTH_INFO rb_depth_info;
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reg::RB_COLOR_INFO rb_color1_info;
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reg::RB_COLOR_INFO rb_color2_info;
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reg::RB_COLOR_INFO rb_color3_info;
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}* cur_regs = reinterpret_cast<decltype(cur_regs)>(
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®ister_file_->values[XE_GPU_REG_RB_COLOR_INFO].u32);
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dirty |=
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regs.rb_color_info.color_format != cur_regs->rb_color_info.color_format;
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dirty |=
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regs.rb_depth_info.depth_format != cur_regs->rb_depth_info.depth_format;
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dirty |=
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regs.rb_color1_info.color_format != cur_regs->rb_color1_info.color_format;
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dirty |=
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regs.rb_color2_info.color_format != cur_regs->rb_color2_info.color_format;
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dirty |=
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regs.rb_color3_info.color_format != cur_regs->rb_color3_info.color_format;
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// And copy the regs over.
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regs.rb_color_info.color_format = cur_regs->rb_color_info.color_format;
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regs.rb_depth_info.depth_format = cur_regs->rb_depth_info.depth_format;
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regs.rb_color1_info.color_format = cur_regs->rb_color1_info.color_format;
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regs.rb_color2_info.color_format = cur_regs->rb_color2_info.color_format;
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regs.rb_color3_info.color_format = cur_regs->rb_color3_info.color_format;
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XXH64_update(&hash_state_, ®s, sizeof(regs));
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if (!dirty) {
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return UpdateStatus::kCompatible;
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}
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return UpdateStatus::kMismatch;
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}
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PipelineCache::UpdateStatus PipelineCache::UpdateShaderStages(
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PipelineCache::UpdateStatus PipelineCache::UpdateShaderStages(
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VulkanShader* vertex_shader, VulkanShader* pixel_shader,
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VulkanShader* vertex_shader, VulkanShader* pixel_shader,
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PrimitiveType primitive_type) {
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PrimitiveType primitive_type) {
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@ -131,6 +131,7 @@ class PipelineCache {
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VulkanShader* pixel_shader,
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VulkanShader* pixel_shader,
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PrimitiveType primitive_type);
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PrimitiveType primitive_type);
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UpdateStatus UpdateRenderTargetState();
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UpdateStatus UpdateShaderStages(VulkanShader* vertex_shader,
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UpdateStatus UpdateShaderStages(VulkanShader* vertex_shader,
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VulkanShader* pixel_shader,
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VulkanShader* pixel_shader,
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PrimitiveType primitive_type);
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PrimitiveType primitive_type);
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@ -144,18 +145,20 @@ class PipelineCache {
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bool SetShadowRegister(uint32_t* dest, uint32_t register_name);
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bool SetShadowRegister(uint32_t* dest, uint32_t register_name);
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bool SetShadowRegister(float* dest, uint32_t register_name);
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bool SetShadowRegister(float* dest, uint32_t register_name);
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bool SetShadowRegisterArray(uint32_t* dest, uint32_t num,
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uint32_t register_name);
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struct UpdateRenderTargetsRegisters {
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struct UpdateRenderTargetsRegisters {
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uint32_t rb_modecontrol;
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uint32_t rb_modecontrol;
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uint32_t rb_surface_info;
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reg::RB_SURFACE_INFO rb_surface_info;
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uint32_t rb_color_info;
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reg::RB_COLOR_INFO rb_color_info;
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uint32_t rb_color1_info;
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reg::RB_DEPTH_INFO rb_depth_info;
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uint32_t rb_color2_info;
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reg::RB_COLOR_INFO rb_color1_info;
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uint32_t rb_color3_info;
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reg::RB_COLOR_INFO rb_color2_info;
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reg::RB_COLOR_INFO rb_color3_info;
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uint32_t rb_color_mask;
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uint32_t rb_color_mask;
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uint32_t rb_depthcontrol;
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uint32_t rb_depthcontrol;
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uint32_t rb_stencilrefmask;
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uint32_t rb_stencilrefmask;
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uint32_t rb_depth_info;
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UpdateRenderTargetsRegisters() { Reset(); }
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UpdateRenderTargetsRegisters() { Reset(); }
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void Reset() { std::memset(this, 0, sizeof(*this)); }
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void Reset() { std::memset(this, 0, sizeof(*this)); }
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