RenderCache: Hardcode surface height to 2560
Fix a couple of other things
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2a924d2b05
commit
254acf2a67
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@ -309,8 +309,15 @@ bool CachedFramebuffer::IsCompatible(
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const RenderConfiguration& desired_config) const {
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// We already know all render pass things line up, so let's verify dimensions,
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// edram offsets, etc. We need an exact match.
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if (desired_config.surface_pitch_px != width ||
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desired_config.surface_height_px != height) {
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uint32_t surface_pitch_px = desired_config.surface_msaa != MsaaSamples::k4X
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? desired_config.surface_pitch_px
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: desired_config.surface_pitch_px * 2;
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uint32_t surface_height_px = desired_config.surface_msaa == MsaaSamples::k1X
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? desired_config.surface_height_px
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: desired_config.surface_height_px * 2;
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surface_pitch_px = std::min(surface_pitch_px, 2560u);
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surface_height_px = std::min(surface_height_px, 2560u);
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if (surface_pitch_px != width || surface_height_px != height) {
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return false;
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}
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// TODO(benvanik): separate image views from images in tiles and store in fb?
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@ -445,7 +452,8 @@ CachedRenderPass::~CachedRenderPass() {
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bool CachedRenderPass::IsCompatible(
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const RenderConfiguration& desired_config) const {
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if (config.surface_msaa != desired_config.surface_msaa) {
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if (config.surface_msaa != desired_config.surface_msaa &&
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FLAGS_vulkan_native_msaa) {
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return false;
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}
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@ -548,8 +556,6 @@ bool RenderCache::dirty() const {
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regs[XE_GPU_REG_PA_SC_WINDOW_SCISSOR_TL].u32;
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dirty |= cur_regs.pa_sc_window_scissor_br !=
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regs[XE_GPU_REG_PA_SC_WINDOW_SCISSOR_BR].u32;
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dirty |= (cur_regs.rb_depthcontrol & (0x4 | 0x2)) <
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(regs[XE_GPU_REG_RB_DEPTHCONTROL].u32 & (0x4 | 0x2));
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return dirty;
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}
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@ -580,11 +586,6 @@ const RenderState* RenderCache::BeginRenderPass(VkCommandBuffer command_buffer,
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XE_GPU_REG_PA_SC_WINDOW_SCISSOR_TL);
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dirty |= SetShadowRegister(®s.pa_sc_window_scissor_br,
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XE_GPU_REG_PA_SC_WINDOW_SCISSOR_BR);
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dirty |=
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(regs.rb_depthcontrol & (0x4 | 0x2)) <
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(register_file_->values[XE_GPU_REG_RB_DEPTHCONTROL].u32 & (0x4 | 0x2));
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regs.rb_depthcontrol =
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register_file_->values[XE_GPU_REG_RB_DEPTHCONTROL].u32 & (0x4 | 0x2);
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if (!dirty && current_state_.render_pass) {
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// No registers have changed so we can reuse the previous render pass -
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// just begin with what we had.
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@ -602,18 +603,17 @@ const RenderState* RenderCache::BeginRenderPass(VkCommandBuffer command_buffer,
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return nullptr;
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}
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// Initial state update.
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UpdateState();
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current_state_.render_pass = render_pass;
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current_state_.render_pass_handle = render_pass->handle;
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current_state_.framebuffer = framebuffer;
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current_state_.framebuffer_handle = framebuffer->handle;
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// TODO(DrChat): Determine if we actually need an EDRAM buffer.
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/*
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// Depth
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auto depth_target = current_state_.framebuffer->depth_stencil_attachment;
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if (depth_target && current_state_.config.depth_stencil.used) {
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// UpdateTileView(command_buffer, depth_target, true);
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UpdateTileView(command_buffer, depth_target, true);
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}
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// Color
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@ -623,8 +623,9 @@ const RenderState* RenderCache::BeginRenderPass(VkCommandBuffer command_buffer,
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continue;
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}
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// UpdateTileView(command_buffer, target, true);
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UpdateTileView(command_buffer, target, true);
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}
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*/
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}
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if (!render_pass) {
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return nullptr;
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@ -647,6 +648,15 @@ const RenderState* RenderCache::BeginRenderPass(VkCommandBuffer command_buffer,
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render_pass_begin_info.renderArea.extent.width = config->surface_pitch_px;
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render_pass_begin_info.renderArea.extent.height = config->surface_height_px;
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if (config->surface_msaa == MsaaSamples::k2X) {
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render_pass_begin_info.renderArea.extent.height =
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std::min(config->surface_height_px * 2, 2560u);
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} else if (config->surface_msaa == MsaaSamples::k4X) {
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render_pass_begin_info.renderArea.extent.width *= 2;
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render_pass_begin_info.renderArea.extent.height =
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std::min(config->surface_height_px * 2, 2560u);
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}
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// Configure clear color, if clearing.
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// TODO(benvanik): enable clearing here during resolve?
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render_pass_begin_info.clearValueCount = 0;
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@ -677,9 +687,15 @@ bool RenderCache::ParseConfiguration(RenderConfiguration* config) {
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// Guess the height from the scissor height.
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// It's wildly inaccurate, but I've never seen it be bigger than the
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// EDRAM tiling.
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/*
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uint32_t ws_y = (regs.pa_sc_window_scissor_tl >> 16) & 0x7FFF;
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uint32_t ws_h = ((regs.pa_sc_window_scissor_br >> 16) & 0x7FFF) - ws_y;
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config->surface_height_px = std::min(2560u, xe::round_up(ws_h, 16));
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*/
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// TODO(DrChat): Find an accurate way to get the surface height. Until we do,
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// we're going to hardcode it to 2560, as that's the absolute maximum.
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config->surface_height_px = 2560;
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// Color attachment configuration.
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if (config->mode_control == ModeControl::kColorDepth) {
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@ -781,9 +797,9 @@ bool RenderCache::ConfigureRenderPass(VkCommandBuffer command_buffer,
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color_key.tile_offset = config->color[i].edram_base;
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color_key.tile_width =
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xe::round_up(config->surface_pitch_px, tile_width) / tile_width;
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color_key.tile_height = std::min(
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2560 / tile_height, 160u); // xe::round_up(config->surface_height_px,
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// tile_height) / tile_height;
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// color_key.tile_height =
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// xe::round_up(config->surface_height_px, tile_height) / tile_height;
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color_key.tile_height = 160;
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color_key.color_or_depth = 1;
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color_key.msaa_samples =
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0; // static_cast<uint16_t>(config->surface_msaa);
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@ -800,9 +816,9 @@ bool RenderCache::ConfigureRenderPass(VkCommandBuffer command_buffer,
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depth_stencil_key.tile_offset = config->depth_stencil.edram_base;
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depth_stencil_key.tile_width =
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xe::round_up(config->surface_pitch_px, tile_width) / tile_width;
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depth_stencil_key.tile_height = std::min(
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2560 / tile_height, 160u); // xe::round_up(config->surface_height_px,
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// tile_height) / tile_height;
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// depth_stencil_key.tile_height =
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// xe::round_up(config->surface_height_px, tile_height) / tile_height;
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depth_stencil_key.tile_height = 160;
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depth_stencil_key.color_or_depth = 0;
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depth_stencil_key.msaa_samples =
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0; // static_cast<uint16_t>(config->surface_msaa);
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@ -815,10 +831,17 @@ bool RenderCache::ConfigureRenderPass(VkCommandBuffer command_buffer,
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return false;
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}
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uint32_t surface_pitch_px = config->surface_msaa != MsaaSamples::k4X
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? config->surface_pitch_px
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: config->surface_pitch_px * 2;
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uint32_t surface_height_px = config->surface_msaa == MsaaSamples::k1X
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? config->surface_height_px
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: config->surface_height_px * 2;
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surface_pitch_px = std::min(surface_pitch_px, 2560u);
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surface_height_px = std::min(surface_height_px, 2560u);
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framebuffer = new CachedFramebuffer(
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*device_, render_pass->handle, config->surface_pitch_px,
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config->surface_height_px, target_color_attachments,
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target_depth_stencil_attachment);
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*device_, render_pass->handle, surface_pitch_px, surface_height_px,
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target_color_attachments, target_depth_stencil_attachment);
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render_pass->cached_framebuffers.push_back(framebuffer);
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}
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@ -923,6 +946,8 @@ void RenderCache::EndRenderPass() {
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// contents of another render target by mistake! Need to reorder copy commands
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// to avoid this.
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// TODO(DrChat): Determine if we actually need an EDRAM buffer.
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/*
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std::vector<CachedTileView*> cached_views;
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// Depth
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@ -946,27 +971,13 @@ void RenderCache::EndRenderPass() {
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[](CachedTileView const* a, CachedTileView const* b) { return *a < *b; });
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for (auto view : cached_views) {
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// UpdateTileView(current_command_buffer_, view, false, false);
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UpdateTileView(current_command_buffer_, view, false, false);
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}
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*/
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current_command_buffer_ = nullptr;
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}
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void RenderCache::UpdateState() {
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// Keep track of whether color attachments were used or not in this pass.
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uint32_t rb_color_mask = register_file_->values[XE_GPU_REG_RB_COLOR_MASK].u32;
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uint32_t rb_depthcontrol =
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register_file_->values[XE_GPU_REG_RB_DEPTHCONTROL].u32;
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for (int i = 0; i < 4; i++) {
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uint32_t color_mask = (rb_color_mask >> (i * 4)) & 0xF;
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current_state_.config.color[i].used |=
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current_state_.config.mode_control == xenos::ModeControl::kColorDepth &&
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color_mask != 0;
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}
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current_state_.config.depth_stencil.used |= !!(rb_depthcontrol & (0x4 | 0x2));
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}
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void RenderCache::ClearCache() {
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// TODO(benvanik): caching.
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}
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@ -1073,9 +1084,8 @@ void RenderCache::BlitToImage(VkCommandBuffer command_buffer,
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key.edram_format = format;
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key.tile_offset = edram_base;
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key.tile_width = xe::round_up(pitch, tile_width) / tile_width;
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key.tile_height =
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std::min(2560 / tile_height,
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160u); // xe::round_up(height, tile_height) / tile_height;
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// key.tile_height = xe::round_up(height, tile_height) / tile_height;
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key.tile_height = 160;
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auto tile_view = FindOrCreateTileView(command_buffer, key);
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assert_not_null(tile_view);
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@ -1115,7 +1125,7 @@ void RenderCache::BlitToImage(VkCommandBuffer command_buffer,
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color_or_depth
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? VK_IMAGE_ASPECT_COLOR_BIT
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: VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT;
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image_blit.srcOffsets[0] = {0, 0, 0};
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image_blit.srcOffsets[0] = {0, 0, offset.z};
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image_blit.srcOffsets[1] = {int32_t(extents.width), int32_t(extents.height),
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int32_t(extents.depth)};
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@ -1191,9 +1201,8 @@ void RenderCache::ClearEDRAMColor(VkCommandBuffer command_buffer,
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key.edram_format = static_cast<uint16_t>(format);
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key.tile_offset = edram_base;
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key.tile_width = xe::round_up(pitch, tile_width) / tile_width;
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key.tile_height =
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std::min(2560 / tile_height,
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160u); // xe::round_up(height, tile_height) / tile_height;
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// key.tile_height = xe::round_up(height, tile_height) / tile_height;
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key.tile_height = 160;
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auto tile_view = FindOrCreateTileView(command_buffer, key);
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assert_not_null(tile_view);
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@ -1228,9 +1237,8 @@ void RenderCache::ClearEDRAMDepthStencil(VkCommandBuffer command_buffer,
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key.edram_format = static_cast<uint16_t>(format);
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key.tile_offset = edram_base;
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key.tile_width = xe::round_up(pitch, tile_width) / tile_width;
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key.tile_height =
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std::min(2560 / tile_height,
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160u); // xe::round_up(height, tile_height) / tile_height;
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// key.tile_height = xe::round_up(height, tile_height) / tile_height;
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key.tile_height = 160;
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auto tile_view = FindOrCreateTileView(command_buffer, key);
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assert_not_null(tile_view);
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@ -278,9 +278,6 @@ class RenderCache {
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// The command buffer will be transitioned out of the render pass phase.
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void EndRenderPass();
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// Updates current render state. Call this every draw with an open render pass
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void UpdateState();
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// Clears all cached content.
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void ClearCache();
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@ -363,7 +360,6 @@ class RenderCache {
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uint32_t rb_color2_info;
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uint32_t rb_color3_info;
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uint32_t rb_depth_info;
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uint32_t rb_depthcontrol;
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uint32_t pa_sc_window_scissor_tl;
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uint32_t pa_sc_window_scissor_br;
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