Merge pull request #396 from DrChat/tests

Tests: vpkshss128/vpkshus128/vpkswss128/vpkswus128/vpkuhum128/vpkuhus…

src/xenia/cpu/frontend/testing/instr_vor.s

@@ -0,0 +1,8 @@
+test_vor_1:
+  #_ REGISTER_IN v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_IN v4 [80081010, 808F0000, 00000000, 8FFFFFFF]
+  vor v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v4 [80081010, 808F0000, 00000000, 8FFFFFFF]
+  #_ REGISTER_OUT v5 [FFFF1111, F0FFFFFF, FFFFFFFF, 8FFFFFFF]

src/xenia/cpu/frontend/testing/instr_vor128.s

@@ -0,0 +1,8 @@
+test_vor128_1:
+  #_ REGISTER_IN v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_IN v4 [80081010, 808F0000, 00000000, 8FFFFFFF]
+  vor128 v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v4 [80081010, 808F0000, 00000000, 8FFFFFFF]
+  #_ REGISTER_OUT v5 [FFFF1111, F0FFFFFF, FFFFFFFF, 8FFFFFFF]

src/xenia/cpu/frontend/testing/instr_vpkshss128.s

@@ -0,0 +1,30 @@
+test_vpkshss128_1:
+  #_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
+  #_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
+  vpkshss128 v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
+  #_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
+  #_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_vpkshss128_2:
+  #_ REGISTER_IN v3 [7FFF8000, 00020003, 00040005, 00060007]
+  #_ REGISTER_IN v4 [7FFF8000, 000A000B, 000C000D, 000E000F]
+  vpkshss128 v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFF8000, 00020003, 00040005, 00060007]
+  #_ REGISTER_OUT v4 [7FFF8000, 000A000B, 000C000D, 000E000F]
+  #_ REGISTER_OUT v5 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
+
+test_vpkshss128_3:
+  # {-1, -128, 0, 127, -2, -129, 1, 128}
+  #_ REGISTER_IN v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  # {-3, -130, 2, 129, -4, -131, 3, 130}
+  #_ REGISTER_IN v4 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vpkshss128 v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v4 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  # {-1, -128, 0, 127, -2, -128, 1, 127,
+  #  -3, -128, 2, 127, -4, -128, 3, 127}
+  #_ REGISTER_OUT v5 [FF80007F, FE80017F, FD80027F, FC80037F]

src/xenia/cpu/frontend/testing/instr_vpkshus128.s

@@ -0,0 +1,11 @@
+test_vpkshus128_1:
+  # {-1, -128, 0, 127, -2, -129, 1, 128}
+  #_ REGISTER_IN v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  # {-3, -130, 2, 129, -4, -131, 3, 130}
+  #_ REGISTER_IN v4 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  vpkshus128 v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
+  #_ REGISTER_OUT v4 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
+  # {0, 0, 0, 127, 0, 0, 1, 128, 0, 0, 2, 129, 0, 0, 3, 130}
+  #_ REGISTER_OUT v5 [0000007F, 00000180, 00000281, 00000382]

src/xenia/cpu/frontend/testing/instr_vpkswss128.s

@@ -0,0 +1,29 @@
+test_vpkswss128_1:
+  #_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
+  #_ REGISTER_IN v4 [00000005, 00000006, 00000007, 00000008]
+  vpkswss128 v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
+  #_ REGISTER_OUT v4 [00000005, 00000006, 00000007, 00000008]
+  #_ REGISTER_OUT v5 [00010002, 00030004, 00050006, 00070008]
+
+test_vpkswss128_2:
+  #_ REGISTER_IN v3 [7FFFFFFF, 80000000, 00000000, 00000004]
+  #_ REGISTER_IN v4 [7FFFFFFF, 80000000, 00000000, 00000008]
+  vpkswss128 v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFFFFFF, 80000000, 00000000, 00000004]
+  #_ REGISTER_OUT v4 [7FFFFFFF, 80000000, 00000000, 00000008]
+  #_ REGISTER_OUT v5 [7FFF8000, 00000004, 7FFF8000, 00000008]
+
+test_vpkswss128_3:
+  # {-1, -32768, 0, 32767}
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFF8000, 00000000, 00007FFF]
+  # {-2, -32769, 1, 32768}
+  #_ REGISTER_IN v4 [FFFFFFFE, FFFF7FFF, 00000001, 00008000]
+  vpkswss128 v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFF8000, 00000000, 00007FFF]
+  #_ REGISTER_OUT v4 [FFFFFFFE, FFFF7FFF, 00000001, 00008000]
+  # {-1, -32768, 0, 32767, -2, -32768, 1, 32767}
+  #_ REGISTER_OUT v5 [FFFF8000, 00007FFF, FFFE8000, 00017FFF]

src/xenia/cpu/frontend/testing/instr_vpkswus128.s

@@ -0,0 +1,11 @@
+test_vpkswus128_1:
+  # {-1, -32768, 0, 32767}
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFF8000, 00000000, 00007FFF]
+  # {-2, -32769, 1, 32768}
+  #_ REGISTER_IN v4 [FFFFFFFE, FFFF7FFF, 00000001, 00008000]
+  vpkswus128 v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFF8000, 00000000, 00007FFF]
+  #_ REGISTER_OUT v4 [FFFFFFFE, FFFF7FFF, 00000001, 00008000]
+  # {0, 0, 0, 32767, 0, 0, 1, 32768}
+  #_ REGISTER_OUT v5 [00000000, 00007FFF, 00000000, 00018000]

src/xenia/cpu/frontend/testing/instr_vpkuhum128.s

@@ -0,0 +1,39 @@
+#vpkuhum128 isn't implemented yet
+#test_vpkuhum128_1:
+#  # {0, 1, 2, 3, 4, 5, 6, 7}
+#  #_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
+#  # {8, 9, 10, 11, 12, 13, 14, 15}
+#  #_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
+#  vpkuhum128 v5, v3, v4
+#  blr
+#  #_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
+#  #_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
+#  # {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}
+#  #_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+#  blr
+
+#test_vpkuhum128_2:
+#  # {-8, -7, -6, -5, -4, -3, -2, -1}
+#  #_ REGISTER_IN v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF]
+#  # {0, 1, 2, 3, 4, 5, 6, 7}
+#  #_ REGISTER_IN v4 [00000001, 00020003, 00040005, 00060007]
+#  vpkuhum128 v5, v3, v4
+#  blr
+#  #_ REGISTER_OUT v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF]
+#  #_ REGISTER_OUT v4 [00000001, 00020003, 00040005, 00060007]
+#  # {-8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7}
+#  #_ REGISTER_OUT v5 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+#  blr
+
+#test_vpkuhum128_3:
+#  # {0, 65535, 65535, 0, 0, 0, 65535, 0}
+#  #_ REGISTER_IN v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+#  # {65535, 0, 0, 65535, 65535, 65535, 0, 65535}
+#  #_ REGISTER_IN v4 [FFFF0000, 0000FFFF, FFFFFFFF, 0000FFFF]
+#  vpkuhum128 v5, v3, v4
+#  blr
+#  #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
+#  #_ REGISTER_OUT v4 [FFFF0000, 0000FFFF, FFFFFFFF, 0000FFFF]
+#  # {0, 255, 255, 0, 0, 0, 255, 0, 255, 0, 0, 255, 255, 255, 0, 255}
+#  #_ REGISTER_OUT v5 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+#  blr

src/xenia/cpu/frontend/testing/instr_vpkuhus128.s

@@ -0,0 +1,11 @@
+test_vpkuhus128_1:
+  # {0, 256, 1, 257, 2, 258, 3, 259}
+  #_ REGISTER_IN v3 [00000100, 00010101, 00020102, 00030103]
+  # {4, 260, 5, 261, 6, 262, 7, 263}
+  #_ REGISTER_IN v4 [00040104, 00050105, 00060106, 00070107]
+  vpkuhus128 v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000100, 00010101, 00020102, 00030103]
+  #_ REGISTER_OUT v4 [00040104, 00050105, 00060106, 00070107]
+  # {0, 255, 1, 255, 2, 255, 3, 255, 4, 255, 5, 255, 6, 255, 7, 255}
+  #_ REGISTER_OUT v5 [00FF01FF, 02FF03FF, 04FF05FF, 06FF07FF]

src/xenia/cpu/frontend/testing/instr_vpkuwum128.s

@@ -0,0 +1,36 @@
+#vpkuwum128 isn't implemented yet
+#test_vpkuwum128_1:
+#  # {0, 1, 2, 3}
+#  #_ REGISTER_IN v3 [00000000, 00000001, 00000002, 00000003]
+#  # {4, 5, 6, 7}
+#  #_ REGISTER_IN v4 [00000004, 00000005, 00000006, 00000007]
+#  vpkuwum128 v5, v3, v4
+#  blr
+#  #_ REGISTER_OUT v3 [00000000, 00000001, 00000002, 00000003]
+#  #_ REGISTER_OUT v4 [00000004, 00000005, 00000006, 00000007]
+#  # {0, 1, 2, 3, 4, 5, 6, 7}
+#  #_ REGISTER_OUT v5 [00000001, 00020003, 00040005, 00060007]
+
+#test_vpkuwum128_2:
+#  # {-4, -3, -2, -1}
+#  #_ REGISTER_IN v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
+#  # {0, 1, 2, 3}
+#  #_ REGISTER_IN v4 [00000000, 00000001, 00000002, 00000003]
+#  vpkuwum128 v5, v3, v4
+#  blr
+#  #_ REGISTER_OUT v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
+#  #_ REGISTER_OUT v4 [00000000, 00000001, 00000002, 00000003]
+#  # {-4, -3, -2, -1, 0, 1, 2, 3}
+#  #_ REGISTER_OUT v5 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
+
+#test_vpkuwum128_3:
+#  # {0, 4294967295, 4294967295, 4294967295}
+#  #_ REGISTER_IN v3 [00000000, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+#  # {4294967295, 0, 0, 0}
+#  #_ REGISTER_IN v4 [FFFFFFFF, 00000000, 00000000, 00000000]
+#  vpkuwum128 v5, v3, v4
+#  blr
+#  #_ REGISTER_OUT v3 [00000000, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+#  #_ REGISTER_OUT v4 [FFFFFFFF, 00000000, 00000000, 00000000]
+#  # {0, 65535, 65535, 65535, 65535, 0, 0, 0}
+#  #_ REGISTER_OUT v5 [0000FFFF, FFFFFFFF, FFFF0000, 00000000]

src/xenia/cpu/frontend/testing/instr_vpkuwus128.s

@@ -0,0 +1,11 @@
+test_vpkuwus128_1:
+  # {0, 65536, 1, 65537}
+  #_ REGISTER_IN v3 [00000000, 00010000, 00000001, 00010001]
+  # {2, 65538, 3, 65539}
+  #_ REGISTER_IN v4 [00000002, 00010002, 00000003, 00010003]
+  vpkuwus128 v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00010000, 00000001, 00010001]
+  #_ REGISTER_OUT v4 [00000002, 00010002, 00000003, 00010003]
+  # {0, 65535, 1, 65535, 2, 65535, 3, 65535}
+  #_ REGISTER_OUT v5 [0000FFFF, 0001FFFF, 0002FFFF, 0003FFFF]

src/xenia/cpu/frontend/testing/instr_vupkhsb128.s

@@ -0,0 +1,15 @@
+test_vupkhsb128_1:
+  # {-8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7}
+  #_ REGISTER_IN v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vupkhsb128 v3, v3
+  blr
+  # {-8, -7, -6, -5, -4, -3, -2, -1}
+  #_ REGISTER_OUT v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF]
+
+test_vupkhsb128_2:
+  # {0, 255, 255, 0, 0, 0, 255, 0, 255, 0, 0, 255, 255, 255, 0, 255}
+  #_ REGISTER_IN v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vupkhsb128 v3, v3
+  blr
+  # {0, 65535, 65535, 0, 0, 0, 65535, 0}
+  #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]

src/xenia/cpu/frontend/testing/instr_vupklsb128.s

@@ -0,0 +1,15 @@
+test_vupklsb128_1:
+  # {-8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7}
+  #_ REGISTER_IN v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
+  vupklsb128 v3, v3
+  blr
+  # {0, 1, 2, 3, 4, 5, 6, 7}
+  #_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
+
+test_vupklsb128_2:
+  # {0, 255, 255, 0, 0, 0, 255, 0, 255, 0, 0, 255, 255, 255, 0, 255}
+  #_ REGISTER_IN v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
+  vupklsb128 v3, v3
+  blr
+  # {65535, 0, 0, 65535, 65535, 65535, 0, 65535}
+  #_ REGISTER_OUT v3 [FFFF0000, 0000FFFF, FFFFFFFF, 0000FFFF]

src/xenia/cpu/frontend/testing/instr_vxor.s

@@ -0,0 +1,8 @@
+test_vxor_1:
+  #_ REGISTER_IN v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_IN v4 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vxor v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v4 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v5 [7FF71111, F0FFFFFF, 80000000, 8FFFFFFF]

src/xenia/cpu/frontend/testing/instr_vxor128.s

@@ -0,0 +1,8 @@
+test_vxor128_1:
+  #_ REGISTER_IN v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_IN v4 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  vxor128 v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
+  #_ REGISTER_OUT v4 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
+  #_ REGISTER_OUT v5 [7FF71111, F0FFFFFF, 80000000, 8FFFFFFF]