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Cleaning up a bit in prep for float/vec.

This commit is contained in:
Ben Vanik 2014-01-26 21:04:30 -08:00
parent 1518523651
commit 1988edfd55
2 changed files with 1344 additions and 1243 deletions
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101
src/alloy/backend/x64/lowering/lowering_sequences.cc
View File

@ -24,7 +24,6 @@ using namespace alloy::runtime;
using namespace Xbyak;
namespace {
#define UNIMPLEMENTED_SEQ() __debugbreak()
@ -33,6 +32,18 @@ namespace {
#define ITRACE 1
#define DTRACE 0
#define SHUFPS_SWAP_DWORDS 0x1B
// A note about vectors:
// Alloy represents vectors as xyzw pairs, with indices 0123.
// XMM registers are xyzw pairs with indices 3210, making them more like wzyx.
// This makes things somewhat confusing. It'd be nice to just shuffle the
// registers around on load/store, however certain operations require that
// data be in the right offset.
// Basically, this identity must hold:
// shuffle(vec, b00011011) -> {x,y,z,w} => {x,y,z,w}
// All indices and operations must respect that.
// TODO(benvanik): emit traces/printfs/etc
void Dummy() {
@ -1150,8 +1161,8 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
} else if (i->Match(SIG_TYPE_V128, SIG_TYPE_IGNORE)) {
Xmm dest;
e.BeginOp(i->dest, dest, REG_DEST);
// TODO(benvanik): we should try to stick to movaps if possible.
e.movups(dest, e.ptr[e.rcx + i->src1.offset]);
// NOTE: we always know we are aligned.
e.movaps(dest, e.ptr[e.rcx + i->src1.offset]);
e.EndOp(dest);
} else {
ASSERT_INVALID_TYPE();
@ -1339,6 +1350,7 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
// TODO(benvanik): we should try to stick to movaps if possible.
e.movups(dest, e.ptr[addr]);
e.EndOp(dest);
e.db(0xCC);
} else {
ASSERT_INVALID_TYPE();
}
@ -1450,6 +1462,7 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
// TODO(benvanik): we should try to stick to movaps if possible.
e.movups(e.ptr[addr], src);
e.EndOp(src);
e.db(0xCC);
} else if (i->Match(SIG_TYPE_X, SIG_TYPE_IGNORE, SIG_TYPE_V128C)) {
e.mov(e.ptr[addr], i->src2.value->constant.v128.low);
e.mov(e.ptr[addr + 8], i->src2.value->constant.v128.high);
@ -1690,6 +1703,7 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
// --------------------------------------------------------------------------
table->AddSequence(OPCODE_ADD, [](X64Emitter& e, Instr*& i) {
if (IsIntType(i->dest->type)) {
BinaryOp(
e, i,
[](X64Emitter& e, Instr& i, const Reg& dest_src, const Operand& src) {
@ -1698,11 +1712,15 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
[](X64Emitter& e, Instr& i, const Reg& dest_src, uint32_t src) {
e.add(dest_src, src);
});
} else {
UNIMPLEMENTED_SEQ();
}
i = e.Advance(i);
return true;
});
table->AddSequence(OPCODE_ADD_CARRY, [](X64Emitter& e, Instr*& i) {
if (IsIntType(i->dest->type)) {
// dest = src1 + src2 + src3.i8
TernaryOp(
e, i,
@ -1734,11 +1752,15 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
e.sahf();
e.adc(dest_src, src2);
});
} else {
UNIMPLEMENTED_SEQ();
}
i = e.Advance(i);
return true;
});
table->AddSequence(OPCODE_SUB, [](X64Emitter& e, Instr*& i) {
if (IsIntType(i->dest->type)) {
BinaryOp(
e, i,
[](X64Emitter& e, Instr& i, const Reg& dest_src, const Operand& src) {
@ -1747,6 +1769,9 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
[](X64Emitter& e, Instr& i, const Reg& dest_src, uint32_t src) {
e.sub(dest_src, src);
});
} else {
UNIMPLEMENTED_SEQ();
}
i = e.Advance(i);
return true;
});
@ -1754,6 +1779,7 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
#define LIKE_REG(dest, like) Operand(dest.getIdx(), dest.getKind(), like.getBit(), false)
table->AddSequence(OPCODE_MUL, [](X64Emitter& e, Instr*& i) {
if (IsIntType(i->dest->type)) {
BinaryOp(
e, i,
[](X64Emitter& e, Instr& i, const Reg& dest_src, const Operand& src) {
@ -1782,11 +1808,15 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
}
e.mov(dest_src, Nax);
});
} else {
UNIMPLEMENTED_SEQ();
}
i = e.Advance(i);
return true;
});
table->AddSequence(OPCODE_MUL_HI, [](X64Emitter& e, Instr*& i) {
if (IsIntType(i->dest->type)) {
BinaryOp(
e, i,
[](X64Emitter& e, Instr& i, const Reg& dest_src, const Operand& src) {
@ -1816,11 +1846,15 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
}
e.mov(dest_src, Ndx);
});
} else {
UNIMPLEMENTED_SEQ();
}
i = e.Advance(i);
return true;
});
table->AddSequence(OPCODE_DIV, [](X64Emitter& e, Instr*& i) {
if (IsIntType(i->dest->type)) {
BinaryOp(
e, i,
[](X64Emitter& e, Instr& i, const Reg& dest_src, const Operand& src) {
@ -1849,6 +1883,9 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
}
e.mov(dest_src, Nax);
});
} else {
UNIMPLEMENTED_SEQ();
}
i = e.Advance(i);
return true;
});
@ -1914,6 +1951,7 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
});
table->AddSequence(OPCODE_AND, [](X64Emitter& e, Instr*& i) {
if (IsIntType(i->dest->type)) {
BinaryOp(
e, i,
[](X64Emitter& e, Instr& i, const Reg& dest_src, const Operand& src) {
@ -1922,11 +1960,15 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
[](X64Emitter& e, Instr& i, const Reg& dest_src, uint32_t src) {
e.and(dest_src, src);
});
} else {
UNIMPLEMENTED_SEQ();
}
i = e.Advance(i);
return true;
});
table->AddSequence(OPCODE_OR, [](X64Emitter& e, Instr*& i) {
if (IsIntType(i->dest->type)) {
BinaryOp(
e, i,
[](X64Emitter& e, Instr& i, const Reg& dest_src, const Operand& src) {
@ -1935,11 +1977,15 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
[](X64Emitter& e, Instr& i, const Reg& dest_src, uint32_t src) {
e.or(dest_src, src);
});
} else {
UNIMPLEMENTED_SEQ();
}
i = e.Advance(i);
return true;
});
table->AddSequence(OPCODE_XOR, [](X64Emitter& e, Instr*& i) {
if (IsIntType(i->dest->type)) {
BinaryOp(
e, i,
[](X64Emitter& e, Instr& i, const Reg& dest_src, const Operand& src) {
@ -1948,21 +1994,29 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
[](X64Emitter& e, Instr& i, const Reg& dest_src, uint32_t src) {
e.xor(dest_src, src);
});
} else {
UNIMPLEMENTED_SEQ();
}
i = e.Advance(i);
return true;
});
table->AddSequence(OPCODE_NOT, [](X64Emitter& e, Instr*& i) {
if (IsIntType(i->dest->type)) {
UnaryOp(
e, i,
[](X64Emitter& e, Instr& i, const Reg& dest_src) {
e.not(dest_src);
});
} else {
UNIMPLEMENTED_SEQ();
}
i = e.Advance(i);
return true;
});
table->AddSequence(OPCODE_SHL, [](X64Emitter& e, Instr*& i) {
if (IsIntType(i->dest->type)) {
// TODO(benvanik): use shlx if available.
BinaryOp(
e, i,
@ -1982,6 +2036,9 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
[](X64Emitter& e, Instr& i, const Reg& dest_src, uint32_t src) {
e.shl(dest_src, src);
});
} else {
UNIMPLEMENTED_SEQ();
}
i = e.Advance(i);
return true;
});
@ -1993,6 +2050,7 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
});
table->AddSequence(OPCODE_SHR, [](X64Emitter& e, Instr*& i) {
if (IsIntType(i->dest->type)) {
// TODO(benvanik): use shrx if available.
BinaryOp(
e, i,
@ -2007,6 +2065,9 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
[](X64Emitter& e, Instr& i, const Reg& dest_src, uint32_t src) {
e.shr(dest_src, src);
});
} else {
UNIMPLEMENTED_SEQ();
}
i = e.Advance(i);
return true;
});
@ -2018,6 +2079,7 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
});
table->AddSequence(OPCODE_SHA, [](X64Emitter& e, Instr*& i) {
if (IsIntType(i->dest->type)) {
// TODO(benvanik): use sarx if available.
BinaryOp(
e, i,
@ -2032,6 +2094,9 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
[](X64Emitter& e, Instr& i, const Reg& dest_src, uint32_t src) {
e.sar(dest_src, src);
});
} else {
UNIMPLEMENTED_SEQ();
}
i = e.Advance(i);
return true;
});
@ -2043,6 +2108,7 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
});
table->AddSequence(OPCODE_ROTATE_LEFT, [](X64Emitter& e, Instr*& i) {
if (IsIntType(i->dest->type)) {
BinaryOp(
e, i,
[](X64Emitter& e, Instr& i, const Reg& dest_src, const Operand& src) {
@ -2056,6 +2122,9 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
[](X64Emitter& e, Instr& i, const Reg& dest_src, uint32_t src) {
e.rol(dest_src, src);
});
} else {
UNIMPLEMENTED_SEQ();
}
i = e.Advance(i);
return true;
});
@ -2100,6 +2169,17 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
e.bswap(d);
}
e.EndOp(d, s1);
} else if (i->Match(SIG_TYPE_V128, SIG_TYPE_V128)) {
Xmm d, s1;
e.db(0xCC);
e.BeginOp(i->dest, d, REG_DEST,
i->src1.value, s1, 0);
if (d != s1) {
e.shufps(d, s1, SHUFPS_SWAP_DWORDS);
} else {
e.shufps(d, d, SHUFPS_SWAP_DWORDS);
}
e.EndOp(d, s1);
} else {
ASSERT_INVALID_TYPE();
}
@ -2185,7 +2265,22 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
});
table->AddSequence(OPCODE_SWIZZLE, [](X64Emitter& e, Instr*& i) {
if (IsVecType(i->dest->type)) {
// Defined by SWIZZLE_MASK()
if (i->flags == INT32_TYPE || i->flags == FLOAT32_TYPE) {
uint8_t swizzle_mask = (uint8_t)i->src2.offset;
e.db(0xCC);
Xmm dest, src1;
e.BeginOp(i->dest, dest, REG_DEST,
i->src1.value, src1, 0);
e.pshufd(dest, src1, swizzle_mask);
e.EndOp(dest, src1);
} else {
UNIMPLEMENTED_SEQ();
}
} else {
UNIMPLEMENTED_SEQ();
}
i = e.Advance(i);
return true;
});

8
src/alloy/hir/value.h
View File

@ -34,7 +34,13 @@ enum TypeName {
};
static bool IsIntType(TypeName type_name) {
return type_name < 4;
return type_name <= INT64_TYPE;
}
static bool IsFloatType(TypeName type_name) {
return type_name == FLOAT32_TYPE || type_name == FLOAT64_TYPE;
}
static bool IsVecType(TypeName type_name) {
return type_name == VEC128_TYPE;
}
enum ValueFlags {