diff --git a/src/alloy/frontend/ppc/test/bin/instr_stvew.bin b/src/alloy/frontend/ppc/test/bin/instr_stvew.bin
new file mode 100644
index 000000000..ceea4226b
Binary files /dev/null and b/src/alloy/frontend/ppc/test/bin/instr_stvew.bin differ
diff --git a/src/alloy/frontend/ppc/test/bin/instr_stvew.dis b/src/alloy/frontend/ppc/test/bin/instr_stvew.dis
new file mode 100644
index 000000000..a5c4cac0b
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_stvew.dis
@@ -0,0 +1,21 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_stvew.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_stvew_1>:
+  100000:	7c 60 21 8e 	stvewx  v3,0,r4
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_stvew_2>:
+  100008:	7c 60 21 8e 	stvewx  v3,0,r4
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_stvew_3>:
+  100010:	7c 60 21 8e 	stvewx  v3,0,r4
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_stvew_4>:
+  100018:	7c 60 21 8e 	stvewx  v3,0,r4
+  10001c:	4e 80 00 20 	blr
diff --git a/src/alloy/frontend/ppc/test/bin/instr_stvew.map b/src/alloy/frontend/ppc/test/bin/instr_stvew.map
new file mode 100644
index 000000000..7a317bfbf
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_stvew.map
@@ -0,0 +1,4 @@
+0000000000000000 t test_stvew_1
+0000000000000008 t test_stvew_2
+0000000000000010 t test_stvew_3
+0000000000000018 t test_stvew_4
diff --git a/src/alloy/frontend/ppc/test/instr_stvew.s b/src/alloy/frontend/ppc/test/instr_stvew.s
new file mode 100644
index 000000000..ec13b25e2
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/instr_stvew.s
@@ -0,0 +1,39 @@
+test_stvew_1:
+  #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
+  #_ REGISTER_IN r4 0x1050
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  stvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x1050
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ MEMORY_OUT 00001050 00010203 CCCCCCCC CCCCCCCC CCCCCCCC
+
+test_stvew_2:
+  #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
+  #_ REGISTER_IN r4 0x1054
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  stvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x1054
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ MEMORY_OUT 00001050 CCCCCCCC 04050607 CCCCCCCC CCCCCCCC
+
+test_stvew_3:
+  #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
+  #_ REGISTER_IN r4 0x1058
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  stvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x1058
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ MEMORY_OUT 00001050 CCCCCCCC CCCCCCCC 08090A0B CCCCCCCC
+
+test_stvew_4:
+  #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
+  #_ REGISTER_IN r4 0x105C
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  stvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0x105C
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ MEMORY_OUT 00001050 CCCCCCCC CCCCCCCC CCCCCCCC 0C0D0E0F