From 0d3e79ad2c2cbc1a68148029c67125e52d981805 Mon Sep 17 00:00:00 2001
From: Ben Vanik <ben.vanik@gmail.com>
Date: Wed, 13 May 2015 00:19:07 -0700
Subject: [PATCH] Supporting const src1 mul_hi.

---
 src/xenia/cpu/backend/x64/x64_sequences.cc    |  24 +++++-
 src/xenia/cpu/frontend/test/bin/instr_eqv.bin | Bin 48 -> 192 bytes
 src/xenia/cpu/frontend/test/bin/instr_eqv.dis |  70 +++++++++++++++---
 src/xenia/cpu/frontend/test/bin/instr_eqv.map |  16 ++--
 .../cpu/frontend/test/bin/instr_lvexx.bin     | Bin 48 -> 120 bytes
 .../cpu/frontend/test/bin/instr_lvexx.dis     |  58 +++++++++++----
 .../cpu/frontend/test/bin/instr_lvexx.map     |  16 ++--
 src/xenia/cpu/frontend/test/bin/instr_lvl.bin | Bin 8 -> 20 bytes
 src/xenia/cpu/frontend/test/bin/instr_lvl.dis |   5 ++
 src/xenia/cpu/frontend/test/bin/instr_lvl.map |   1 +
 src/xenia/cpu/frontend/test/bin/instr_lvr.bin | Bin 8 -> 24 bytes
 src/xenia/cpu/frontend/test/bin/instr_lvr.dis |   6 ++
 src/xenia/cpu/frontend/test/bin/instr_lvr.map |   1 +
 .../cpu/frontend/test/bin/instr_lvsl.bin      | Bin 24 -> 60 bytes
 .../cpu/frontend/test/bin/instr_lvsl.dis      |  27 +++++--
 .../cpu/frontend/test/bin/instr_lvsl.map      |   7 +-
 .../cpu/frontend/test/bin/instr_lvsr.bin      | Bin 24 -> 60 bytes
 .../cpu/frontend/test/bin/instr_lvsr.dis      |  27 +++++--
 .../cpu/frontend/test/bin/instr_lvsr.map      |   7 +-
 .../cpu/frontend/test/bin/instr_mulhd.bin     | Bin 40 -> 120 bytes
 .../cpu/frontend/test/bin/instr_mulhd.dis     |  48 +++++++++---
 .../cpu/frontend/test/bin/instr_mulhd.map     |  13 +++-
 22 files changed, 258 insertions(+), 68 deletions(-)

diff --git a/src/xenia/cpu/backend/x64/x64_sequences.cc b/src/xenia/cpu/backend/x64/x64_sequences.cc
index a6b78feb5..a99ace327 100644
--- a/src/xenia/cpu/backend/x64/x64_sequences.cc
+++ b/src/xenia/cpu/backend/x64/x64_sequences.cc
@@ -3299,7 +3299,11 @@ EMITTER(MUL_HI_I8, MATCH(I<OPCODE_MUL_HI, I8<>, I8<>, I8<>>)) {
         }
       }
     } else {
-      e.mov(e.al, i.src1);
+      if (i.src1.is_constant) {
+        e.mov(e.al, i.src1.constant());
+      } else {
+        e.mov(e.al, i.src1);
+      }
       if (i.src2.is_constant) {
         e.mov(e.al, i.src2.constant());
         e.imul(e.al);
@@ -3339,7 +3343,11 @@ EMITTER(MUL_HI_I16, MATCH(I<OPCODE_MUL_HI, I16<>, I16<>, I16<>>)) {
         }
       }
     } else {
-      e.mov(e.ax, i.src1);
+      if (i.src1.is_constant) {
+        e.mov(e.ax, i.src1.constant());
+      } else {
+        e.mov(e.ax, i.src1);
+      }
       if (i.src2.is_constant) {
         e.mov(e.dx, i.src2.constant());
         e.imul(e.dx);
@@ -3384,7 +3392,11 @@ EMITTER(MUL_HI_I32, MATCH(I<OPCODE_MUL_HI, I32<>, I32<>, I32<>>)) {
         }
       }
     } else {
-      e.mov(e.eax, i.src1);
+      if (i.src1.is_constant) {
+        e.mov(e.eax, i.src1.constant());
+      } else {
+        e.mov(e.eax, i.src1);
+      }
       if (i.src2.is_constant) {
         e.mov(e.edx, i.src2.constant());
         e.imul(e.edx);
@@ -3429,7 +3441,11 @@ EMITTER(MUL_HI_I64, MATCH(I<OPCODE_MUL_HI, I64<>, I64<>, I64<>>)) {
         }
       }
     } else {
-      e.mov(e.rax, i.src1);
+      if (i.src1.is_constant) {
+        e.mov(e.rax, i.src1.constant());
+      } else {
+        e.mov(e.rax, i.src1);
+      }
       if (i.src2.is_constant) {
         e.mov(e.rdx, i.src2.constant());
         e.imul(e.rdx);
diff --git a/src/xenia/cpu/frontend/test/bin/instr_eqv.bin b/src/xenia/cpu/frontend/test/bin/instr_eqv.bin
index 35b148a570fbbe0eedb3569a9ca975bf131f93ca..c134dd44142a0f0916d193363b59a7c62922e6de 100644
GIT binary patch
literal 192
zcmb<v*0S(xU{J7VU|_IVz`$4o<-=%;hX4P8;tVi8jE0E+{}1ECXq$$6YZF@by{~9x
dKUUGgpir|!xuT{Oh|$c&rp{skapobr2LLngNEHA8

literal 48
Scmb<v*0S(xU{I(bk_G@@jSbrX

diff --git a/src/xenia/cpu/frontend/test/bin/instr_eqv.dis b/src/xenia/cpu/frontend/test/bin/instr_eqv.dis
index c7bfef7ff..bfb525b44 100644
--- a/src/xenia/cpu/frontend/test/bin/instr_eqv.dis
+++ b/src/xenia/cpu/frontend/test/bin/instr_eqv.dis
@@ -4,22 +4,70 @@ Disassembly of section .text:
   100000:       7c 83 2a 38     eqv     r3,r4,r5
   100004:       4e 80 00 20     blr
 
-0000000000100008 <test_eqv_2>:
-  100008:       7c 83 2a 38     eqv     r3,r4,r5
-  10000c:       4e 80 00 20     blr
-
-0000000000100010 <test_eqv_3>:
+0000000000100008 <test_eqv_1_constant>:
+  100008:       38 80 00 00     li      r4,0
+  10000c:       38 a0 00 01     li      r5,1
   100010:       7c 83 2a 38     eqv     r3,r4,r5
   100014:       4e 80 00 20     blr
 
-0000000000100018 <test_eqv_4>:
+0000000000100018 <test_eqv_2>:
   100018:       7c 83 2a 38     eqv     r3,r4,r5
   10001c:       4e 80 00 20     blr
 
-0000000000100020 <test_eqv_5>:
-  100020:       7c 83 2a 38     eqv     r3,r4,r5
-  100024:       4e 80 00 20     blr
-
-0000000000100028 <test_eqv_6>:
+0000000000100020 <test_eqv_2_constant>:
+  100020:       38 80 ff ff     li      r4,-1
+  100024:       38 a0 00 00     li      r5,0
   100028:       7c 83 2a 38     eqv     r3,r4,r5
   10002c:       4e 80 00 20     blr
+
+0000000000100030 <test_eqv_3>:
+  100030:       7c 83 2a 38     eqv     r3,r4,r5
+  100034:       4e 80 00 20     blr
+
+0000000000100038 <test_eqv_3_constant>:
+  100038:       38 80 ff ff     li      r4,-1
+  10003c:       38 a0 ff ff     li      r5,-1
+  100040:       7c 83 2a 38     eqv     r3,r4,r5
+  100044:       4e 80 00 20     blr
+
+0000000000100048 <test_eqv_4>:
+  100048:       7c 83 2a 38     eqv     r3,r4,r5
+  10004c:       4e 80 00 20     blr
+
+0000000000100050 <test_eqv_4_constant>:
+  100050:       3c 80 de ad     lis     r4,-8531
+  100054:       60 84 be ef     ori     r4,r4,48879
+  100058:       78 85 07 c6     rldicr  r5,r4,32,31
+  10005c:       78 84 00 20     clrldi  r4,r4,32
+  100060:       7c a4 23 78     or      r4,r5,r4
+  100064:       7c 85 23 78     mr      r5,r4
+  100068:       7c 83 2a 38     eqv     r3,r4,r5
+  10006c:       4e 80 00 20     blr
+
+0000000000100070 <test_eqv_5>:
+  100070:       7c 83 2a 38     eqv     r3,r4,r5
+  100074:       4e 80 00 20     blr
+
+0000000000100078 <test_eqv_5_constant>:
+  100078:       3c 80 de ad     lis     r4,-8531
+  10007c:       60 84 be ef     ori     r4,r4,48879
+  100080:       78 85 07 c6     rldicr  r5,r4,32,31
+  100084:       78 84 00 20     clrldi  r4,r4,32
+  100088:       7c a4 23 78     or      r4,r5,r4
+  10008c:       38 a0 ff ff     li      r5,-1
+  100090:       7c 83 2a 38     eqv     r3,r4,r5
+  100094:       4e 80 00 20     blr
+
+0000000000100098 <test_eqv_6>:
+  100098:       7c 83 2a 38     eqv     r3,r4,r5
+  10009c:       4e 80 00 20     blr
+
+00000000001000a0 <test_eqv_6_constant>:
+  1000a0:       3c 80 de ad     lis     r4,-8531
+  1000a4:       60 84 be ef     ori     r4,r4,48879
+  1000a8:       78 85 07 c6     rldicr  r5,r4,32,31
+  1000ac:       78 84 00 20     clrldi  r4,r4,32
+  1000b0:       7c a4 23 78     or      r4,r5,r4
+  1000b4:       38 a0 00 00     li      r5,0
+  1000b8:       7c 83 2a 38     eqv     r3,r4,r5
+  1000bc:       4e 80 00 20     blr
diff --git a/src/xenia/cpu/frontend/test/bin/instr_eqv.map b/src/xenia/cpu/frontend/test/bin/instr_eqv.map
index 5b234eaec..51d902831 100644
--- a/src/xenia/cpu/frontend/test/bin/instr_eqv.map
+++ b/src/xenia/cpu/frontend/test/bin/instr_eqv.map
@@ -1,6 +1,12 @@
 0000000000000000 t test_eqv_1
-0000000000000008 t test_eqv_2
-0000000000000010 t test_eqv_3
-0000000000000018 t test_eqv_4
-0000000000000020 t test_eqv_5
-0000000000000028 t test_eqv_6
+0000000000000008 t test_eqv_1_constant
+0000000000000018 t test_eqv_2
+0000000000000020 t test_eqv_2_constant
+0000000000000030 t test_eqv_3
+0000000000000038 t test_eqv_3_constant
+0000000000000048 t test_eqv_4
+0000000000000050 t test_eqv_4_constant
+0000000000000070 t test_eqv_5
+0000000000000078 t test_eqv_5_constant
+0000000000000098 t test_eqv_6
+00000000000000a0 t test_eqv_6_constant
diff --git a/src/xenia/cpu/frontend/test/bin/instr_lvexx.bin b/src/xenia/cpu/frontend/test/bin/instr_lvexx.bin
index 29aed79e213cf6a0929d0e992a66a54f33b85b98..0d1495754109f21dd541ba62df022978cd4913c6 100644
GIT binary patch
literal 120
zcmb<PP~h`xU{J7VU|^_$vSBn(j0MI9(tb$lz-%NjkUE%HACfvS8z=`81E~YE0U7lk
A{Qv*}

literal 48
acmb<PP~h`xU{I(*(0))pjP8T-!88CsGYwGy

diff --git a/src/xenia/cpu/frontend/test/bin/instr_lvexx.dis b/src/xenia/cpu/frontend/test/bin/instr_lvexx.dis
index 8c28024d9..7fdb3c2f0 100644
--- a/src/xenia/cpu/frontend/test/bin/instr_lvexx.dis
+++ b/src/xenia/cpu/frontend/test/bin/instr_lvexx.dis
@@ -4,22 +4,52 @@ Disassembly of section .text:
   100000:       7c 60 20 0e     lvebx   v3,0,r4
   100004:       4e 80 00 20     blr
 
-0000000000100008 <test_lvebx_2>:
-  100008:       7c 60 20 0e     lvebx   v3,0,r4
-  10000c:       4e 80 00 20     blr
+0000000000100008 <test_lvebx_1_constant>:
+  100008:       38 80 00 00     li      r4,0
+  10000c:       7c 60 20 0e     lvebx   v3,0,r4
+  100010:       4e 80 00 20     blr
 
-0000000000100010 <test_lvehx_1>:
-  100010:       7c 60 20 4e     lvehx   v3,0,r4
-  100014:       4e 80 00 20     blr
+0000000000100014 <test_lvebx_2>:
+  100014:       7c 60 20 0e     lvebx   v3,0,r4
+  100018:       4e 80 00 20     blr
 
-0000000000100018 <test_lvehx_2>:
-  100018:       7c 60 20 4e     lvehx   v3,0,r4
-  10001c:       4e 80 00 20     blr
-
-0000000000100020 <test_lvewx_1>:
-  100020:       7c 60 20 8e     lvewx   v3,0,r4
+000000000010001c <test_lvebx_2_constant>:
+  10001c:       38 80 00 04     li      r4,4
+  100020:       7c 60 20 0e     lvebx   v3,0,r4
   100024:       4e 80 00 20     blr
 
-0000000000100028 <test_lvewx_2>:
-  100028:       7c 60 20 8e     lvewx   v3,0,r4
+0000000000100028 <test_lvehx_1>:
+  100028:       7c 60 20 4e     lvehx   v3,0,r4
   10002c:       4e 80 00 20     blr
+
+0000000000100030 <test_lvehx_1_constant>:
+  100030:       38 80 00 00     li      r4,0
+  100034:       7c 60 20 4e     lvehx   v3,0,r4
+  100038:       4e 80 00 20     blr
+
+000000000010003c <test_lvehx_2>:
+  10003c:       7c 60 20 4e     lvehx   v3,0,r4
+  100040:       4e 80 00 20     blr
+
+0000000000100044 <test_lvehx_2_constant>:
+  100044:       38 80 00 04     li      r4,4
+  100048:       7c 60 20 4e     lvehx   v3,0,r4
+  10004c:       4e 80 00 20     blr
+
+0000000000100050 <test_lvewx_1>:
+  100050:       7c 60 20 8e     lvewx   v3,0,r4
+  100054:       4e 80 00 20     blr
+
+0000000000100058 <test_lvewx_1_constant>:
+  100058:       38 80 00 00     li      r4,0
+  10005c:       7c 60 20 8e     lvewx   v3,0,r4
+  100060:       4e 80 00 20     blr
+
+0000000000100064 <test_lvewx_2>:
+  100064:       7c 60 20 8e     lvewx   v3,0,r4
+  100068:       4e 80 00 20     blr
+
+000000000010006c <test_lvewx_2_constant>:
+  10006c:       38 80 00 04     li      r4,4
+  100070:       7c 60 20 8e     lvewx   v3,0,r4
+  100074:       4e 80 00 20     blr
diff --git a/src/xenia/cpu/frontend/test/bin/instr_lvexx.map b/src/xenia/cpu/frontend/test/bin/instr_lvexx.map
index 2e0940590..5308d578b 100644
--- a/src/xenia/cpu/frontend/test/bin/instr_lvexx.map
+++ b/src/xenia/cpu/frontend/test/bin/instr_lvexx.map
@@ -1,6 +1,12 @@
 0000000000000000 t test_lvebx_1
-0000000000000008 t test_lvebx_2
-0000000000000010 t test_lvehx_1
-0000000000000018 t test_lvehx_2
-0000000000000020 t test_lvewx_1
-0000000000000028 t test_lvewx_2
+0000000000000008 t test_lvebx_1_constant
+0000000000000014 t test_lvebx_2
+000000000000001c t test_lvebx_2_constant
+0000000000000028 t test_lvehx_1
+0000000000000030 t test_lvehx_1_constant
+000000000000003c t test_lvehx_2
+0000000000000044 t test_lvehx_2_constant
+0000000000000050 t test_lvewx_1
+0000000000000058 t test_lvewx_1_constant
+0000000000000064 t test_lvewx_2
+000000000000006c t test_lvewx_2_constant
diff --git a/src/xenia/cpu/frontend/test/bin/instr_lvl.bin b/src/xenia/cpu/frontend/test/bin/instr_lvl.bin
index 671e6951f3433fdcd6a86adb041a2f331d109b37..dff227017c00a785e5afb4b3e1ddb35c9cc9c4e0 100644
GIT binary patch
literal 20
Vcmb<PVd3*@U{J7V5Gb#KvH>?I1poj5

literal 8
Pcmb<PVd3*@U{C-63EBbS

diff --git a/src/xenia/cpu/frontend/test/bin/instr_lvl.dis b/src/xenia/cpu/frontend/test/bin/instr_lvl.dis
index 9844e4b03..cc0115aad 100644
--- a/src/xenia/cpu/frontend/test/bin/instr_lvl.dis
+++ b/src/xenia/cpu/frontend/test/bin/instr_lvl.dis
@@ -3,3 +3,8 @@ Disassembly of section .text:
 0000000000100000 <test_lvl_1>:
   100000:       7c 64 04 0e     lvlx    v3,r4,r0
   100004:       4e 80 00 20     blr
+
+0000000000100008 <test_lvl_1_constant>:
+  100008:       38 80 10 77     li      r4,4215
+  10000c:       7c 64 04 0e     lvlx    v3,r4,r0
+  100010:       4e 80 00 20     blr
diff --git a/src/xenia/cpu/frontend/test/bin/instr_lvl.map b/src/xenia/cpu/frontend/test/bin/instr_lvl.map
index a5a3ba36c..f43fe3fa1 100644
--- a/src/xenia/cpu/frontend/test/bin/instr_lvl.map
+++ b/src/xenia/cpu/frontend/test/bin/instr_lvl.map
@@ -1 +1,2 @@
 0000000000000000 t test_lvl_1
+0000000000000008 t test_lvl_1_constant
diff --git a/src/xenia/cpu/frontend/test/bin/instr_lvr.bin b/src/xenia/cpu/frontend/test/bin/instr_lvr.bin
index a8e07544ebb6f5faf1ef689b6d842c47b59e6a20..10f29611f8e873ed82d0528625fae7277cab742e 100644
GIT binary patch
literal 24
acmb<P(ed+ZU{J7V5ZG?9fI*-J$_D^j*9Q0i

literal 8
Pcmb<P(ed+ZU{C-63<?5C

diff --git a/src/xenia/cpu/frontend/test/bin/instr_lvr.dis b/src/xenia/cpu/frontend/test/bin/instr_lvr.dis
index 326f29bdc..4620e3111 100644
--- a/src/xenia/cpu/frontend/test/bin/instr_lvr.dis
+++ b/src/xenia/cpu/frontend/test/bin/instr_lvr.dis
@@ -3,3 +3,9 @@ Disassembly of section .text:
 0000000000100000 <test_lvr_1>:
   100000:       7c 64 2c 4e     lvrx    v3,r4,r5
   100004:       4e 80 00 20     blr
+
+0000000000100008 <test_lvr_1_constant>:
+  100008:       38 80 10 b7     li      r4,4279
+  10000c:       38 a0 00 10     li      r5,16
+  100010:       7c 64 2c 4e     lvrx    v3,r4,r5
+  100014:       4e 80 00 20     blr
diff --git a/src/xenia/cpu/frontend/test/bin/instr_lvr.map b/src/xenia/cpu/frontend/test/bin/instr_lvr.map
index 770c292eb..d86874b56 100644
--- a/src/xenia/cpu/frontend/test/bin/instr_lvr.map
+++ b/src/xenia/cpu/frontend/test/bin/instr_lvr.map
@@ -1 +1,2 @@
 0000000000000000 t test_lvr_1
+0000000000000008 t test_lvr_1_constant
diff --git a/src/xenia/cpu/frontend/test/bin/instr_lvsl.bin b/src/xenia/cpu/frontend/test/bin/instr_lvsl.bin
index c8d11323ccb2782b6e9f926931c4993bf39d8122..ce4cf428967d373a8c84e2e797a95e57d7c87f91 100644
GIT binary patch
literal 60
icmb<PVc_v=U{J7V5GbgDvSBn(tPsYA(Lk|!7#je~7Y@|`

literal 24
Rcmb<PVc_v=U{I(*qX9{n1&;s#

diff --git a/src/xenia/cpu/frontend/test/bin/instr_lvsl.dis b/src/xenia/cpu/frontend/test/bin/instr_lvsl.dis
index 3a70349f8..80b248453 100644
--- a/src/xenia/cpu/frontend/test/bin/instr_lvsl.dis
+++ b/src/xenia/cpu/frontend/test/bin/instr_lvsl.dis
@@ -4,10 +4,25 @@ Disassembly of section .text:
   100000:       7c 64 00 0c     lvsl    v3,r4,r0
   100004:       4e 80 00 20     blr
 
-0000000000100008 <test_lvsl_2>:
-  100008:       7c 64 00 0c     lvsl    v3,r4,r0
-  10000c:       4e 80 00 20     blr
+0000000000100008 <test_lvsl_1_constant>:
+  100008:       38 80 10 70     li      r4,4208
+  10000c:       7c 64 00 0c     lvsl    v3,r4,r0
+  100010:       4e 80 00 20     blr
 
-0000000000100010 <test_lvsl_3>:
-  100010:       7c 64 00 0c     lvsl    v3,r4,r0
-  100014:       4e 80 00 20     blr
+0000000000100014 <test_lvsl_2>:
+  100014:       7c 64 00 0c     lvsl    v3,r4,r0
+  100018:       4e 80 00 20     blr
+
+000000000010001c <test_lvsl_2_constant>:
+  10001c:       38 80 10 71     li      r4,4209
+  100020:       7c 64 00 0c     lvsl    v3,r4,r0
+  100024:       4e 80 00 20     blr
+
+0000000000100028 <test_lvsl_3>:
+  100028:       7c 64 00 0c     lvsl    v3,r4,r0
+  10002c:       4e 80 00 20     blr
+
+0000000000100030 <test_lvsl_3_constant>:
+  100030:       38 80 10 7f     li      r4,4223
+  100034:       7c 64 00 0c     lvsl    v3,r4,r0
+  100038:       4e 80 00 20     blr
diff --git a/src/xenia/cpu/frontend/test/bin/instr_lvsl.map b/src/xenia/cpu/frontend/test/bin/instr_lvsl.map
index 9092d008f..81ddc9d6e 100644
--- a/src/xenia/cpu/frontend/test/bin/instr_lvsl.map
+++ b/src/xenia/cpu/frontend/test/bin/instr_lvsl.map
@@ -1,3 +1,6 @@
 0000000000000000 t test_lvsl_1
-0000000000000008 t test_lvsl_2
-0000000000000010 t test_lvsl_3
+0000000000000008 t test_lvsl_1_constant
+0000000000000014 t test_lvsl_2
+000000000000001c t test_lvsl_2_constant
+0000000000000028 t test_lvsl_3
+0000000000000030 t test_lvsl_3_constant
diff --git a/src/xenia/cpu/frontend/test/bin/instr_lvsr.bin b/src/xenia/cpu/frontend/test/bin/instr_lvsr.bin
index 7ea145691725b6fe68e2c4f2728cd19a5d0d2e46..e2ed022cb6313d91b92edcd90b7c0e2118f0062f 100644
GIT binary patch
literal 60
icmb<PVes*5U{J7V5GbgDvSBn(tPsYA(Lk|!7#jfjmk?C|

literal 24
Rcmb<PVes*5U{I(*qXAP`22TJ0

diff --git a/src/xenia/cpu/frontend/test/bin/instr_lvsr.dis b/src/xenia/cpu/frontend/test/bin/instr_lvsr.dis
index a870e00b8..81d01b7ac 100644
--- a/src/xenia/cpu/frontend/test/bin/instr_lvsr.dis
+++ b/src/xenia/cpu/frontend/test/bin/instr_lvsr.dis
@@ -4,10 +4,25 @@ Disassembly of section .text:
   100000:       7c 64 00 4c     lvsr    v3,r4,r0
   100004:       4e 80 00 20     blr
 
-0000000000100008 <test_lvsr_2>:
-  100008:       7c 64 00 4c     lvsr    v3,r4,r0
-  10000c:       4e 80 00 20     blr
+0000000000100008 <test_lvsr_1_constant>:
+  100008:       38 80 10 70     li      r4,4208
+  10000c:       7c 64 00 4c     lvsr    v3,r4,r0
+  100010:       4e 80 00 20     blr
 
-0000000000100010 <test_lvsr_3>:
-  100010:       7c 64 00 4c     lvsr    v3,r4,r0
-  100014:       4e 80 00 20     blr
+0000000000100014 <test_lvsr_2>:
+  100014:       7c 64 00 4c     lvsr    v3,r4,r0
+  100018:       4e 80 00 20     blr
+
+000000000010001c <test_lvsr_2_constant>:
+  10001c:       38 80 10 71     li      r4,4209
+  100020:       7c 64 00 4c     lvsr    v3,r4,r0
+  100024:       4e 80 00 20     blr
+
+0000000000100028 <test_lvsr_3>:
+  100028:       7c 64 00 4c     lvsr    v3,r4,r0
+  10002c:       4e 80 00 20     blr
+
+0000000000100030 <test_lvsr_3_constant>:
+  100030:       38 80 10 7f     li      r4,4223
+  100034:       7c 64 00 4c     lvsr    v3,r4,r0
+  100038:       4e 80 00 20     blr
diff --git a/src/xenia/cpu/frontend/test/bin/instr_lvsr.map b/src/xenia/cpu/frontend/test/bin/instr_lvsr.map
index daf1ee1cc..3dcbe79f9 100644
--- a/src/xenia/cpu/frontend/test/bin/instr_lvsr.map
+++ b/src/xenia/cpu/frontend/test/bin/instr_lvsr.map
@@ -1,3 +1,6 @@
 0000000000000000 t test_lvsr_1
-0000000000000008 t test_lvsr_2
-0000000000000010 t test_lvsr_3
+0000000000000008 t test_lvsr_1_constant
+0000000000000014 t test_lvsr_2
+000000000000001c t test_lvsr_2_constant
+0000000000000028 t test_lvsr_3
+0000000000000030 t test_lvsr_3_constant
diff --git a/src/xenia/cpu/frontend/test/bin/instr_mulhd.bin b/src/xenia/cpu/frontend/test/bin/instr_mulhd.bin
index 7b4ce8e351a78549851afb14c3e2ed4bad60d30f..d147782444f0e4dd8f26e067520f4538c4981e60 100644
GIT binary patch
literal 120
zcmb<P(U|1dz@T8!z`$s+fPtX~%7@Vw4gdcG#Tj9I7!4I?g7INANNvTEA8ar_jE1QH
I{~yK&0C0{ffB*mh

literal 40
Scmb<P(U|1dz@Sh=fCc~z?F^{^

diff --git a/src/xenia/cpu/frontend/test/bin/instr_mulhd.dis b/src/xenia/cpu/frontend/test/bin/instr_mulhd.dis
index fae492834..a6ea9ea2e 100644
--- a/src/xenia/cpu/frontend/test/bin/instr_mulhd.dis
+++ b/src/xenia/cpu/frontend/test/bin/instr_mulhd.dis
@@ -4,18 +4,48 @@ Disassembly of section .text:
   100000:       7c 64 28 92     mulhd   r3,r4,r5
   100004:       4e 80 00 20     blr
 
-0000000000100008 <test_mulhd_2>:
-  100008:       7c 64 28 92     mulhd   r3,r4,r5
-  10000c:       4e 80 00 20     blr
-
-0000000000100010 <test_mulhd_3>:
+0000000000100008 <test_mulhd_1_constant>:
+  100008:       38 80 00 01     li      r4,1
+  10000c:       38 a0 00 00     li      r5,0
   100010:       7c 64 28 92     mulhd   r3,r4,r5
   100014:       4e 80 00 20     blr
 
-0000000000100018 <test_mulhd_4>:
+0000000000100018 <test_mulhd_2>:
   100018:       7c 64 28 92     mulhd   r3,r4,r5
   10001c:       4e 80 00 20     blr
 
-0000000000100020 <test_mulhd_5>:
-  100020:       7c 64 28 92     mulhd   r3,r4,r5
-  100024:       4e 80 00 20     blr
+0000000000100020 <test_mulhd_2_constant>:
+  100020:       38 80 ff ff     li      r4,-1
+  100024:       38 a0 00 01     li      r5,1
+  100028:       7c 64 28 92     mulhd   r3,r4,r5
+  10002c:       4e 80 00 20     blr
+
+0000000000100030 <test_mulhd_3>:
+  100030:       7c 64 28 92     mulhd   r3,r4,r5
+  100034:       4e 80 00 20     blr
+
+0000000000100038 <test_mulhd_3_constant>:
+  100038:       38 80 ff ff     li      r4,-1
+  10003c:       38 a0 00 02     li      r5,2
+  100040:       7c 64 28 92     mulhd   r3,r4,r5
+  100044:       4e 80 00 20     blr
+
+0000000000100048 <test_mulhd_4>:
+  100048:       7c 64 28 92     mulhd   r3,r4,r5
+  10004c:       4e 80 00 20     blr
+
+0000000000100050 <test_mulhd_4_constant>:
+  100050:       38 a0 00 01     li      r5,1
+  100054:       78 a4 f8 06     rldicr  r4,r5,63,0
+  100058:       7c 64 28 92     mulhd   r3,r4,r5
+  10005c:       4e 80 00 20     blr
+
+0000000000100060 <test_mulhd_5>:
+  100060:       7c 64 28 92     mulhd   r3,r4,r5
+  100064:       4e 80 00 20     blr
+
+0000000000100068 <test_mulhd_5_constant>:
+  100068:       38 80 ff ff     li      r4,-1
+  10006c:       38 a0 ff ff     li      r5,-1
+  100070:       7c 64 28 92     mulhd   r3,r4,r5
+  100074:       4e 80 00 20     blr
diff --git a/src/xenia/cpu/frontend/test/bin/instr_mulhd.map b/src/xenia/cpu/frontend/test/bin/instr_mulhd.map
index 3699fc0f3..0a067f460 100644
--- a/src/xenia/cpu/frontend/test/bin/instr_mulhd.map
+++ b/src/xenia/cpu/frontend/test/bin/instr_mulhd.map
@@ -1,5 +1,10 @@
 0000000000000000 t test_mulhd_1
-0000000000000008 t test_mulhd_2
-0000000000000010 t test_mulhd_3
-0000000000000018 t test_mulhd_4
-0000000000000020 t test_mulhd_5
+0000000000000008 t test_mulhd_1_constant
+0000000000000018 t test_mulhd_2
+0000000000000020 t test_mulhd_2_constant
+0000000000000030 t test_mulhd_3
+0000000000000038 t test_mulhd_3_constant
+0000000000000048 t test_mulhd_4
+0000000000000050 t test_mulhd_4_constant
+0000000000000060 t test_mulhd_5
+0000000000000068 t test_mulhd_5_constant