Tests: vand/vand128/vandc/vandc128/vcmpxxfp128/vmaxfp/vmaxfp128/vmaxsh/vmaxuh/vminfp/vminfp128

src/xenia/cpu/frontend/testing/instr_vand.s

@@ -0,0 +1,8 @@
+test_vand_1:
+  #_ REGISTER_IN v3 [FFFF0101, 7070FFFF, 7FFFFFFF, 00000000]
+  #_ REGISTER_IN v4 [80081010, 808F0020, 7FFFFFF0, 8FFFFFFF]
+  vand v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, 7FFFFFFF, 00000000]
+  #_ REGISTER_OUT v4 [80081010, 808F0020, 7FFFFFF0, 8FFFFFFF]
+  #_ REGISTER_OUT v5 [80080000, 00000020, 7FFFFFF0, 00000000]

src/xenia/cpu/frontend/testing/instr_vand128.s

@@ -0,0 +1,8 @@
+test_vand128_1:
+  #_ REGISTER_IN v3 [FFFF0101, 7070FFFF, 7FFFFFFF, 00000000]
+  #_ REGISTER_IN v4 [80081010, 808F0020, 7FFFFFF0, 8FFFFFFF]
+  vand128 v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, 7FFFFFFF, 00000000]
+  #_ REGISTER_OUT v4 [80081010, 808F0020, 7FFFFFF0, 8FFFFFFF]
+  #_ REGISTER_OUT v5 [80080000, 00000020, 7FFFFFF0, 00000000]

src/xenia/cpu/frontend/testing/instr_vandc.s

@@ -0,0 +1,8 @@
+test_vandc_1:
+  #_ REGISTER_IN v3 [FFFF0101, 7070FFFF, 7FFFFFFF, 00000000]
+  #_ REGISTER_IN v4 [80081010, 808F0020, 7FFFFFF0, 8FFFFFFF]
+  vandc v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, 7FFFFFFF, 00000000]
+  #_ REGISTER_OUT v4 [80081010, 808F0020, 7FFFFFF0, 8FFFFFFF]
+  #_ REGISTER_OUT v5 [7FF70101, 7070FFDF, 0000000F, 00000000]

src/xenia/cpu/frontend/testing/instr_vandc128.s

@@ -0,0 +1,8 @@
+test_vandc128_1:
+  #_ REGISTER_IN v3 [FFFF0101, 7070FFFF, 7FFFFFFF, 00000000]
+  #_ REGISTER_IN v4 [80081010, 808F0020, 7FFFFFF0, 8FFFFFFF]
+  vandc128 v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, 7FFFFFFF, 00000000]
+  #_ REGISTER_OUT v4 [80081010, 808F0020, 7FFFFFF0, 8FFFFFFF]
+  #_ REGISTER_OUT v5 [7FF70101, 7070FFDF, 0000000F, 00000000]

src/xenia/cpu/frontend/testing/instr_vcmpxxfp128.s

@@ -0,0 +1,32 @@
+test_vcmpxxfp128_1:
+  #_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_IN v5 [3f800000, 3f800000, 3f800000, 3f800000]
+  vcmpeqfp128. v3, v4, v5
+  mfocrf  r3, 2  # cr6
+  blr
+  #_ REGISTER_OUT v3 [ffffffff, ffffffff, ffffffff, ffffffff]
+  #_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_OUT v5 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_OUT r3 0x00000080
+
+test_vcmpxxfp128_2:
+  #_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_IN v5 [3f800001, 3f800000, 3f800000, 3f800000]
+  vcmpeqfp128. v3, v4, v5
+  mfocrf  r3, 2  # cr6
+  blr
+  #_ REGISTER_OUT v3 [00000000, ffffffff, ffffffff, ffffffff]
+  #_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_OUT v5 [3f800001, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_OUT r3 0x00000000
+
+test_vcmpxxfp128_3:
+  #_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_IN v5 [3f800001, 3f800001, 3f800001, 3f800001]
+  vcmpeqfp128. v3, v4, v5
+  mfocrf  r3, 2  # cr6
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
+  #_ REGISTER_OUT v5 [3f800001, 3f800001, 3f800001, 3f800001]
+  #_ REGISTER_OUT r3 0x00000020

src/xenia/cpu/frontend/testing/instr_vmaxfp.s

@@ -0,0 +1,10 @@
+test_vmaxfp_1:
+  # v3 = [10.0, -10.0, 15.0, -15.0]
+  # v4 = [-10.0, 20.0, -20.0, 30.0]
+  #_ REGISTER_IN v3 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_IN v4 [C1200000, 41A00000, C1A00000, 41F00000]
+  vmaxfp v0, v3, v4
+  blr
+  #_ REGISTER_OUT v0 [41200000, 41A00000, 41700000, 41F00000]
+  #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v4 [C1200000, 41A00000, C1A00000, 41F00000]

src/xenia/cpu/frontend/testing/instr_vmaxfp128.s

@@ -0,0 +1,10 @@
+test_vmaxfp128_1:
+  # v3 = [10.0, -10.0, 15.0, -15.0]
+  # v4 = [-10.0, 20.0, -20.0, 30.0]
+  #_ REGISTER_IN v3 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_IN v4 [C1200000, 41A00000, C1A00000, 41F00000]
+  vmaxfp128 v0, v3, v4
+  blr
+  #_ REGISTER_OUT v0 [41200000, 41A00000, 41700000, 41F00000]
+  #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v4 [C1200000, 41A00000, C1A00000, 41F00000]

src/xenia/cpu/frontend/testing/instr_vmaxsh.s

@@ -0,0 +1,17 @@
+test_vmaxsh_1:
+  #_ REGISTER_IN v3 [00000001, 00020003, 00040005, 80060007]
+  #_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
+  vmaxsh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 80060007]
+  #_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
+  #_ REGISTER_OUT v5 [00080009, 000A000B, 000C000D, 000E000F]
+
+test_vmaxsh_2:
+  #_ REGISTER_IN v3 [00000009, 0002000B, 0004000D, 0006000F]
+  #_ REGISTER_IN v4 [00080001, 000A0003, 000C0005, 000E0007]
+  vmaxsh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000009, 0002000B, 0004000D, 0006000F]
+  #_ REGISTER_OUT v4 [00080001, 000A0003, 000C0005, 000E0007]
+  #_ REGISTER_OUT v5 [00080009, 000A000B, 000C000D, 000E000F]

src/xenia/cpu/frontend/testing/instr_vmaxuh.s

@@ -0,0 +1,17 @@
+test_vmaxuh_1:
+  #_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
+  #_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 800E000F]
+  vmaxuh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
+  #_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 800E000F]
+  #_ REGISTER_OUT v5 [00080009, 000A000B, 000C000D, 800E000F]
+
+test_vmaxuh_2:
+  #_ REGISTER_IN v3 [00000009, 0002000B, 0004000D, 0006000F]
+  #_ REGISTER_IN v4 [00080001, 000A0003, 000C0005, 000E0007]
+  vmaxuh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000009, 0002000B, 0004000D, 0006000F]
+  #_ REGISTER_OUT v4 [00080001, 000A0003, 000C0005, 000E0007]
+  #_ REGISTER_OUT v5 [00080009, 000A000B, 000C000D, 000E000F]

src/xenia/cpu/frontend/testing/instr_vminfp.s

@@ -0,0 +1,10 @@
+test_vminfp_1:
+  # v3 = [10.0, -10.0, 15.0, -15.0]
+  # v4 = [-10.0, 20.0, -20.0, 30.0]
+  #_ REGISTER_IN v3 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_IN v4 [C1200000, 41A00000, C1A00000, 41F00000]
+  vminfp v0, v3, v4
+  blr
+  #_ REGISTER_OUT v0 [C1200000, C1200000, C1A00000, C1700000]
+  #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v4 [C1200000, 41A00000, C1A00000, 41F00000]

src/xenia/cpu/frontend/testing/instr_vminfp128.s

@@ -0,0 +1,10 @@
+test_vminfp128_1:
+  # v3 = [10.0, -10.0, 15.0, -15.0]
+  # v4 = [-10.0, 20.0, -20.0, 30.0]
+  #_ REGISTER_IN v3 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_IN v4 [C1200000, 41A00000, C1A00000, 41F00000]
+  vminfp128 v0, v3, v4
+  blr
+  #_ REGISTER_OUT v0 [C1200000, C1200000, C1A00000, C1700000]
+  #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
+  #_ REGISTER_OUT v4 [C1200000, 41A00000, C1A00000, 41F00000]