//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeEDRAMLoadStoreConstants
// {
//
//   uint4 xe_edram_load_store_constants;// Offset:    0 Size:    16
//   uint xe_edram_base_samples_2x_depth_pitch;// Offset:   16 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_edram_load_store_source        texture    byte         r/o      T0             t0      1 
// xe_edram_load_store_dest              UAV    byte         r/w      U0             u0      1 
// XeEDRAMLoadStoreConstants         cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadGroupID.xy
dcl_input vThreadIDInGroup.xy
dcl_input vThreadID.xy
dcl_temps 4
dcl_thread_group 40, 16, 1
ishl r0.x, vThreadIDInGroup.x, l(1)
and r0.yz, CB0[0][1].xxxx, l(0, 0x00008000, 2047, 0)
if_nz r0.y
  ult r0.y, vThreadIDInGroup.x, l(20)
  uge r0.w, vThreadIDInGroup.x, l(20)
  and r0.yw, r0.yyyw, l(0, 40, 0, -40)
  iadd r0.y, r0.w, r0.y
  iadd r0.x, r0.y, r0.x
endif 
ushr r0.y, CB0[0][1].x, l(16)
imad r0.y, vThreadGroupID.y, r0.y, r0.z
iadd r0.y, r0.y, vThreadGroupID.x
imul null, r0.z, vThreadIDInGroup.y, l(320)
imad r0.y, r0.y, l(5120), r0.z
ishl r0.x, r0.x, l(2)
iadd r0.x, r0.x, r0.y
ubfe r0.yzw, l(0, 1, 1, 1), l(0, 13, 12, 11), CB0[0][1].xxxx
ishl r0.y, r0.y, l(1)
ishl r0.x, r0.x, r0.y
ld_raw r1.xyzw, r0.x, T0[0].xyzw
iadd r0.x, r0.x, l(16)
ld_raw r2.xyzw, r0.x, T0[0].xzyw
if_nz r0.z
  mov r3.x, r2.x
  mov r3.y, r1.y
  mov r2.x, r2.y
  mov r2.y, r1.w
else 
  mov r3.x, r1.y
  mov r3.y, r2.x
  mov r2.x, r1.w
endif 
not r0.x, r0.w
and r0.xy, r0.xwxx, vThreadID.yyyy
imad r0.x, r0.x, l(2), r0.y
ishl r0.y, vThreadID.x, l(4)
imad r0.x, r0.x, CB0[0][0].y, r0.y
mov r3.z, r1.x
mov r3.w, r2.z
store_raw U0[0].xyzw, r0.x, r3.zxyw
ishl r0.y, l(1), r0.w
imad r0.x, r0.y, CB0[0][0].y, r0.x
mov r2.z, r1.z
store_raw U0[0].xyzw, r0.x, r2.zxyw
ret 
// Approximately 45 instruction slots used
