//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeEDRAMLoadStoreConstants
// {
//
//   uint4 xe_edram_load_store_constants;// Offset:    0 Size:    16
//   uint xe_edram_base_samples_2x_depth_pitch;// Offset:   16 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_edram_load_store_dest              UAV    byte         r/w      U0             u0      1 
// XeEDRAMLoadStoreConstants         cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadGroupID.xy
dcl_input vThreadIDInGroup.xy
dcl_input vThreadID.xy
dcl_temps 2
dcl_thread_group 40, 16, 1
and r0.xy, CB0[0][0].xyxx, l(0x0000ffff, 0x0000ffff, 0, 0)
ushr r0.zw, CB0[0][0].xxxy, l(0, 0, 16, 16)
ishl r1.x, vThreadID.x, l(1)
uge r0.x, r1.x, r0.x
ult r0.y, r1.x, r0.y
and r0.x, r0.y, r0.x
ult r0.y, vThreadID.y, r0.z
uge r0.z, vThreadID.y, r0.w
or r0.y, r0.z, r0.y
ieq r0.z, r0.x, l(0)
or r0.y, r0.z, r0.y
if_nz r0.y
  ret 
endif 
ishl r0.y, vThreadIDInGroup.x, l(1)
and r0.zw, CB0[0][1].xxxx, l(0, 0, 0x00008000, 2047)
if_nz r0.z
  ult r0.z, vThreadIDInGroup.x, l(20)
  and r0.z, r0.z, l(40)
  uge r1.x, vThreadIDInGroup.x, l(20)
  and r1.x, r1.x, l(-40)
  iadd r0.z, r0.z, r1.x
  iadd r0.y, r0.z, r0.y
endif 
ushr r0.z, CB0[0][1].x, l(16)
imad r0.z, vThreadGroupID.y, r0.z, r0.w
iadd r0.z, r0.z, vThreadGroupID.x
imul null, r0.w, vThreadIDInGroup.y, l(320)
imad r0.z, r0.z, l(5120), r0.w
ishl r0.y, r0.y, l(2)
iadd r0.y, r0.y, r0.z
ubfe r0.z, l(1), l(13), CB0[0][1].x
ishl r0.w, r0.z, l(1)
ishl r0.y, r0.y, r0.w
if_nz r0.z
  if_nz r0.x
    store_raw U0[0].xyzw, r0.y, CB0[0][0].zzzz
    iadd r0.z, r0.y, l(16)
    store_raw U0[0].xyzw, r0.z, CB0[0][0].zzzz
  endif 
else 
  if_nz r0.x
    store_raw U0[0].xy, r0.y, CB0[0][0].zzzz
  endif 
endif 
ret 
// Approximately 46 instruction slots used
