//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer xe_system_cbuffer
// {
//
//   uint xe_flags;                     // Offset:    0 Size:     4 [unused]
//   uint xe_line_loop_closing_index;   // Offset:    4 Size:     4 [unused]
//   uint xe_vertex_index_endian_and_edge_factors;// Offset:    8 Size:     4 [unused]
//   int xe_vertex_base_index;          // Offset:   12 Size:     4 [unused]
//   float4 xe_user_clip_planes[6];     // Offset:   16 Size:    96 [unused]
//   float3 xe_ndc_scale;               // Offset:  112 Size:    12 [unused]
//   uint xe_pixel_pos_reg;             // Offset:  124 Size:     4 [unused]
//   float3 xe_ndc_offset;              // Offset:  128 Size:    12 [unused]
//   float xe_pixel_half_pixel_offset;  // Offset:  140 Size:     4 [unused]
//   float2 xe_point_size;              // Offset:  144 Size:     8 [unused]
//   float2 xe_point_size_min_max;      // Offset:  152 Size:     8 [unused]
//   float2 xe_point_screen_to_ndc;     // Offset:  160 Size:     8 [unused]
//   uint2 xe_sample_count_log2;        // Offset:  168 Size:     8 [unused]
//   float xe_alpha_test_reference;     // Offset:  176 Size:     4 [unused]
//   uint xe_edram_resolution_square_scale;// Offset:  180 Size:     4 [unused]
//   uint xe_edram_pitch_tiles;         // Offset:  184 Size:     4 [unused]
//   uint xe_edram_depth_base_dwords;   // Offset:  188 Size:     4 [unused]
//   float4 xe_color_exp_bias;          // Offset:  192 Size:    16 [unused]
//   uint4 xe_color_output_map;         // Offset:  208 Size:    16 [unused]
//   float2 xe_tessellation_factor_range;// Offset:  224 Size:     8
//   float2 xe_edram_depth_range;       // Offset:  232 Size:     8 [unused]
//   float2 xe_edram_poly_offset_front; // Offset:  240 Size:     8 [unused]
//   float2 xe_edram_poly_offset_back;  // Offset:  248 Size:     8 [unused]
//   uint4 xe_edram_stencil[2];         // Offset:  256 Size:    32 [unused]
//   uint4 xe_edram_rt_base_dwords_scaled;// Offset:  288 Size:    16 [unused]
//   uint4 xe_edram_rt_format_flags;    // Offset:  304 Size:    16 [unused]
//   float4 xe_edram_rt_clamp[4];       // Offset:  320 Size:    64 [unused]
//   uint4 xe_edram_rt_keep_mask[2];    // Offset:  384 Size:    32 [unused]
//   uint4 xe_edram_rt_blend_factors_ops;// Offset:  416 Size:    16 [unused]
//   float4 xe_edram_blend_constant;    // Offset:  432 Size:    16 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_system_cbuffer                 cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Patch Constant signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_TessFactor            0   x           0 QUADEDGE   float   x   
// SV_TessFactor            1   x           1 QUADEDGE   float   x   
// SV_TessFactor            2   x           2 QUADEDGE   float   x   
// SV_TessFactor            3   x           3 QUADEDGE   float   x   
// SV_InsideTessFactor      0   x           4  QUADINT   float   x   
// SV_InsideTessFactor      1   x           5  QUADINT   float   x   
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
// Tessellation Domain   # of control points
// -------------------- --------------------
// Quadrilateral                           4
//
// Tessellation Output Primitive  Partitioning Type 
// ------------------------------ ------------------
// Clockwise Triangles            Integer           
//
hs_5_1
hs_decls 
dcl_input_control_point_count 4
dcl_output_control_point_count 4
dcl_tessellator_domain domain_quad
dcl_tessellator_partitioning partitioning_integer
dcl_tessellator_output_primitive output_triangle_cw
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][15], immediateIndexed, space=0
hs_fork_phase 
dcl_hs_fork_phase_instance_count 4
dcl_input vForkInstanceID
dcl_output_siv o0.x, finalQuadUeq0EdgeTessFactor
dcl_output_siv o1.x, finalQuadVeq0EdgeTessFactor
dcl_output_siv o2.x, finalQuadUeq1EdgeTessFactor
dcl_output_siv o3.x, finalQuadVeq1EdgeTessFactor
dcl_temps 1
dcl_indexrange o0.x 4
mov r0.x, vForkInstanceID.x
mov o[r0.x + 0].x, CB0[0][14].y
ret 
hs_fork_phase 
dcl_hs_fork_phase_instance_count 2
dcl_input vForkInstanceID
dcl_output_siv o4.x, finalQuadUInsideTessFactor
dcl_output_siv o5.x, finalQuadVInsideTessFactor
dcl_temps 1
dcl_indexrange o4.x 2
mov r0.x, vForkInstanceID.x
mov o[r0.x + 4].x, CB0[0][14].y
ret 
// Approximately 6 instruction slots used
