From feffe590f2dc1e6c9ae7b62b0c6806c276af43e6 Mon Sep 17 00:00:00 2001 From: Ben Vanik Date: Wed, 10 Sep 2014 21:26:35 -0700 Subject: [PATCH] Shift tests and fix for bad sradi decoding. --- src/alloy/frontend/ppc/ppc_emit_alu.cc | 17 +-- src/alloy/frontend/ppc/ppc_instr_tables.h | 6 +- src/alloy/frontend/ppc/test/bin/instr_ori.bin | Bin 8 -> 16 bytes src/alloy/frontend/ppc/test/bin/instr_ori.dis | 6 +- src/alloy/frontend/ppc/test/bin/instr_ori.map | 3 +- src/alloy/frontend/ppc/test/bin/instr_sld.bin | Bin 0 -> 56 bytes src/alloy/frontend/ppc/test/bin/instr_sld.dis | 33 ++++++ src/alloy/frontend/ppc/test/bin/instr_sld.map | 7 ++ src/alloy/frontend/ppc/test/bin/instr_slw.bin | Bin 0 -> 72 bytes src/alloy/frontend/ppc/test/bin/instr_slw.dis | 41 ++++++++ src/alloy/frontend/ppc/test/bin/instr_slw.map | 9 ++ .../frontend/ppc/test/bin/instr_srad.bin | Bin 0 -> 84 bytes .../frontend/ppc/test/bin/instr_srad.dis | 40 +++++++ .../frontend/ppc/test/bin/instr_srad.map | 7 ++ .../frontend/ppc/test/bin/instr_sradi.bin | Bin 0 -> 60 bytes .../frontend/ppc/test/bin/instr_sradi.dis | 30 ++++++ .../frontend/ppc/test/bin/instr_sradi.map | 5 + .../frontend/ppc/test/bin/instr_sraw.bin | Bin 0 -> 108 bytes .../frontend/ppc/test/bin/instr_sraw.dis | 50 +++++++++ .../frontend/ppc/test/bin/instr_sraw.map | 9 ++ .../frontend/ppc/test/bin/instr_srawi.bin | Bin 0 -> 60 bytes .../frontend/ppc/test/bin/instr_srawi.dis | 30 ++++++ .../frontend/ppc/test/bin/instr_srawi.map | 5 + src/alloy/frontend/ppc/test/bin/instr_srd.bin | Bin 0 -> 56 bytes src/alloy/frontend/ppc/test/bin/instr_srd.dis | 33 ++++++ src/alloy/frontend/ppc/test/bin/instr_srd.map | 7 ++ src/alloy/frontend/ppc/test/bin/instr_srw.bin | Bin 0 -> 72 bytes src/alloy/frontend/ppc/test/bin/instr_srw.dis | 41 ++++++++ src/alloy/frontend/ppc/test/bin/instr_srw.map | 9 ++ src/alloy/frontend/ppc/test/instr_ori.s | 11 +- src/alloy/frontend/ppc/test/instr_sld.s | 62 +++++++++++ src/alloy/frontend/ppc/test/instr_slw.s | 80 ++++++++++++++ src/alloy/frontend/ppc/test/instr_srad.s | 76 ++++++++++++++ src/alloy/frontend/ppc/test/instr_sradi.s | 44 ++++++++ src/alloy/frontend/ppc/test/instr_sraw.s | 98 ++++++++++++++++++ src/alloy/frontend/ppc/test/instr_srawi.s | 44 ++++++++ src/alloy/frontend/ppc/test/instr_srd.s | 62 +++++++++++ src/alloy/frontend/ppc/test/instr_srw.s | 80 ++++++++++++++ 38 files changed, 935 insertions(+), 10 deletions(-) create mode 100644 src/alloy/frontend/ppc/test/bin/instr_sld.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_sld.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_sld.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_slw.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_slw.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_slw.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_srad.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_srad.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_srad.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_sradi.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_sradi.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_sradi.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_sraw.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_sraw.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_sraw.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_srawi.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_srawi.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_srawi.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_srd.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_srd.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_srd.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_srw.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_srw.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_srw.map create mode 100644 src/alloy/frontend/ppc/test/instr_sld.s create mode 100644 src/alloy/frontend/ppc/test/instr_slw.s create mode 100644 src/alloy/frontend/ppc/test/instr_srad.s create mode 100644 src/alloy/frontend/ppc/test/instr_sradi.s create mode 100644 src/alloy/frontend/ppc/test/instr_sraw.s create mode 100644 src/alloy/frontend/ppc/test/instr_srawi.s create mode 100644 src/alloy/frontend/ppc/test/instr_srd.s create mode 100644 src/alloy/frontend/ppc/test/instr_srw.s diff --git a/src/alloy/frontend/ppc/ppc_emit_alu.cc b/src/alloy/frontend/ppc/ppc_emit_alu.cc index acfa78e47..3826cc8aa 100644 --- a/src/alloy/frontend/ppc/ppc_emit_alu.cc +++ b/src/alloy/frontend/ppc/ppc_emit_alu.cc @@ -1112,13 +1112,17 @@ XEEMITTER(sradix, 0x7C000674, XS)(PPCHIRBuilder& f, InstrData& i) { // CA is set if any bits are shifted out of the right and if the result // is negative. - assert_true(sh); - uint64_t mask = XEMASK(64 - sh, 63); - Value* ca = f.And(f.Truncate(f.Shr(v, 63), INT8_TYPE), - f.IsTrue(f.And(v, f.LoadConstant(mask)))); - f.StoreCA(ca); + if (sh) { + uint64_t mask = XEMASK(64 - sh, 63); + Value* ca = f.And(f.Truncate(f.Shr(v, 63), INT8_TYPE), + f.IsTrue(f.And(v, f.LoadConstant(mask)))); + f.StoreCA(ca); + + v = f.Sha(v, sh); + } else { + f.StoreCA(f.LoadZero(INT8_TYPE)); + } - v = f.Sha(v, sh); f.StoreGPR(i.XS.RA, v); if (i.XS.Rc) { f.UpdateCR(0, v); @@ -1252,6 +1256,7 @@ void RegisterEmitCategoryALU() { XEREGISTERINSTR(srwx, 0x7C000430); XEREGISTERINSTR(sradx, 0x7C000634); XEREGISTERINSTR(sradix, 0x7C000674); + XEREGISTERINSTR(sradix, 0x7C000676); // HACK XEREGISTERINSTR(srawx, 0x7C000630); XEREGISTERINSTR(srawix, 0x7C000670); } diff --git a/src/alloy/frontend/ppc/ppc_instr_tables.h b/src/alloy/frontend/ppc/ppc_instr_tables.h index bab5e48f1..15819efc2 100644 --- a/src/alloy/frontend/ppc/ppc_instr_tables.h +++ b/src/alloy/frontend/ppc/ppc_instr_tables.h @@ -591,7 +591,11 @@ static InstrType instr_table_31_unprep[] = { INSTRUCTION(srawix, 0x7C000670, X, General, srawix, "Shift Right Algebraic Word Immediate"), INSTRUCTION(sradix, 0x7C000674, XS, General, sradix, - "Shift Right Algebraic Doubleword Immediate"), // TODO + "Shift Right Algebraic Doubleword Immediate"), + INSTRUCTION(sradix, 0x7C000674, XS, General, sradix, + "Shift Right Algebraic Doubleword Immediate"), + INSTRUCTION(sradix, 0x7C000676, XS, General, sradix, + "Shift Right Algebraic Doubleword Immediate"), // HACK INSTRUCTION(eieio, 0x7C0006AC, X, General, _, "Enforce In-Order Execution of I/O Instruction"), INSTRUCTION(sthbrx, 0x7C00072C, X, General, X_RT_RA0_RB, diff --git a/src/alloy/frontend/ppc/test/bin/instr_ori.bin b/src/alloy/frontend/ppc/test/bin/instr_ori.bin index a95f2547aa7addb4a4f2a3822b8e47ee5a575af0..5ddf028d1403ee1ab842d59bb37f83e9273eb570 100644 GIT binary patch literal 16 ScmYdj{&&Z(fk7bwN&^5y!UtCX literal 8 PcmYdj{&&Z(fk6QP6SV`Z diff --git a/src/alloy/frontend/ppc/test/bin/instr_ori.dis b/src/alloy/frontend/ppc/test/bin/instr_ori.dis index d2c2c2cd8..c34e05f06 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_ori.dis +++ b/src/alloy/frontend/ppc/test/bin/instr_ori.dis @@ -4,6 +4,10 @@ Disassembly of section .text: -0000000000100000 : +0000000000100000 : 100000: 60 83 fe dc ori r3,r4,65244 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 60 83 fe dc ori r3,r4,65244 + 10000c: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_ori.map b/src/alloy/frontend/ppc/test/bin/instr_ori.map index 52dfd4aed..63737967f 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_ori.map +++ b/src/alloy/frontend/ppc/test/bin/instr_ori.map @@ -1 +1,2 @@ -0000000000000000 t test_ori +0000000000000000 t test_ori_1 +0000000000000008 t test_ori_2 diff --git a/src/alloy/frontend/ppc/test/bin/instr_sld.bin b/src/alloy/frontend/ppc/test/bin/instr_sld.bin new file mode 100644 index 0000000000000000000000000000000000000000..029f49b3dfa778c87431e8a0b8ee25141e355975 GIT binary patch literal 56 Scmb: + 100000: 7c 83 28 36 sld r3,r4,r5 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 7c 83 28 36 sld r3,r4,r5 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 7c 83 28 36 sld r3,r4,r5 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 83 28 36 sld r3,r4,r5 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 7c 83 28 36 sld r3,r4,r5 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 7c 83 28 36 sld r3,r4,r5 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 83 28 36 sld r3,r4,r5 + 100034: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_sld.map b/src/alloy/frontend/ppc/test/bin/instr_sld.map new file mode 100644 index 000000000..7cc25ae42 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_sld.map @@ -0,0 +1,7 @@ +0000000000000000 t test_sld_1 +0000000000000008 t test_sld_2 +0000000000000010 t test_sld_3 +0000000000000018 t test_sld_4 +0000000000000020 t test_sld_5 +0000000000000028 t test_sld_6 +0000000000000030 t test_sld_7 diff --git a/src/alloy/frontend/ppc/test/bin/instr_slw.bin b/src/alloy/frontend/ppc/test/bin/instr_slw.bin new file mode 100644 index 0000000000000000000000000000000000000000..e27c33b20fdf4ba8287d0fed44b9ce5064e720be GIT binary patch literal 72 Scmb: + 100000: 7c 83 28 30 slw r3,r4,r5 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 7c 83 28 30 slw r3,r4,r5 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 7c 83 28 30 slw r3,r4,r5 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 83 28 30 slw r3,r4,r5 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 7c 83 28 30 slw r3,r4,r5 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 7c 83 28 30 slw r3,r4,r5 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 83 28 30 slw r3,r4,r5 + 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 7c 83 28 30 slw r3,r4,r5 + 10003c: 4e 80 00 20 blr + +0000000000100040 : + 100040: 7c 83 28 30 slw r3,r4,r5 + 100044: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_slw.map b/src/alloy/frontend/ppc/test/bin/instr_slw.map new file mode 100644 index 000000000..911e66b36 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_slw.map @@ -0,0 +1,9 @@ +0000000000000000 t test_slw_1 +0000000000000008 t test_slw_2 +0000000000000010 t test_slw_3 +0000000000000018 t test_slw_4 +0000000000000020 t test_slw_5 +0000000000000028 t test_slw_6 +0000000000000030 t test_slw_7 +0000000000000038 t test_slw_8 +0000000000000040 t test_slw_9 diff --git a/src/alloy/frontend/ppc/test/bin/instr_srad.bin b/src/alloy/frontend/ppc/test/bin/instr_srad.bin new file mode 100644 index 0000000000000000000000000000000000000000..76656b1f7f484d8747df58a4e6e92b20b78e3429 GIT binary patch literal 84 Wcmb: + 100000: 7c 83 2e 34 srad r3,r4,r5 + 100004: 7c c0 01 14 adde r6,r0,r0 + 100008: 4e 80 00 20 blr + +000000000010000c : + 10000c: 7c 83 2e 34 srad r3,r4,r5 + 100010: 7c c0 01 14 adde r6,r0,r0 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 83 2e 34 srad r3,r4,r5 + 10001c: 7c c0 01 14 adde r6,r0,r0 + 100020: 4e 80 00 20 blr + +0000000000100024 : + 100024: 7c 83 2e 34 srad r3,r4,r5 + 100028: 7c c0 01 14 adde r6,r0,r0 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 83 2e 34 srad r3,r4,r5 + 100034: 7c c0 01 14 adde r6,r0,r0 + 100038: 4e 80 00 20 blr + +000000000010003c : + 10003c: 7c 83 2e 34 srad r3,r4,r5 + 100040: 7c c0 01 14 adde r6,r0,r0 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 83 2e 34 srad r3,r4,r5 + 10004c: 7c c0 01 14 adde r6,r0,r0 + 100050: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_srad.map b/src/alloy/frontend/ppc/test/bin/instr_srad.map new file mode 100644 index 000000000..a4e958547 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_srad.map @@ -0,0 +1,7 @@ +0000000000000000 t test_srad_1 +000000000000000c t test_srad_2 +0000000000000018 t test_srad_3 +0000000000000024 t test_srad_4 +0000000000000030 t test_srad_5 +000000000000003c t test_srad_6 +0000000000000048 t test_srad_7 diff --git a/src/alloy/frontend/ppc/test/bin/instr_sradi.bin b/src/alloy/frontend/ppc/test/bin/instr_sradi.bin new file mode 100644 index 0000000000000000000000000000000000000000..e5e0466f31106c84525b8a1b4a9278c657aa0626 GIT binary patch literal 60 gcmb: + 100000: 7c 83 06 74 sradi r3,r4,0 + 100004: 7c c0 01 14 adde r6,r0,r0 + 100008: 4e 80 00 20 blr + +000000000010000c : + 10000c: 7c 83 06 74 sradi r3,r4,0 + 100010: 7c c0 01 14 adde r6,r0,r0 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 83 0e 74 sradi r3,r4,1 + 10001c: 7c c0 01 14 adde r6,r0,r0 + 100020: 4e 80 00 20 blr + +0000000000100024 : + 100024: 7c 83 f6 76 sradi r3,r4,62 + 100028: 7c c0 01 14 adde r6,r0,r0 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 83 fe 76 sradi r3,r4,63 + 100034: 7c c0 01 14 adde r6,r0,r0 + 100038: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_sradi.map b/src/alloy/frontend/ppc/test/bin/instr_sradi.map new file mode 100644 index 000000000..f06dd5ac8 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_sradi.map @@ -0,0 +1,5 @@ +0000000000000000 t test_sradi_1 +000000000000000c t test_sradi_2 +0000000000000018 t test_sradi_3 +0000000000000024 t test_sradi_4 +0000000000000030 t test_sradi_5 diff --git a/src/alloy/frontend/ppc/test/bin/instr_sraw.bin b/src/alloy/frontend/ppc/test/bin/instr_sraw.bin new file mode 100644 index 0000000000000000000000000000000000000000..e66cbcd681f90a6423d66615526a43563a93d13c GIT binary patch literal 108 WcmbSQ{+#r1b literal 0 HcmV?d00001 diff --git a/src/alloy/frontend/ppc/test/bin/instr_sraw.dis b/src/alloy/frontend/ppc/test/bin/instr_sraw.dis new file mode 100644 index 000000000..09e359e0f --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_sraw.dis @@ -0,0 +1,50 @@ + +/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_sraw.o: file format elf64-powerpc + + +Disassembly of section .text: + +0000000000100000 : + 100000: 7c 83 2e 30 sraw r3,r4,r5 + 100004: 7c c0 01 14 adde r6,r0,r0 + 100008: 4e 80 00 20 blr + +000000000010000c : + 10000c: 7c 83 2e 30 sraw r3,r4,r5 + 100010: 7c c0 01 14 adde r6,r0,r0 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 83 2e 30 sraw r3,r4,r5 + 10001c: 7c c0 01 14 adde r6,r0,r0 + 100020: 4e 80 00 20 blr + +0000000000100024 : + 100024: 7c 83 2e 30 sraw r3,r4,r5 + 100028: 7c c0 01 14 adde r6,r0,r0 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 83 2e 30 sraw r3,r4,r5 + 100034: 7c c0 01 14 adde r6,r0,r0 + 100038: 4e 80 00 20 blr + +000000000010003c : + 10003c: 7c 83 2e 30 sraw r3,r4,r5 + 100040: 7c c0 01 14 adde r6,r0,r0 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 83 2e 30 sraw r3,r4,r5 + 10004c: 7c c0 01 14 adde r6,r0,r0 + 100050: 4e 80 00 20 blr + +0000000000100054 : + 100054: 7c 83 2e 30 sraw r3,r4,r5 + 100058: 7c c0 01 14 adde r6,r0,r0 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 7c 83 2e 30 sraw r3,r4,r5 + 100064: 7c c0 01 14 adde r6,r0,r0 + 100068: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_sraw.map b/src/alloy/frontend/ppc/test/bin/instr_sraw.map new file mode 100644 index 000000000..b932d9501 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_sraw.map @@ -0,0 +1,9 @@ +0000000000000000 t test_sraw_1 +000000000000000c t test_sraw_2 +0000000000000018 t test_sraw_3 +0000000000000024 t test_sraw_4 +0000000000000030 t test_sraw_5 +000000000000003c t test_sraw_6 +0000000000000048 t test_sraw_7 +0000000000000054 t test_sraw_8 +0000000000000060 t test_sraw_9 diff --git a/src/alloy/frontend/ppc/test/bin/instr_srawi.bin b/src/alloy/frontend/ppc/test/bin/instr_srawi.bin new file mode 100644 index 0000000000000000000000000000000000000000..d050827549fd6358ef61b60285bf53db2f89efbd GIT binary patch literal 60 fcmb: + 100000: 7c 83 06 70 srawi r3,r4,0 + 100004: 7c c0 01 14 adde r6,r0,r0 + 100008: 4e 80 00 20 blr + +000000000010000c : + 10000c: 7c 83 06 70 srawi r3,r4,0 + 100010: 7c c0 01 14 adde r6,r0,r0 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 83 0e 70 srawi r3,r4,1 + 10001c: 7c c0 01 14 adde r6,r0,r0 + 100020: 4e 80 00 20 blr + +0000000000100024 : + 100024: 7c 83 f6 70 srawi r3,r4,30 + 100028: 7c c0 01 14 adde r6,r0,r0 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 83 fe 70 srawi r3,r4,31 + 100034: 7c c0 01 14 adde r6,r0,r0 + 100038: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_srawi.map b/src/alloy/frontend/ppc/test/bin/instr_srawi.map new file mode 100644 index 000000000..6f4af09e8 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_srawi.map @@ -0,0 +1,5 @@ +0000000000000000 t test_srawi_1 +000000000000000c t test_srawi_2 +0000000000000018 t test_srawi_3 +0000000000000024 t test_srawi_4 +0000000000000030 t test_srawi_5 diff --git a/src/alloy/frontend/ppc/test/bin/instr_srd.bin b/src/alloy/frontend/ppc/test/bin/instr_srd.bin new file mode 100644 index 0000000000000000000000000000000000000000..cee9f21e5790f48f7ba021ac091ef5ac9ae2bce9 GIT binary patch literal 56 Scmb: + 100000: 7c 83 2c 36 srd r3,r4,r5 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 7c 83 2c 36 srd r3,r4,r5 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 7c 83 2c 36 srd r3,r4,r5 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 83 2c 36 srd r3,r4,r5 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 7c 83 2c 36 srd r3,r4,r5 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 7c 83 2c 36 srd r3,r4,r5 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 83 2c 36 srd r3,r4,r5 + 100034: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_srd.map b/src/alloy/frontend/ppc/test/bin/instr_srd.map new file mode 100644 index 000000000..0febab071 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_srd.map @@ -0,0 +1,7 @@ +0000000000000000 t test_srd_1 +0000000000000008 t test_srd_2 +0000000000000010 t test_srd_3 +0000000000000018 t test_srd_4 +0000000000000020 t test_srd_5 +0000000000000028 t test_srd_6 +0000000000000030 t test_srd_7 diff --git a/src/alloy/frontend/ppc/test/bin/instr_srw.bin b/src/alloy/frontend/ppc/test/bin/instr_srw.bin new file mode 100644 index 0000000000000000000000000000000000000000..952c4ba31005421baf840a7afc2775c63a912cf4 GIT binary patch literal 72 Scmb: + 100000: 7c 83 2c 30 srw r3,r4,r5 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 7c 83 2c 30 srw r3,r4,r5 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 7c 83 2c 30 srw r3,r4,r5 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 83 2c 30 srw r3,r4,r5 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 7c 83 2c 30 srw r3,r4,r5 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 7c 83 2c 30 srw r3,r4,r5 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 83 2c 30 srw r3,r4,r5 + 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 7c 83 2c 30 srw r3,r4,r5 + 10003c: 4e 80 00 20 blr + +0000000000100040 : + 100040: 7c 83 2c 30 srw r3,r4,r5 + 100044: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_srw.map b/src/alloy/frontend/ppc/test/bin/instr_srw.map new file mode 100644 index 000000000..5ba1b866b --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_srw.map @@ -0,0 +1,9 @@ +0000000000000000 t test_srw_1 +0000000000000008 t test_srw_2 +0000000000000010 t test_srw_3 +0000000000000018 t test_srw_4 +0000000000000020 t test_srw_5 +0000000000000028 t test_srw_6 +0000000000000030 t test_srw_7 +0000000000000038 t test_srw_8 +0000000000000040 t test_srw_9 diff --git a/src/alloy/frontend/ppc/test/instr_ori.s b/src/alloy/frontend/ppc/test/instr_ori.s index 1a1210e61..e8b85edb3 100644 --- a/src/alloy/frontend/ppc/test/instr_ori.s +++ b/src/alloy/frontend/ppc/test/instr_ori.s @@ -1,4 +1,4 @@ -test_ori: +test_ori_1: #_ REGISTER_IN r4 0xDEADBEEF00000000 ori r3, r4, 0xFEDC @@ -6,3 +6,12 @@ test_ori: blr #_ REGISTER_OUT r3 0xDEADBEEF0000FEDC #_ REGISTER_OUT r4 0xDEADBEEF00000000 + +test_ori_2: + #_ REGISTER_IN r4 0xDEADBEEF10000000 + + ori r3, r4, 0xFEDC + + blr + #_ REGISTER_OUT r3 0xDEADBEEF1000FEDC + #_ REGISTER_OUT r4 0xDEADBEEF10000000 diff --git a/src/alloy/frontend/ppc/test/instr_sld.s b/src/alloy/frontend/ppc/test/instr_sld.s new file mode 100644 index 000000000..a0c525043 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_sld.s @@ -0,0 +1,62 @@ +test_sld_1: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 0 + sld r3, r4, r5 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + +test_sld_2: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0 + sld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + +test_sld_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 1 + sld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + +test_sld_4: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 62 + sld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xc000000000000000 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 62 + +test_sld_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 63 + sld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x8000000000000000 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 63 + +test_sld_6: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 64 + sld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 64 + +test_sld_7: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 100 + sld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 100 diff --git a/src/alloy/frontend/ppc/test/instr_slw.s b/src/alloy/frontend/ppc/test/instr_slw.s new file mode 100644 index 000000000..98438a18b --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_slw.s @@ -0,0 +1,80 @@ +test_slw_1: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 0 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + +test_slw_2: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + +test_slw_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 1 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFE + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + +test_slw_4: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 63 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 63 + +test_slw_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 64 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 64 + +test_slw_6: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 100 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 100 + +test_slw_7: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 30 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000c0000000 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 30 + +test_slw_8: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 31 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000080000000 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 31 + +test_slw_9: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 32 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 32 diff --git a/src/alloy/frontend/ppc/test/instr_srad.s b/src/alloy/frontend/ppc/test/instr_srad.s new file mode 100644 index 000000000..9d9b400d5 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_srad.s @@ -0,0 +1,76 @@ +test_srad_1: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 0 + srad r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r6 0 + +test_srad_2: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0 + srad r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r6 0 + +test_srad_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 1 + srad r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + #_ REGISTER_OUT r6 1 + +test_srad_4: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 62 + srad r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 62 + #_ REGISTER_OUT r6 1 + +test_srad_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 63 + srad r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 63 + #_ REGISTER_OUT r6 1 + +test_srad_6: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 64 + srad r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 64 + #_ REGISTER_OUT r6 1 + +test_srad_7: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 100 + srad r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 100 + #_ REGISTER_OUT r6 1 diff --git a/src/alloy/frontend/ppc/test/instr_sradi.s b/src/alloy/frontend/ppc/test/instr_sradi.s new file mode 100644 index 000000000..4315f22ed --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_sradi.s @@ -0,0 +1,44 @@ +test_sradi_1: + #_ REGISTER_IN r4 1 + sradi r3, r4, 0 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r6 0 + +test_sradi_2: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + sradi r3, r4, 0 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 0 + +test_sradi_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + sradi r3, r4, 1 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + +test_sradi_4: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + sradi r3, r4, 62 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + +test_sradi_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + sradi r3, r4, 63 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 diff --git a/src/alloy/frontend/ppc/test/instr_sraw.s b/src/alloy/frontend/ppc/test/instr_sraw.s new file mode 100644 index 000000000..888ff900d --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_sraw.s @@ -0,0 +1,98 @@ +test_sraw_1: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 0 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r6 0 + +test_sraw_2: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r6 0 + +test_sraw_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 1 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + #_ REGISTER_OUT r6 1 + +test_sraw_4: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 63 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 63 + #_ REGISTER_OUT r6 1 + +test_sraw_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 64 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 64 + #_ REGISTER_OUT r6 0 + +test_sraw_6: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 100 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 100 + #_ REGISTER_OUT r6 1 + +test_sraw_7: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 30 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 30 + #_ REGISTER_OUT r6 1 + +test_sraw_8: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 31 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 31 + #_ REGISTER_OUT r6 1 + +test_sraw_9: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 32 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 32 + #_ REGISTER_OUT r6 1 diff --git a/src/alloy/frontend/ppc/test/instr_srawi.s b/src/alloy/frontend/ppc/test/instr_srawi.s new file mode 100644 index 000000000..725c688d8 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_srawi.s @@ -0,0 +1,44 @@ +test_srawi_1: + #_ REGISTER_IN r4 1 + srawi r3, r4, 0 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r6 0 + +test_srawi_2: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + srawi r3, r4, 0 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 0 + +test_srawi_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + srawi r3, r4, 1 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + +test_srawi_4: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + srawi r3, r4, 30 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + +test_srawi_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + srawi r3, r4, 31 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 diff --git a/src/alloy/frontend/ppc/test/instr_srd.s b/src/alloy/frontend/ppc/test/instr_srd.s new file mode 100644 index 000000000..c6d2e0707 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_srd.s @@ -0,0 +1,62 @@ +test_srd_1: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 0 + srd r3, r4, r5 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + +test_srd_2: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0 + srd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + +test_srd_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 1 + srd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + +test_srd_4: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 62 + srd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000003 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 62 + +test_srd_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 63 + srd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 63 + +test_srd_6: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 64 + srd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 64 + +test_srd_7: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 100 + srd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 100 diff --git a/src/alloy/frontend/ppc/test/instr_srw.s b/src/alloy/frontend/ppc/test/instr_srw.s new file mode 100644 index 000000000..874035416 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_srw.s @@ -0,0 +1,80 @@ +test_srw_1: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 0 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + +test_srw_2: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + +test_srw_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 1 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x000000007FFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + +test_srw_4: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 63 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 63 + +test_srw_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 64 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 64 + +test_srw_6: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 100 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 100 + +test_srw_7: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 30 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000003 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 30 + +test_srw_8: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 31 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 31 + +test_srw_9: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 32 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 32