From fc397456340ac35965d232d740b69f51eaac28ab Mon Sep 17 00:00:00 2001
From: Ben Vanik <ben.vanik@gmail.com>
Date: Sun, 11 Jan 2015 16:00:16 -0800
Subject: [PATCH] lvsl/lvsr tests.

---
 .../frontend/ppc/test/bin/instr_lvsl.bin      | Bin 0 -> 24 bytes
 .../frontend/ppc/test/bin/instr_lvsl.dis      |  17 +++++++++++++++
 .../frontend/ppc/test/bin/instr_lvsl.map      |   3 +++
 .../frontend/ppc/test/bin/instr_lvsr.bin      | Bin 0 -> 24 bytes
 .../frontend/ppc/test/bin/instr_lvsr.dis      |  17 +++++++++++++++
 .../frontend/ppc/test/bin/instr_lvsr.map      |   3 +++
 src/alloy/frontend/ppc/test/instr_lvsl.s      |  20 ++++++++++++++++++
 src/alloy/frontend/ppc/test/instr_lvsr.s      |  20 ++++++++++++++++++
 8 files changed, 80 insertions(+)
 create mode 100644 src/alloy/frontend/ppc/test/bin/instr_lvsl.bin
 create mode 100644 src/alloy/frontend/ppc/test/bin/instr_lvsl.dis
 create mode 100644 src/alloy/frontend/ppc/test/bin/instr_lvsl.map
 create mode 100644 src/alloy/frontend/ppc/test/bin/instr_lvsr.bin
 create mode 100644 src/alloy/frontend/ppc/test/bin/instr_lvsr.dis
 create mode 100644 src/alloy/frontend/ppc/test/bin/instr_lvsr.map
 create mode 100644 src/alloy/frontend/ppc/test/instr_lvsl.s
 create mode 100644 src/alloy/frontend/ppc/test/instr_lvsr.s

diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvsl.bin b/src/alloy/frontend/ppc/test/bin/instr_lvsl.bin
new file mode 100644
index 0000000000000000000000000000000000000000..c8d11323ccb2782b6e9f926931c4993bf39d8122
GIT binary patch
literal 24
Rcmb<PVc_v=U{I(*qX9{n1&;s#

literal 0
HcmV?d00001

diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvsl.dis b/src/alloy/frontend/ppc/test/bin/instr_lvsl.dis
new file mode 100644
index 000000000..809e14bb3
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_lvsl.dis
@@ -0,0 +1,17 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_lvsl.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_lvsl_1>:
+  100000:	7c 64 00 0c 	lvsl    v3,r4,r0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_lvsl_2>:
+  100008:	7c 64 00 0c 	lvsl    v3,r4,r0
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_lvsl_3>:
+  100010:	7c 64 00 0c 	lvsl    v3,r4,r0
+  100014:	4e 80 00 20 	blr
diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvsl.map b/src/alloy/frontend/ppc/test/bin/instr_lvsl.map
new file mode 100644
index 000000000..9092d008f
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_lvsl.map
@@ -0,0 +1,3 @@
+0000000000000000 t test_lvsl_1
+0000000000000008 t test_lvsl_2
+0000000000000010 t test_lvsl_3
diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvsr.bin b/src/alloy/frontend/ppc/test/bin/instr_lvsr.bin
new file mode 100644
index 0000000000000000000000000000000000000000..7ea145691725b6fe68e2c4f2728cd19a5d0d2e46
GIT binary patch
literal 24
Rcmb<PVes*5U{I(*qXAP`22TJ0

literal 0
HcmV?d00001

diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvsr.dis b/src/alloy/frontend/ppc/test/bin/instr_lvsr.dis
new file mode 100644
index 000000000..5a7853740
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_lvsr.dis
@@ -0,0 +1,17 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_lvsr.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_lvsr_1>:
+  100000:	7c 64 00 4c 	lvsr    v3,r4,r0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_lvsr_2>:
+  100008:	7c 64 00 4c 	lvsr    v3,r4,r0
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_lvsr_3>:
+  100010:	7c 64 00 4c 	lvsr    v3,r4,r0
+  100014:	4e 80 00 20 	blr
diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvsr.map b/src/alloy/frontend/ppc/test/bin/instr_lvsr.map
new file mode 100644
index 000000000..daf1ee1cc
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_lvsr.map
@@ -0,0 +1,3 @@
+0000000000000000 t test_lvsr_1
+0000000000000008 t test_lvsr_2
+0000000000000010 t test_lvsr_3
diff --git a/src/alloy/frontend/ppc/test/instr_lvsl.s b/src/alloy/frontend/ppc/test/instr_lvsl.s
new file mode 100644
index 000000000..31cd73194
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/instr_lvsl.s
@@ -0,0 +1,20 @@
+test_lvsl_1:
+  #_ REGISTER_IN r4 0x1070
+  lvsl v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1070
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvsl_2:
+  #_ REGISTER_IN r4 0x1071
+  lvsl v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1071
+  #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
+
+test_lvsl_3:
+  #_ REGISTER_IN r4 0x107F
+  lvsl v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x107F
+  #_ REGISTER_OUT v3 [0F101112, 13141516, 1718191A, 1B1C1D1E]
diff --git a/src/alloy/frontend/ppc/test/instr_lvsr.s b/src/alloy/frontend/ppc/test/instr_lvsr.s
new file mode 100644
index 000000000..c3e29b963
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/instr_lvsr.s
@@ -0,0 +1,20 @@
+test_lvsr_1:
+  #_ REGISTER_IN r4 0x1070
+  lvsr v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1070
+  #_ REGISTER_OUT v3 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+
+test_lvsr_2:
+  #_ REGISTER_IN r4 0x1071
+  lvsr v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1071
+  #_ REGISTER_OUT v3 [0F101112, 13141516, 1718191A, 1B1C1D1E]
+
+test_lvsr_3:
+  #_ REGISTER_IN r4 0x107F
+  lvsr v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x107F
+  #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]