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xenia-canary
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just boring formatting consistancy

This commit is contained in:
Cancerous 2020-01-25 13:07:06 -05:00 committed by illusion98
parent de7f025db3
commit fb5cf78e82
2 changed files with 191 additions and 194 deletions
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6
src/xenia/cpu/backend/x64/x64_emitter.cc
View File

@ -211,8 +211,7 @@ bool X64Emitter::Emit(HIRBuilder* builder, EmitFunctionInfo& func_info) {
// Record call history value into slot (guest addr in RDX).
mov(dword[Xbyak::RegExp(uint32_t(uint64_t(
low_address(&trace_header->function_caller_history)))) +
rax * 4],
edx);
rax * 4], edx);
// Calling thread. Load ax with thread ID.
EmitGetCurrentThreadId();
@ -826,11 +825,9 @@ void X64Emitter::LoadConstantXmm(Xbyak::Xmm dest, float v) {
// TODO(benvanik): see what other common values are.
// TODO(benvanik): build constant table - 99% are reused.
unsigned raw_bits =*reinterpret_cast<unsigned*>(&v);
for (unsigned i = 0; i < (kConstDataSize / sizeof(vec128_t)); ++i) {
if(xmm_consts[i].u32[0] == raw_bits) {
vmovss(dest, GetXmmConstPtr((XmmConst)i));
return;
@ -861,7 +858,6 @@ void X64Emitter::LoadConstantXmm(Xbyak::Xmm dest, double v) {
uint64_t raw_bits = *reinterpret_cast<uint64_t*>(&v);
for (unsigned i = 0; i < (kConstDataSize / sizeof(vec128_t)); ++i) {
if(xmm_consts[i].u64[0] == raw_bits) {
vmovsd(dest, GetXmmConstPtr((XmmConst)i));
return;

35
src/xenia/cpu/backend/x64/x64_sequences.cc
View File

@ -865,7 +865,6 @@ struct IS_NAN_F32 : Sequence<IS_NAN_F32, I<OPCODE_IS_NAN, I8Op, F32Op>> {
e.setp(i.dest);
}
};
struct IS_NAN_F64 : Sequence<IS_NAN_F64, I<OPCODE_IS_NAN, I8Op, F64Op>> {
static void Emit(X64Emitter& e, const EmitArgType& i) {
e.vucomisd(i.src1, i.src1);
@ -1200,8 +1199,10 @@ EMITTER_OPCODE_TABLE(OPCODE_ADD, ADD_I8, ADD_I16, ADD_I32, ADD_I64, ADD_F32,
// TODO(benvanik): put dest/src1|2 together.
template <typename SEQ, typename REG, typename ARGS>
void EmitAddCarryXX(X64Emitter& e, const ARGS& i) {
// TODO(benvanik): faster setting? we could probably do some fun math tricks
// here to get the carry flag set.
// chrisps: faster setting now, but i think the i.src3.is_constant check is
// dead code
@ -1214,7 +1215,6 @@ void EmitAddCarryXX(X64Emitter& e, const ARGS& i) {
} else {
e.bt(i.src3.reg().cvt32(), 0);
}
SEQ::EmitCommutativeBinaryOp(
e, i,
[](X64Emitter& e, const REG& dest_src, const REG& src) {
@ -1325,8 +1325,9 @@ struct MUL_I8 : Sequence<MUL_I8, I<OPCODE_MUL, I8Op, I8Op, I8Op>> {
static void Emit(X64Emitter& e, const EmitArgType& i) {
if (i.src1.is_constant || i.src2.is_constant) {
uint64_t cval =i.src1.is_constant ? i.src1.constant() : i.src2.constant();
uint64_t cval = i.src1.is_constant
? i.src1.constant()
: i.src2.constant();
if (cval < (1ull << 32)) {
@ -1338,7 +1339,6 @@ struct MUL_I8 : Sequence<MUL_I8, I<OPCODE_MUL, I8Op, I8Op, I8Op>> {
}
if (e.IsFeatureEnabled(kX64EmitBMI2)) {
// mulx: $1:$2 = EDX * $3
// TODO(benvanik): place src2 in edx?
if (i.src1.is_constant) {
assert_true(!i.src2.is_constant);
@ -1356,7 +1356,6 @@ struct MUL_I8 : Sequence<MUL_I8, I<OPCODE_MUL, I8Op, I8Op, I8Op>> {
} else {
// x86 mul instruction
// AH:AL = AL * $1;
if (i.src1.is_constant) {
assert_true(!i.src2.is_constant);
e.mov(e.al, i.src1.constant());
@ -1379,8 +1378,9 @@ struct MUL_I16 : Sequence<MUL_I16, I<OPCODE_MUL, I16Op, I16Op, I16Op>> {
static void Emit(X64Emitter& e, const EmitArgType& i) {
if (i.src1.is_constant || i.src2.is_constant) {
uint64_t cval =i.src1.is_constant ? i.src1.constant() : i.src2.constant();
uint64_t cval = i.src1.is_constant
? i.src1.constant()
: i.src2.constant();
if (cval < (1ull << 32)) {
@ -1441,8 +1441,9 @@ struct MUL_I32 : Sequence<MUL_I32, I<OPCODE_MUL, I32Op, I32Op, I32Op>> {
if (i.src1.is_constant || i.src2.is_constant) {
uint64_t cval =i.src1.is_constant ? i.src1.constant() : i.src2.constant();
uint64_t cval = i.src1.is_constant
? i.src1.constant()
: i.src2.constant();
if (cval < (1ull << 32)) {
@ -1505,8 +1506,9 @@ struct MUL_I64 : Sequence<MUL_I64, I<OPCODE_MUL, I64Op, I64Op, I64Op>> {
if (i.src1.is_constant || i.src2.is_constant) {
uint64_t cval =i.src1.is_constant ? i.src1.constant() : i.src2.constant();
uint64_t cval = i.src1.is_constant
? i.src1.constant()
: i.src2.constant();
if (cval < (1ull << 32)) {
@ -1593,7 +1595,6 @@ struct MUL_HI_I8 : Sequence<MUL_HI_I8, I<OPCODE_MUL_HI, I8Op, I8Op, I8Op>> {
static void Emit(X64Emitter& e, const EmitArgType& i) {
if (i.instr->flags & ARITHMETIC_UNSIGNED) {
// mulx: $1:$2 = EDX * $3
if (e.IsFeatureEnabled(kX64EmitBMI2)) {
// TODO(benvanik): place src1 in eax? still need to sign extend
e.movzx(e.edx, i.src1);
@ -1774,6 +1775,7 @@ struct MUL_HI_I64
};
EMITTER_OPCODE_TABLE(OPCODE_MUL_HI, MUL_HI_I8, MUL_HI_I16, MUL_HI_I32,
MUL_HI_I64);
/* from Hackers Delight - by Henry S. Warren Jr. Calculate magic number for
* unsigned division */
template <typename T>
@ -1781,9 +1783,7 @@ auto magicu(T d) {
constexpr unsigned NBITS = sizeof(T) * CHAR_BIT;
constexpr unsigned NBITS_M1 = NBITS - 1;
constexpr T SIGNBIT = T(1) << NBITS_M1;
constexpr T POSMASK = ~SIGNBIT;
struct mu {
T M; // Magic number,
int a; // "add" indicator,
@ -1794,7 +1794,6 @@ auto magicu(T d) {
int p, gt = 0;
T nc, delta, q1, r1, q2, r2;
struct mu magu;
magu.a = 0; // Initialize "add" indicator.
nc = -1 - ((T)- (std::make_signed_t<T>)d) % d; // Unsigned arithmetic here.
p = NBITS_M1; // Init. p.
@ -1824,12 +1823,14 @@ auto magicu(T d) {
r2 = 2 * r2 + 1;
}
delta = d - 1 - r2;
} while (gt == 0 && (q1 < delta || (q1 == delta && r1 == 0)));
}
while (gt == 0 && (q1 < delta || (q1 == delta && r1 == 0)));
magu.M = q2 + 1; // Magic number
magu.s = p - NBITS; // and shift amount to return
return magu; // (magu.a was set above).
}
// ============================================================================
// OPCODE_DIV
// ============================================================================