just boring formatting consistancy
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@ -211,8 +211,7 @@ bool X64Emitter::Emit(HIRBuilder* builder, EmitFunctionInfo& func_info) {
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// Record call history value into slot (guest addr in RDX).
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// Record call history value into slot (guest addr in RDX).
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mov(dword[Xbyak::RegExp(uint32_t(uint64_t(
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mov(dword[Xbyak::RegExp(uint32_t(uint64_t(
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low_address(&trace_header->function_caller_history)))) +
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low_address(&trace_header->function_caller_history)))) +
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rax * 4],
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rax * 4], edx);
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edx);
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// Calling thread. Load ax with thread ID.
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// Calling thread. Load ax with thread ID.
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EmitGetCurrentThreadId();
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EmitGetCurrentThreadId();
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@ -826,11 +825,9 @@ void X64Emitter::LoadConstantXmm(Xbyak::Xmm dest, float v) {
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// TODO(benvanik): see what other common values are.
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// TODO(benvanik): see what other common values are.
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// TODO(benvanik): build constant table - 99% are reused.
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// TODO(benvanik): build constant table - 99% are reused.
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unsigned raw_bits =*reinterpret_cast<unsigned*>(&v);
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unsigned raw_bits =*reinterpret_cast<unsigned*>(&v);
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for (unsigned i = 0; i < (kConstDataSize / sizeof(vec128_t)); ++i) {
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for (unsigned i = 0; i < (kConstDataSize / sizeof(vec128_t)); ++i) {
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if(xmm_consts[i].u32[0] == raw_bits) {
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if(xmm_consts[i].u32[0] == raw_bits) {
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vmovss(dest, GetXmmConstPtr((XmmConst)i));
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vmovss(dest, GetXmmConstPtr((XmmConst)i));
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return;
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return;
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@ -861,7 +858,6 @@ void X64Emitter::LoadConstantXmm(Xbyak::Xmm dest, double v) {
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uint64_t raw_bits = *reinterpret_cast<uint64_t*>(&v);
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uint64_t raw_bits = *reinterpret_cast<uint64_t*>(&v);
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for (unsigned i = 0; i < (kConstDataSize / sizeof(vec128_t)); ++i) {
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for (unsigned i = 0; i < (kConstDataSize / sizeof(vec128_t)); ++i) {
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if(xmm_consts[i].u64[0] == raw_bits) {
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if(xmm_consts[i].u64[0] == raw_bits) {
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vmovsd(dest, GetXmmConstPtr((XmmConst)i));
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vmovsd(dest, GetXmmConstPtr((XmmConst)i));
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return;
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return;
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@ -865,7 +865,6 @@ struct IS_NAN_F32 : Sequence<IS_NAN_F32, I<OPCODE_IS_NAN, I8Op, F32Op>> {
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e.setp(i.dest);
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e.setp(i.dest);
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}
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}
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};
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};
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struct IS_NAN_F64 : Sequence<IS_NAN_F64, I<OPCODE_IS_NAN, I8Op, F64Op>> {
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struct IS_NAN_F64 : Sequence<IS_NAN_F64, I<OPCODE_IS_NAN, I8Op, F64Op>> {
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static void Emit(X64Emitter& e, const EmitArgType& i) {
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static void Emit(X64Emitter& e, const EmitArgType& i) {
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e.vucomisd(i.src1, i.src1);
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e.vucomisd(i.src1, i.src1);
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@ -1200,8 +1199,10 @@ EMITTER_OPCODE_TABLE(OPCODE_ADD, ADD_I8, ADD_I16, ADD_I32, ADD_I64, ADD_F32,
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// TODO(benvanik): put dest/src1|2 together.
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// TODO(benvanik): put dest/src1|2 together.
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template <typename SEQ, typename REG, typename ARGS>
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template <typename SEQ, typename REG, typename ARGS>
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void EmitAddCarryXX(X64Emitter& e, const ARGS& i) {
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void EmitAddCarryXX(X64Emitter& e, const ARGS& i) {
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// TODO(benvanik): faster setting? we could probably do some fun math tricks
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// TODO(benvanik): faster setting? we could probably do some fun math tricks
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// here to get the carry flag set.
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// here to get the carry flag set.
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// chrisps: faster setting now, but i think the i.src3.is_constant check is
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// chrisps: faster setting now, but i think the i.src3.is_constant check is
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// dead code
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// dead code
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@ -1214,7 +1215,6 @@ void EmitAddCarryXX(X64Emitter& e, const ARGS& i) {
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} else {
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} else {
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e.bt(i.src3.reg().cvt32(), 0);
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e.bt(i.src3.reg().cvt32(), 0);
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}
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}
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SEQ::EmitCommutativeBinaryOp(
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SEQ::EmitCommutativeBinaryOp(
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e, i,
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e, i,
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[](X64Emitter& e, const REG& dest_src, const REG& src) {
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[](X64Emitter& e, const REG& dest_src, const REG& src) {
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@ -1325,8 +1325,9 @@ struct MUL_I8 : Sequence<MUL_I8, I<OPCODE_MUL, I8Op, I8Op, I8Op>> {
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static void Emit(X64Emitter& e, const EmitArgType& i) {
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static void Emit(X64Emitter& e, const EmitArgType& i) {
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if (i.src1.is_constant || i.src2.is_constant) {
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if (i.src1.is_constant || i.src2.is_constant) {
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uint64_t cval = i.src1.is_constant
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uint64_t cval =i.src1.is_constant ? i.src1.constant() : i.src2.constant();
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? i.src1.constant()
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: i.src2.constant();
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if (cval < (1ull << 32)) {
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if (cval < (1ull << 32)) {
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@ -1338,7 +1339,6 @@ struct MUL_I8 : Sequence<MUL_I8, I<OPCODE_MUL, I8Op, I8Op, I8Op>> {
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}
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}
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if (e.IsFeatureEnabled(kX64EmitBMI2)) {
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if (e.IsFeatureEnabled(kX64EmitBMI2)) {
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// mulx: $1:$2 = EDX * $3
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// mulx: $1:$2 = EDX * $3
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// TODO(benvanik): place src2 in edx?
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// TODO(benvanik): place src2 in edx?
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if (i.src1.is_constant) {
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if (i.src1.is_constant) {
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assert_true(!i.src2.is_constant);
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assert_true(!i.src2.is_constant);
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@ -1356,7 +1356,6 @@ struct MUL_I8 : Sequence<MUL_I8, I<OPCODE_MUL, I8Op, I8Op, I8Op>> {
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} else {
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} else {
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// x86 mul instruction
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// x86 mul instruction
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// AH:AL = AL * $1;
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// AH:AL = AL * $1;
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if (i.src1.is_constant) {
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if (i.src1.is_constant) {
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assert_true(!i.src2.is_constant);
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assert_true(!i.src2.is_constant);
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e.mov(e.al, i.src1.constant());
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e.mov(e.al, i.src1.constant());
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@ -1379,8 +1378,9 @@ struct MUL_I16 : Sequence<MUL_I16, I<OPCODE_MUL, I16Op, I16Op, I16Op>> {
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static void Emit(X64Emitter& e, const EmitArgType& i) {
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static void Emit(X64Emitter& e, const EmitArgType& i) {
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if (i.src1.is_constant || i.src2.is_constant) {
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if (i.src1.is_constant || i.src2.is_constant) {
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uint64_t cval = i.src1.is_constant
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uint64_t cval =i.src1.is_constant ? i.src1.constant() : i.src2.constant();
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? i.src1.constant()
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: i.src2.constant();
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if (cval < (1ull << 32)) {
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if (cval < (1ull << 32)) {
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@ -1441,8 +1441,9 @@ struct MUL_I32 : Sequence<MUL_I32, I<OPCODE_MUL, I32Op, I32Op, I32Op>> {
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if (i.src1.is_constant || i.src2.is_constant) {
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if (i.src1.is_constant || i.src2.is_constant) {
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uint64_t cval = i.src1.is_constant
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uint64_t cval =i.src1.is_constant ? i.src1.constant() : i.src2.constant();
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? i.src1.constant()
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: i.src2.constant();
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if (cval < (1ull << 32)) {
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if (cval < (1ull << 32)) {
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@ -1505,8 +1506,9 @@ struct MUL_I64 : Sequence<MUL_I64, I<OPCODE_MUL, I64Op, I64Op, I64Op>> {
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if (i.src1.is_constant || i.src2.is_constant) {
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if (i.src1.is_constant || i.src2.is_constant) {
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uint64_t cval = i.src1.is_constant
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uint64_t cval =i.src1.is_constant ? i.src1.constant() : i.src2.constant();
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? i.src1.constant()
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: i.src2.constant();
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if (cval < (1ull << 32)) {
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if (cval < (1ull << 32)) {
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@ -1593,7 +1595,6 @@ struct MUL_HI_I8 : Sequence<MUL_HI_I8, I<OPCODE_MUL_HI, I8Op, I8Op, I8Op>> {
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static void Emit(X64Emitter& e, const EmitArgType& i) {
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static void Emit(X64Emitter& e, const EmitArgType& i) {
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if (i.instr->flags & ARITHMETIC_UNSIGNED) {
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if (i.instr->flags & ARITHMETIC_UNSIGNED) {
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// mulx: $1:$2 = EDX * $3
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// mulx: $1:$2 = EDX * $3
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if (e.IsFeatureEnabled(kX64EmitBMI2)) {
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if (e.IsFeatureEnabled(kX64EmitBMI2)) {
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// TODO(benvanik): place src1 in eax? still need to sign extend
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// TODO(benvanik): place src1 in eax? still need to sign extend
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e.movzx(e.edx, i.src1);
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e.movzx(e.edx, i.src1);
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@ -1774,6 +1775,7 @@ struct MUL_HI_I64
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};
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};
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EMITTER_OPCODE_TABLE(OPCODE_MUL_HI, MUL_HI_I8, MUL_HI_I16, MUL_HI_I32,
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EMITTER_OPCODE_TABLE(OPCODE_MUL_HI, MUL_HI_I8, MUL_HI_I16, MUL_HI_I32,
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MUL_HI_I64);
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MUL_HI_I64);
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/* from Hackers Delight - by Henry S. Warren Jr. Calculate magic number for
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/* from Hackers Delight - by Henry S. Warren Jr. Calculate magic number for
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* unsigned division */
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* unsigned division */
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template <typename T>
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template <typename T>
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@ -1781,9 +1783,7 @@ auto magicu(T d) {
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constexpr unsigned NBITS = sizeof(T) * CHAR_BIT;
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constexpr unsigned NBITS = sizeof(T) * CHAR_BIT;
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constexpr unsigned NBITS_M1 = NBITS - 1;
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constexpr unsigned NBITS_M1 = NBITS - 1;
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constexpr T SIGNBIT = T(1) << NBITS_M1;
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constexpr T SIGNBIT = T(1) << NBITS_M1;
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constexpr T POSMASK = ~SIGNBIT;
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constexpr T POSMASK = ~SIGNBIT;
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struct mu {
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struct mu {
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T M; // Magic number,
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T M; // Magic number,
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int a; // "add" indicator,
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int a; // "add" indicator,
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@ -1794,7 +1794,6 @@ auto magicu(T d) {
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int p, gt = 0;
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int p, gt = 0;
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T nc, delta, q1, r1, q2, r2;
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T nc, delta, q1, r1, q2, r2;
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struct mu magu;
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struct mu magu;
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magu.a = 0; // Initialize "add" indicator.
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magu.a = 0; // Initialize "add" indicator.
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nc = -1 - ((T)- (std::make_signed_t<T>)d) % d; // Unsigned arithmetic here.
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nc = -1 - ((T)- (std::make_signed_t<T>)d) % d; // Unsigned arithmetic here.
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p = NBITS_M1; // Init. p.
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p = NBITS_M1; // Init. p.
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@ -1824,12 +1823,14 @@ auto magicu(T d) {
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r2 = 2 * r2 + 1;
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r2 = 2 * r2 + 1;
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}
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}
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delta = d - 1 - r2;
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delta = d - 1 - r2;
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} while (gt == 0 && (q1 < delta || (q1 == delta && r1 == 0)));
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}
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while (gt == 0 && (q1 < delta || (q1 == delta && r1 == 0)));
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magu.M = q2 + 1; // Magic number
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magu.M = q2 + 1; // Magic number
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magu.s = p - NBITS; // and shift amount to return
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magu.s = p - NBITS; // and shift amount to return
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return magu; // (magu.a was set above).
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return magu; // (magu.a was set above).
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}
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}
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// ============================================================================
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// ============================================================================
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// OPCODE_DIV
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// OPCODE_DIV
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// ============================================================================
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// ============================================================================
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