From f632895fbb3c598325e02486dd4785195f16b45a Mon Sep 17 00:00:00 2001 From: Ben Vanik Date: Sat, 24 Jan 2015 10:21:54 -0800 Subject: [PATCH] srdi special case and tests for sldi/srdi. --- src/alloy/frontend/ppc/ppc_emit_alu.cc | 19 +++++---- .../frontend/ppc/test/bin/instr_rldicl.bin | Bin 80 -> 128 bytes .../frontend/ppc/test/bin/instr_rldicl.dis | 20 ++++++++++ .../frontend/ppc/test/bin/instr_rldicl.map | 4 ++ .../frontend/ppc/test/bin/instr_rldicr.bin | Bin 72 -> 120 bytes .../frontend/ppc/test/bin/instr_rldicr.dis | 20 ++++++++++ .../frontend/ppc/test/bin/instr_rldicr.map | 4 ++ src/alloy/frontend/ppc/test/instr_rldicl.s | 36 ++++++++++++++++++ src/alloy/frontend/ppc/test/instr_rldicr.s | 36 ++++++++++++++++++ 9 files changed, 132 insertions(+), 7 deletions(-) diff --git a/src/alloy/frontend/ppc/ppc_emit_alu.cc b/src/alloy/frontend/ppc/ppc_emit_alu.cc index bf1b5ed44..fb37b2e69 100644 --- a/src/alloy/frontend/ppc/ppc_emit_alu.cc +++ b/src/alloy/frontend/ppc/ppc_emit_alu.cc @@ -837,11 +837,16 @@ XEEMITTER(rld, 0x78000000, MDS)(PPCHIRBuilder& f, InstrData& i) { uint32_t mb = (i.MD.MB5 << 5) | i.MD.MB; uint64_t m = XEMASK(mb, 63); Value* v = f.LoadGPR(i.MD.RT); - if (sh) { - v = f.RotateLeft(v, f.LoadConstant((int8_t)sh)); - } - if (m != 0xFFFFFFFFFFFFFFFF) { - v = f.And(v, f.LoadConstant(m)); + if (sh == 64 - mb) { + // srdi == rldicl ra,rs,64-n,n + v = f.Shr(v, int8_t(mb)); + } else { + if (sh) { + v = f.RotateLeft(v, f.LoadConstant((int8_t)sh)); + } + if (m != 0xFFFFFFFFFFFFFFFF) { + v = f.And(v, f.LoadConstant(m)); + } } f.StoreGPR(i.MD.RA, v); if (i.MD.Rc) { @@ -860,8 +865,8 @@ XEEMITTER(rld, 0x78000000, MDS)(PPCHIRBuilder& f, InstrData& i) { uint64_t m = XEMASK(0, mb); Value* v = f.LoadGPR(i.MD.RT); if (mb == 63 - sh) { - // Shift left. - v = f.Shl(v, f.LoadConstant((int8_t)sh)); + // sldi == rldicr ra,rs,n,63-n + v = f.Shl(v, int8_t(sh)); } else { if (sh) { v = f.RotateLeft(v, f.LoadConstant((int8_t)sh)); diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicl.bin b/src/alloy/frontend/ppc/test/bin/instr_rldicl.bin index 121cb7ff60d0d56282a50d9e807cfab1de803a46..1b8e7abd071e3f65482c5c4cd5e5616d8aa1ce87 100644 GIT binary patch delta 54 xcmWG&V4M(OP?5~QP|?D`;Mc&QP?7w@siNhF6NJs61Qb_-u=yWUwD3Owu>sjl5sUx; delta 5 McmZo*444oA00ij)vH$=8 diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicl.dis b/src/alloy/frontend/ppc/test/bin/instr_rldicl.dis index 226852357..9933b7437 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_rldicl.dis +++ b/src/alloy/frontend/ppc/test/bin/instr_rldicl.dis @@ -43,3 +43,23 @@ Disassembly of section .text: 0000000000100048 : 100048: 78 83 d1 82 rldicl r3,r4,58,6 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 78 63 00 00 rotldi r3,r3,0 + 100054: 78 84 00 00 rotldi r4,r4,0 + 100058: 4e 80 00 20 blr + +000000000010005c : + 10005c: 78 63 f8 42 rldicl r3,r3,63,1 + 100060: 78 84 f8 42 rldicl r4,r4,63,1 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 78 63 00 22 rldicl r3,r3,32,32 + 10006c: 78 84 00 22 rldicl r4,r4,32,32 + 100070: 4e 80 00 20 blr + +0000000000100074 : + 100074: 78 63 0f e0 rldicl r3,r3,1,63 + 100078: 78 84 0f e0 rldicl r4,r4,1,63 + 10007c: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicl.map b/src/alloy/frontend/ppc/test/bin/instr_rldicl.map index c581b1fcc..2c701aa7b 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_rldicl.map +++ b/src/alloy/frontend/ppc/test/bin/instr_rldicl.map @@ -8,3 +8,7 @@ 0000000000000038 t test_rldicl_8 0000000000000040 t test_rldicl_9 0000000000000048 t test_rldicl_10 +0000000000000050 t test_srdi_1 +000000000000005c t test_srdi_2 +0000000000000068 t test_srdi_3 +0000000000000074 t test_srdi_4 diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicr.bin b/src/alloy/frontend/ppc/test/bin/instr_rldicr.bin index cf03dfbfc1b43a3060db98adbbb78be633679855..0a6e90dc068716b372acfa04963f8544c82184f2 100644 GIT binary patch delta 53 xcmeaMnBZYhk<9+2qJ{m5Uju_eMKb@AiWdGQ5H|ZUp!hKe`v+S^%MUgX8vq;+6R!XO delta 4 Lcmb>MnBV~b1SA2O diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicr.dis b/src/alloy/frontend/ppc/test/bin/instr_rldicr.dis index 5e5546a69..1be1d4db4 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_rldicr.dis +++ b/src/alloy/frontend/ppc/test/bin/instr_rldicr.dis @@ -39,3 +39,23 @@ Disassembly of section .text: 0000000000100040 : 100040: 78 83 f8 04 rldicr r3,r4,31,0 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 78 63 07 e4 rldicr r3,r3,0,63 + 10004c: 78 84 07 e4 rldicr r4,r4,0,63 + 100050: 4e 80 00 20 blr + +0000000000100054 : + 100054: 78 63 0f a4 rldicr r3,r3,1,62 + 100058: 78 84 0f a4 rldicr r4,r4,1,62 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 78 63 07 c6 rldicr r3,r3,32,31 + 100064: 78 84 07 c6 rldicr r4,r4,32,31 + 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 78 63 f8 06 rldicr r3,r3,63,0 + 100070: 78 84 f8 06 rldicr r4,r4,63,0 + 100074: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicr.map b/src/alloy/frontend/ppc/test/bin/instr_rldicr.map index 93ee471fc..b576758fe 100644 --- a/src/alloy/frontend/ppc/test/bin/instr_rldicr.map +++ b/src/alloy/frontend/ppc/test/bin/instr_rldicr.map @@ -7,3 +7,7 @@ 0000000000000030 t test_rldicr_7 0000000000000038 t test_rldicr_8 0000000000000040 t test_rldicr_9 +0000000000000048 t test_sldi_1 +0000000000000054 t test_sldi_2 +0000000000000060 t test_sldi_3 +000000000000006c t test_sldi_4 diff --git a/src/alloy/frontend/ppc/test/instr_rldicl.s b/src/alloy/frontend/ppc/test/instr_rldicl.s index 2f55ff595..f301d7c98 100644 --- a/src/alloy/frontend/ppc/test/instr_rldicl.s +++ b/src/alloy/frontend/ppc/test/instr_rldicl.s @@ -67,3 +67,39 @@ test_rldicl_10: blr #_ REGISTER_OUT r3 0x58C000 #_ REGISTER_OUT r4 0x16300000 + +test_srdi_1: + #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r4 0x0123456789ABCDEF + srdi r3, r3, 0 + srdi r4, r4, 0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_srdi_2: + #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r4 0x0123456789ABCDEF + srdi r3, r3, 1 + srdi r4, r4, 1 + blr + #_ REGISTER_OUT r3 0x7fffffffffffffff + #_ REGISTER_OUT r4 0x0091a2b3c4d5e6f7 + +test_srdi_3: + #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r4 0x0123456789ABCDEF + srdi r3, r3, 32 + srdi r4, r4, 32 + blr + #_ REGISTER_OUT r3 0x00000000ffffffff + #_ REGISTER_OUT r4 0x0000000001234567 + +test_srdi_4: + #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r4 0x0123456789ABCDEF + srdi r3, r3, 63 + srdi r4, r4, 63 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000000 diff --git a/src/alloy/frontend/ppc/test/instr_rldicr.s b/src/alloy/frontend/ppc/test/instr_rldicr.s index 7380eca31..6a249b23a 100644 --- a/src/alloy/frontend/ppc/test/instr_rldicr.s +++ b/src/alloy/frontend/ppc/test/instr_rldicr.s @@ -60,3 +60,39 @@ test_rldicr_9: blr #_ REGISTER_OUT r3 0x8000000000000000 #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_sldi_1: + #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r4 0x0123456789ABCDEF + sldi r3, r3, 0 + sldi r4, r4, 0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_sldi_2: + #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r4 0x0123456789ABCDEF + sldi r3, r3, 1 + sldi r4, r4, 1 + blr + #_ REGISTER_OUT r3 0xfffffffffffffffe + #_ REGISTER_OUT r4 0x02468acf13579bde + +test_sldi_3: + #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r4 0x0123456789ABCDEF + sldi r3, r3, 32 + sldi r4, r4, 32 + blr + #_ REGISTER_OUT r3 0xffffffff00000000 + #_ REGISTER_OUT r4 0x89abcdef00000000 + +test_sldi_4: + #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r4 0x0123456789ABCDEF + sldi r3, r3, 63 + sldi r4, r4, 63 + blr + #_ REGISTER_OUT r3 0x8000000000000000 + #_ REGISTER_OUT r4 0x8000000000000000