diff --git a/src/xenia/cpu/ppc/disasm.h b/src/xenia/cpu/ppc/disasm.h
index 3fb5a5b14..ec7552563 100644
--- a/src/xenia/cpu/ppc/disasm.h
+++ b/src/xenia/cpu/ppc/disasm.h
@@ -18,6 +18,7 @@ namespace cpu {
 namespace ppc {
 
 
+void RegisterDisasmCategoryAltivec();
 void RegisterDisasmCategoryALU();
 void RegisterDisasmCategoryControl();
 void RegisterDisasmCategoryFPU();
diff --git a/src/xenia/cpu/ppc/disasm_altivec.cc b/src/xenia/cpu/ppc/disasm_altivec.cc
new file mode 100644
index 000000000..c7f03932c
--- /dev/null
+++ b/src/xenia/cpu/ppc/disasm_altivec.cc
@@ -0,0 +1,2644 @@
+/*
+ ******************************************************************************
+ * Xenia : Xbox 360 Emulator Research Project                                 *
+ ******************************************************************************
+ * Copyright 2013 Ben Vanik. All rights reserved.                             *
+ * Released under the BSD license - see LICENSE in the root for more details. *
+ ******************************************************************************
+ */
+
+#include <xenia/cpu/ppc/disasm.h>
+
+
+using namespace xe::cpu::ppc;
+
+
+namespace xe {
+namespace cpu {
+namespace ppc {
+
+
+// Most of this file comes from:
+// http://biallas.net/doc/vmx128/vmx128.txt
+// https://github.com/kakaroto/ps3ida/blob/master/plugins/PPCAltivec/src/main.cpp
+
+
+#define OP(x)             ((((uint32_t)(x)) & 0x3f) << 26)
+#define VX128(op, xop)    (OP(op) | (((uint32_t)(xop)) & 0x3d0))
+#define VX128_1(op, xop)  (OP(op) | (((uint32_t)(xop)) & 0x7f3))
+#define VX128_2(op, xop)  (OP(op) | (((uint32_t)(xop)) & 0x210))
+#define VX128_3(op, xop)  (OP(op) | (((uint32_t)(xop)) & 0x7f0))
+#define VX128_4(op, xop)  (OP(op) | (((uint32_t)(xop)) & 0x730))
+#define VX128_5(op, xop)  (OP(op) | (((uint32_t)(xop)) & 0x10))
+#define VX128_P(op, xop)  (OP(op) | (((uint32_t)(xop)) & 0x630))
+
+
+XEDISASMR(dst,            0x7C0002AC, XDSS)(InstrData& i, InstrDisasm& d) {
+  d.Init("dst", "Data Stream Touch",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(dstst,          0x7C0002EC, XDSS)(InstrData& i, InstrDisasm& d) {
+  d.Init("dstst", "Data Stream Touch for Store",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(dss,            0x7C00066C, XDSS)(InstrData& i, InstrDisasm& d) {
+  d.Init("dss", "Data Stream Stop",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvebx,          0x7C00000E, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("lvebx", "Load Vector Element Byte Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvehx,          0x7C00004E, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("lvehx", "Load Vector Element Half Word Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvewx,          0x7C00008E, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("lvewx", "Load Vector Element Word Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvewx128,       VX128_1(4, 131),  VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("lvewx128", "Load Vector128 Element Word Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvsl,           0x7C00000C, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("lvsl", "Load Vector for Shift Left",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvsl128,        VX128_1(4, 3),    VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("lvsl128", "Load Vector128 for Shift Left",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvsr,           0x7C00004C, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("lvsr", "Load Vector for Shift Right",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvsr128,        VX128_1(4, 67),   VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("lvsr128", "Load Vector128 for Shift Right",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvx,            0x7C0000CE, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("lvx", "Load Vector Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvx128,         VX128_1(4, 195),  VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("lvx128", "Load Vector128 Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvxl,           0x7C0002CE, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("lvxl", "Load Vector Indexed LRU",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvxl128,        VX128_1(4, 707),  VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("lvxl128", "Load Vector128 Left Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvebx,         0x7C00010E, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("stvebx", "Store Vector Element Byte Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvehx,         0x7C00014E, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("stvehx", "Store Vector Element Half Word Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvewx,         0x7C00018E, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("stvewx", "Store Vector Element Word Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvewx128,      VX128_1(4, 387),  VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("stvewx128", "Store Vector128 Element Word Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvx,           0x7C0001CE, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("stvx", "Store Vector Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvx128,        VX128_1(4, 451),  VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("stvx128", "Store Vector128 Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvxl,          0x7C0003CE, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("stvxl", "Store Vector Indexed LRU",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvxl128,       VX128_1(4, 963),  VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("stvxl128", "Store Vector128 Indexed LRU",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvlx,           0x7C00040E, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("lvlx", "Load Vector Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvlx128,        VX128_1(4, 1027), VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("lvlx128", "Load Vector128 Left Indexed LRU",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvlxl,          0x7C00060E, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("lvlxl", "Load Vector Indexed LRU",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvlxl128,       VX128_1(4, 1539), VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("lvlxl128", "Load Vector128 Indexed LRU",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvrx,           0x7C00044E, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("lvrx", "Load Vector Right Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvrx128,        VX128_1(4, 1091), VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("lvrx128", "Load Vector128 Right Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvrxl,          0x7C00064E, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("lvrxl", "Load Vector Right Indexed LRU",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(lvrxl128,       VX128_1(4, 1603), VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("lvrxl128", "Load Vector128 Right Indexed LRU",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvlx,          0x7C00050E, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("stvlx", "Store Vector Left Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvlx128,       VX128_1(4, 1283), VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("stvlx128", "Store Vector128 Left Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvlxl,         0x7C00070E, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("stvlxl", "Store Vector Left Indexed LRU",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvlxl128,      VX128_1(4, 1795), VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("stvlxl128", "Store Vector128 Left Indexed LRU",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvrx,          0x7C00054E, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("stvrx", "Store Vector Right Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvrx128,       VX128_1(4, 1347), VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("stvrx128", "Store Vector128 Right Indexed",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvrxl,         0x7C00074E, X   )(InstrData& i, InstrDisasm& d) {
+  d.Init("stvrxl", "Store Vector Right Indexed LRU",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(stvrxl128,      VX128_1(4, 1859), VX128_1)(InstrData& i, InstrDisasm& d) {
+  d.Init("stvrxl128", "Store Vector128 Right Indexed LRU",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(mfvscr,         0x10000604, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("mfvscr", "Move from Vector Status and Control Register",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(mtvscr,         0x10000644, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("mtvscr", "Move to Vector Status and Control Register",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vaddcuw,        0x10000180, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vaddcuw", "Vector Add Carryout Unsigned Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vaddfp,         0x1000000A, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vaddfp", "Vector Add Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vaddfp128,      VX128(5, 16),     VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vaddfp128", "Vector128 Add Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vaddsbs,        0x10000300, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vaddsbs", "Vector Add Signed Byte Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vaddshs,        0x10000340, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vaddshs", "Vector Add Signed Half Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vaddsws,        0x10000380, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vaddsws", "Vector Add Signed Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vaddubm,        0x10000000, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vaddubm", "Vector Add Unsigned Byte Modulo",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vaddubs,        0x10000200, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vaddubs", "Vector Add Unsigned Byte Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vadduhm,        0x10000040, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vadduhm", "Vector Add Unsigned Half Word Modulo",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vadduhs,        0x10000240, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vadduhs", "Vector Add Unsigned Half Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vadduwm,        0x10000080, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vadduwm", "Vector Add Unsigned Word Modulo",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vadduws,        0x10000280, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vadduws", "Vector Add Unsigned Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vand,           0x10000404, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vand", "Vector Logical AND",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vand128,        VX128(5, 528),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vand128", "Vector128 Logical AND",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vandc,          0x10000444, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vandc", "Vector Logical AND with Complement",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vandc128,       VX128(5, 592),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vandc128", "Vector128 Logical AND with Complement",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vavgsb,         0x10000502, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vavgsb", "Vector Average Signed Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vavgsh,         0x10000542, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vavgsh", "Vector Average Signed Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vavgsw,         0x10000582, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vavgsw", "Vector Average Signed Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vavgub,         0x10000402, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vavgub", "Vector Average Unsigned Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vavguh,         0x10000442, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vavguh", "Vector Average Unsigned Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vavguw,         0x10000482, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vavguw", "Vector Average Unsigned Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcfsx,          0x1000034A, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcfsx", "Vector Convert from Signed Fixed-Point Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcsxwfp128,     VX128_3(6, 688),  VX128_3)(InstrData& i, InstrDisasm& d) {
+  d.Init("vcsxwfp128", "Vector128 Convert From Signed Fixed-Point Word to Floating-Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcfpsxws128,    VX128_3(6, 560),  VX128_3)(InstrData& i, InstrDisasm& d) {
+  d.Init("vcfpsxws128", "Vector128 Convert From Floating-Point to Signed Fixed-Point Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcfux,          0x1000030A, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcfux", "Vector Convert from Unsigned Fixed-Point Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcuxwfp128,     VX128_3(6, 752),  VX128_3)(InstrData& i, InstrDisasm& d) {
+  d.Init("vcuxwfp128", "Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcfpuxws128,    VX128_3(6, 624),  VX128_3)(InstrData& i, InstrDisasm& d) {
+  d.Init("vcfpuxws128", "Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpbfp,        0x100003C6, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpbfp", "Vector Compare Bounds Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpbfp128,     VX128(6, 384),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpbfp128", "Vector128 Compare Bounds Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpbfp_c,      0x100007C6, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpbfp", "Vector Compare Bounds Floating Point",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpbfp128c,    VX128(6, 448),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpbfp128", "Vector128 Compare Equal-to Floating Point",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpeqfp,       0x100000C6, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpeqfp", "Vector Compare Equal-to Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpeqfp128,    VX128(6, 0),      VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpeqfp128", "Vector128 Compare Equal-to Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpeqfp_c,     0x100004C6, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpeqfp", "Vector Compare Equal-to Floating Point",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpeqfp128c,   VX128(6, 64),     VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpeqfp128", "Vector Compare Equal-to Floating Point",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpequb,       0x10000006, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpequb", "Vector Compare Equal-to Unsigned Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpequb_c,     0x10000406, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpequb", "Vector Compare Equal-to Unsigned Byte",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpequh,       0x10000046, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpequh", "Vector Compare Equal-to Unsigned Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpequh_c,     0x10000446, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpequh", "Vector Compare Equal-to Unsigned Half Word",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpequw,       0x10000086, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpequw", "Vector Compare Equal-to Unsigned Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpequw128,    VX128(6, 512),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpequw128", "Vector128 Compare Equal-to Unsigned Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpequw_c,     0x10000486, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpequw", "Vector Compare Equal-to Unsigned Word",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpequw128c,   VX128(6, 576),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpequw128", "Vector Compare Equal-to Unsigned Word",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgefp,       0x100001C6, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgefp", "Vector Compare Greater-Than-or-Equal-to Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgefp128,    VX128(6, 128),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgefp128", "Vector128 Compare Greater-Than-or-Equal-to Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgefp_c,     0x100005C6, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgefp", "Vector Compare Greater-Than-or-Equal-to Floating Point",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgefp128c,   VX128(6, 192),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgefp128", "Vector128 Compare Greater-Than-or-Equal-to Floating Point",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtfp,       0x100002C6, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtfp", "Vector Compare Greater-Than Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtfp128,    VX128(6, 256),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtfp128", "Vector128 Compare Greater-Than Floating-Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtfp_c,     0x100006C6, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtfp", "Vector Compare Greater-Than Floating Point",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtfp128c,   VX128(6, 320),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtfp128", "Vector128 Compare Greater-Than Floating-Point",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtsb,       0x10000306, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtsb", "Vector Compare Greater-Than Signed Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtsb_c,     0x10000706, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtsb", "Vector Compare Greater-Than Signed Byte",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtsh,       0x10000346, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtsh", "Vector Compare Greater-Than Signed Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtsh_c,     0x10000746, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtsh", "Vector Compare Greater-Than Signed Half Word",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtsw,       0x10000386, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtsw", "Vector Compare Greater-Than Signed Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtsw_c,     0x10000786, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtsw", "Vector Compare Greater-Than Signed Word",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtub,       0x10000206, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtub", "Vector Compare Greater-Than Unsigned Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtub_c,     0x10000606, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtub", "Vector Compare Greater-Than Unsigned Byte",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtuh,       0x10000246, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtuh", "Vector Compare Greater-Than Unsigned Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtuh_c,     0x10000646, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtuh", "Vector Compare Greater-Than Unsigned Half Word",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtuw,       0x10000286, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtuw", "Vector Compare Greater-Than Unsigned Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vcmpgtuw_c,     0x10000686, VXR )(InstrData& i, InstrDisasm& d) {
+  d.Init("vcmpgtuw", "Vector Compare Greater-Than Unsigned Word",
+         InstrDisasm::kVMX | InstrDisasm::kRc);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vctsxs,         0x100003CA, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vctsxs", "Vector Convert to Signed Fixed-Point Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vctuxs,         0x1000038A, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vctuxs", "Vector Convert to Unsigned Fixed-Point Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vexptefp,       0x1000018A, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vexptefp", "Vector 2 Raised to the Exponent Estimate Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vexptefp128,    VX128_3(6, 1712), VX128_3)(InstrData& i, InstrDisasm& d) {
+  d.Init("vexptefp128", "Vector128 2 Raised to the Exponent Estimate Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vlogefp,        0x100001CA, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vlogefp", "Vector Log2 Estimate Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vlogefp128,     VX128_3(6, 1776), VX128_3)(InstrData& i, InstrDisasm& d) {
+  d.Init("vlogefp128", "Vector128 Log2 Estimate Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmaddfp,        0x1000002E, VXA )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmaddfp", "Vector Multiply-Add Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmaddfp128,     VX128(5, 208),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmaddfp128", "Vector128 Multiply Add Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmaddcfp128,    VX128(5, 272),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmaddcfp128", "Vector128 Multiply Add Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmaxfp,         0x1000040A, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmaxfp", "Vector Maximum Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmaxfp128,      VX128(6, 640),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmaxfp128", "Vector128 Maximum Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmaxsb,         0x10000102, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmaxsb", "Vector Maximum Signed Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmaxsh,         0x10000142, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmaxsh", "Vector Maximum Signed Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmaxsw,         0x10000182, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmaxsw", "Vector Maximum Signed Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmaxub,         0x10000002, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmaxub", "Vector Maximum Unsigned Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmaxuh,         0x10000042, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmaxuh", "Vector Maximum Unsigned Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmaxuw,         0x10000082, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmaxuw", "Vector Maximum Unsigned Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmhaddshs,      0x10000020, VXA )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmhaddshs", "Vector Multiply-High and Add Signed Signed Half Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmhraddshs,     0x10000021, VXA )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmhraddshs", "Vector Multiply-High Round and Add Signed Signed Half Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vminfp,         0x1000044A, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vminfp", "Vector Minimum Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vminfp128,      VX128(6, 704),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vminfp128", "Vector128 Minimum Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vminsb,         0x10000302, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vminsb", "Vector Minimum Signed Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vminsh,         0x10000342, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vminsh", "Vector Minimum Signed Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vminsw,         0x10000382, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vminsw", "Vector Minimum Signed Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vminub,         0x10000202, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vminub", "Vector Minimum Unsigned Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vminuh,         0x10000242, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vminuh", "Vector Minimum Unsigned Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vminuw,         0x10000282, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vminuw", "Vector Minimum Unsigned Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmladduhm,      0x10000022, VXA )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmladduhm", "Vector Multiply-Low and Add Unsigned Half Word Modulo",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmrghb,         0x1000000C, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmrghb", "Vector Merge High Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmrghh,         0x1000004C, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmrghh", "Vector Merge High Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmrghw,         0x1000008C, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmrghw", "Vector Merge High Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmrghw128,      VX128(6, 768),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmrghw128", "Vector128 Merge High Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmrglb,         0x1000010C, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmrglb", "Vector Merge Low Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmrglh,         0x1000014C, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmrglh", "Vector Merge Low Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmrglw,         0x1000018C, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmrglw", "Vector Merge Low Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmrglw128,      VX128(6, 832),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmrglw128", "Vector128 Merge Low Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmsummbm,       0x10000025, VXA )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmsummbm", "Vector Multiply-Sum Mixed-Sign Byte Modulo",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmsumshm,       0x10000028, VXA )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmsumshm", "Vector Multiply-Sum Signed Half Word Modulo",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmsumshs,       0x10000029, VXA )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmsumshs", "Vector Multiply-Sum Signed Half Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmsumubm,       0x10000024, VXA )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmsumubm", "Vector Multiply-Sum Unsigned Byte Modulo",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmsumuhm,       0x10000026, VXA )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmsumuhm", "Vector Multiply-Sum Unsigned Half Word Modulo",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmsumuhs,       0x10000027, VXA )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmsumuhs", "Vector Multiply-Sum Unsigned Half Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmsum3fp128,    VX128(5, 400),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmsum3fp128", "Vector128 Multiply Sum 3-way Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmsum4fp128,    VX128(5, 464),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmsum4fp128", "Vector128 Multiply Sum 4-way Floating-Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmulesb,        0x10000308, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmulesb", "Vector Multiply Even Signed Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmulesh,        0x10000348, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmulesh", "Vector Multiply Even Signed Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmuleub,        0x10000208, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmuleub", "Vector Multiply Even Unsigned Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmuleuh,        0x10000248, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmuleuh", "Vector Multiply Even Unsigned Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmulosb,        0x10000108, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmulosb", "Vector Multiply Odd Signed Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmulosh,        0x10000148, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmulosh", "Vector Multiply Odd Signed Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmuloub,        0x10000008, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmuloub", "Vector Multiply Odd Unsigned Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmulouh,        0x10000048, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmulouh", "Vector Multiply Odd Unsigned Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vmulfp128,      VX128(5, 144),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vmulfp128", "Vector128 Multiply Floating-Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vnmsubfp,       0x1000002F, VXA )(InstrData& i, InstrDisasm& d) {
+  d.Init("vnmsubfp", "Vector Negative Multiply-Subtract Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vnmsubfp128,    VX128(5, 336),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vnmsubfp128", "Vector128 Negative Multiply-Subtract Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vnor,           0x10000504, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vnor", "Vector Logical NOR",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vnor128,        VX128(5, 656),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vnor128", "Vector128 Logical NOR",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vor,            0x10000484, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vor", "Vector Logical OR",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vor128,         VX128(5, 720),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vor128", "Vector128 Logical OR",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vperm,          0x1000002B, VXA )(InstrData& i, InstrDisasm& d) {
+  d.Init("vperm", "Vector Permute",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vperm128,       VX128_2(5, 0),    VX128_2)(InstrData& i, InstrDisasm& d) {
+  d.Init("vperm128", "Vector128 Permute",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpermwi128,     VX128_P(6, 528),  VX128_P)(InstrData& i, InstrDisasm& d) {
+  d.Init("vpermwi128", "Vector128 Permutate Word Immediate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkpx,          0x1000030E, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkpx", "Vector Pack Pixel",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkshss,        0x1000018E, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkshss", "Vector Pack Signed Half Word Signed Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkshss128,     VX128(5, 512),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkshss128", "Vector128 Pack Signed Half Word Signed Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkswss,        0x100001CE, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkswss", "Vector Pack Signed Word Signed Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkswss128,     VX128(5, 640),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkswss128", "Vector128 Pack Signed Word Signed Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkswus,        0x1000014E, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkswus", "Vector Pack Signed Word Unsigned Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkswus128,     VX128(5, 704),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkswus128", "Vector128 Pack Signed Word Unsigned Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkuhum,        0x1000000E, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkuhum", "Vector Pack Unsigned Half Word Unsigned Modulo",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkuhum128,     VX128(5, 768),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkuhum128", "Vector128 Pack Unsigned Half Word Unsigned Modulo",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkuhus,        0x1000008E, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkuhus", "Vector Pack Unsigned Half Word Unsigned Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkuhus128,     VX128(5, 832),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkuhus128", "Vector128 Pack Unsigned Half Word Unsigned Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkshus,        0x1000010E, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkshus", "Vector Pack Signed Half Word Unsigned Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkshus128,     VX128(5, 576),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkshus128", "Vector128 Pack Signed Half Word Unsigned Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkuwum,        0x1000004E, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkuwum", "Vector Pack Unsigned Word Unsigned Modulo",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkuwum128,     VX128(5, 896),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkuwum128", "Vector128 Pack Unsigned Word Unsigned Modulo",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkuwus,        0x100000CE, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkuwus", "Vector Pack Unsigned Word Unsigned Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkuwus128,     VX128(5, 960),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkuwus128", "Vector128 Pack Unsigned Word Unsigned Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vpkd3d128,      VX128_4(6, 1552), VX128_4)(InstrData& i, InstrDisasm& d) {
+  d.Init("vpkd3d128", "Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrefp,          0x1000010A, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vrefp", "Vector Reciprocal Estimate Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrefp128,       VX128_3(6, 1584), VX128_3)(InstrData& i, InstrDisasm& d) {
+  d.Init("vrefp128", "Vector128 Reciprocal Estimate Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrfim,          0x100002CA, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vrfim", "Vector Round to Floating-Point Integer toward -Infinity",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrfim128,       VX128_3(6, 816),  VX128_3)(InstrData& i, InstrDisasm& d) {
+  d.Init("vrfim128", "Vector128 Round to Floating-Point Integer toward -Infinity",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrfin,          0x1000020A, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vrfin", "Vector Round to Floating-Point Integer Nearest",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrfin128,       VX128_3(6, 880),  VX128_3)(InstrData& i, InstrDisasm& d) {
+  d.Init("vrfin128", "Vector128 Round to Floating-Point Integer Nearest",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrfip,          0x1000028A, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vrfip", "Vector Round to Floating-Point Integer toward +Infinity",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrfip128,       VX128_3(6, 944),  VX128_3)(InstrData& i, InstrDisasm& d) {
+  d.Init("vrfip128", "Vector128 Round to Floating-Point Integer toward +Infinity",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrfiz,          0x1000024A, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vrfiz", "Vector Round to Floating-Point Integer toward Zero",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrfiz128,       VX128_3(6, 1008), VX128_3)(InstrData& i, InstrDisasm& d) {
+  d.Init("vrfiz128", "Vector128 Round to Floating-Point Integer toward Zero",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrlb,           0x10000004, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vrlb", "Vector Rotate Left Integer Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrlh,           0x10000044, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vrlh", "Vector Rotate Left Integer Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrlw,           0x10000084, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vrlw", "Vector Rotate Left Integer Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrlw128,        VX128(6, 80),     VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vrlw128", "Vector128 Rotate Left Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrlimi128,      VX128_4(6, 1808), VX128_4)(InstrData& i, InstrDisasm& d) {
+  d.Init("vrlimi128", "Vector128 Rotate Left Immediate and Mask Insert",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrsqrtefp,      0x1000014A, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vrsqrtefp", "Vector Reciprocal Square Root Estimate Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vrsqrtefp128,   VX128_3(6, 1648), VX128_3)(InstrData& i, InstrDisasm& d) {
+  d.Init("vrsqrtefp128", "Vector128 Reciprocal Square Root Estimate Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsel,           0x1000002A, VXA )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsel", "Vector Conditional Select",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsel128,        VX128(5, 848),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsel128", "Vector128 Conditional Select",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsl,            0x100001C4, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsl", "Vector Shift Left",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vslb,           0x10000104, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vslb", "Vector Shift Left Integer Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsldoi,         0x1000002C, VXA )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsldoi", "Vector Shift Left Double by Octet Immediate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsldoi128,      VX128_5(4, 16),   VX128_5)(InstrData& i, InstrDisasm& d) {
+  d.Init("vsldoi128", "Vector128 Shift Left Double by Octet Immediate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vslh,           0x10000144, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vslh", "Vector Shift Left Integer Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vslo,           0x1000040C, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vslo", "Vector Shift Left by Octet",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vslo128,        VX128(5, 912),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vslo128", "Vector128 Shift Left Octet",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vslw,           0x10000184, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vslw", "Vector Shift Left Integer Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vslw128,        VX128(6, 208),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vslw128", "Vector128 Shift Left Integer Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vspltb,         0x1000020C, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vspltb", "Vector Splat Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsplth,         0x1000024C, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsplth", "Vector Splat Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vspltisb,       0x1000030C, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vspltisb", "Vector Splat Immediate Signed Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vspltish,       0x1000034C, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vspltish", "Vector Splat Immediate Signed Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vspltisw,       0x1000038C, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vspltisw", "Vector Splat Immediate Signed Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vspltisw128,    VX128_3(6, 1904), VX128_3)(InstrData& i, InstrDisasm& d) {
+  d.Init("vspltisw128", "Vector128 Splat Immediate Signed Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vspltw,         0x1000028C, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vspltw", "Vector Splat Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vspltw128,      VX128_3(6, 1840), VX128_3)(InstrData& i, InstrDisasm& d) {
+  d.Init("vspltw128", " Vector128 Splat Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsr,            0x100002C4, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsr", "Vector Shift Right",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsrab,          0x10000304, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsrab", "Vector Shift Right Algebraic Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsrah,          0x10000344, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsrah", "Vector Shift Right Algebraic Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsraw,          0x10000384, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsraw", "Vector Shift Right Algebraic Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsraw128,       VX128(6, 336),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsraw128", "Vector128 Shift Right Arithmetic Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsrb,           0x10000204, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsrb", "Vector Shift Right Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsrh,           0x10000244, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsrh", "Vector Shift Right Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsro,           0x1000044C, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsro", "Vector Shift Right Octet",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsro128,        VX128(5, 976),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsro128", "Vector128 Shift Right Octet",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsrw,           0x10000284, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsrw", "Vector Shift Right Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsrw128,        VX128(6, 464),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsrw128", "Vector128 Shift Right Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsubcuw,        0x10000580, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsubcuw", "Vector Subtract Carryout Unsigned Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsubfp,         0x1000004A, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsubfp", "Vector Subtract Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsubfp128,      VX128(5, 80),     VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsubfp128", "Vector128 Subtract Floating Point",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsubsbs,        0x10000700, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsubsbs", "Vector Subtract Signed Byte Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsubshs,        0x10000740, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsubshs", "Vector Subtract Signed Half Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsubsws,        0x10000780, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsubsws", "Vector Subtract Signed Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsububm,        0x10000400, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsububm", "Vector Subtract Unsigned Byte Modulo",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsububs,        0x10000600, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsububs", "Vector Subtract Unsigned Byte Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsubuhm,        0x10000440, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsubuhm", "Vector Subtract Unsigned Half Word Modulo",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsubuhs,        0x10000640, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsubuhs", "Vector Subtract Unsigned Half Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsubuwm,        0x10000480, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsubuwm", "Vector Subtract Unsigned Word Modulo",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsubuws,        0x10000680, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsubuws", "Vector Subtract Unsigned Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsumsws,        0x10000788, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsumsws", "Vector Sum Across Signed Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsum2sws,       0x10000688, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsum2sws", "Vector Sum Across Partial (1/2) Signed Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsum4sbs,       0x10000708, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsum4sbs", "Vector Sum Across Partial (1/4) Signed Byte Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsum4shs,       0x10000648, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsum4shs", "Vector Sum Across Partial (1/4) Signed Half Word Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vsum4ubs,       0x10000608, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vsum4ubs", "Vector Sum Across Partial (1/4) Unsigned Byte Saturate",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vupkhpx,        0x1000034E, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vupkhpx", "Vector Unpack High Pixel",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vupkhsb,        0x1000020E, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vupkhsb", "Vector Unpack High Signed Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vupkhsb128,     VX128(6, 896),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vupkhsb128", "Vector128 Unpack High Signed Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vupkhsh,        0x1000024E, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vupkhsh", "Vector Unpack High Signed Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vupklpx,        0x100003CE, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vupklpx", "Vector Unpack Low Pixel",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vupklsb,        0x1000028E, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vupklsb", "Vector Unpack Low Signed Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vupklsb128,     VX128(6, 960),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vupklsb128", "Vector128 Unpack Low Signed Byte",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vupklsh,        0x100002CE, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vupklsh", "Vector Unpack Low Signed Half Word",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vupkd3d128,     VX128_3(6, 2032), VX128_3)(InstrData& i, InstrDisasm& d) {
+  d.Init("vupkd3d128", "Vector128 Unpack D3Dtype",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vxor,           0x100004C4, VX  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vxor", "Vector Logical XOR",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+XEDISASMR(vxor128,        VX128(5, 784),    VX128  )(InstrData& i, InstrDisasm& d) {
+  d.Init("vxor128", "Vector128 Logical XOR",
+         InstrDisasm::kVMX);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRT, InstrRegister::kWrite);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRA, InstrRegister::kRead);
+  //d.AddRegOperand(InstrRegister::kVMX, i.VX.FRB, InstrRegister::kRead);
+  return d.Finish();
+}
+
+
+void RegisterDisasmCategoryAltivec() {
+  XEREGISTERINSTR(dst,            0x7C0002AC);
+  XEREGISTERINSTR(dstst,          0x7C0002EC);
+  XEREGISTERINSTR(dss,            0x7C00066C);
+  XEREGISTERINSTR(lvebx,          0x7C00000E);
+  XEREGISTERINSTR(lvehx,          0x7C00004E);
+  XEREGISTERINSTR(lvewx,          0x7C00008E);
+  XEREGISTERINSTR(lvewx128,       VX128_1(4, 131));
+  XEREGISTERINSTR(lvsl,           0x7C00000C);
+  XEREGISTERINSTR(lvsl128,        VX128_1(4, 3));
+  XEREGISTERINSTR(lvsr,           0x7C00004C);
+  XEREGISTERINSTR(lvsr128,        VX128_1(4, 67));
+  XEREGISTERINSTR(lvx,            0x7C0000CE);
+  XEREGISTERINSTR(lvx128,         VX128_1(4, 195));
+  XEREGISTERINSTR(lvxl,           0x7C0002CE);
+  XEREGISTERINSTR(lvxl128,        VX128_1(4, 707));
+  XEREGISTERINSTR(stvebx,         0x7C00010E);
+  XEREGISTERINSTR(stvehx,         0x7C00014E);
+  XEREGISTERINSTR(stvewx,         0x7C00018E);
+  XEREGISTERINSTR(stvewx128,      VX128_1(4, 387));
+  XEREGISTERINSTR(stvx,           0x7C0001CE);
+  XEREGISTERINSTR(stvx128,        VX128_1(4, 451));
+  XEREGISTERINSTR(stvxl,          0x7C0003CE);
+  XEREGISTERINSTR(stvxl128,       VX128_1(4, 963));
+  XEREGISTERINSTR(lvlx,           0x7C00040E);
+  XEREGISTERINSTR(lvlx128,        VX128_1(4, 1027));
+  XEREGISTERINSTR(lvlxl,          0x7C00060E);
+  XEREGISTERINSTR(lvlxl128,       VX128_1(4, 1539));
+  XEREGISTERINSTR(lvrx,           0x7C00044E);
+  XEREGISTERINSTR(lvrx128,        VX128_1(4, 1091));
+  XEREGISTERINSTR(lvrxl,          0x7C00064E);
+  XEREGISTERINSTR(lvrxl128,       VX128_1(4, 1603));
+  XEREGISTERINSTR(stvlx,          0x7C00050E);
+  XEREGISTERINSTR(stvlx128,       VX128_1(4, 1283));
+  XEREGISTERINSTR(stvlxl,         0x7C00070E);
+  XEREGISTERINSTR(stvlxl128,      VX128_1(4, 1795));
+  XEREGISTERINSTR(stvrx,          0x7C00054E);
+  XEREGISTERINSTR(stvrx128,       VX128_1(4, 1347));
+  XEREGISTERINSTR(stvrxl,         0x7C00074E);
+  XEREGISTERINSTR(stvrxl128,      VX128_1(4, 1859));
+
+  XEREGISTERINSTR(mfvscr,         0x10000604);
+  XEREGISTERINSTR(mtvscr,         0x10000644);
+  XEREGISTERINSTR(vaddcuw,        0x10000180);
+  XEREGISTERINSTR(vaddfp,         0x1000000A);
+  XEREGISTERINSTR(vaddfp128,      VX128(5, 16));
+  XEREGISTERINSTR(vaddsbs,        0x10000300);
+  XEREGISTERINSTR(vaddshs,        0x10000340);
+  XEREGISTERINSTR(vaddsws,        0x10000380);
+  XEREGISTERINSTR(vaddubm,        0x10000000);
+  XEREGISTERINSTR(vaddubs,        0x10000200);
+  XEREGISTERINSTR(vadduhm,        0x10000040);
+  XEREGISTERINSTR(vadduhs,        0x10000240);
+  XEREGISTERINSTR(vadduwm,        0x10000080);
+  XEREGISTERINSTR(vadduws,        0x10000280);
+  XEREGISTERINSTR(vand,           0x10000404);
+  XEREGISTERINSTR(vand128,        VX128(5, 528));
+  XEREGISTERINSTR(vandc,          0x10000444);
+  XEREGISTERINSTR(vandc128,       VX128(5, 592));
+  XEREGISTERINSTR(vavgsb,         0x10000502);
+  XEREGISTERINSTR(vavgsh,         0x10000542);
+  XEREGISTERINSTR(vavgsw,         0x10000582);
+  XEREGISTERINSTR(vavgub,         0x10000402);
+  XEREGISTERINSTR(vavguh,         0x10000442);
+  XEREGISTERINSTR(vavguw,         0x10000482);
+  XEREGISTERINSTR(vcfsx,          0x1000034A);
+  XEREGISTERINSTR(vcsxwfp128,     VX128_3(6, 688));
+  XEREGISTERINSTR(vcfpsxws128,    VX128_3(6, 560));
+  XEREGISTERINSTR(vcfux,          0x1000030A);
+  XEREGISTERINSTR(vcuxwfp128,     VX128_3(6, 752));
+  XEREGISTERINSTR(vcfpuxws128,    VX128_3(6, 624));
+  XEREGISTERINSTR(vcmpbfp,        0x100003C6);
+  XEREGISTERINSTR(vcmpbfp128,     VX128(6, 384));
+  XEREGISTERINSTR(vcmpbfp_c,      0x100007C6);
+  XEREGISTERINSTR(vcmpbfp128c,    VX128(6, 448));
+  XEREGISTERINSTR(vcmpeqfp,       0x100000C6);
+  XEREGISTERINSTR(vcmpeqfp128,    VX128(6, 0));
+  XEREGISTERINSTR(vcmpeqfp_c,     0x100004C6);
+  XEREGISTERINSTR(vcmpeqfp128c,   VX128(6, 64));
+  XEREGISTERINSTR(vcmpequb,       0x10000006);
+  XEREGISTERINSTR(vcmpequb_c,     0x10000406);
+  XEREGISTERINSTR(vcmpequh,       0x10000046);
+  XEREGISTERINSTR(vcmpequh_c,     0x10000446);
+  XEREGISTERINSTR(vcmpequw,       0x10000086);
+  XEREGISTERINSTR(vcmpequw128,    VX128(6, 512));
+  XEREGISTERINSTR(vcmpequw_c,     0x10000486);
+  XEREGISTERINSTR(vcmpequw128c,   VX128(6, 576));
+  XEREGISTERINSTR(vcmpgefp,       0x100001C6);
+  XEREGISTERINSTR(vcmpgefp128,    VX128(6, 128));
+  XEREGISTERINSTR(vcmpgefp_c,     0x100005C6);
+  XEREGISTERINSTR(vcmpgefp128c,   VX128(6, 192));
+  XEREGISTERINSTR(vcmpgtfp,       0x100002C6);
+  XEREGISTERINSTR(vcmpgtfp128,    VX128(6, 256));
+  XEREGISTERINSTR(vcmpgtfp_c,     0x100006C6);
+  XEREGISTERINSTR(vcmpgtfp128c,   VX128(6, 320));
+  XEREGISTERINSTR(vcmpgtsb,       0x10000306);
+  XEREGISTERINSTR(vcmpgtsb_c,     0x10000706);
+  XEREGISTERINSTR(vcmpgtsh,       0x10000346);
+  XEREGISTERINSTR(vcmpgtsh_c,     0x10000746);
+  XEREGISTERINSTR(vcmpgtsw,       0x10000386);
+  XEREGISTERINSTR(vcmpgtsw_c,     0x10000786);
+  XEREGISTERINSTR(vcmpgtub,       0x10000206);
+  XEREGISTERINSTR(vcmpgtub_c,     0x10000606);
+  XEREGISTERINSTR(vcmpgtuh,       0x10000246);
+  XEREGISTERINSTR(vcmpgtuh_c,     0x10000646);
+  XEREGISTERINSTR(vcmpgtuw,       0x10000286);
+  XEREGISTERINSTR(vcmpgtuw_c,     0x10000686);
+  XEREGISTERINSTR(vctsxs,         0x100003CA);
+  XEREGISTERINSTR(vctuxs,         0x1000038A);
+  XEREGISTERINSTR(vexptefp,       0x1000018A);
+  XEREGISTERINSTR(vexptefp128,    VX128_3(6, 1712));
+  XEREGISTERINSTR(vlogefp,        0x100001CA);
+  XEREGISTERINSTR(vlogefp128,     VX128_3(6, 1776));
+  XEREGISTERINSTR(vmaddfp,        0x1000002E);
+  XEREGISTERINSTR(vmaddfp128,     VX128(5, 208));
+  XEREGISTERINSTR(vmaddcfp128,    VX128(5, 272));
+  XEREGISTERINSTR(vmaxfp,         0x1000040A);
+  XEREGISTERINSTR(vmaxfp128,      VX128(6, 640));
+  XEREGISTERINSTR(vmaxsb,         0x10000102);
+  XEREGISTERINSTR(vmaxsh,         0x10000142);
+  XEREGISTERINSTR(vmaxsw,         0x10000182);
+  XEREGISTERINSTR(vmaxub,         0x10000002);
+  XEREGISTERINSTR(vmaxuh,         0x10000042);
+  XEREGISTERINSTR(vmaxuw,         0x10000082);
+  XEREGISTERINSTR(vmhaddshs,      0x10000020);
+  XEREGISTERINSTR(vmhraddshs,     0x10000021);
+  XEREGISTERINSTR(vminfp,         0x1000044A);
+  XEREGISTERINSTR(vminfp128,      VX128(6, 704));
+  XEREGISTERINSTR(vminsb,         0x10000302);
+  XEREGISTERINSTR(vminsh,         0x10000342);
+  XEREGISTERINSTR(vminsw,         0x10000382);
+  XEREGISTERINSTR(vminub,         0x10000202);
+  XEREGISTERINSTR(vminuh,         0x10000242);
+  XEREGISTERINSTR(vminuw,         0x10000282);
+  XEREGISTERINSTR(vmladduhm,      0x10000022);
+  XEREGISTERINSTR(vmrghb,         0x1000000C);
+  XEREGISTERINSTR(vmrghh,         0x1000004C);
+  XEREGISTERINSTR(vmrghw,         0x1000008C);
+  XEREGISTERINSTR(vmrghw128,      VX128(6, 768));
+  XEREGISTERINSTR(vmrglb,         0x1000010C);
+  XEREGISTERINSTR(vmrglh,         0x1000014C);
+  XEREGISTERINSTR(vmrglw,         0x1000018C);
+  XEREGISTERINSTR(vmrglw128,      VX128(6, 832));
+  XEREGISTERINSTR(vmsummbm,       0x10000025);
+  XEREGISTERINSTR(vmsumshm,       0x10000028);
+  XEREGISTERINSTR(vmsumshs,       0x10000029);
+  XEREGISTERINSTR(vmsumubm,       0x10000024);
+  XEREGISTERINSTR(vmsumuhm,       0x10000026);
+  XEREGISTERINSTR(vmsumuhs,       0x10000027);
+  XEREGISTERINSTR(vmsum3fp128,    VX128(5, 400));
+  XEREGISTERINSTR(vmsum4fp128,    VX128(5, 464));
+  XEREGISTERINSTR(vmulesb,        0x10000308);
+  XEREGISTERINSTR(vmulesh,        0x10000348);
+  XEREGISTERINSTR(vmuleub,        0x10000208);
+  XEREGISTERINSTR(vmuleuh,        0x10000248);
+  XEREGISTERINSTR(vmulosb,        0x10000108);
+  XEREGISTERINSTR(vmulosh,        0x10000148);
+  XEREGISTERINSTR(vmuloub,        0x10000008);
+  XEREGISTERINSTR(vmulouh,        0x10000048);
+  XEREGISTERINSTR(vmulfp128,      VX128(5, 144));
+  XEREGISTERINSTR(vnmsubfp,       0x1000002F);
+  XEREGISTERINSTR(vnmsubfp128,    VX128(5, 336));
+  XEREGISTERINSTR(vnor,           0x10000504);
+  XEREGISTERINSTR(vnor128,        VX128(5, 656));
+  XEREGISTERINSTR(vor,            0x10000484);
+  XEREGISTERINSTR(vor128,         VX128(5, 720));
+  XEREGISTERINSTR(vperm,          0x1000002B);
+  XEREGISTERINSTR(vperm128,       VX128_2(5, 0));
+  XEREGISTERINSTR(vpermwi128,     VX128_P(6, 528));
+  XEREGISTERINSTR(vpkpx,          0x1000030E);
+  XEREGISTERINSTR(vpkshss,        0x1000018E);
+  XEREGISTERINSTR(vpkshss128,     VX128(5, 512));
+  XEREGISTERINSTR(vpkshus,        0x1000010E);
+  XEREGISTERINSTR(vpkshus128,     VX128(5, 576));
+  XEREGISTERINSTR(vpkswss,        0x100001CE);
+  XEREGISTERINSTR(vpkswss128,     VX128(5, 640));
+  XEREGISTERINSTR(vpkswus,        0x1000014E);
+  XEREGISTERINSTR(vpkswus128,     VX128(5, 704));
+  XEREGISTERINSTR(vpkuhum,        0x1000000E);
+  XEREGISTERINSTR(vpkuhum128,     VX128(5, 768));
+  XEREGISTERINSTR(vpkuhus,        0x1000008E);
+  XEREGISTERINSTR(vpkuhus128,     VX128(5, 832));
+  XEREGISTERINSTR(vpkuwum,        0x1000004E);
+  XEREGISTERINSTR(vpkuwum128,     VX128(5, 896));
+  XEREGISTERINSTR(vpkuwus,        0x100000CE);
+  XEREGISTERINSTR(vpkuwus128,     VX128(5, 960));
+  XEREGISTERINSTR(vpkd3d128,      VX128_4(6, 1552));
+  XEREGISTERINSTR(vrefp,          0x1000010A);
+  XEREGISTERINSTR(vrefp128,       VX128_3(6, 1584));
+  XEREGISTERINSTR(vrfim,          0x100002CA);
+  XEREGISTERINSTR(vrfim128,       VX128_3(6, 816));
+  XEREGISTERINSTR(vrfin,          0x1000020A);
+  XEREGISTERINSTR(vrfin128,       VX128_3(6, 880));
+  XEREGISTERINSTR(vrfip,          0x1000028A);
+  XEREGISTERINSTR(vrfip128,       VX128_3(6, 944));
+  XEREGISTERINSTR(vrfiz,          0x1000024A);
+  XEREGISTERINSTR(vrfiz128,       VX128_3(6, 1008));
+  XEREGISTERINSTR(vrlb,           0x10000004);
+  XEREGISTERINSTR(vrlh,           0x10000044);
+  XEREGISTERINSTR(vrlw,           0x10000084);
+  XEREGISTERINSTR(vrlw128,        VX128(6, 80));
+  XEREGISTERINSTR(vrlimi128,      VX128_4(6, 1808));
+  XEREGISTERINSTR(vrsqrtefp,      0x1000014A);
+  XEREGISTERINSTR(vrsqrtefp128,   VX128_3(6, 1648));
+  XEREGISTERINSTR(vsel,           0x1000002A);
+  XEREGISTERINSTR(vsel128,        VX128(5, 848));
+  XEREGISTERINSTR(vsl,            0x100001C4);
+  XEREGISTERINSTR(vslb,           0x10000104);
+  XEREGISTERINSTR(vsldoi,         0x1000002C);
+  XEREGISTERINSTR(vsldoi128,      VX128_5(4, 16));
+  XEREGISTERINSTR(vslh,           0x10000144);
+  XEREGISTERINSTR(vslo,           0x1000040C);
+  XEREGISTERINSTR(vslo128,        VX128(5, 912));
+  XEREGISTERINSTR(vslw,           0x10000184);
+  XEREGISTERINSTR(vslw128,        VX128(6, 208));
+  XEREGISTERINSTR(vspltb,         0x1000020C);
+  XEREGISTERINSTR(vsplth,         0x1000024C);
+  XEREGISTERINSTR(vspltisb,       0x1000030C);
+  XEREGISTERINSTR(vspltish,       0x1000034C);
+  XEREGISTERINSTR(vspltisw,       0x1000038C);
+  XEREGISTERINSTR(vspltisw128,    VX128_3(6, 1904));
+  XEREGISTERINSTR(vspltw,         0x1000028C);
+  XEREGISTERINSTR(vspltw128,      VX128_3(6, 1840));
+  XEREGISTERINSTR(vsr,            0x100002C4);
+  XEREGISTERINSTR(vsrab,          0x10000304);
+  XEREGISTERINSTR(vsrah,          0x10000344);
+  XEREGISTERINSTR(vsraw,          0x10000384);
+  XEREGISTERINSTR(vsraw128,       VX128(6, 336));
+  XEREGISTERINSTR(vsrb,           0x10000204);
+  XEREGISTERINSTR(vsrh,           0x10000244);
+  XEREGISTERINSTR(vsro,           0x1000044C);
+  XEREGISTERINSTR(vsro128,        VX128(5, 976));
+  XEREGISTERINSTR(vsrw,           0x10000284);
+  XEREGISTERINSTR(vsrw128,        VX128(6, 464));
+  XEREGISTERINSTR(vsubcuw,        0x10000580);
+  XEREGISTERINSTR(vsubfp,         0x1000004A);
+  XEREGISTERINSTR(vsubfp128,      VX128(5, 80));
+  XEREGISTERINSTR(vsubsbs,        0x10000700);
+  XEREGISTERINSTR(vsubshs,        0x10000740);
+  XEREGISTERINSTR(vsubsws,        0x10000780);
+  XEREGISTERINSTR(vsububm,        0x10000400);
+  XEREGISTERINSTR(vsububs,        0x10000600);
+  XEREGISTERINSTR(vsubuhm,        0x10000440);
+  XEREGISTERINSTR(vsubuhs,        0x10000640);
+  XEREGISTERINSTR(vsubuwm,        0x10000480);
+  XEREGISTERINSTR(vsubuws,        0x10000680);
+  XEREGISTERINSTR(vsumsws,        0x10000788);
+  XEREGISTERINSTR(vsum2sws,       0x10000688);
+  XEREGISTERINSTR(vsum4sbs,       0x10000708);
+  XEREGISTERINSTR(vsum4shs,       0x10000648);
+  XEREGISTERINSTR(vsum4ubs,       0x10000608);
+  XEREGISTERINSTR(vupkhpx,        0x1000034E);
+  XEREGISTERINSTR(vupkhsb,        0x1000020E);
+  XEREGISTERINSTR(vupkhsb128,     VX128(6, 896));
+  XEREGISTERINSTR(vupkhsh,        0x1000024E);
+  XEREGISTERINSTR(vupklpx,        0x100003CE);
+  XEREGISTERINSTR(vupklsb,        0x1000028E);
+  XEREGISTERINSTR(vupklsb128,     VX128(6, 960));
+  XEREGISTERINSTR(vupklsh,        0x100002CE);
+  XEREGISTERINSTR(vupkd3d128,     VX128_3(6, 2032));
+  XEREGISTERINSTR(vxor,           0x100004C4);
+  XEREGISTERINSTR(vxor128,        VX128(5, 784));
+}
+
+
+}  // namespace ppc
+}  // namespace cpu
+}  // namespace xe
diff --git a/src/xenia/cpu/ppc/instr.cc b/src/xenia/cpu/ppc/instr.cc
index 815fa19b3..3ea4b8b1a 100644
--- a/src/xenia/cpu/ppc/instr.cc
+++ b/src/xenia/cpu/ppc/instr.cc
@@ -350,11 +350,12 @@ void InstrDisasm::Dump(std::string& out_str, size_t pad) {
 
 
 InstrType* xe::cpu::ppc::GetInstrType(uint32_t code) {
+  // Fast lookup via tables.
   InstrType* slot = NULL;
   switch (code >> 26) {
   case 4:
-    // Opcode = 4, index = bits 5-0 (6)
-    slot = xe::cpu::ppc::tables::instr_table_4[XESELECTBITS(code, 0, 5)];
+    // Opcode = 4, index = bits 11-0 (6)
+    slot = xe::cpu::ppc::tables::instr_table_4[XESELECTBITS(code, 0, 11)];
     break;
   case 19:
     // Opcode = 19, index = bits 10-1 (10)
@@ -390,10 +391,21 @@ InstrType* xe::cpu::ppc::GetInstrType(uint32_t code) {
     slot = xe::cpu::ppc::tables::instr_table[XESELECTBITS(code, 26, 31)];
     break;
   }
-  if (!slot || !slot->opcode) {
-    return NULL;
+  if (slot && slot->opcode) {
+    return slot;
   }
-  return slot;
+
+  // Slow lookup via linear scan.
+  // This is primarily due to laziness. It could be made fast like the others.
+  for (size_t n = 0; n < XECOUNT(xe::cpu::ppc::tables::instr_table_vx128);
+       n++) {
+    slot = &(xe::cpu::ppc::tables::instr_table_vx128[n]);
+    if (slot->opcode == (code & slot->opcode_mask)) {
+      return slot;
+    }
+  }
+
+  return NULL;
 }
 
 int xe::cpu::ppc::RegisterInstrDisassemble(
diff --git a/src/xenia/cpu/ppc/instr.h b/src/xenia/cpu/ppc/instr.h
index d25e77cda..347ddf579 100644
--- a/src/xenia/cpu/ppc/instr.h
+++ b/src/xenia/cpu/ppc/instr.h
@@ -23,26 +23,44 @@ namespace ppc {
 
 // TODO(benvanik): rename these
 typedef enum {
-  kXEPPCInstrFormatI    = 0,
-  kXEPPCInstrFormatB    = 1,
-  kXEPPCInstrFormatSC   = 2,
-  kXEPPCInstrFormatD    = 3,
-  kXEPPCInstrFormatDS   = 4,
-  kXEPPCInstrFormatX    = 5,
-  kXEPPCInstrFormatXL   = 6,
-  kXEPPCInstrFormatXFX  = 7,
-  kXEPPCInstrFormatXFL  = 8,
-  kXEPPCInstrFormatXS   = 9,
-  kXEPPCInstrFormatXO   = 10,
-  kXEPPCInstrFormatA    = 11,
-  kXEPPCInstrFormatM    = 12,
-  kXEPPCInstrFormatMD   = 13,
-  kXEPPCInstrFormatMDS  = 14,
-  kXEPPCInstrFormatVA   = 15,
-  kXEPPCInstrFormatVX   = 16,
-  kXEPPCInstrFormatVXR  = 17,
+  kXEPPCInstrFormatI        = 0,
+  kXEPPCInstrFormatB        = 1,
+  kXEPPCInstrFormatSC       = 2,
+  kXEPPCInstrFormatD        = 3,
+  kXEPPCInstrFormatDS       = 4,
+  kXEPPCInstrFormatX        = 5,
+  kXEPPCInstrFormatXL       = 6,
+  kXEPPCInstrFormatXFX      = 7,
+  kXEPPCInstrFormatXFL      = 8,
+  kXEPPCInstrFormatXS       = 9,
+  kXEPPCInstrFormatXO       = 10,
+  kXEPPCInstrFormatA        = 11,
+  kXEPPCInstrFormatM        = 12,
+  kXEPPCInstrFormatMD       = 13,
+  kXEPPCInstrFormatMDS      = 14,
+  kXEPPCInstrFormatVXA      = 15,
+  kXEPPCInstrFormatVX       = 16,
+  kXEPPCInstrFormatVXR      = 17,
+  kXEPPCInstrFormatVX128    = 18,
+  kXEPPCInstrFormatVX128_1  = 19,
+  kXEPPCInstrFormatVX128_2  = 20,
+  kXEPPCInstrFormatVX128_3  = 21,
+  kXEPPCInstrFormatVX128_4  = 22,
+  kXEPPCInstrFormatVX128_5  = 23,
+  kXEPPCInstrFormatVX128_P  = 24,
+  kXEPPCInstrFormatXDSS     = 25,
 } xe_ppc_instr_format_e;
 
+typedef enum {
+  kXEPPCInstrMaskVX128      = 0xFC0003D0,
+  kXEPPCInstrMaskVX128_1    = 0xFC0007F3,
+  kXEPPCInstrMaskVX128_2    = 0xFC000210,
+  kXEPPCInstrMaskVX128_3    = 0xFC0007F0,
+  kXEPPCInstrMaskVX128_4    = 0xFC000730,
+  kXEPPCInstrMaskVX128_5    = 0xFC000010,
+  kXEPPCInstrMaskVX128_P    = 0xFC000630,
+} xe_ppc_instr_mask_e;
+
 typedef enum {
   kXEPPCInstrTypeGeneral      = (1 << 0),
   kXEPPCInstrTypeBranch       = (1 << 1),
@@ -212,9 +230,39 @@ typedef struct {
       uint32_t        RT      : 5;
       uint32_t                : 6;
     } MDS;
-    // kXEPPCInstrFormatVA
+    // kXEPPCInstrFormatVXA
+    struct {
+    } VXA;
     // kXEPPCInstrFormatVX
+    struct {
+    } VX;
     // kXEPPCInstrFormatVXR
+    struct {
+    } VXR;
+    // kXEPPCInstrFormatVX128
+    struct {
+    } VX128;
+    // kXEPPCInstrFormatVX128_1
+    struct {
+    } VX128_1;
+    // kXEPPCInstrFormatVX128_2
+    struct {
+    } VX128_2;
+    // kXEPPCInstrFormatVX128_3
+    struct {
+    } VX128_3;
+    // kXEPPCInstrFormatVX128_4
+    struct {
+    } VX128_4;
+    // kXEPPCInstrFormatVX128_5
+    struct {
+    } VX128_5;
+    // kXEPPCInstrFormatVX128_P
+    struct {
+    } VX128_P;
+    // kXEPPCInstrFormatXDSS
+    struct {
+    } XDSS;
   };
 } InstrData;
 
@@ -275,6 +323,7 @@ public:
   uint64_t cr;    // cr7/6/5/4/3/2/1/0
   uint64_t gpr;   // r31-0
   uint64_t fpr;   // f31-0
+  // TODO(benvanik): vr128-0
 
   void Clear();
   void Extend(InstrAccessBits& other);
@@ -286,11 +335,12 @@ public:
 class InstrDisasm {
 public:
   enum Flags {
-    kOE = 1 << 0,
-    kRc = 1 << 1,
-    kCA = 1 << 2,
-    kLR = 1 << 4,
-    kFP = 1 << 5,
+    kOE   = 1 << 0,
+    kRc   = 1 << 1,
+    kCA   = 1 << 2,
+    kLR   = 1 << 4,
+    kFP   = 1 << 5,
+    kVMX  = 1 << 6,
   };
 
   const char*   name;
@@ -321,9 +371,10 @@ typedef void* InstrEmitFn;
 class InstrType {
 public:
   uint32_t    opcode;
-  uint32_t    format;   // xe_ppc_instr_format_e
-  uint32_t    type;     // xe_ppc_instr_type_e
-  uint32_t    flags;    // xe_ppc_instr_flag_e
+  uint32_t    opcode_mask;    // Only used for certain opcodes (altivec, etc).
+  uint32_t    format;         // xe_ppc_instr_format_e
+  uint32_t    type;           // xe_ppc_instr_type_e
+  uint32_t    flags;          // xe_ppc_instr_flag_e
   char        name[16];
 
   InstrDisassembleFn disassemble;
diff --git a/src/xenia/cpu/ppc/instr_tables.h b/src/xenia/cpu/ppc/instr_tables.h
index 1f693c719..f8289bd52 100644
--- a/src/xenia/cpu/ppc/instr_tables.h
+++ b/src/xenia/cpu/ppc/instr_tables.h
@@ -53,6 +53,7 @@ static InstrType** instr_table_prep_63(
 #define EMPTY(slot) {0}
 #define INSTRUCTION(name, opcode, format, type, flag)  { \
   opcode, \
+  0, \
   kXEPPCInstrFormat##format, \
   kXEPPCInstrType##type, \
   flag, \
@@ -65,13 +66,169 @@ static InstrType** instr_table_prep_63(
 //   pem_64bit_v3.0.2005jul15.pdf, A.2
 //   PowerISA_V2.06B_V2_PUBLIC.pdf
 
-// Opcode = 4, index = bits 5-0 (6)
+// Opcode = 4, index = bits 11-0 (6)
 static InstrType instr_table_4_unprep[] = {
   // TODO: all of the vector ops
-  INSTRUCTION(vperm,          0x1000002B, VA , General        , 0),
+  INSTRUCTION(mfvscr,         0x10000604, VX      , General       , 0),
+  INSTRUCTION(mtvscr,         0x10000644, VX      , General       , 0),
+  INSTRUCTION(vaddcuw,        0x10000180, VX      , General       , 0),
+  INSTRUCTION(vaddfp,         0x1000000A, VX      , General       , 0),
+  INSTRUCTION(vaddsbs,        0x10000300, VX      , General       , 0),
+  INSTRUCTION(vaddshs,        0x10000340, VX      , General       , 0),
+  INSTRUCTION(vaddsws,        0x10000380, VX      , General       , 0),
+  INSTRUCTION(vaddubm,        0x10000000, VX      , General       , 0),
+  INSTRUCTION(vaddubs,        0x10000200, VX      , General       , 0),
+  INSTRUCTION(vadduhm,        0x10000040, VX      , General       , 0),
+  INSTRUCTION(vadduhs,        0x10000240, VX      , General       , 0),
+  INSTRUCTION(vadduwm,        0x10000080, VX      , General       , 0),
+  INSTRUCTION(vadduws,        0x10000280, VX      , General       , 0),
+  INSTRUCTION(vand,           0x10000404, VX      , General       , 0),
+  INSTRUCTION(vandc,          0x10000444, VX      , General       , 0),
+  INSTRUCTION(vavgsb,         0x10000502, VX      , General       , 0),
+  INSTRUCTION(vavgsh,         0x10000542, VX      , General       , 0),
+  INSTRUCTION(vavgsw,         0x10000582, VX      , General       , 0),
+  INSTRUCTION(vavgub,         0x10000402, VX      , General       , 0),
+  INSTRUCTION(vavguh,         0x10000442, VX      , General       , 0),
+  INSTRUCTION(vavguw,         0x10000482, VX      , General       , 0),
+  INSTRUCTION(vcfsx,          0x1000034A, VX      , General       , 0),
+  INSTRUCTION(vcfux,          0x1000030A, VX      , General       , 0),
+  INSTRUCTION(vcmpbfp,        0x100003C6, VXR     , General       , 0),
+  INSTRUCTION(vcmpbfp_c,      0x100007C6, VXR     , General       , 0),
+  INSTRUCTION(vcmpeqfp,       0x100000C6, VXR     , General       , 0),
+  INSTRUCTION(vcmpeqfp_c,     0x100004C6, VXR     , General       , 0),
+  INSTRUCTION(vcmpequb,       0x10000006, VXR     , General       , 0),
+  INSTRUCTION(vcmpequb_c,     0x10000406, VXR     , General       , 0),
+  INSTRUCTION(vcmpequh,       0x10000046, VXR     , General       , 0),
+  INSTRUCTION(vcmpequh_c,     0x10000446, VXR     , General       , 0),
+  INSTRUCTION(vcmpequw,       0x10000086, VXR     , General       , 0),
+  INSTRUCTION(vcmpequw_c,     0x10000486, VXR     , General       , 0),
+  INSTRUCTION(vcmpgefp,       0x100001C6, VXR     , General       , 0),
+  INSTRUCTION(vcmpgefp_c,     0x100005C6, VXR     , General       , 0),
+  INSTRUCTION(vcmpgtfp,       0x100002C6, VXR     , General       , 0),
+  INSTRUCTION(vcmpgtfp_c,     0x100006C6, VXR     , General       , 0),
+  INSTRUCTION(vcmpgtsb,       0x10000306, VXR     , General       , 0),
+  INSTRUCTION(vcmpgtsb_c,     0x10000706, VXR     , General       , 0),
+  INSTRUCTION(vcmpgtsh,       0x10000346, VXR     , General       , 0),
+  INSTRUCTION(vcmpgtsh_c,     0x10000746, VXR     , General       , 0),
+  INSTRUCTION(vcmpgtsw,       0x10000386, VXR     , General       , 0),
+  INSTRUCTION(vcmpgtsw_c,     0x10000786, VXR     , General       , 0),
+  INSTRUCTION(vcmpgtub,       0x10000206, VXR     , General       , 0),
+  INSTRUCTION(vcmpgtub_c,     0x10000606, VXR     , General       , 0),
+  INSTRUCTION(vcmpgtuh,       0x10000246, VXR     , General       , 0),
+  INSTRUCTION(vcmpgtuh_c,     0x10000646, VXR     , General       , 0),
+  INSTRUCTION(vcmpgtuw,       0x10000286, VXR     , General       , 0),
+  INSTRUCTION(vcmpgtuw_c,     0x10000686, VXR     , General       , 0),
+  INSTRUCTION(vctsxs,         0x100003CA, VX      , General       , 0),
+  INSTRUCTION(vctuxs,         0x1000038A, VX      , General       , 0),
+  INSTRUCTION(vexptefp,       0x1000018A, VX      , General       , 0),
+  INSTRUCTION(vlogefp,        0x100001CA, VX      , General       , 0),
+  INSTRUCTION(vmaddfp,        0x1000002E, VXA     , General       , 0),
+  INSTRUCTION(vmaxfp,         0x1000040A, VX      , General       , 0),
+  INSTRUCTION(vmaxsb,         0x10000102, VX      , General       , 0),
+  INSTRUCTION(vmaxsh,         0x10000142, VX      , General       , 0),
+  INSTRUCTION(vmaxsw,         0x10000182, VX      , General       , 0),
+  INSTRUCTION(vmaxub,         0x10000002, VX      , General       , 0),
+  INSTRUCTION(vmaxuh,         0x10000042, VX      , General       , 0),
+  INSTRUCTION(vmaxuw,         0x10000082, VX      , General       , 0),
+  INSTRUCTION(vmhaddshs,      0x10000020, VXA     , General       , 0),
+  INSTRUCTION(vmhraddshs,     0x10000021, VXA     , General       , 0),
+  INSTRUCTION(vminfp,         0x1000044A, VX      , General       , 0),
+  INSTRUCTION(vminsb,         0x10000302, VX      , General       , 0),
+  INSTRUCTION(vminsh,         0x10000342, VX      , General       , 0),
+  INSTRUCTION(vminsw,         0x10000382, VX      , General       , 0),
+  INSTRUCTION(vminub,         0x10000202, VX      , General       , 0),
+  INSTRUCTION(vminuh,         0x10000242, VX      , General       , 0),
+  INSTRUCTION(vminuw,         0x10000282, VX      , General       , 0),
+  INSTRUCTION(vmladduhm,      0x10000022, VXA     , General       , 0),
+  INSTRUCTION(vmrghb,         0x1000000C, VX      , General       , 0),
+  INSTRUCTION(vmrghh,         0x1000004C, VX      , General       , 0),
+  INSTRUCTION(vmrghw,         0x1000008C, VX      , General       , 0),
+  INSTRUCTION(vmrglb,         0x1000010C, VX      , General       , 0),
+  INSTRUCTION(vmrglh,         0x1000014C, VX      , General       , 0),
+  INSTRUCTION(vmrglw,         0x1000018C, VX      , General       , 0),
+  INSTRUCTION(vmsummbm,       0x10000025, VXA     , General       , 0),
+  INSTRUCTION(vmsumshm,       0x10000028, VXA     , General       , 0),
+  INSTRUCTION(vmsumshs,       0x10000029, VXA     , General       , 0),
+  INSTRUCTION(vmsumubm,       0x10000024, VXA     , General       , 0),
+  INSTRUCTION(vmsumuhm,       0x10000026, VXA     , General       , 0),
+  INSTRUCTION(vmsumuhs,       0x10000027, VXA     , General       , 0),
+  INSTRUCTION(vmulesb,        0x10000308, VX      , General       , 0),
+  INSTRUCTION(vmulesh,        0x10000348, VX      , General       , 0),
+  INSTRUCTION(vmuleub,        0x10000208, VX      , General       , 0),
+  INSTRUCTION(vmuleuh,        0x10000248, VX      , General       , 0),
+  INSTRUCTION(vmulosb,        0x10000108, VX      , General       , 0),
+  INSTRUCTION(vmulosh,        0x10000148, VX      , General       , 0),
+  INSTRUCTION(vmuloub,        0x10000008, VX      , General       , 0),
+  INSTRUCTION(vmulouh,        0x10000048, VX      , General       , 0),
+  INSTRUCTION(vnmsubfp,       0x1000002F, VXA     , General       , 0),
+  INSTRUCTION(vnor,           0x10000504, VX      , General       , 0),
+  INSTRUCTION(vor,            0x10000484, VX      , General       , 0),
+  INSTRUCTION(vperm,          0x1000002B, VXA     , General       , 0),
+  INSTRUCTION(vpkpx,          0x1000030E, VX      , General       , 0),
+  INSTRUCTION(vpkshss,        0x1000018E, VX      , General       , 0),
+  INSTRUCTION(vpkshus,        0x1000010E, VX      , General       , 0),
+  INSTRUCTION(vpkswss,        0x100001CE, VX      , General       , 0),
+  INSTRUCTION(vpkswus,        0x1000014E, VX      , General       , 0),
+  INSTRUCTION(vpkuhum,        0x1000000E, VX      , General       , 0),
+  INSTRUCTION(vpkuhus,        0x1000008E, VX      , General       , 0),
+  INSTRUCTION(vpkuwum,        0x1000004E, VX      , General       , 0),
+  INSTRUCTION(vpkuwus,        0x100000CE, VX      , General       , 0),
+  INSTRUCTION(vrefp,          0x1000010A, VX      , General       , 0),
+  INSTRUCTION(vrfim,          0x100002CA, VX      , General       , 0),
+  INSTRUCTION(vrfin,          0x1000020A, VX      , General       , 0),
+  INSTRUCTION(vrfip,          0x1000028A, VX      , General       , 0),
+  INSTRUCTION(vrfiz,          0x1000024A, VX      , General       , 0),
+  INSTRUCTION(vrlb,           0x10000004, VX      , General       , 0),
+  INSTRUCTION(vrlh,           0x10000044, VX      , General       , 0),
+  INSTRUCTION(vrlw,           0x10000084, VX      , General       , 0),
+  INSTRUCTION(vrsqrtefp,      0x1000014A, VX      , General       , 0),
+  INSTRUCTION(vsel,           0x1000002A, VXA     , General       , 0),
+  INSTRUCTION(vsl,            0x100001C4, VX      , General       , 0),
+  INSTRUCTION(vslb,           0x10000104, VX      , General       , 0),
+  INSTRUCTION(vsldoi,         0x1000002C, VXA     , General       , 0),
+  INSTRUCTION(vslh,           0x10000144, VX      , General       , 0),
+  INSTRUCTION(vslo,           0x1000040C, VX      , General       , 0),
+  INSTRUCTION(vslw,           0x10000184, VX      , General       , 0),
+  INSTRUCTION(vspltb,         0x1000020C, VX      , General       , 0),
+  INSTRUCTION(vsplth,         0x1000024C, VX      , General       , 0),
+  INSTRUCTION(vspltisb,       0x1000030C, VX      , General       , 0),
+  INSTRUCTION(vspltish,       0x1000034C, VX      , General       , 0),
+  INSTRUCTION(vspltisw,       0x1000038C, VX      , General       , 0),
+  INSTRUCTION(vspltw,         0x1000028C, VX      , General       , 0),
+  INSTRUCTION(vsr,            0x100002C4, VX      , General       , 0),
+  INSTRUCTION(vsrab,          0x10000304, VX      , General       , 0),
+  INSTRUCTION(vsrah,          0x10000344, VX      , General       , 0),
+  INSTRUCTION(vsraw,          0x10000384, VX      , General       , 0),
+  INSTRUCTION(vsrb,           0x10000204, VX      , General       , 0),
+  INSTRUCTION(vsrh,           0x10000244, VX      , General       , 0),
+  INSTRUCTION(vsro,           0x1000044C, VX      , General       , 0),
+  INSTRUCTION(vsrw,           0x10000284, VX      , General       , 0),
+  INSTRUCTION(vsubcuw,        0x10000580, VX      , General       , 0),
+  INSTRUCTION(vsubfp,         0x1000004A, VX      , General       , 0),
+  INSTRUCTION(vsubsbs,        0x10000700, VX      , General       , 0),
+  INSTRUCTION(vsubshs,        0x10000740, VX      , General       , 0),
+  INSTRUCTION(vsubsws,        0x10000780, VX      , General       , 0),
+  INSTRUCTION(vsububm,        0x10000400, VX      , General       , 0),
+  INSTRUCTION(vsububs,        0x10000600, VX      , General       , 0),
+  INSTRUCTION(vsubuhm,        0x10000440, VX      , General       , 0),
+  INSTRUCTION(vsubuhs,        0x10000640, VX      , General       , 0),
+  INSTRUCTION(vsubuwm,        0x10000480, VX      , General       , 0),
+  INSTRUCTION(vsubuws,        0x10000680, VX      , General       , 0),
+  INSTRUCTION(vsumsws,        0x10000788, VX      , General       , 0),
+  INSTRUCTION(vsum2sws,       0x10000688, VX      , General       , 0),
+  INSTRUCTION(vsum4sbs,       0x10000708, VX      , General       , 0),
+  INSTRUCTION(vsum4shs,       0x10000648, VX      , General       , 0),
+  INSTRUCTION(vsum4ubs,       0x10000608, VX      , General       , 0),
+  INSTRUCTION(vupkhpx,        0x1000034E, VX      , General       , 0),
+  INSTRUCTION(vupkhsb,        0x1000020E, VX      , General       , 0),
+  INSTRUCTION(vupkhsh,        0x1000024E, VX      , General       , 0),
+  INSTRUCTION(vupklpx,        0x100003CE, VX      , General       , 0),
+  INSTRUCTION(vupklsb,        0x1000028E, VX      , General       , 0),
+  INSTRUCTION(vupklsh,        0x100002CE, VX      , General       , 0),
+  INSTRUCTION(vxor,           0x100004C4, VX      , General       , 0),
 };
 static InstrType** instr_table_4 = instr_table_prep(
-    instr_table_4_unprep, XECOUNT(instr_table_4_unprep), 0, 5);
+    instr_table_4_unprep, XECOUNT(instr_table_4_unprep), 0, 11);
 
 // Opcode = 19, index = bits 10-1 (10)
 static InstrType instr_table_19_unprep[] = {
@@ -115,7 +272,7 @@ static InstrType instr_table_31_unprep[] = {
   INSTRUCTION(lvebx,          0x7C00000E, X  , General        , 0),
   INSTRUCTION(subfcx,         0x7C000010, XO , General        , 0),
   INSTRUCTION(mulhdux,        0x7C000012, XO , General        , 0),
-  INSTRUCTION(addcx,          0X7C000014, XO , General        , 0),
+  INSTRUCTION(addcx,          0x7C000014, XO , General        , 0),
   INSTRUCTION(mulhwux,        0x7C000016, XO , General        , 0),
   INSTRUCTION(mfcr,           0x7C000026, X  , General        , 0),
   INSTRUCTION(lwarx,          0x7C000028, X  , General        , 0),
@@ -229,6 +386,29 @@ static InstrType instr_table_31_unprep[] = {
   INSTRUCTION(stfiwx,         0x7C0007AE, X  , General        , 0),
   INSTRUCTION(extswx,         0x7C0007B4, X  , General        , 0),
   INSTRUCTION(dcbz,           0x7C0007EC, X  , General        , 0), // 0x7C2007EC = DCBZ128
+  INSTRUCTION(dst,            0x7C0002AC, XDSS, General       , 0),
+  INSTRUCTION(dstst,          0x7C0002EC, XDSS, General       , 0),
+  INSTRUCTION(dss,            0x7C00066C, XDSS, General       , 0),
+  INSTRUCTION(lvebx,          0x7C00000E, X  , General        , 0),
+  INSTRUCTION(lvehx,          0x7C00004E, X  , General        , 0),
+  INSTRUCTION(lvewx,          0x7C00008E, X  , General        , 0),
+  INSTRUCTION(lvsl,           0x7C00000C, X  , General        , 0),
+  INSTRUCTION(lvsr,           0x7C00004C, X  , General        , 0),
+  INSTRUCTION(lvx,            0x7C0000CE, X  , General        , 0),
+  INSTRUCTION(lvxl,           0x7C0002CE, X  , General        , 0),
+  INSTRUCTION(stvebx,         0x7C00010E, X  , General        , 0),
+  INSTRUCTION(stvehx,         0x7C00014E, X  , General        , 0),
+  INSTRUCTION(stvewx,         0x7C00018E, X  , General        , 0),
+  INSTRUCTION(stvx,           0x7C0001CE, X  , General        , 0),
+  INSTRUCTION(stvxl,          0x7C0003CE, X  , General        , 0),
+  INSTRUCTION(lvlx,           0x7C00040E, X  , General        , 0),
+  INSTRUCTION(lvlxl,          0x7C00060E, X  , General        , 0),
+  INSTRUCTION(lvrx,           0x7C00044E, X  , General        , 0),
+  INSTRUCTION(lvrxl,          0x7C00064E, X  , General        , 0),
+  INSTRUCTION(stvlx,          0x7C00050E, X  , General        , 0),
+  INSTRUCTION(stvlxl,         0x7C00070E, X  , General        , 0),
+  INSTRUCTION(stvrx,          0x7C00054E, X  , General        , 0),
+  INSTRUCTION(stvrxl,         0x7C00074E, X  , General        , 0),
 };
 static InstrType** instr_table_31 = instr_table_prep(
     instr_table_31_unprep, XECOUNT(instr_table_31_unprep), 1, 10);
@@ -355,6 +535,116 @@ static InstrType instr_table_unprep[64] = {
 static InstrType** instr_table = instr_table_prep(
     instr_table_unprep, XECOUNT(instr_table_unprep), 26, 31);
 
+// Altivec instructions.
+// TODO(benvanik): build a table like the other instructions.
+// This table is looked up via linear scan of opcodes.
+#define VX128_INSTRUCTION(name, opcode, format, type, flag)  { \
+  opcode, \
+  kXEPPCInstrMask##format, \
+  kXEPPCInstrFormat##format, \
+  kXEPPCInstrType##type, \
+  flag, \
+  #name, \
+}
+#define OP(x)             ((((uint32_t)(x)) & 0x3f) << 26)
+#define VX128(op, xop)    (OP(op) | (((uint32_t)(xop)) & 0x3d0))
+#define VX128_1(op, xop)  (OP(op) | (((uint32_t)(xop)) & 0x7f3))
+#define VX128_2(op, xop)  (OP(op) | (((uint32_t)(xop)) & 0x210))
+#define VX128_3(op, xop)  (OP(op) | (((uint32_t)(xop)) & 0x7f0))
+#define VX128_4(op, xop)  (OP(op) | (((uint32_t)(xop)) & 0x730))
+#define VX128_5(op, xop)  (OP(op) | (((uint32_t)(xop)) & 0x10))
+#define VX128_P(op, xop)  (OP(op) | (((uint32_t)(xop)) & 0x630))
+static InstrType instr_table_vx128[] = {
+  VX128_INSTRUCTION(lvsl128,        VX128_1(4, 3),    VX128_1 , General       , 0),
+  VX128_INSTRUCTION(lvsr128,        VX128_1(4, 67),   VX128_1 , General       , 0),
+  VX128_INSTRUCTION(lvewx128,       VX128_1(4, 131),  VX128_1 , General       , 0),
+  VX128_INSTRUCTION(lvx128,         VX128_1(4, 195),  VX128_1 , General       , 0),
+  VX128_INSTRUCTION(stvewx128,      VX128_1(4, 387),  VX128_1 , General       , 0),
+  VX128_INSTRUCTION(stvx128,        VX128_1(4, 451),  VX128_1 , General       , 0),
+  VX128_INSTRUCTION(lvxl128,        VX128_1(4, 707),  VX128_1 , General       , 0),
+  VX128_INSTRUCTION(stvxl128,       VX128_1(4, 963),  VX128_1 , General       , 0),
+  VX128_INSTRUCTION(lvlx128,        VX128_1(4, 1027), VX128_1 , General       , 0),
+  VX128_INSTRUCTION(lvrx128,        VX128_1(4, 1091), VX128_1 , General       , 0),
+  VX128_INSTRUCTION(stvlx128,       VX128_1(4, 1283), VX128_1 , General       , 0),
+  VX128_INSTRUCTION(stvrx128,       VX128_1(4, 1347), VX128_1 , General       , 0),
+  VX128_INSTRUCTION(lvlxl128,       VX128_1(4, 1539), VX128_1 , General       , 0),
+  VX128_INSTRUCTION(lvrxl128,       VX128_1(4, 1603), VX128_1 , General       , 0),
+  VX128_INSTRUCTION(stvlxl128,      VX128_1(4, 1795), VX128_1 , General       , 0),
+  VX128_INSTRUCTION(stvrxl128,      VX128_1(4, 1859), VX128_1 , General       , 0),
+  VX128_INSTRUCTION(vsldoi128,      VX128_5(4, 16),   VX128_5 , General       , 0),
+  VX128_INSTRUCTION(vperm128,       VX128_2(5, 0),    VX128_2 , General       , 0),
+  VX128_INSTRUCTION(vaddfp128,      VX128(5, 16),     VX128   , General       , 0),
+  VX128_INSTRUCTION(vsubfp128,      VX128(5,  80),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vmulfp128,      VX128(5, 144),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vmaddfp128,     VX128(5, 208),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vmaddcfp128,    VX128(5, 272),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vnmsubfp128,    VX128(5, 336),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vmsum3fp128,    VX128(5, 400),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vmsum4fp128,    VX128(5, 464),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vpkshss128,     VX128(5, 512),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vand128,        VX128(5, 528),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vpkshus128,     VX128(5, 576),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vandc128,       VX128(5, 592),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vpkswss128,     VX128(5, 640),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vnor128,        VX128(5, 656),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vpkswus128,     VX128(5, 704),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vor128,         VX128(5, 720),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vpkuhum128,     VX128(5, 768),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vxor128,        VX128(5, 784),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vpkuhus128,     VX128(5, 832),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vsel128,        VX128(5, 848),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vpkuwum128,     VX128(5, 896),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vslo128,        VX128(5, 912),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vpkuwus128,     VX128(5, 960),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vsro128,        VX128(5, 976),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vpermwi128,     VX128_P(6, 528),  VX128_P , General       , 0),
+  VX128_INSTRUCTION(vcfpsxws128,    VX128_3(6, 560),  VX128_3 , General       , 0),
+  VX128_INSTRUCTION(vcfpuxws128,    VX128_3(6, 624),  VX128_3 , General       , 0),
+  VX128_INSTRUCTION(vcsxwfp128,     VX128_3(6, 688),  VX128_3 , General       , 0),
+  VX128_INSTRUCTION(vcuxwfp128,     VX128_3(6, 752),  VX128_3 , General       , 0),
+  VX128_INSTRUCTION(vrfim128,       VX128_3(6, 816),  VX128_3 , General       , 0),
+  VX128_INSTRUCTION(vrfin128,       VX128_3(6, 880),  VX128_3 , General       , 0),
+  VX128_INSTRUCTION(vrfip128,       VX128_3(6, 944),  VX128_3 , General       , 0),
+  VX128_INSTRUCTION(vrfiz128,       VX128_3(6, 1008), VX128_3 , General       , 0),
+  VX128_INSTRUCTION(vpkd3d128,      VX128_4(6, 1552), VX128_4 , General       , 0),
+  VX128_INSTRUCTION(vrefp128,       VX128_3(6, 1584), VX128_3 , General       , 0),
+  VX128_INSTRUCTION(vrsqrtefp128,   VX128_3(6, 1648), VX128_3 , General       , 0),
+  VX128_INSTRUCTION(vexptefp128,    VX128_3(6, 1712), VX128_3 , General       , 0),
+  VX128_INSTRUCTION(vlogefp128,     VX128_3(6, 1776), VX128_3 , General       , 0),
+  VX128_INSTRUCTION(vrlimi128,      VX128_4(6, 1808), VX128_4 , General       , 0),
+  VX128_INSTRUCTION(vspltw128,      VX128_3(6, 1840), VX128_3 , General       , 0),
+  VX128_INSTRUCTION(vspltisw128,    VX128_3(6, 1904), VX128_3 , General       , 0),
+  VX128_INSTRUCTION(vupkd3d128,     VX128_3(6, 2032), VX128_3 , General       , 0),
+  VX128_INSTRUCTION(vcmpeqfp128,    VX128(6, 0),      VX128   , General       , 0),
+  VX128_INSTRUCTION(vcmpeqfp128c,   VX128(6, 64),     VX128   , General       , 0),
+  VX128_INSTRUCTION(vrlw128,        VX128(6, 80),     VX128   , General       , 0),
+  VX128_INSTRUCTION(vcmpgefp128,    VX128(6, 128),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vcmpgefp128c,   VX128(6, 192),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vslw128,        VX128(6, 208),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vcmpgtfp128,    VX128(6, 256),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vcmpgtfp128c,   VX128(6, 320),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vsraw128,       VX128(6, 336),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vcmpbfp128,     VX128(6, 384),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vcmpbfp128c,    VX128(6, 448),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vsrw128,        VX128(6, 464),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vcmpequw128,    VX128(6, 512),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vcmpequw128c,   VX128(6, 576),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vmaxfp128,      VX128(6, 640),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vminfp128,      VX128(6, 704),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vmrghw128,      VX128(6, 768),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vmrglw128,      VX128(6, 832),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vupkhsb128,     VX128(6, 896),    VX128   , General       , 0),
+  VX128_INSTRUCTION(vupklsb128,     VX128(6, 960),    VX128   , General       , 0),
+};
+#undef OP
+#undef VX128
+#undef VX128_1
+#undef VX128_2
+#undef VX128_3
+#undef VX128_4
+#undef VX128_5
+#undef VX128_P
+
 
 #undef FLAG
 #undef INSTRUCTION
diff --git a/src/xenia/cpu/ppc/sources.gypi b/src/xenia/cpu/ppc/sources.gypi
index db3494381..1a346ec32 100644
--- a/src/xenia/cpu/ppc/sources.gypi
+++ b/src/xenia/cpu/ppc/sources.gypi
@@ -2,6 +2,7 @@
 {
   'sources': [
     'disasm.h',
+    'disasm_altivec.cc',
     'disasm_alu.cc',
     'disasm_control.cc',
     'disasm_fpu.cc',
diff --git a/src/xenia/cpu/processor.cc b/src/xenia/cpu/processor.cc
index d8c2c16bc..81722a2ca 100644
--- a/src/xenia/cpu/processor.cc
+++ b/src/xenia/cpu/processor.cc
@@ -31,6 +31,7 @@ namespace {
     }
     has_initialized = true;
 
+    ppc::RegisterDisasmCategoryAltivec();
     ppc::RegisterDisasmCategoryALU();
     ppc::RegisterDisasmCategoryControl();
     ppc::RegisterDisasmCategoryFPU();
diff --git a/src/xenia/cpu/x64/sources.gypi b/src/xenia/cpu/x64/sources.gypi
index 6a1eed7a1..545a6a70a 100644
--- a/src/xenia/cpu/x64/sources.gypi
+++ b/src/xenia/cpu/x64/sources.gypi
@@ -4,6 +4,7 @@
     'x64_backend.cc',
     'x64_backend.h',
     'x64_emit.h',
+    'x64_emit_altivec.cc',
     'x64_emit_alu.cc',
     'x64_emit_control.cc',
     'x64_emit_fpu.cc',
diff --git a/src/xenia/cpu/x64/x64_backend.cc b/src/xenia/cpu/x64/x64_backend.cc
index 6217822bc..9832cca50 100644
--- a/src/xenia/cpu/x64/x64_backend.cc
+++ b/src/xenia/cpu/x64/x64_backend.cc
@@ -31,6 +31,7 @@ namespace {
     }
     has_initialized = true;
 
+    X64RegisterEmitCategoryAltivec();
     X64RegisterEmitCategoryALU();
     X64RegisterEmitCategoryControl();
     X64RegisterEmitCategoryFPU();
diff --git a/src/xenia/cpu/x64/x64_emit.h b/src/xenia/cpu/x64/x64_emit.h
index 02eb793df..60ef435a0 100644
--- a/src/xenia/cpu/x64/x64_emit.h
+++ b/src/xenia/cpu/x64/x64_emit.h
@@ -20,6 +20,7 @@ namespace cpu {
 namespace x64 {
 
 
+void X64RegisterEmitCategoryAltivec();
 void X64RegisterEmitCategoryALU();
 void X64RegisterEmitCategoryControl();
 void X64RegisterEmitCategoryFPU();
diff --git a/src/xenia/cpu/x64/x64_emit_altivec.cc b/src/xenia/cpu/x64/x64_emit_altivec.cc
new file mode 100644
index 000000000..5b0aaf55d
--- /dev/null
+++ b/src/xenia/cpu/x64/x64_emit_altivec.cc
@@ -0,0 +1,39 @@
+/*
+ ******************************************************************************
+ * Xenia : Xbox 360 Emulator Research Project                                 *
+ ******************************************************************************
+ * Copyright 2013 Ben Vanik. All rights reserved.                             *
+ * Released under the BSD license - see LICENSE in the root for more details. *
+ ******************************************************************************
+ */
+
+#include <xenia/cpu/x64/x64_emit.h>
+
+#include <xenia/cpu/cpu-private.h>
+
+
+using namespace xe::cpu;
+using namespace xe::cpu::ppc;
+
+using namespace AsmJit;
+
+
+namespace xe {
+namespace cpu {
+namespace x64 {
+
+
+// XEEMITTER(fnabsx,       0xFC000110, X  )(X64Emitter& e, X86Compiler& c, InstrData& i) {
+//   XEINSTRNOTIMPLEMENTED();
+//   return 1;
+// }
+
+
+void X64RegisterEmitCategoryAltivec() {
+  // XEREGISTERINSTR(faddx,        0xFC00002A);
+}
+
+
+}  // namespace x64
+}  // namespace cpu
+}  // namespace xe