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[D3D12] Slightly better logging

This commit is contained in:
Triang3l 2018-09-19 16:49:37 +03:00
parent fdd536f572
commit ed66694319
2 changed files with 12 additions and 2 deletions
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10
src/xenia/gpu/d3d12/pipeline_cache.cc
View File

@ -686,6 +686,16 @@ PipelineCache::Pipeline* PipelineCache::GetPipeline(uint64_t hash_key) {
// TODO(Triang3l): Cache create pipelines using CachedPSO.
if (update_shader_stages_regs_.pixel_shader != nullptr) {
XELOGGPU(
"Creating pipeline %.16" PRIX64 ", VS %.16" PRIX64 ", PS %.16" PRIX64,
hash_key, update_shader_stages_regs_.vertex_shader->ucode_data_hash(),
update_shader_stages_regs_.pixel_shader->ucode_data_hash());
} else {
XELOGGPU("Creating pipeline %.16" PRIX64 ", VS %.16" PRIX64, hash_key,
update_shader_stages_regs_.vertex_shader->ucode_data_hash());
}
auto device =
command_processor_->GetD3D12Context()->GetD3D12Provider()->GetDevice();
ID3D12PipelineState* state;

2
src/xenia/gpu/d3d12/texture_cache.cc
View File

@ -1111,7 +1111,7 @@ void TextureCache::WatchCallback(Texture* texture, bool is_mip) {
texture->base_in_sync = false;
texture->base_watch_handle = nullptr;
}
XELOGE("Texture %s at %.8X invalidated", is_mip ? "mips" : "base",
XELOGGPU("Texture %s at 0x%.8X invalidated", is_mip ? "mips" : "base",
(is_mip ? texture->key.mip_page : texture->key.base_page) << 12);
texture_invalidated_.store(true, std::memory_order_relaxed);
}