srawx, vsldoi, vupkd3d of D3DCOLOR -- all untested
This commit is contained in:
Ben Vanik
parent
3ec930d9fc
commit
eb2d596c27
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@ -1249,85 +1249,51 @@ XEEMITTER(vslw128, VX128(6, 208), VX128 )(PPCFunctionBuilder& f, Inst
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return InstrEmit_vslw_(f, VX128_VD128, VX128_VA128, VX128_VB128);
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return InstrEmit_vslw_(f, VX128_VD128, VX128_VA128, VX128_VB128);
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}
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}
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// static __m128i __shift_table_out[16] = {
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static uint8_t __vsldoi_table[16][16] = {
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// _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0), // unused
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{15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0}, // unused
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// _mm_set_epi8( 0, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1),
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{16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1},
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// _mm_set_epi8( 0, 0, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2),
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{17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2},
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// _mm_set_epi8( 0, 0, 0, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3),
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{18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3},
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// _mm_set_epi8( 0, 0, 0, 0, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4),
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{19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4},
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// _mm_set_epi8( 0, 0, 0, 0, 0, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5),
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{20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5},
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// _mm_set_epi8( 0, 0, 0, 0, 0, 0, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6),
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{21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6},
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// _mm_set_epi8( 0, 0, 0, 0, 0, 0, 0, 15, 14, 13, 12, 11, 10, 9, 8, 7),
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{22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7},
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// _mm_set_epi8( 0, 0, 0, 0, 0, 0, 0, 0, 15, 14, 13, 12, 11, 10, 9, 8),
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{23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8},
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// _mm_set_epi8( 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 14, 13, 12, 11, 10, 9),
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{24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9},
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// _mm_set_epi8( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 14, 13, 12, 11, 10),
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{25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10},
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// _mm_set_epi8( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 14, 13, 12, 11),
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{26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11},
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// _mm_set_epi8( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 14, 13, 12),
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{27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12},
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// _mm_set_epi8( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 14, 13),
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{28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13},
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// _mm_set_epi8( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 14),
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{29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14},
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// _mm_set_epi8( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15),
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{30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15},
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// };
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};
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// static __m128i __shift_table_in[16] = {
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int InstrEmit_vsldoi_(PPCFunctionBuilder& f, uint32_t vd, uint32_t va, uint32_t vb, uint32_t sh) {
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// _mm_set_epi8(15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15), // unused
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// (VD) <- ((VA) || (VB)) << (SH << 3)
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// _mm_set_epi8( 0, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15),
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if (!sh) {
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// _mm_set_epi8( 1, 0, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15),
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f.StoreVR(vd, f.LoadVR(va));
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// _mm_set_epi8( 2, 1, 0, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15),
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return 0;
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// _mm_set_epi8( 3, 2, 1, 0, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15),
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} else if (sh == 16) {
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// _mm_set_epi8( 4, 3, 2, 1, 0, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15),
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f.StoreVR(vd, f.LoadVR(vb));
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// _mm_set_epi8( 5, 4, 3, 2, 1, 0, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15),
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return 0;
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// _mm_set_epi8( 6, 5, 4, 3, 2, 1, 0, 15, 15, 15, 15, 15, 15, 15, 15, 15),
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}
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// _mm_set_epi8( 7, 6, 5, 4, 3, 2, 1, 0, 15, 15, 15, 15, 15, 15, 15, 15),
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// TODO(benvanik): optimize for the rotation case:
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// _mm_set_epi8( 8, 7, 6, 5, 4, 3, 2, 1, 0, 15, 15, 15, 15, 15, 15, 15),
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// vsldoi128 vr63,vr63,vr63,4
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// _mm_set_epi8( 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15, 15, 15, 15, 15, 15),
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// (ABCD ABCD) << 4b = (BCDA)
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// _mm_set_epi8(10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15, 15, 15, 15, 15),
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// (VA << SH) OR (VB >> (16 - SH))
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// _mm_set_epi8(11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15, 15, 15, 15),
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Value* control = f.LoadConstant(*((vec128_t*)(__vsldoi_table[sh])));
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// _mm_set_epi8(12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15, 15, 15),
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Value* v = f.Permute(
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// _mm_set_epi8(13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15, 15),
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control,
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// _mm_set_epi8(14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15),
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f.LoadVR(va),
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// };
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f.LoadVR(vb), INT8_TYPE);
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// int InstrEmit_vsldoi_(PPCFunctionBuilder& f, uint32_t vd, uint32_t va, uint32_t vb, uint32_t sh) {
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f.StoreVR(vd, v);
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// // (VD) <- ((VA) || (VB)) << (SH << 3)
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return 0;
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// if (!sh) {
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}
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// // No shift?
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XEEMITTER(vsldoi, 0x1000002C, VXA )(PPCFunctionBuilder& f, InstrData& i) {
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// f.StoreVR(vd, f.LoadVR(va));
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return InstrEmit_vsldoi_(f, i.VXA.VD, i.VXA.VA, i.VXA.VB, i.VXA.VC & 0xF);
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// e.TraceVR(vd, va, vb);
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}
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// return 0;
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XEEMITTER(vsldoi128, VX128_5(4, 16), VX128_5)(PPCFunctionBuilder& f, InstrData& i) {
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// } else if (sh == 16) {
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return InstrEmit_vsldoi_(f, VX128_5_VD128, VX128_5_VA128, VX128_5_VB128, VX128_5_SH);
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// f.StoreVR(vd, f.LoadVR(vb));
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}
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// e.TraceVR(vd, va, vb);
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// return 0;
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// }
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// // TODO(benvanik): optimize for the rotation case:
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// // vsldoi128 vr63,vr63,vr63,4
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// // (ABCD ABCD) << 4b = (BCDA)
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// // TODO(benvanik): rewrite this piece of shit.
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// XmmVar v(c.newXmmVar());
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// c.movaps(v, f.LoadVR(va));
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// XmmVar v_r(c.newXmmVar());
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// c.movaps(v_r, f.LoadVR(vb));
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// // (VA << SH) OR (VB >> (16 - SH))
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// GpVar gt(c.newGpVar());
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// c.xor_(gt, gt);
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// c.pinsrb(v, gt.r8(), imm(0));
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// c.pinsrb(v_r, gt.r8(), imm(15));
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// c.mov(gt, imm((sysint_t)&__shift_table_out[sh]));
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// XmmVar shuf(c.newXmmVar());
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// c.movaps(shuf, xmmword_ptr(gt));
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// c.pshufb(v, shuf);
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// c.mov(gt, imm((sysint_t)&__shift_table_in[sh]));
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// c.movaps(shuf, xmmword_ptr(gt));
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// c.pshufb(v_r, shuf);
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// c.por(v, v_r);
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// f.StoreVR(vd, v);
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// e.TraceVR(vd, va, vb);
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// return 0;
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// }
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// XEEMITTER(vsldoi, 0x1000002C, VXA )(PPCFunctionBuilder& f, InstrData& i) {
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// return InstrEmit_vsldoi_(f, i.VXA.VD, i.VXA.VA, i.VXA.VB, i.VXA.VC & 0xF);
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// }
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// XEEMITTER(vsldoi128, VX128_5(4, 16), VX128_5)(PPCFunctionBuilder& f, InstrData& i) {
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// return InstrEmit_vsldoi_(f, VX128_5_VD128, VX128_5_VA128, VX128_5_VB128, VX128_5_SH);
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// }
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XEEMITTER(vslo, 0x1000040C, VX )(PPCFunctionBuilder& f, InstrData& i) {
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XEEMITTER(vslo, 0x1000040C, VX )(PPCFunctionBuilder& f, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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XEINSTRNOTIMPLEMENTED();
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@ -1637,45 +1603,27 @@ XEEMITTER(vupkd3d128, VX128_3(6, 2032), VX128_3)(PPCFunctionBuilder& f, Inst
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switch (type) {
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switch (type) {
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case 0: // VPACK_D3DCOLOR
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case 0: // VPACK_D3DCOLOR
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{
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{
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XEASSERTALWAYS();
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return 1;
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// http://hlssmod.net/he_code/public/pixelwriter.h
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// http://hlssmod.net/he_code/public/pixelwriter.h
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// ARGB (WXYZ) -> RGBA (XYZW)
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// ARGB (WXYZ) -> RGBA (XYZW)
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// zzzzZZZZzzzzARGB
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// zzzzZZZZzzzzARGB
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//c.movaps(vt, f.LoadVR(vb));
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v = f.LoadVR(vb);
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//// zzzzZZZZzzzzARGB
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// 0zzzZZZZzzzzARGB
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//// 000R000G000B000A
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v = f.Insert(v, 0, f.LoadConstant((int8_t)0));
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//c.mov(gt, imm(
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// 000R000G000B000A
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// ((1ull << 7) << 56) |
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vec128_t shuf_v = { 0 };
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// ((1ull << 7) << 48) |
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shuf_v.b16[3] = 13;
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// ((1ull << 7) << 40) |
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shuf_v.b16[7] = 14;
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// ((0ull) << 32) | // B
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shuf_v.b16[11] = 15;
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// ((1ull << 7) << 24) |
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shuf_v.b16[15] = 12;
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// ((1ull << 7) << 16) |
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Value* shuf = f.LoadConstant(shuf_v);
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// ((1ull << 7) << 8) |
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v = f.Permute(shuf, v, v, INT8_TYPE);
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// ((3ull) << 0)) // A
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// {256*R.0, 256*G.0, 256*B.0, 256*A.0}
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// ); // lo
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v = f.VectorConvertI2F(v);
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//c.movq(v, gt);
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// {R.0, G.0, B.0 A.0}
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//c.mov(gt, imm(
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// 1/256 = 0.00390625 = 0x3B800000
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// ((1ull << 7) << 56) |
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v = f.Mul(
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// ((1ull << 7) << 48) |
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v,
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// ((1ull << 7) << 40) |
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f.Splat(f.LoadConstant((uint32_t)0x3B800000), VEC128_TYPE));
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// ((2ull) << 32) | // R
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// ((1ull << 7) << 24) |
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// ((1ull << 7) << 16) |
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// ((1ull << 7) << 8) |
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// ((1ull) << 0)) // G
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// ); // hi
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//c.pinsrq(v, gt, imm(1));
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//c.pshufb(vt, v);
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//// {256*R.0, 256*G.0, 256*B.0, 256*A.0}
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//c.cvtdq2ps(v, vt);
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//// {R.0, G.0, B.0 A.0}
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//// 1/256 = 0.00390625 = 0x3B800000
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//c.mov(gt, imm(0x3B800000));
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//c.movd(vt, gt.r32());
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//c.shufps(vt, vt, imm(0));
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//c.mulps(v, vt);
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}
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}
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break;
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break;
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case 1: // VPACK_NORMSHORT2
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case 1: // VPACK_NORMSHORT2
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@ -1955,8 +1903,8 @@ void RegisterEmitCategoryAltivec() {
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XEREGISTERINSTR(vslo128, VX128(5, 912));
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XEREGISTERINSTR(vslo128, VX128(5, 912));
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XEREGISTERINSTR(vslw, 0x10000184);
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XEREGISTERINSTR(vslw, 0x10000184);
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XEREGISTERINSTR(vslw128, VX128(6, 208));
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XEREGISTERINSTR(vslw128, VX128(6, 208));
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// XEREGISTERINSTR(vsldoi, 0x1000002C);
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XEREGISTERINSTR(vsldoi, 0x1000002C);
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// XEREGISTERINSTR(vsldoi128, VX128_5(4, 16));
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XEREGISTERINSTR(vsldoi128, VX128_5(4, 16));
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XEREGISTERINSTR(vspltb, 0x1000020C);
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XEREGISTERINSTR(vspltb, 0x1000020C);
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XEREGISTERINSTR(vsplth, 0x1000024C);
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XEREGISTERINSTR(vsplth, 0x1000024C);
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XEREGISTERINSTR(vspltw, 0x1000028C);
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XEREGISTERINSTR(vspltw, 0x1000028C);
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@ -1159,65 +1159,34 @@ XEEMITTER(sradix, 0x7C000674, XS )(PPCFunctionBuilder& f, InstrData& i) {
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return 0;
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return 0;
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}
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}
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// XEEMITTER(srawx, 0x7C000630, X )(PPCFunctionBuilder& f, InstrData& i) {
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XEEMITTER(srawx, 0x7C000630, X )(PPCFunctionBuilder& f, InstrData& i) {
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// // n <- rB[59-63]
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// n <- rB[59-63]
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// // r <- ROTL32((RS)[32:63], 64-n)
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// r <- ROTL32((RS)[32:63], 64-n)
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// // m <- MASK(n+32, 63)
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// m <- MASK(n+32, 63)
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// // s <- (RS)[32]
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// s <- (RS)[32]
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// // RA <- r&m | (i64.s)&¬m
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// RA <- r&m | (i64.s)&¬m
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// // CA <- s & ((r&¬m)[32:63]≠0)
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// CA <- s & ((r&¬m)[32:63]≠0)
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// if n == 0: rA <- sign_extend(rS), XER[CA] = 0
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// // if n == 0: rA <- sign_extend(rS), XER[CA] = 0
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// if n >= 32: rA <- 64 sign bits of rS, XER[CA] = sign bit of lo_32(rS)
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// // if n >= 32: rA <- 64 sign bits of rS, XER[CA] = sign bit of lo_32(rS)
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Value* v = f.Truncate(f.LoadGPR(i.X.RT), INT32_TYPE);
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Value* sh = f.And(
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// GpVar v(c.newGpVar());
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f.Truncate(f.LoadGPR(i.X.RB), INT32_TYPE),
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// c.mov(v, f.LoadGPR(i.X.RT));
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f.LoadConstant((int8_t)0x7F));
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// GpVar sh(c.newGpVar());
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// CA is set if any bits are shifted out of the right and if the result
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// c.mov(sh, f.LoadGPR(i.X.RB));
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// is negative.
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// c.and_(sh, imm(0x7F));
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Value* mask = f.Not(f.Shl(f.LoadConstant(-1), sh));
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Value* ca = f.And(
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// GpVar ca(c.newGpVar());
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f.Shr(v, 31),
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// Label skip(c.newLabel());
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f.IsTrue(f.And(v, mask)));
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// Label full(c.newLabel());
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f.StoreCA(ca);
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// c.test(sh, sh);
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v = f.Sha(v, sh),
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// c.jnz(full);
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v = f.SignExtend(v, INT64_TYPE);
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// {
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f.StoreGPR(i.X.RA, v);
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// // No shift, just a fancy sign extend and CA clearer.
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if (i.X.Rc) {
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// c.cdqe(v);
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f.UpdateCR(0, v);
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// c.mov(ca, imm(0));
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}
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// }
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return 0;
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// c.jmp(skip);
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}
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// c.bind(full);
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// {
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// // CA is set if any bits are shifted out of the right and if the result
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// // is negative. Start tracking that here.
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// c.mov(ca, v);
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// c.and_(ca, imm(~XEMASK(32 + i.X.RB, 64)));
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// c.cmp(ca, imm(0));
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// c.xor_(ca, ca);
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// c.setnz(ca.r8());
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// // Shift right and sign extend the 32bit part.
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// c.sar(v.r32(), imm(i.X.RB));
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// c.cdqe(v);
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// // CA is set to 1 if the low-order 32 bits of (RS) contain a negative number
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// // and any 1-bits are shifted out of position 63; otherwise CA is set to 0.
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// // We already have ca set to indicate the shift bits, now just and in sign.
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// GpVar ca_2(c.newGpVar());
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// c.mov(ca_2, v.r32());
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// c.shr(ca_2, imm(31));
|
|
||||||
// c.and_(ca, ca_2);
|
|
||||||
// }
|
|
||||||
// c.bind(skip);
|
|
||||||
|
|
||||||
// f.StoreGPR(i.X.RA, v);
|
|
||||||
// e.update_xer_with_carry(ca);
|
|
||||||
// if (i.X.Rc) {
|
|
||||||
// f.UpdateCR(0, v);
|
|
||||||
// }
|
|
||||||
// return 0;
|
|
||||||
// }
|
|
||||||
|
|
||||||
XEEMITTER(srawix, 0x7C000670, X )(PPCFunctionBuilder& f, InstrData& i) {
|
XEEMITTER(srawix, 0x7C000670, X )(PPCFunctionBuilder& f, InstrData& i) {
|
||||||
// n <- SH
|
// n <- SH
|
||||||
|
|
@ -1226,10 +1195,8 @@ XEEMITTER(srawix, 0x7C000670, X )(PPCFunctionBuilder& f, InstrData& i) {
|
||||||
// s <- (RS)[32]
|
// s <- (RS)[32]
|
||||||
// RA <- r&m | (i64.s)&¬m
|
// RA <- r&m | (i64.s)&¬m
|
||||||
// CA <- s & ((r&¬m)[32:63]≠0)
|
// CA <- s & ((r&¬m)[32:63]≠0)
|
||||||
|
|
||||||
// if n == 0: rA <- sign_extend(rS), XER[CA] = 0
|
// if n == 0: rA <- sign_extend(rS), XER[CA] = 0
|
||||||
// if n >= 32: rA <- 64 sign bits of rS, XER[CA] = sign bit of lo_32(rS)
|
// if n >= 32: rA <- 64 sign bits of rS, XER[CA] = sign bit of lo_32(rS)
|
||||||
|
|
||||||
Value* v = f.Truncate(f.LoadGPR(i.X.RT), INT32_TYPE);
|
Value* v = f.Truncate(f.LoadGPR(i.X.RT), INT32_TYPE);
|
||||||
Value* ca;
|
Value* ca;
|
||||||
if (!i.X.RB) {
|
if (!i.X.RB) {
|
||||||
|
|
@ -1323,7 +1290,7 @@ void RegisterEmitCategoryALU() {
|
||||||
XEREGISTERINSTR(srwx, 0x7C000430);
|
XEREGISTERINSTR(srwx, 0x7C000430);
|
||||||
// XEREGISTERINSTR(sradx, 0x7C000634);
|
// XEREGISTERINSTR(sradx, 0x7C000634);
|
||||||
XEREGISTERINSTR(sradix, 0x7C000674);
|
XEREGISTERINSTR(sradix, 0x7C000674);
|
||||||
// XEREGISTERINSTR(srawx, 0x7C000630);
|
XEREGISTERINSTR(srawx, 0x7C000630);
|
||||||
XEREGISTERINSTR(srawix, 0x7C000670);
|
XEREGISTERINSTR(srawix, 0x7C000670);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue