diff --git a/src/alloy/frontend/ppc/test/bin/instr_eqv.bin b/src/alloy/frontend/ppc/test/bin/instr_eqv.bin
new file mode 100644
index 000000000..35b148a57
Binary files /dev/null and b/src/alloy/frontend/ppc/test/bin/instr_eqv.bin differ
diff --git a/src/alloy/frontend/ppc/test/bin/instr_eqv.dis b/src/alloy/frontend/ppc/test/bin/instr_eqv.dis
new file mode 100644
index 000000000..af9569cd1
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_eqv.dis
@@ -0,0 +1,29 @@
+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_eqv.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_eqv_1>:
+  100000:	7c 83 2a 38 	eqv     r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_eqv_2>:
+  100008:	7c 83 2a 38 	eqv     r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_eqv_3>:
+  100010:	7c 83 2a 38 	eqv     r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_eqv_4>:
+  100018:	7c 83 2a 38 	eqv     r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_eqv_5>:
+  100020:	7c 83 2a 38 	eqv     r3,r4,r5
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_eqv_6>:
+  100028:	7c 83 2a 38 	eqv     r3,r4,r5
+  10002c:	4e 80 00 20 	blr
diff --git a/src/alloy/frontend/ppc/test/bin/instr_eqv.map b/src/alloy/frontend/ppc/test/bin/instr_eqv.map
new file mode 100644
index 000000000..5b234eaec
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_eqv.map
@@ -0,0 +1,6 @@
+0000000000000000 t test_eqv_1
+0000000000000008 t test_eqv_2
+0000000000000010 t test_eqv_3
+0000000000000018 t test_eqv_4
+0000000000000020 t test_eqv_5
+0000000000000028 t test_eqv_6
diff --git a/src/alloy/frontend/ppc/test/instr_eqv.s b/src/alloy/frontend/ppc/test/instr_eqv.s
new file mode 100644
index 000000000..c21e1a1b4
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/instr_eqv.s
@@ -0,0 +1,53 @@
+test_eqv_1:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 1
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 1
+
+test_eqv_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+
+test_eqv_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_eqv_4:
+  #_ REGISTER_IN r4 0xDEADBEEFDEADBEEF
+  #_ REGISTER_IN r5 0xDEADBEEFDEADBEEF
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
+  #_ REGISTER_OUT r5 0xDEADBEEFDEADBEEF
+
+test_eqv_5:
+  #_ REGISTER_IN r4 0xDEADBEEFDEADBEEF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xDEADBEEFDEADBEEF
+  #_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_eqv_6:
+  #_ REGISTER_IN r4 0xDEADBEEFDEADBEEF
+  #_ REGISTER_IN r5 0
+  eqv r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x2152411021524110
+  #_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
+  #_ REGISTER_OUT r5 0