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Constant tests for add, addc, adde.

This commit is contained in:
gibbed 2015-05-13 00:21:43 -05:00
parent f96dda4983
commit dc1b1ca638
3 changed files with 206 additions and 0 deletions
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24
src/xenia/cpu/frontend/test/instr_add.s
View File

@ -9,6 +9,18 @@ test_add_1:
#_ REGISTER_OUT r25 0x0000FFFF #_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0010FFFF #_ REGISTER_OUT r11 0x0010FFFF
test_add_1_constant:
lis r5, 0x10
li r25, -1
clrldi r25, r25, 48
add r11, r5, r25
blr
#_ REGISTER_OUT r5 0x00100000
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0010FFFF
test_add_2: test_add_2:
#_ REGISTER_IN r0 0x00100000 #_ REGISTER_IN r0 0x00100000
#_ REGISTER_IN r25 0x0000FFFF #_ REGISTER_IN r25 0x0000FFFF
@ -19,3 +31,15 @@ test_add_2:
#_ REGISTER_OUT r0 0x00100000 #_ REGISTER_OUT r0 0x00100000
#_ REGISTER_OUT r25 0x0000FFFF #_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0010FFFF #_ REGISTER_OUT r11 0x0010FFFF
test_add_2_constant:
lis r0, 0x10
li r25, -1
clrldi r25, r25, 48
add r11, r0, r25
blr
#_ REGISTER_OUT r0 0x00100000
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0010FFFF

57
src/xenia/cpu/frontend/test/instr_addc.s
View File

@ -1,3 +1,5 @@
# constant tests are commented since add_carry isn't supported
test_addc_1: test_addc_1:
#_ REGISTER_IN r4 1 #_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2 #_ REGISTER_IN r5 2
@ -9,6 +11,17 @@ test_addc_1:
#_ REGISTER_OUT r5 2 #_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0 #_ REGISTER_OUT r6 0
#test_addc_1_constant:
# li r4, 1
# li r5, 2
# addc r3, r4, r5
# adde r6, r0, r0
# blr
# #_ REGISTER_OUT r3 3
# #_ REGISTER_OUT r4 1
# #_ REGISTER_OUT r5 2
# #_ REGISTER_OUT r6 0
test_addc_2: test_addc_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0 #_ REGISTER_IN r5 0
@ -20,6 +33,17 @@ test_addc_2:
#_ REGISTER_OUT r5 0 #_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0 #_ REGISTER_OUT r6 0
#test_addc_2_constant:
# li r4, -1
# li r5, 0
# addc r3, r4, r5
# adde r6, r0, r0
# blr
# #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
# #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
# #_ REGISTER_OUT r5 0
# #_ REGISTER_OUT r6 0
test_addc_3: test_addc_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1 #_ REGISTER_IN r5 1
@ -31,6 +55,17 @@ test_addc_3:
#_ REGISTER_OUT r5 1 #_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1 #_ REGISTER_OUT r6 1
#test_addc_3_constant:
# li r4, -1
# li r5, 1
# addc r3, r4, r5
# adde r6, r0, r0
# blr
# #_ REGISTER_OUT r3 0
# #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
# #_ REGISTER_OUT r5 1
# #_ REGISTER_OUT r6 1
test_addc_4: test_addc_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 123 #_ REGISTER_IN r5 123
@ -42,6 +77,17 @@ test_addc_4:
#_ REGISTER_OUT r5 123 #_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1 #_ REGISTER_OUT r6 1
#test_addc_4_constant:
# li r4, -1
# li r5, 123
# addc r3, r4, r5
# adde r6, r0, r0
# blr
# #_ REGISTER_OUT r3 0x000000000000007A
# #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
# #_ REGISTER_OUT r5 123
# #_ REGISTER_OUT r6 1
test_addc_5: test_addc_5:
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
@ -52,3 +98,14 @@ test_addc_5:
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1 #_ REGISTER_OUT r6 1
#test_addc_5_constant:
# li r4, -1
# sldi r5, r4, 1
# addc r3, r4, r5
# adde r6, r0, r0
# blr
# #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
# #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
# #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
# #_ REGISTER_OUT r6 1

125
src/xenia/cpu/frontend/test/instr_adde.s
View File

@ -9,6 +9,17 @@ test_adde_1:
#_ REGISTER_OUT r5 2 #_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0 #_ REGISTER_OUT r6 0
test_adde_1_constant:
li r4, 1
li r5, 2
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 3
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
test_adde_2: test_adde_2:
#_ REGISTER_IN r4 1 #_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2 #_ REGISTER_IN r5 2
@ -23,6 +34,20 @@ test_adde_2:
#_ REGISTER_OUT r5 2 #_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0 #_ REGISTER_OUT r6 0
test_adde_2_constant:
li r4, 1
li r5, 2
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 4
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
test_adde_3: test_adde_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0 #_ REGISTER_IN r5 0
@ -34,6 +59,17 @@ test_adde_3:
#_ REGISTER_OUT r5 0 #_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0 #_ REGISTER_OUT r6 0
test_adde_3_constant:
li r4, -1
li r5, 0
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_adde_4: test_adde_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0 #_ REGISTER_IN r5 0
@ -48,6 +84,20 @@ test_adde_4:
#_ REGISTER_OUT r5 0 #_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 1 #_ REGISTER_OUT r6 1
test_adde_4_constant:
li r4, -1
li r5, 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 1
test_adde_5: test_adde_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1 #_ REGISTER_IN r5 1
@ -59,6 +109,17 @@ test_adde_5:
#_ REGISTER_OUT r5 1 #_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1 #_ REGISTER_OUT r6 1
test_adde_5_constant:
li r4, -1
li r5, 1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_adde_6: test_adde_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1 #_ REGISTER_IN r5 1
@ -73,6 +134,20 @@ test_adde_6:
#_ REGISTER_OUT r5 1 #_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1 #_ REGISTER_OUT r6 1
test_adde_6_constant:
li r4, -1
li r5, 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_adde_7: test_adde_7:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 123 #_ REGISTER_IN r5 123
@ -84,6 +159,17 @@ test_adde_7:
#_ REGISTER_OUT r5 123 #_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1 #_ REGISTER_OUT r6 1
test_adde_7_constant:
li r4, -1
li r5, 123
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x000000000000007A
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1
test_adde_8: test_adde_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 123 #_ REGISTER_IN r5 123
@ -98,6 +184,20 @@ test_adde_8:
#_ REGISTER_OUT r5 123 #_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1 #_ REGISTER_OUT r6 1
test_adde_8_constant:
li r4, -1
li r5, 123
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x000000000000007B
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1
test_adde_9: test_adde_9:
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
@ -109,6 +209,17 @@ test_adde_9:
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1 #_ REGISTER_OUT r6 1
test_adde_9_constant:
li r5, -1
sldi r4, r5, 1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_adde_10: test_adde_10:
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
@ -122,3 +233,17 @@ test_adde_10:
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1 #_ REGISTER_OUT r6 1
test_adde_10_constant:
li r5, -1
sldi r4, r5, 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1