From d8a1c5ce79039c4c9612c3947c55ffea32b12404 Mon Sep 17 00:00:00 2001
From: Ben Vanik <ben.vanik@gmail.com>
Date: Sat, 25 Oct 2014 19:28:06 -0700
Subject: [PATCH] Fixing lvr.

---
 src/alloy/frontend/ppc/ppc_emit_altivec.cc    |   5 ++---
 src/alloy/frontend/ppc/test/bin/instr_lvr.bin | Bin 0 -> 8 bytes
 src/alloy/frontend/ppc/test/bin/instr_lvr.dis |   9 +++++++++
 src/alloy/frontend/ppc/test/bin/instr_lvr.map |   1 +
 src/alloy/frontend/ppc/test/instr_lvr.s       |   9 +++++++++
 5 files changed, 21 insertions(+), 3 deletions(-)
 create mode 100644 src/alloy/frontend/ppc/test/bin/instr_lvr.bin
 create mode 100644 src/alloy/frontend/ppc/test/bin/instr_lvr.dis
 create mode 100644 src/alloy/frontend/ppc/test/bin/instr_lvr.map
 create mode 100644 src/alloy/frontend/ppc/test/instr_lvr.s

diff --git a/src/alloy/frontend/ppc/ppc_emit_altivec.cc b/src/alloy/frontend/ppc/ppc_emit_altivec.cc
index e5de7e4cf..7bc00959e 100644
--- a/src/alloy/frontend/ppc/ppc_emit_altivec.cc
+++ b/src/alloy/frontend/ppc/ppc_emit_altivec.cc
@@ -241,9 +241,8 @@ int InstrEmit_lvrx_(PPCHIRBuilder& f, InstrData& i, uint32_t vd, uint32_t ra,
   // ea &= ~0xF
   ea = f.And(ea, f.LoadConstant(~0xFull));
   // v = (new >> (16 - eb))
-  Value* v = f.Permute(f.LoadVectorShr(f.Sub(f.LoadConstant((int8_t)16), eb)),
-                       f.ByteSwap(f.Load(ea, VEC128_TYPE)),
-                       f.LoadZero(VEC128_TYPE), INT8_TYPE);
+  Value* v = f.Permute(f.LoadVectorShl(eb), f.LoadZero(VEC128_TYPE),
+                       f.ByteSwap(f.Load(ea, VEC128_TYPE)), INT8_TYPE);
   f.StoreVR(vd, v);
   return 0;
 }
diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvr.bin b/src/alloy/frontend/ppc/test/bin/instr_lvr.bin
new file mode 100644
index 0000000000000000000000000000000000000000..a8e07544ebb6f5faf1ef689b6d842c47b59e6a20
GIT binary patch
literal 8
Pcmb<P(ed+ZU{C-63<?5C

literal 0
HcmV?d00001

diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvr.dis b/src/alloy/frontend/ppc/test/bin/instr_lvr.dis
new file mode 100644
index 000000000..41b6065df
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_lvr.dis
@@ -0,0 +1,9 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_lvr.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_lvr_1>:
+  100000:	7c 64 2c 4e 	lvrx    v3,r4,r5
+  100004:	4e 80 00 20 	blr
diff --git a/src/alloy/frontend/ppc/test/bin/instr_lvr.map b/src/alloy/frontend/ppc/test/bin/instr_lvr.map
new file mode 100644
index 000000000..770c292eb
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_lvr.map
@@ -0,0 +1 @@
+0000000000000000 t test_lvr_1
diff --git a/src/alloy/frontend/ppc/test/instr_lvr.s b/src/alloy/frontend/ppc/test/instr_lvr.s
new file mode 100644
index 000000000..4c6e9f942
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/instr_lvr.s
@@ -0,0 +1,9 @@
+test_lvr_1:
+  #_ MEMORY_IN 000010B0 090A0A0B 0C0F120A 0B0C0D0E 0F10130C 0D0E1011 121314FF FFFFFFFF
+  #_ REGISTER_IN r4 0x10B7
+  #_ REGISTER_IN r5 0x10
+  lvrx v3, r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x10B7
+  #_ REGISTER_OUT r5 0x10
+  #_ REGISTER_OUT v3 [00000000, 00000000, 000D0E10, 11121314]