ShuriZma
/
xenia-canary
mirror of https://github.com/xenia-canary/xenia-canary.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Marking some memory instructions as kM.

This commit is contained in:
Ben Vanik 2015-12-29 17:53:49 -08:00
parent 077f73449d
commit d7eff7c9e3
3 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/xenia/cpu/ppc/ppc_opcode_disasm.cc
View File

@ -4998,11 +4998,11 @@ PPCOpcodeDisasmInfo ppc_opcode_disasm_table[] = {
INSTRUCTION(0x4c000382, "cror" , kXL , kC, kGeneral, "Condition Register OR" , (PPCOpcodeField::kCRBA,PPCOpcodeField::kCRBB), (PPCOpcodeField::kCRBD), PrintDisasm_cror), INSTRUCTION(0x4c000382, "cror" , kXL , kC, kGeneral, "Condition Register OR" , (PPCOpcodeField::kCRBA,PPCOpcodeField::kCRBB), (PPCOpcodeField::kCRBD), PrintDisasm_cror),
INSTRUCTION(0x4c000342, "crorc" , kXL , kC, kGeneral, "Condition Register OR with Complement" , (PPCOpcodeField::kCRBA,PPCOpcodeField::kCRBB), (PPCOpcodeField::kCRBD), PrintDisasm_crorc), INSTRUCTION(0x4c000342, "crorc" , kXL , kC, kGeneral, "Condition Register OR with Complement" , (PPCOpcodeField::kCRBA,PPCOpcodeField::kCRBB), (PPCOpcodeField::kCRBD), PrintDisasm_crorc),
INSTRUCTION(0x4c000182, "crxor" , kXL , kC, kGeneral, "Condition Register XOR" , (PPCOpcodeField::kCRBA,PPCOpcodeField::kCRBB), (PPCOpcodeField::kCRBD), PrintDisasm_crxor), INSTRUCTION(0x4c000182, "crxor" , kXL , kC, kGeneral, "Condition Register XOR" , (PPCOpcodeField::kCRBA,PPCOpcodeField::kCRBB), (PPCOpcodeField::kCRBD), PrintDisasm_crxor),
INSTRUCTION(0x7c0000ac, "dcbf" , kX , kI, kGeneral, "Data Cache Block Flush" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbf), INSTRUCTION(0x7c0000ac, "dcbf" , kX , kM, kGeneral, "Data Cache Block Flush" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbf),
INSTRUCTION(0x7c0003ac, "dcbi" , kX , kI, kGeneral, "Data Cache Block Invalidate" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbi), INSTRUCTION(0x7c0003ac, "dcbi" , kX , kM, kGeneral, "Data Cache Block Invalidate" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbi),
INSTRUCTION(0x7c00006c, "dcbst" , kX , kI, kGeneral, "Data Cache Block Store" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbst), INSTRUCTION(0x7c00006c, "dcbst" , kX , kM, kGeneral, "Data Cache Block Store" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbst),
INSTRUCTION(0x7c00022c, "dcbt" , kX , kI, kGeneral, "Data Cache Block Touch" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbt), INSTRUCTION(0x7c00022c, "dcbt" , kX , kM, kGeneral, "Data Cache Block Touch" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbt),
INSTRUCTION(0x7c0001ec, "dcbtst" , kX , kI, kGeneral, "Data Cache Block Touch for Store" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbtst), INSTRUCTION(0x7c0001ec, "dcbtst" , kX , kM, kGeneral, "Data Cache Block Touch for Store" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbtst),
INSTRUCTION(0x7c0007ec, "dcbz" , kDCBZ , kM, kGeneral, "Data Cache Block Clear to Zero" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbz), INSTRUCTION(0x7c0007ec, "dcbz" , kDCBZ , kM, kGeneral, "Data Cache Block Clear to Zero" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbz),
INSTRUCTION(0x7c2007ec, "dcbz128" , kDCBZ , kM, kGeneral, "Data Cache Block Clear to Zero 128" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbz128), INSTRUCTION(0x7c2007ec, "dcbz128" , kDCBZ , kM, kGeneral, "Data Cache Block Clear to Zero 128" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbz128),
INSTRUCTION(0x7c000392, "divdux" , kXO , kI, kGeneral, "Divide Doubleword Unsigned" , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kOEcond,PPCOpcodeField::kCRcond), PrintDisasm_divdux), INSTRUCTION(0x7c000392, "divdux" , kXO , kI, kGeneral, "Divide Doubleword Unsigned" , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kOEcond,PPCOpcodeField::kCRcond), PrintDisasm_divdux),
@ -5047,7 +5047,7 @@ PPCOpcodeDisasmInfo ppc_opcode_disasm_table[] = {
INSTRUCTION(0xfc00002c, "fsqrtx" , kA , kF, kGeneral, "Floating Square Root" , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fsqrtx), INSTRUCTION(0xfc00002c, "fsqrtx" , kA , kF, kGeneral, "Floating Square Root" , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fsqrtx),
INSTRUCTION(0xec000028, "fsubsx" , kA , kF, kGeneral, "Floating Subtract Single" , (PPCOpcodeField::kFA,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fsubsx), INSTRUCTION(0xec000028, "fsubsx" , kA , kF, kGeneral, "Floating Subtract Single" , (PPCOpcodeField::kFA,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fsubsx),
INSTRUCTION(0xfc000028, "fsubx" , kA , kF, kGeneral, "Floating Subtract" , (PPCOpcodeField::kFA,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fsubx), INSTRUCTION(0xfc000028, "fsubx" , kA , kF, kGeneral, "Floating Subtract" , (PPCOpcodeField::kFA,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fsubx),
INSTRUCTION(0x7c0007ac, "icbi" , kX , kI, kGeneral, "Instruction Cache Block Invalidate" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_icbi), INSTRUCTION(0x7c0007ac, "icbi" , kX , kM, kGeneral, "Instruction Cache Block Invalidate" , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_icbi),
INSTRUCTION(0x4c00012c, "isync" , kXL , kI, kGeneral, "Instruction Synchronize" , (), (), PrintDisasm_isync), INSTRUCTION(0x4c00012c, "isync" , kXL , kI, kGeneral, "Instruction Synchronize" , (), (), PrintDisasm_isync),
INSTRUCTION(0x88000000, "lbz" , kD , kM, kGeneral, "Load Byte and Zero" , (PPCOpcodeField::kRA0,PPCOpcodeField::kd), (PPCOpcodeField::kRD), PrintDisasm_lbz), INSTRUCTION(0x88000000, "lbz" , kD , kM, kGeneral, "Load Byte and Zero" , (PPCOpcodeField::kRA0,PPCOpcodeField::kd), (PPCOpcodeField::kRD), PrintDisasm_lbz),
INSTRUCTION(0x8c000000, "lbzu" , kD , kM, kGeneral, "Load Byte and Zero with Update" , (PPCOpcodeField::kRA,PPCOpcodeField::kd), (PPCOpcodeField::kRD,PPCOpcodeField::kRA), PrintDisasm_lbzu), INSTRUCTION(0x8c000000, "lbzu" , kD , kM, kGeneral, "Load Byte and Zero with Update" , (PPCOpcodeField::kRA,PPCOpcodeField::kd), (PPCOpcodeField::kRD,PPCOpcodeField::kRA), PrintDisasm_lbzu),

12
src/xenia/cpu/ppc/ppc_opcode_table.cc
View File

@ -44,11 +44,11 @@ PPCOpcodeInfo ppc_opcode_table[] = {
INSTRUCTION(0x4c000382, "cror" , kXL , kC, kGeneral), INSTRUCTION(0x4c000382, "cror" , kXL , kC, kGeneral),
INSTRUCTION(0x4c000342, "crorc" , kXL , kC, kGeneral), INSTRUCTION(0x4c000342, "crorc" , kXL , kC, kGeneral),
INSTRUCTION(0x4c000182, "crxor" , kXL , kC, kGeneral), INSTRUCTION(0x4c000182, "crxor" , kXL , kC, kGeneral),
INSTRUCTION(0x7c0000ac, "dcbf" , kX , kI, kGeneral), INSTRUCTION(0x7c0000ac, "dcbf" , kX , kM, kGeneral),
INSTRUCTION(0x7c0003ac, "dcbi" , kX , kI, kGeneral), INSTRUCTION(0x7c0003ac, "dcbi" , kX , kM, kGeneral),
INSTRUCTION(0x7c00006c, "dcbst" , kX , kI, kGeneral), INSTRUCTION(0x7c00006c, "dcbst" , kX , kM, kGeneral),
INSTRUCTION(0x7c00022c, "dcbt" , kX , kI, kGeneral), INSTRUCTION(0x7c00022c, "dcbt" , kX , kM, kGeneral),
INSTRUCTION(0x7c0001ec, "dcbtst" , kX , kI, kGeneral), INSTRUCTION(0x7c0001ec, "dcbtst" , kX , kM, kGeneral),
INSTRUCTION(0x7c0007ec, "dcbz" , kDCBZ , kM, kGeneral), INSTRUCTION(0x7c0007ec, "dcbz" , kDCBZ , kM, kGeneral),
INSTRUCTION(0x7c2007ec, "dcbz128" , kDCBZ , kM, kGeneral), INSTRUCTION(0x7c2007ec, "dcbz128" , kDCBZ , kM, kGeneral),
INSTRUCTION(0x7c000392, "divdux" , kXO , kI, kGeneral), INSTRUCTION(0x7c000392, "divdux" , kXO , kI, kGeneral),
@ -93,7 +93,7 @@ PPCOpcodeInfo ppc_opcode_table[] = {
INSTRUCTION(0xfc00002c, "fsqrtx" , kA , kF, kGeneral), INSTRUCTION(0xfc00002c, "fsqrtx" , kA , kF, kGeneral),
INSTRUCTION(0xec000028, "fsubsx" , kA , kF, kGeneral), INSTRUCTION(0xec000028, "fsubsx" , kA , kF, kGeneral),
INSTRUCTION(0xfc000028, "fsubx" , kA , kF, kGeneral), INSTRUCTION(0xfc000028, "fsubx" , kA , kF, kGeneral),
INSTRUCTION(0x7c0007ac, "icbi" , kX , kI, kGeneral), INSTRUCTION(0x7c0007ac, "icbi" , kX , kM, kGeneral),
INSTRUCTION(0x4c00012c, "isync" , kXL , kI, kGeneral), INSTRUCTION(0x4c00012c, "isync" , kXL , kI, kGeneral),
INSTRUCTION(0x88000000, "lbz" , kD , kM, kGeneral), INSTRUCTION(0x88000000, "lbz" , kD , kM, kGeneral),
INSTRUCTION(0x8c000000, "lbzu" , kD , kM, kGeneral), INSTRUCTION(0x8c000000, "lbzu" , kD , kM, kGeneral),

12
tools/ppc-instructions.xml
View File

@ -229,27 +229,27 @@
<out field="CRBD" /> <out field="CRBD" />
<disasm>crxor [CRBD], [CRBA], [CRBB]</disasm> <disasm>crxor [CRBD], [CRBA], [CRBB]</disasm>
</insn> </insn>
<insn mnem="dcbf" opcode="7c0000ac" form="X" group="i" desc="Data Cache Block Flush"> <insn mnem="dcbf" opcode="7c0000ac" form="X" group="m" desc="Data Cache Block Flush">
<in field="RA0" /> <in field="RA0" />
<in field="RB" /> <in field="RB" />
<disasm>dcbf [RA0], [RB]</disasm> <disasm>dcbf [RA0], [RB]</disasm>
</insn> </insn>
<insn mnem="dcbi" opcode="7c0003ac" form="X" group="i" desc="Data Cache Block Invalidate"> <insn mnem="dcbi" opcode="7c0003ac" form="X" group="m" desc="Data Cache Block Invalidate">
<in field="RA0" /> <in field="RA0" />
<in field="RB" /> <in field="RB" />
<disasm>dcbi [RA0], [RB]</disasm> <disasm>dcbi [RA0], [RB]</disasm>
</insn> </insn>
<insn mnem="dcbst" opcode="7c00006c" form="X" group="i" desc="Data Cache Block Store"> <insn mnem="dcbst" opcode="7c00006c" form="X" group="m" desc="Data Cache Block Store">
<in field="RA0" /> <in field="RA0" />
<in field="RB" /> <in field="RB" />
<disasm>dcbst [RA0], [RB]</disasm> <disasm>dcbst [RA0], [RB]</disasm>
</insn> </insn>
<insn mnem="dcbt" opcode="7c00022c" form="X" group="i" desc="Data Cache Block Touch"> <insn mnem="dcbt" opcode="7c00022c" form="X" group="m" desc="Data Cache Block Touch">
<in field="RA0" /> <in field="RA0" />
<in field="RB" /> <in field="RB" />
<disasm>dcbt [RA0], [RB]</disasm> <disasm>dcbt [RA0], [RB]</disasm>
</insn> </insn>
<insn mnem="dcbtst" opcode="7c0001ec" form="X" group="i" desc="Data Cache Block Touch for Store"> <insn mnem="dcbtst" opcode="7c0001ec" form="X" group="m" desc="Data Cache Block Touch for Store">
<in field="RA0" /> <in field="RA0" />
<in field="RB" /> <in field="RB" />
<disasm>dcbtst [RA0], [RB]</disasm> <disasm>dcbtst [RA0], [RB]</disasm>
@ -576,7 +576,7 @@
<out field="FPSCR" /> <out field="FPSCR" />
<disasm>fsubs[Rc] [FD], [FA], [FB]</disasm> <disasm>fsubs[Rc] [FD], [FA], [FB]</disasm>
</insn> </insn>
<insn mnem="icbi" opcode="7c0007ac" form="X" group="i" desc="Instruction Cache Block Invalidate"> <insn mnem="icbi" opcode="7c0007ac" form="X" group="m" desc="Instruction Cache Block Invalidate">
<in field="RA0" /> <in field="RA0" />
<in field="RB" /> <in field="RB" />
<disasm>icbi [RA], [RB]</disasm> <disasm>icbi [RA], [RB]</disasm>