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Add a few more vector tests

This commit is contained in:
Dr. Chat 2016-06-12 21:45:51 -05:00
parent 0ef16b10e2
commit d5865740e2
8 changed files with 155 additions and 45 deletions
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34
src/xenia/cpu/ppc/testing/instr_lvexx.s
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@ -99,3 +99,37 @@ test_lvewx_2_constant:
blr
#_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx128_1:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x10001000
lvewx128 v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx128_1_constant:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
lis r4, 0x1000
ori r4, r4, 0x1000
lvewx128 v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx128_2:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x10001004
lvewx128 v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx128_2_constant:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
lis r4, 0x1000
ori r4, r4, 0x1004
lvewx128 v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]

8
src/xenia/cpu/ppc/testing/instr_stvl.s
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@ -1,4 +1,4 @@
test_stvl_1:
test_stvlx_1:
#_ MEMORY_IN 10001040 00000000 00000000 00000000 3F800000
#_ REGISTER_IN r4 0x10001040
#_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
@ -8,7 +8,7 @@ test_stvl_1:
#_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
#_ MEMORY_OUT 10001040 BE74FCBD BD912ABA BF317BBB BF2D135F
test_stvl_1_constant:
test_stvlx_1_constant:
#_ MEMORY_IN 10001040 00000000 00000000 00000000 3F800000
lis r4, 0x1000
ori r4, r4, 0x1040
@ -19,7 +19,7 @@ test_stvl_1_constant:
#_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
#_ MEMORY_OUT 10001040 BE74FCBD BD912ABA BF317BBB BF2D135F
test_stvl_2:
test_stvlx_2:
#_ MEMORY_IN 10001040 00010203 04050607 08090A0B 0C0D0E0F
#_ REGISTER_IN r4 0x10001044
#_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
@ -29,7 +29,7 @@ test_stvl_2:
#_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
#_ MEMORY_OUT 10001040 00010203 F0F1F2F3 F4F5F6F7 F8F9FAFB
test_stvl_2_constant:
test_stvlx_2_constant:
#_ MEMORY_IN 10001040 00010203 04050607 08090A0B 0C0D0E0F
lis r4, 0x1000
ori r4, r4, 0x1044

37
src/xenia/cpu/ppc/testing/instr_vcmpxxfp128.s
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@ -31,13 +31,38 @@ test_vcmpxxfp128_3:
#_ REGISTER_OUT v5 [3f800001, 3f800001, 3f800001, 3f800001]
#_ REGISTER_OUT r3 0x00000020
test_vcmpxxfp128_4:
#_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_IN v5 [3f800001, 3f800001, 3f800001, 3f800001]
vcmpgefp128. v3, v4, v5
test_vcmpbfp128_1:
# [5.0, 5.0, 5.0, 5.0]
#_ REGISTER_IN v4 [40A00000, 40A00000, 40A00000, 40A00000]
#_ REGISTER_IN v5 [40A00000, 40A00000, 40A00000, 40A00000]
vcmpbfp128. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v4 [40A00000, 40A00000, 40A00000, 40A00000]
#_ REGISTER_OUT v5 [40A00000, 40A00000, 40A00000, 40A00000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_OUT v5 [3f800001, 3f800001, 3f800001, 3f800001]
#_ REGISTER_OUT r3 0x00000020
test_vcmpbfp128_2:
# [-5.0, -5.0, -5.0, -5.0]
#_ REGISTER_IN v4 [C0A00000, C0A00000, C0A00000, C0A00000]
#_ REGISTER_IN v5 [40A00000, 40A00000, 40A00000, 40A00000]
vcmpbfp128. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v4 [C0A00000, C0A00000, C0A00000, C0A00000]
#_ REGISTER_OUT v5 [40A00000, 40A00000, 40A00000, 40A00000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT r3 0x00000020
test_vcmpbfp128_3:
# [7.0, -7.0, 5.0, 5.0]
#_ REGISTER_IN v4 [40E00000, C0E00000, 40A00000, 40A00000]
#_ REGISTER_IN v5 [40A00000, 40A00000, 40A00000, 40A00000]
vcmpbfp128. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v4 [40E00000, C0E00000, 40A00000, 40A00000]
#_ REGISTER_OUT v5 [40A00000, 40A00000, 40A00000, 40A00000]
#_ REGISTER_OUT v3 [80000000, 40000000, 00000000, 00000000]
#_ REGISTER_OUT r3 0x00000000

12
src/xenia/cpu/ppc/testing/instr_vperm.s
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@ -42,3 +42,15 @@ test_vperm_4:
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [21212121, 21212121, 21212121, 21212121]
#_ REGISTER_OUT v6 [01010101, 01010101, 01010101, 01010101]
test_vperm_5:
#_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v5 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v6 [01020003, 14150001, 1F1C1D1E, 00141518]
vperm v3, v4, v5, v6
blr
#_ REGISTER_OUT v3 [01020003, 14150001, 1F1C1D1E, 00141518]
#_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v5 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v6 [01020003, 14150001, 1F1C1D1E, 00141518]

67
src/xenia/cpu/ppc/testing/instr_vpkuwum128.s
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@ -1,36 +1,35 @@
#vpkuwum128 isn't implemented yet
#test_vpkuwum128_1:
# # {0, 1, 2, 3}
# #_ REGISTER_IN v3 [00000000, 00000001, 00000002, 00000003]
# # {4, 5, 6, 7}
# #_ REGISTER_IN v4 [00000004, 00000005, 00000006, 00000007]
# vpkuwum128 v5, v3, v4
# blr
# #_ REGISTER_OUT v3 [00000000, 00000001, 00000002, 00000003]
# #_ REGISTER_OUT v4 [00000004, 00000005, 00000006, 00000007]
# # {0, 1, 2, 3, 4, 5, 6, 7}
# #_ REGISTER_OUT v5 [00000001, 00020003, 00040005, 00060007]
test_vpkuwum128_1:
# {0, 1, 2, 3}
#_ REGISTER_IN v3 [00000000, 00000001, 00000002, 00000003]
# {4, 5, 6, 7}
#_ REGISTER_IN v4 [00000004, 00000005, 00000006, 00000007]
vpkuwum128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000000, 00000001, 00000002, 00000003]
#_ REGISTER_OUT v4 [00000004, 00000005, 00000006, 00000007]
# {0, 1, 2, 3, 4, 5, 6, 7}
#_ REGISTER_OUT v5 [00000001, 00020003, 00040005, 00060007]
#test_vpkuwum128_2:
# # {-4, -3, -2, -1}
# #_ REGISTER_IN v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
# # {0, 1, 2, 3}
# #_ REGISTER_IN v4 [00000000, 00000001, 00000002, 00000003]
# vpkuwum128 v5, v3, v4
# blr
# #_ REGISTER_OUT v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
# #_ REGISTER_OUT v4 [00000000, 00000001, 00000002, 00000003]
# # {-4, -3, -2, -1, 0, 1, 2, 3}
# #_ REGISTER_OUT v5 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
test_vpkuwum128_2:
# {-4, -3, -2, -1}
#_ REGISTER_IN v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
# {0, 1, 2, 3}
#_ REGISTER_IN v4 [00000000, 00000001, 00000002, 00000003]
vpkuwum128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
#_ REGISTER_OUT v4 [00000000, 00000001, 00000002, 00000003]
# {-4, -3, -2, -1, 0, 1, 2, 3}
#_ REGISTER_OUT v5 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#test_vpkuwum128_3:
# # {0, 4294967295, 4294967295, 4294967295}
# #_ REGISTER_IN v3 [00000000, FFFFFFFF, FFFFFFFF, FFFFFFFF]
# # {4294967295, 0, 0, 0}
# #_ REGISTER_IN v4 [FFFFFFFF, 00000000, 00000000, 00000000]
# vpkuwum128 v5, v3, v4
# blr
# #_ REGISTER_OUT v3 [00000000, FFFFFFFF, FFFFFFFF, FFFFFFFF]
# #_ REGISTER_OUT v4 [FFFFFFFF, 00000000, 00000000, 00000000]
# # {0, 65535, 65535, 65535, 65535, 0, 0, 0}
# #_ REGISTER_OUT v5 [0000FFFF, FFFFFFFF, FFFF0000, 00000000]
test_vpkuwum128_3:
# {0, 4294967295, 4294967295, 4294967295}
#_ REGISTER_IN v3 [00000000, FFFFFFFF, FFFFFFFF, FFFFFFFF]
# {4294967295, 0, 0, 0}
#_ REGISTER_IN v4 [FFFFFFFF, 00000000, 00000000, 00000000]
vpkuwum128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000000, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v4 [FFFFFFFF, 00000000, 00000000, 00000000]
# {0, 65535, 65535, 65535, 65535, 0, 0, 0}
#_ REGISTER_OUT v5 [0000FFFF, FFFFFFFF, FFFF0000, 00000000]

12
src/xenia/cpu/ppc/testing/instr_vpkuwus128.s
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@ -9,3 +9,15 @@ test_vpkuwus128_1:
#_ REGISTER_OUT v4 [00000002, 00010002, 00000003, 00010003]
# {0, 65535, 1, 65535, 2, 65535, 3, 65535}
#_ REGISTER_OUT v5 [0000FFFF, 0001FFFF, 0002FFFF, 0003FFFF]
test_vpkuwus128_2:
# {2147483648, 2147483647, 2, 3}
#_ REGISTER_IN v3 [80000000, 7FFFFFFF, 00000002, 00000003]
# {4294967295, 65538, 4294967294, 16}
#_ REGISTER_IN v4 [FFFFFFFF, 00010002, FFFFFFFE, 00000010]
vpkuwus128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [80000000, 7FFFFFFF, 00000002, 00000003]
#_ REGISTER_OUT v4 [FFFFFFFF, 00010002, FFFFFFFE, 00000010]
# {65535, 65535, 2, 3, 65535, 65535, 65535, 16}
#_ REGISTER_OUT v5 [FFFFFFFF, 00020003, FFFFFFFF, FFFF0010]

20
src/xenia/cpu/ppc/testing/instr_vsel.s
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@ -27,3 +27,23 @@ test_vsel_3:
#_ REGISTER_OUT v3 [0C010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [1D111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [1C111213, 14151617, 18191A1B, 1C1D1E1F]
test_vsel_4:
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v5 [01234567, 89ABCDEF, FEDCBA98, 76543210]
vsel v5, v3, v4, v5
blr
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v5 [01234567, 89ABCDEF, FEDCBA98, 76543210]
test_vsel_5:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v5 [01234567, 89ABCDEF, FEDCBA98, 76543210]
vsel v5, v3, v4, v5
blr
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v5 [FEDCBA98, 76543210, 01234567, 89ABCDEF]

8
src/xenia/cpu/ppc/testing/instr_vsubshs.s
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@ -5,3 +5,11 @@ test_vsubshs_1:
blr
#_ REGISTER_OUT v3 [7ffe0000, 6fff8003, 3da9fee1, 80068007]
#_ REGISTER_OUT v4 [00018001, 10000000, 42568124, 00000000]
test_vsubshs_2:
#_ REGISTER_IN v3 [7FFF8002, 7FFF8003, 7FFF8005, 80068007]
#_ REGISTER_IN v4 [FFFF0005, 10000000, 42568124, 00000000]
vsubshs v3, v3, v4
blr
#_ REGISTER_OUT v3 [7FFF8000, 6FFF8003, 3DA9FEE1, 80068007]
#_ REGISTER_OUT v4 [FFFF0005, 10000000, 42568124, 00000000]