From cff80bd782b7a0f61a17a2c0020fe839d4f07134 Mon Sep 17 00:00:00 2001
From: DrChat <arkolbed@gmail.com>
Date: Wed, 26 Apr 2017 12:28:35 -0500
Subject: [PATCH] fctiw[z]x: Sign-extend the result (verified by HW)

---
 src/xenia/cpu/ppc/ppc_emit_fpu.cc        |  2 +-
 src/xenia/cpu/ppc/testing/instr_fctixz.s | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/xenia/cpu/ppc/ppc_emit_fpu.cc b/src/xenia/cpu/ppc/ppc_emit_fpu.cc
index c3bc2e83a..70e01cd80 100644
--- a/src/xenia/cpu/ppc/ppc_emit_fpu.cc
+++ b/src/xenia/cpu/ppc/ppc_emit_fpu.cc
@@ -261,7 +261,7 @@ int InstrEmit_fctiwx(PPCHIRBuilder& f, const InstrData& i) {
   // TODO(benvanik): pull from FPSCR[RN]
   RoundMode round_mode = ROUND_TO_ZERO;
   Value* v = f.Convert(f.LoadFPR(i.X.RB), INT32_TYPE, round_mode);
-  v = f.Cast(f.ZeroExtend(v, INT64_TYPE), FLOAT64_TYPE);
+  v = f.Cast(f.SignExtend(v, INT64_TYPE), FLOAT64_TYPE);
   f.StoreFPR(i.X.RT, v);
   f.UpdateFPSCR(v, i.X.Rc);
   return 0;
diff --git a/src/xenia/cpu/ppc/testing/instr_fctixz.s b/src/xenia/cpu/ppc/testing/instr_fctixz.s
index c2df12eaf..4f132a68f 100644
--- a/src/xenia/cpu/ppc/testing/instr_fctixz.s
+++ b/src/xenia/cpu/ppc/testing/instr_fctixz.s
@@ -45,7 +45,7 @@ test_fctiwz_6:
   fctiwz f1, f0
   blr
   #_ REGISTER_OUT f0 0xbff0000000000000
-  #_ REGISTER_OUT f1 0x00000000ffffffff
+  #_ REGISTER_OUT f1 0xffffffffffffffff
 
 # -(2^31)
 test_fctiwz_7:
@@ -53,7 +53,7 @@ test_fctiwz_7:
   fctiwz f1, f0
   blr
   #_ REGISTER_OUT f0 0xc1e0000000000000
-  #_ REGISTER_OUT f1 0x0000000080000000
+  #_ REGISTER_OUT f1 0xFFFFFFFF80000000
 
 # 2^31 - 1
 test_fctiwz_8:
@@ -77,7 +77,7 @@ test_fctiwz_10:
   fctiwz f1, f0
   blr
   #_ REGISTER_OUT f0 0xfff0000000000000
-  #_ REGISTER_OUT f1 0x0000000080000000
+  #_ REGISTER_OUT f1 0xFFFFFFFF80000000
 
 # TODO(DrChat): Xenia doesn't handle NaNs yet.
 # # QNaN
@@ -86,7 +86,7 @@ test_fctiwz_10:
 #   fctiwz f1, f0
 #   blr
 #   #_ REGISTER_OUT f0 0xfff8000000000000
-#   #_ REGISTER_OUT f1 0x0000000080000000
+#   #_ REGISTER_OUT f1 0xFFFFFFFF80000000
 # 
 # # SNaN
 # test_fctiwz_12:
@@ -94,7 +94,7 @@ test_fctiwz_10:
 #   fctiwz f1, f0
 #   blr
 #   #_ REGISTER_OUT f0 0xfff4000000000000
-#   #_ REGISTER_OUT f1 0x0000000080000000
+#   #_ REGISTER_OUT f1 0xFFFFFFFF80000000
 
 # +0
 test_fctidz_1: