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+ 2006/09/01                                         Revision 1.2
+-----------------------------------------------------------------
+
+
+   This is a description of the VMX128-type opcodes found on
+   the xbox360 processor. I figured this out by looking at
+   various disassmblies, so there might some errors and
+   missing instructions. Some instructions have unknown
+   semantics for me.
+
+   See comments or corrections to sb#biallas.net
+
+
+=================================================================
+Conventions:
+   VD128, VS128:  5 lower bits of a VMX128 vector register 
+                  number
+   VDh:	          upper 2 bits of VD128
+                  (so register number is (VDh << 5 | VD128))
+		 
+   VA128:         same as VD128
+   A:             bit 6 of VA128
+   a:             bit 5 of VA128
+                  (so register number is (A<<6 | a<<5 | VA128))
+                     
+   VB128:         same as VD128
+   VBh:           same as VDh
+   
+   VC128:         3 bits of a VMX128 vector register number
+                  (you can only use vr0-vr7 here)
+   
+   RA, RB:        general purpose register number
+
+   UIMM:          unsigned immediate value
+   SIMM:          signed immediate value
+   
+   PERMh:         upper 3 bits of a permutation
+   PERMl:         lower 5 bits of a permutation
+   
+   x, y, z:       unknown immediate values
+
+=================================================================
+   lvewx128                  Load Vector128 Element Word Indexed
+|0 0 0 1 0 0|  VD128  |   RA    |   RB    |0 0 0 1 0 0 0|VDh|1 1|
+
+   lvewx128      vr(VD128), r(RA), r(RB)
+
+
+=================================================================
+   lvlx128                           Load Vector128 Left Indexed
+|0 0 0 1 0 0|  VD128  |   RA    |   RB    |1 0 0 0 0 0 0|VDh|1 1|
+
+   lvlx128       vr(VD128), r(RA), r(RB)
+
+
+=================================================================
+   lvrx128                          Load Vector128 Right Indexed
+|0 0 0 1 0 0|  VD128  |   RA    |   RB    |1 0 0 0 1 0 0|VDh|1 1|
+
+   lvrx128       vr(VD128), r(RA), r(RB)
+
+
+=================================================================
+   lvlxl128                      Load Vector128 Left Indexed LRU
+|0 0 0 1 0 0|  VD128  |   RA    |   RB    |1 1 0 0 0 0 0|VDh|1 1|
+
+   lvlxl128      vr(VD128), r(RA), r(RB)
+
+
+=================================================================
+   lvrxl128                     Load Vector128 Right Indexed LRU
+|0 0 0 1 0 0|  VD128  |   RA    |   RB    |1 1 0 0 1 0 0|VDh|1 1|
+
+   lvrxl128      vr(VD128), r(RA), r(RB)
+
+
+=================================================================
+   lvsl128                         Load Vector128 for Shift Left
+|0 0 0 1 0 0|  VD128  |   RA    |   RB    |0 0 0 0 0 0 0|VDh|1 1|
+
+   lvsl128       vr(VD128), r(RA), r(RB)
+
+
+=================================================================
+   lvsr128                        Load Vector128 for Shift Right
+|0 0 0 1 0 0|  VD128  |   RA    |   RB    |0 0 0 0 1 0 0|VDh|1 1|
+
+   lvsr128       vr(VD128), r(RA), r(RB)
+
+
+=================================================================
+   lvx128                                 Load Vector128 Indexed
+|0 0 0 1 0 0|  VD128  |   RA    |   RB    |0 0 0 1 1 0 0|VDh|1 1|
+
+   lvx128        vr(VD128), r(RA), r(RB)
+
+
+=================================================================
+   lvxl128                            Load Vector128 Indexed LRU
+|0 0 0 1 0 0|  VD128  |   RA    |   RB    |0 1 0 1 1 0 0|VDh|1 1|
+
+   lvxl128       vr(VD128), r(RA), r(RB)
+
+
+=================================================================
+   stewx128                 Store Vector128 Element Word Indexed
+|0 0 0 1 0 0|  VS128  |   RA    |   RB    |0 1 1 0 0 0 0|VDh|1 1|
+
+   stvewx128     vr(VS128), r(RA), r(RB)
+
+
+=================================================================
+   stvlx128                         Store Vector128 Left Indexed
+|0 0 0 1 0 0|  VS128  |   RA    |   RB    |1 0 1 0 0 0 0|VDh|1 1|
+
+   stvlx128      vr(VS128), r(RA), r(RB)
+
+
+=================================================================
+   stvlxl128                    Store Vector128 Left Indexed LRU
+|0 0 0 1 0 0|  VS128  |   RA    |   RB    |1 1 1 0 0 0 0|VDh|1 1|
+
+   lvlxl128      vr(VS128), r(RA), r(RB)
+
+
+=================================================================
+   stvrx128                        Store Vector128 Right Indexed
+|0 0 0 1 0 0|  VS128  |   RA    |   RB    |1 0 1 0 1 0 0|VDh|1 1|
+
+   stvrx128       vr(VS128), r(RA), r(RB)
+
+
+=================================================================
+   stvrxl128                   Store Vector128 Right Indexed LRU
+|0 0 0 1 0 0|  VS128  |   RA    |   RB    |1 1 1 0 1 0 0|VDh|1 1|
+
+   stvrxl128     vr(VS128), r(RA), r(RB)
+
+
+=================================================================
+   stvx128                               Store Vector128 Indexed
+|0 0 0 1 0 0|  VS128  |   RA    |   RB    |0 0 1 1 1 0 0|VDh|1 1|
+
+   stvx128       vr(VS128), r(RA), r(RB)
+
+
+=================================================================
+   stvxl128                          Store Vector128 Indexed LRU
+|0 0 0 1 0 0|  VS128  |   RA    |   RB    |0 1 1 1 1 0 0|VDh|1 1|
+
+   stvxl128      vr(VS128), r(RA), r(RB)
+
+
+=================================================================
+   vaddfp128                        Vector128 Add Floating Point
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|0 0 0 0|a|1|VDh|VBh|
+
+   vaddfp128     vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vand128                                 Vector128 Logical AND
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|1 0 0 0|a|1|VDh|VBh|
+
+   vand128       vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vandc128                                Vector128 Logical AND 
+                                                 with Complement
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|1 0 1 0|a|1|VDh|VBh|
+
+   vandc128      vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vcfpsxws128          Vector128 Convert From Floating-Point to 
+                                Signed Fixed-Point Word Saturate
+|0 0 0 1 1 0|  VD128  |  SIMM   |  VB128  |0 1 0 0 0 1 1|VDh|VBh|
+
+   vcfpsxws128   vr(VD128), vr(VB128), SIMM
+
+
+=================================================================
+   vcfpuxws128          Vector128 Convert From Floating-Point to 
+                              Unsigned Fixed-Point Word Saturate
+|0 0 0 1 1 0|  VD128  |  UIMM   |  VB128  |0 1 0 0 1 1 1|VDh|VBh|
+
+   vcfpuxws128   vr(VD128), vr(VB128), UIMM
+
+
+=================================================================
+   vcmpbfp128                           Vector128 Compare Bounds 
+                                                  Floating Point
+|0 0 0 1 1 0|  VD128  |  VA128  |  VB128  |A|0 1 1|R|a|0|VDh|VBh|
+
+   vcmpbfp128    vr(VD128), vr(VA128), vr(VB128)         (R == 0)
+   vcmpbfp128.   vr(VD128), vr(VA128), vr(VB128)         (R == 1)
+
+
+=================================================================
+   vcmpeqfp128                        Vector128 Compare Equal-to
+                                                  Floating Point
+|0 0 0 1 1 0|  VD128  |  VA128  |  VB128  |A|0 0 0|R|a|0|VDh|VBh|
+
+   vcmpeqfp128   vr(VD128), vr(VA128), vr(VB128)         (R == 0)
+   vcmpeqfp128.  vr(VD128), vr(VA128), vr(VB128)         (R == 1)
+
+
+=================================================================
+   vcmpequw128                        Vector128 Compare Equal-to 
+                                                   Unsigned Word
+|0 0 0 1 1 0|  VD128  |  VA128  |  VB128  |A|1 0 0|R|a|0|VDh|VBh|
+
+   vcmpequw128   vr(VD128), vr(VA128), vr(VB128)         (R == 0)
+   vcmpequw128.  vr(VD128), vr(VA128), vr(VB128)         (R == 1)
+
+
+=================================================================
+   vcmpgefp128                    Vector128 Compare Greater-Than-
+                                      or-Equal-to Floating Point
+|0 0 0 1 1 0|  VD128  |  VA128  |  VB128  |A|0 0 1|R|a|0|VDh|VBh|
+
+   vcmpgefp128   vr(VD128), vr(VA128), vr(VB128)         (R == 0)
+   vcmpgefp128.  vr(VD128), vr(VA128), vr(VB128)         (R == 1)
+
+
+=================================================================
+   vcmpgtfp128                    Vector128 Compare Greater-Than 
+                                                  Floating-Point
+|0 0 0 1 1 0|  VD128  |  VA128  |  VB128  |A|0 1 0|R|a|0|VDh|VBh|
+
+   vcmpgtfp128   vr(VD128), vr(VA128), vr(VB128)         (R == 0)
+   vcmpgtfp128.  vr(VD128), vr(VA128), vr(VB128)         (R == 1)
+
+
+=================================================================
+   vcsxwfp128          Vector128 Convert From Signed Fixed-Point 
+                                          Word to Floating-Point
+|0 0 0 1 1 0|  VD128  |  UIMM   |  VB128  |0 1 0 1 0 1 1|VDh|VBh|
+
+   vcsxwfp128    vr(VD128), vr(VB128), SIMM
+
+
+=================================================================
+   vcuxwfp128        Vector128 Convert From Unsigned Fixed-Point
+                                          Word to Floating-Point
+|0 0 0 1 1 0|  VD128  |  UIMM   |  VB128  |0 1 0 1 1 1 1|VDh|VBh|
+
+   vcuxwfp128    vr(VD128), vr(VB128), UIMM
+
+
+=================================================================
+   vexptefp128                Vector128 2 Raised to the Exponent 
+                                         Estimate Floating Point
+|0 0 0 1 1 0|  VD128  |0 0 0 0 0|  VB128  |1 1 0 1 0 1 1|VDh|VBh|
+
+   vexptefp128   vr(VD128), vr(VB128)
+
+
+=================================================================
+   vlogefp128                            Vector128 Log2 Estimate 
+                                                  Floating Point
+|0 0 0 1 1 0|  VD128  |0 0 0 0 0|  VB128  |1 1 0 1 1 1 1|VDh|VBh|
+
+   vlogefp128    vr(VD128), vr(VB128)
+
+
+=================================================================
+   vmaddcfp128                            Vector128 Multiply Add 
+                                                  Floating Point
+|0 0 0 1 0 1|  VDS128 |  VA128  |  VB128  |A|0 1 0 0|a|1|VDh|VBh|
+
+   vmaddcfp128   vr(VDS128), vr(VA128), vr(VSD128), vr(VB128)
+
+
+=================================================================
+   vmaddfp128                             Vector128 Multiply Add 
+                                                  Floating Point
+|0 0 0 1 0 1|  VDS128 |  VA128  |  VB128  |A|0 0 1 1|a|1|VDh|VBh|
+
+   vmaddfp128    vr(VDS128), vr(VA128), vr(VB128), vr(VDS128)
+
+
+=================================================================
+   vmaxfp128                                   Vector128 Maximum 
+                                                  Floating Point
+|0 0 0 1 1 0|  VD128  |  VA128  |  VB128  |A|1 0 1 0|a|0|VDh|VBh|
+
+   vmaxfp128     vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vminfp128                                   Vector128 Minimum
+                                                  Floating Point
+|0 0 0 1 1 0|  VD128  |  VA128  |  VB128  |A|1 0 1 1|a|0|VDh|VBh|
+
+   vminfp128     vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vmrghw128                           Vector128 Merge High Word
+|0 0 0 1 1 0|  VD128  |  VA128  |  VB128  |A|1 1 0 0|a|0|VDh|VBh|
+
+   vmrghw128     vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vmrglw128                            Vector128 Merge Low Word
+|0 0 0 1 1 0|  VD128  |  VA128  |  VB128  |A|1 1 0 1|a|0|VDh|VBh|
+
+   vmrglw128     vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vmsum3fp128                      Vector128 Multiply Sum 3-way 
+                                                  Floating Point
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|0 1 1 0|a|1|VDh|VBh|
+
+   vmsub3fp128   vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vmsum4fp128                      Vector128 Multiply Sum 4-way 
+                                                  Floating-Point
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|0 1 1 1|a|1|VDh|VBh|
+
+   vmsub4fp128   vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vmulfp128                                  Vector128 Multiply
+                                                  Floating-Point
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|0 0 1 0|a|1|VDh|VBh|
+
+   vmulfp128     vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vnmsubfp128              Vector128 Negative Multiply-Subtract 
+                                                  Floating Point
+|0 0 0 1 0 1|  VDS128 |  VA128  |  VB128  |A|0 1 0 1|a|1|VDh|VBh|
+
+   vnmsubfp128   vr(VDS128), vr(VA128), vr(VB128), vr(VDS128)
+
+
+=================================================================
+   vnor128                                 Vector128 Logical NOR
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|1 0 1 0|a|1|VDh|VBh|
+
+   vnor128       vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vor128                                   Vector128 Logical OR
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|1 0 1 1|a|1|VDh|VBh|
+
+   vor128        vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vperm128                                Vector128 Permutation
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|0| VC  |a|0|VDh|VBh|
+
+   vperm128      vr(VD128), vr(VA128), vr(VB128), vr(VC)
+
+
+=================================================================
+   vpermwi128                 Vector128 Permutate Word Immediate
+|0 0 0 1 1 0|  VD128  |  PERMl  |  VB128  |0|1|PERMh|0|1|VDh|VBh|
+
+   vpermwi128    vr(VD128), vr(VB128), (PERMh << 5 | PERMl)
+
+
+=================================================================
+   vpkd3d128                 Vector128 Pack D3Dtype, Rotate Left 
+                                       Immediate and Mask Insert
+|0 0 0 1 1 0|  VD128  |  x  | y |  VB128  |1 1 0| z |0 1|VDh|VBh|
+
+   vpkd3d128     vr(VD128), vr(VB128), x, y, z
+
+
+=================================================================
+   vpkshss128                    Vector128 Pack Signed Half Word 
+                                                 Signed Saturate
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|1 0 0 0|a|0|VDh|VBh|
+
+   vpkshss128    vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vpkshus128                    Vector128 Pack Signed Half Word 
+                                               Unsigned Saturate
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|1 0 0 1|a|0|VDh|VBh|
+
+   vpkshus128    vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vpkswss128                         Vector128 Pack Signed Word
+                                                 Signed Saturate
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|1 0 1 0|a|0|VDh|VBh|
+
+   vpkswss128    vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vpkswus128                         Vector128 Pack Signed Word   
+                                               Unsigned Saturate
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|1 0 1 1|a|0|VDh|VBh|
+
+   vpkswus128    vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vpkuhum128                  Vector128 Pack Unsigned Half Word 
+                                                 Unsigned Modulo
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|1 1 0 0|a|0|VDh|VBh|
+
+   vpkuhum128    vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vpkuhus128                  Vector128 Pack Unsigned Half Word 
+                                               Unsigned Saturate
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|1 1 0 1|a|0|VDh|VBh|
+
+   vpkuhus128    vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vpkuwum128                       Vector128 Pack Unsigned Word
+                                                 Unsigned Modulo
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|1 1 1 0|a|0|VDh|VBh|
+
+   vpkuwum128    vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vpkuwus128                       Vector128 Pack Unsigned Word
+                                               Unsigned Saturate
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|1 1 1 1|a|0|VDh|VBh|
+
+   vpkuwus128    vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vrefp128                        Vector128 Reciprocal Estimate 
+                                                  Floating Point
+|0 0 0 1 1 0|  VD128  |0 0 0 0 0|  VB128  |1 1 0 0 0 1 1|VDh|VBh|
+
+   vrefp128      vr(VD128), vr(VB128)
+
+
+=================================================================
+   vrfim128                    Vector128 Round to Floating-Point 
+                                              Integer toward -oo
+|0 0 0 1 1 0|  VD128  |0 0 0 0 0|  VB128  |0 1 1 0 0 1 1|VDh|VBh|
+
+   vrfim128      vr(VD128), vr(VB128)
+
+
+=================================================================
+   vrfin128                    Vector128 Round to Floating-Point 
+                                          Integer toward Nearest
+|0 0 0 1 1 0|  VD128  |0 0 0 0 0|  VB128  |0 1 1 0 1 1 1|VDh|VBh|
+
+   vrfin128      vr(VD128), vr(VB128)
+
+
+=================================================================
+   vrfip128                    Vector128 Round to Floating-Point 
+                                              Integer toward +oo
+|0 0 0 1 1 0|  VD128  |0 0 0 0 0|  VB128  |0 1 1 1 0 1 1|VDh|VBh|
+
+   vrfip128      vr(VD128), vr(VB128)
+
+
+=================================================================
+   vrfiz128                    Vector128 Round to Floating-Point 
+                                             Integer toward Zero
+|0 0 0 1 1 0|  VD128  |0 0 0 0 0|  VB128  |0 1 1 1 1 1 1|VDh|VBh|
+
+   vrfiz128      vr(VD128), vr(VB128)
+
+
+=================================================================
+   vrlimi128                     Vector128 Rotate Left Immediate 
+                                                 and Mask Insert
+|0 0 0 1 1 0|  VD128  |  UIMM   |  VB128  |1 1 1| z |0 1|VDh|VBh|
+
+   vrlimi128     vr(VD128), vr(VB128), UIMM, z
+
+
+=================================================================
+   vrlw128                            Vector128 Rotate Left Word
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|0 0 0 1|a|1|VDh|VBh|
+
+   vrlw128       vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vrsqrtefp128                 Vector128 Reciprocal Square Root 
+                                         Estimate Floating Point
+|0 0 0 1 1 0|  VD128  |0 0 0 0 0|  VB128  |1 1 0 0 1 1 1|VDh|VBh|
+
+   vrsqrtefp128  vr(VD128), vr(VB128)
+
+
+=================================================================
+   vsel128                                      Vector128 Select
+|0 0 0 1 0 1| VDS128  |  VA128  |  VB128  |A|1 1 0 1|a|1|VDh|VBh|
+
+   vsel128       vr(VDS128), vr(VA128), vr(VB128), vr(VDS128)
+
+
+=================================================================
+   vsldoi128                         Vector128 Shift Left Double 
+                                              by Octet Immediate
+|0 0 0 1 0 0|  VD128  |  VA128  |  VB128  |A|  SHB  |a|1|VDh|VBh|
+
+   vsldoi128     vr(VD128), vr(VA128), vr(VB128), SHB
+
+
+=================================================================
+   vslo128                            Vector128 Shift Left Octet
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|1 1 1 0|a|1|VDh|VBh|
+
+   vslo128       vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vslw128                             Vector128 Shift Left Word
+|0 0 0 1 1 0|  VD128  |  VA128  |  VB128  |A|0 0 1 1|a|1|VDh|VBh|
+
+   vslw128       vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vspltisw128                         Vector128 Splat Immediate 
+                                                     Signed Word
+|0 0 0 1 1 0|  VD128  |  SIMM   |  VB128  |1 1 1 0 1 1 1|VDh|VBh|
+
+   vspltisw128   vr(VD128), vr(VB128), SIMM
+
+
+=================================================================
+   vspltw128                                Vector128 Splat Word
+|0 0 0 1 1 0|  VD128  |  UIMM   |  VB128  |1 1 1 0 0 1 1|VDh|VBh|
+
+   vspltw128     vr(VD128), vr(VB128), UIMM
+
+
+=================================================================
+   vsraw128                                Vector128 Shift Right 
+                                                 Arithmetic Word
+|0 0 0 1 1 0|  VD128  |  VA128  |  VB128  |A|0 1 0 1|a|1|VDh|VBh|
+
+   vsraw128      vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vsro128                           Vector128 Shift Right Octet
+|0 0 0 1 1 0|  VD128  |  VA128  |  VB128  |A|1 1 1 1|a|1|VDh|VBh|
+
+   vsro128       vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vsrw128                            Vector128 Shift Right Word
+|0 0 0 1 1 0|  VD128  |  VA128  |  VB128  |A|0 1 1 1|a|1|VDh|VBh|
+
+   vsrw128       vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vsubfp128                   Vector128 Subtract Floating Point
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|0 0 0 1|a|1|VDh|VBh|
+
+   vsubfp128     vr(VD128), vr(VA128), vr(VB128)
+
+
+=================================================================
+   vupkd3d128                           Vector128 Unpack D3Dtype
+|0 0 0 1 1 0|  VD128  |  UIMM   |  VB128  |1 1 1 1 1 1 1|VDh|VBh|
+
+   vupkd3d128    vr(VD128), vr(VB128), UIMM
+
+
+=================================================================
+   vupkhsb128                                   Vector128 Unpack 
+                                                High Signed Byte
+|0 0 0 1 1 0|  VD128  |0 0 0 0 0|  VB128  |0 1 1 1 0 0 0|VDh|VBh|
+
+   vupkhsb128    vr(VD128), vr(VB128)
+
+
+=================================================================
+   vupklsb128                                   Vector128 Unpack 
+                                                 Low Signed Byte
+|0 0 0 1 1 0|  VD128  |0 0 0 0 0|  VB128  |0 1 1 1 1 0 0|VDh|VBh|
+
+   vupkhsb128    vr(VD128), vr(VB128)
+
+
+=================================================================
+   vxor128                                 Vector128 Logical XOR
+|0 0 0 1 0 1|  VD128  |  VA128  |  VB128  |A|1 1 0 0|a|1|VDh|VBh|
+
+   vxor128       vr(VD128), vr(VA128), vr(VB128)
diff --git a/src/xenia/base/math.h b/src/xenia/base/math.h
index eefcbba1a..824a1d746 100644
--- a/src/xenia/base/math.h
+++ b/src/xenia/base/math.h
@@ -56,6 +56,14 @@ T next_pow2(T value) {
   return value;
 }
 
+constexpr uint32_t make_bitmask(uint32_t a, uint32_t b) {
+  return (static_cast<uint32_t>(-1) >> (31 - b)) & ~((1u << a) - 1);
+}
+
+constexpr uint32_t select_bits(uint32_t value, uint32_t a, uint32_t b) {
+  return (value & make_bitmask(a, b)) >> a;
+}
+
 // lzcnt instruction, typed for integers of all sizes.
 // The number of leading zero bits in the value parameter. If value is zero, the
 // return value is the size of the input operand (8, 16, 32, or 64). If the most
diff --git a/src/xenia/cpu/ppc/ppc_decode_data.h b/src/xenia/cpu/ppc/ppc_decode_data.h
new file mode 100644
index 000000000..c61c26799
--- /dev/null
+++ b/src/xenia/cpu/ppc/ppc_decode_data.h
@@ -0,0 +1,687 @@
+/**
+ ******************************************************************************
+ * Xenia : Xbox 360 Emulator Research Project                                 *
+ ******************************************************************************
+ * Copyright 2015 Ben Vanik. All rights reserved.                             *
+ * Released under the BSD license - see LICENSE in the root for more details. *
+ ******************************************************************************
+ */
+
+#ifndef XENIA_CPU_PPC_PPC_DECODE_DATA_H_
+#define XENIA_CPU_PPC_PPC_DECODE_DATA_H_
+
+#include <cstdint>
+
+#include "xenia/base/math.h"
+#include "xenia/base/string_buffer.h"
+#include "xenia/cpu/ppc/ppc_instr.h"
+#include "xenia/cpu/ppc/ppc_opcode_info.h"
+
+namespace xe {
+namespace cpu {
+namespace ppc {
+
+constexpr int64_t XEEXTS16(uint32_t v) { return (int64_t)((int16_t)v); }
+constexpr int64_t XEEXTS26(uint32_t v) {
+  return (int64_t)(v & 0x02000000 ? (int32_t)v | 0xFC000000 : (int32_t)(v));
+}
+constexpr uint64_t XEEXTZ16(uint32_t v) { return (uint64_t)((uint16_t)v); }
+static inline uint64_t XEMASK(uint32_t mstart, uint32_t mstop) {
+  // if mstart ≤ mstop then
+  //   mask[mstart:mstop] = ones
+  //   mask[all other bits] = zeros
+  // else
+  //   mask[mstart:63] = ones
+  //   mask[0:mstop] = ones
+  //   mask[all other bits] = zeros
+  mstart &= 0x3F;
+  mstop &= 0x3F;
+  uint64_t value =
+      (UINT64_MAX >> mstart) ^ ((mstop >= 63) ? 0 : UINT64_MAX >> (mstop + 1));
+  return mstart <= mstop ? value : ~value;
+}
+
+struct PPCDecodeData {
+  struct FormatSC {};
+  struct FormatD {
+    uint32_t RT() const { return bits_.RT; }
+    uint32_t RD() const { return RT(); }
+    uint32_t RS() const { return RT(); }
+    uint32_t FD() const { return RT(); }
+    uint32_t FS() const { return RT(); }
+    uint32_t TO() const { return RT(); }
+    uint32_t RA() const { return bits_.RA; }
+    uint32_t RA0() const { return RA(); }
+    uint32_t DS() const { return bits_.DS; }
+    int32_t d() const { return static_cast<int32_t>(XEEXTS16(DS())); }
+    int32_t SIMM() const { return d(); }
+    uint32_t UIMM() const { return static_cast<uint32_t>(XEEXTZ16(DS())); }
+
+    uint32_t CRFD() const { return bits_.RT >> 2; }
+    uint32_t L() const { return bits_.RT & 0x1; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t DS : 16;
+        uint32_t RA : 5;
+        uint32_t RT : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatDS {
+    uint32_t RT() const { return bits_.RT; }
+    uint32_t RD() const { return RT(); }
+    uint32_t RS() const { return RT(); }
+    uint32_t RA() const { return bits_.RA; }
+    uint32_t RA0() const { return RA(); }
+    uint32_t DS() const { return bits_.DS; }
+    int32_t ds() const { return static_cast<int32_t>(XEEXTS16(DS() << 2)); }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t DS : 14;
+        uint32_t RA : 5;
+        uint32_t RT : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatB {
+    uint32_t BO() const { return bits_.BO; }
+    uint32_t BI() const { return bits_.BI; }
+    uint32_t BD() const { return bits_.BD; }
+    uint32_t ADDR() const {
+      return static_cast<uint32_t>(XEEXTS16(BD() << 2)) + (AA() ? 0 : address_);
+    }
+    bool AA() const { return bits_.AA ? true : false; }
+    bool LK() const { return bits_.LK ? true : false; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t LK : 1;
+        uint32_t AA : 1;
+        uint32_t BD : 14;
+        uint32_t BI : 5;
+        uint32_t BO : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatI {
+    uint32_t LI() const { return bits_.LI; }
+    uint32_t ADDR() const {
+      return static_cast<uint32_t>(XEEXTS16(LI() << 2)) + (AA() ? 0 : address_);
+    }
+    bool AA() const { return bits_.AA ? true : false; }
+    bool LK() const { return bits_.LK ? true : false; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t LK : 1;
+        uint32_t AA : 1;
+        uint32_t LI : 24;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatX {
+    uint32_t RT() const { return bits_.RT; }
+    uint32_t RD() const { return RT(); }
+    uint32_t RS() const { return RT(); }
+    uint32_t FD() const { return RT(); }
+    uint32_t FS() const { return RT(); }
+    uint32_t VD() const { return RT(); }
+    uint32_t VS() const { return RT(); }
+    uint32_t TO() const { return RT(); }
+    uint32_t RA() const { return bits_.RA; }
+    uint32_t RA0() const { return RA(); }
+    uint32_t FA() const { return RA(); }
+    uint32_t RB() const { return bits_.RB; }
+    uint32_t FB() const { return RB(); }
+    uint32_t SH() const { return RB(); }
+    uint32_t IMM() const { return RB(); }
+    bool Rc() const { return bits_.Rc ? true : false; }
+
+    uint32_t CRFD() const { return bits_.RT >> 2; }
+    uint32_t L() const { return bits_.RT & 0x1; }
+    uint32_t CRFS() const { return bits_.RA >> 2; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t Rc : 1;
+        uint32_t : 10;
+        uint32_t RB : 5;
+        uint32_t RA : 5;
+        uint32_t RT : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatXL {
+    uint32_t BO() const { return bits_.BO; }
+    uint32_t CRBD() const { return BO(); }
+    uint32_t BI() const { return bits_.BI; }
+    uint32_t CRBA() const { return BI(); }
+    uint32_t BB() const { return bits_.BB; }
+    uint32_t CRBB() const { return BB(); }
+    bool LK() const { return bits_.LK ? true : false; }
+
+    uint32_t CRFD() const { return CRBD() >> 2; }
+    uint32_t CRFS() const { return CRBA() >> 2; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t LK : 1;
+        uint32_t : 10;
+        uint32_t BB : 5;
+        uint32_t BI : 5;
+        uint32_t BO : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatXFX {
+    uint32_t RT() const { return bits_.RT; }
+    uint32_t RD() const { return RT(); }
+    uint32_t RS() const { return RT(); }
+    uint32_t SPR() const { return bits_.SPR; }
+    uint32_t TBR() const {
+      return ((bits_.SPR & 0x1F) << 5) | ((bits_.SPR >> 5) & 0x1F);
+    }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t : 1;
+        uint32_t : 10;
+        uint32_t SPR : 10;
+        uint32_t RT : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatXFL {
+    bool L() const { return bits_.L ? true : false; }
+    uint32_t FM() const { return bits_.FM; }
+    bool W() const { return bits_.W ? true : false; }
+    uint32_t RB() const { return bits_.RB; }
+    uint32_t FB() const { return RB(); }
+    bool Rc() const { return bits_.Rc ? true : false; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t Rc : 1;
+        uint32_t : 10;
+        uint32_t RB : 5;
+        uint32_t W : 1;
+        uint32_t FM : 8;
+        uint32_t L : 1;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatXS {
+    uint32_t RT() const { return bits_.RT; }
+    uint32_t RS() const { return RT(); }
+    uint32_t RA() const { return bits_.RA; }
+    uint32_t SH() const { return (bits_.SH5 << 5) | bits_.SH; }
+    bool Rc() const { return bits_.Rc ? true : false; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t Rc : 1;
+        uint32_t SH5 : 1;
+        uint32_t : 9;
+        uint32_t SH : 5;
+        uint32_t RA : 5;
+        uint32_t RT : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatXO {
+    uint32_t RT() const { return bits_.RT; }
+    uint32_t RD() const { return RT(); }
+    uint32_t RA() const { return bits_.RA; }
+    uint32_t RB() const { return bits_.RB; }
+    bool OE() const { return bits_.OE ? true : false; }
+    bool Rc() const { return bits_.Rc ? true : false; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t Rc : 1;
+        uint32_t : 9;
+        uint32_t OE : 1;
+        uint32_t RB : 5;
+        uint32_t RA : 5;
+        uint32_t RT : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatA {
+    uint32_t FT() const { return bits_.FT; }
+    uint32_t FD() const { return FT(); }
+    uint32_t FS() const { return FT(); }
+    uint32_t FA() const { return bits_.FA; }
+    uint32_t FB() const { return bits_.FB; }
+    uint32_t FC() const { return bits_.FC; }
+    uint32_t XO() const { return bits_.XO; }
+    bool Rc() const { return bits_.Rc ? true : false; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t Rc : 1;
+        uint32_t XO : 5;
+        uint32_t FC : 5;
+        uint32_t FB : 5;
+        uint32_t FA : 5;
+        uint32_t FT : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatM {
+    uint32_t RT() const { return bits_.RT; }
+    uint32_t RS() const { return RT(); }
+    uint32_t RA() const { return bits_.RA; }
+    uint32_t SH() const { return bits_.SH; }
+    uint32_t RB() const { return SH(); }
+    uint32_t MB() const { return bits_.MB; }
+    uint32_t ME() const { return bits_.ME; }
+    bool Rc() const { return bits_.Rc ? true : false; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t Rc : 1;
+        uint32_t ME : 5;
+        uint32_t MB : 5;
+        uint32_t SH : 5;
+        uint32_t RA : 5;
+        uint32_t RT : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatMD {
+    uint32_t RT() const { return bits_.RT; }
+    uint32_t RS() const { return RT(); }
+    uint32_t RA() const { return bits_.RA; }
+    uint32_t SH() const { return (bits_.SH5 << 5) | bits_.SH; }
+    uint32_t MB() const { return (bits_.MB5 << 5) | bits_.MB; }
+    uint32_t ME() const { return MB(); }
+    bool Rc() const { return bits_.Rc ? true : false; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t Rc : 1;
+        uint32_t SH5 : 1;
+        uint32_t : 3;
+        uint32_t MB5 : 1;
+        uint32_t MB : 5;
+        uint32_t SH : 5;
+        uint32_t RA : 5;
+        uint32_t RT : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatMDS {
+    uint32_t RT() const { return bits_.RT; }
+    uint32_t RS() const { return RT(); }
+    uint32_t RA() const { return bits_.RA; }
+    uint32_t RB() const { return bits_.RB; }
+    uint32_t MB() const { return (bits_.MB5 << 5) | bits_.MB; }
+    uint32_t ME() const { return MB(); }
+    bool Rc() const { return bits_.Rc ? true : false; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t Rc : 1;
+        uint32_t : 4;
+        uint32_t MB5 : 1;
+        uint32_t MB : 5;
+        uint32_t RB : 5;
+        uint32_t RA : 5;
+        uint32_t RT : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatVX {
+    uint32_t VD() const { return bits_.VD; }
+    uint32_t VA() const { return bits_.VA; }
+    uint32_t VB() const { return bits_.VB; }
+    uint32_t UIMM() const { return VA(); }
+    int32_t SIMM() const { return static_cast<int32_t>(XEEXTS16(VA())); }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t : 11;
+        uint32_t VB : 5;
+        uint32_t VA : 5;
+        uint32_t VD : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatVC {
+    uint32_t VD() const { return bits_.VD; }
+    uint32_t VA() const { return bits_.VA; }
+    uint32_t VB() const { return bits_.VB; }
+    bool Rc() const { return bits_.Rc ? true : false; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t : 10;
+        uint32_t Rc : 1;
+        uint32_t VB : 5;
+        uint32_t VA : 5;
+        uint32_t VD : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatVA {
+    uint32_t VD() const { return bits_.VD; }
+    uint32_t VA() const { return bits_.VA; }
+    uint32_t VB() const { return bits_.VB; }
+    uint32_t VC() const { return bits_.VC; }
+    uint32_t SHB() const { return VC() & 0xF; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t : 6;
+        uint32_t VC : 5;
+        uint32_t VB : 5;
+        uint32_t VA : 5;
+        uint32_t VD : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatVX128 {
+    uint32_t VD() const { return bits_.VD128l | (bits_.VD128h << 5); }
+    uint32_t VA() const {
+      return bits_.VA128l | (bits_.VA128h << 5) | (bits_.VA128H << 6);
+    }
+    uint32_t VB() const { return bits_.VB128l | (bits_.VB128h << 5); }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t VB128h : 2;
+        uint32_t VD128h : 2;
+        uint32_t : 1;
+        uint32_t VA128h : 1;
+        uint32_t : 4;
+        uint32_t VA128H : 1;
+        uint32_t VB128l : 5;
+        uint32_t VA128l : 5;
+        uint32_t VD128l : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatVX128_1 {
+    uint32_t VD() const { return bits_.VD128l | (bits_.VD128h << 5); }
+    uint32_t VS() const { return VD(); }
+    uint32_t RA() const { return bits_.RA; }
+    uint32_t RA0() const { return RA(); }
+    uint32_t RB() const { return bits_.RB; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t : 2;
+        uint32_t VD128h : 2;
+        uint32_t : 7;
+        uint32_t RB : 5;
+        uint32_t RA : 5;
+        uint32_t VD128l : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatVX128_2 {
+    uint32_t VD() const { return bits_.VD128l | (bits_.VD128h << 5); }
+    uint32_t VA() const {
+      return bits_.VA128l | (bits_.VA128h << 5) | (bits_.VA128H << 6);
+    }
+    uint32_t VB() const { return bits_.VB128l | (bits_.VB128h << 5); }
+    uint32_t VC() const { return bits_.VC; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t VB128h : 2;
+        uint32_t VD128h : 2;
+        uint32_t : 1;
+        uint32_t VA128h : 1;
+        uint32_t VC : 3;
+        uint32_t : 1;
+        uint32_t VA128H : 1;
+        uint32_t VB128l : 5;
+        uint32_t VA128l : 5;
+        uint32_t VD128l : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatVX128_3 {
+    uint32_t VD() const { return bits_.VD128l | (bits_.VD128h << 5); }
+    uint32_t VB() const { return bits_.VB128l | (bits_.VB128h << 5); }
+    uint32_t UIMM() const { return bits_.UIMM; }
+    int32_t SIMM() const { return static_cast<int32_t>(XEEXTS16(bits_.UIMM)); }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t VB128h : 2;
+        uint32_t VD128h : 2;
+        uint32_t : 7;
+        uint32_t VB128l : 5;
+        uint32_t UIMM : 5;
+        uint32_t VD128l : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatVX128_4 {
+    uint32_t VD() const { return bits_.VD128l | (bits_.VD128h << 5); }
+    uint32_t VB() const { return bits_.VB128l | (bits_.VB128h << 5); }
+    uint32_t IMM() const { return bits_.IMM; }
+    uint32_t z() const { return bits_.z; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t VB128h : 2;
+        uint32_t VD128h : 2;
+        uint32_t : 2;
+        uint32_t z : 2;
+        uint32_t : 3;
+        uint32_t VB128l : 5;
+        uint32_t IMM : 5;
+        uint32_t VD128l : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatVX128_5 {
+    uint32_t VD() const { return bits_.VD128l | (bits_.VD128h << 5); }
+    uint32_t VA() const {
+      return bits_.VA128l | (bits_.VA128h << 5) | (bits_.VA128H << 6);
+    }
+    uint32_t VB() const { return bits_.VB128l | (bits_.VB128h << 5); }
+    uint32_t SH() const { return bits_.SH; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t VB128h : 2;
+        uint32_t VD128h : 2;
+        uint32_t : 1;
+        uint32_t VA128h : 1;
+        uint32_t SH : 4;
+        uint32_t VA128H : 1;
+        uint32_t VB128l : 5;
+        uint32_t VA128l : 5;
+        uint32_t VD128l : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatVX128_R {
+    uint32_t VD() const { return bits_.VD128l | (bits_.VD128h << 5); }
+    uint32_t VA() const {
+      return bits_.VA128l | (bits_.VA128h << 5) | (bits_.VA128H << 6);
+    }
+    uint32_t VB() const { return bits_.VB128l | (bits_.VB128h << 5); }
+    bool Rc() const { return bits_.Rc ? true : false; }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t VB128h : 2;
+        uint32_t VD128h : 2;
+        uint32_t : 1;
+        uint32_t VA128h : 1;
+        uint32_t Rc : 1;
+        uint32_t : 3;
+        uint32_t VA128H : 1;
+        uint32_t VB128l : 5;
+        uint32_t VA128l : 5;
+        uint32_t VD128l : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+  struct FormatVX128_P {
+    uint32_t VD() const { return bits_.VD128l | (bits_.VD128h << 5); }
+    uint32_t VB() const { return bits_.VB128l | (bits_.VB128h << 5); }
+    uint32_t UIMM() const { return bits_.PERMl | (bits_.PERMh << 5); }
+
+   private:
+    uint32_t address_;
+    union {
+      uint32_t value_;
+      struct {
+        uint32_t VB128h : 2;
+        uint32_t VD128h : 2;
+        uint32_t : 2;
+        uint32_t PERMh : 3;
+        uint32_t : 2;
+        uint32_t VB128l : 5;
+        uint32_t PERMl : 5;
+        uint32_t VD128l : 5;
+        uint32_t : 6;
+      } bits_;
+    };
+  };
+
+  union {
+    struct {
+      uint32_t address;
+      uint32_t code;
+    };
+    FormatSC SC;
+    FormatD D;
+    FormatDS DS;
+    FormatB B;
+    FormatI I;
+    FormatX X;
+    FormatXL XL;
+    FormatXFX XFX;
+    FormatXFL XFL;
+    FormatXS XS;
+    FormatXO XO;
+    FormatA A;
+    FormatM M;
+    FormatMD MD;
+    FormatMDS MDS;
+    FormatX DCBZ;
+    FormatVX VX;
+    FormatVC VC;
+    FormatVA VA;
+    FormatVX128 VX128;
+    FormatVX128_1 VX128_1;
+    FormatVX128_2 VX128_2;
+    FormatVX128_3 VX128_3;
+    FormatVX128_4 VX128_4;
+    FormatVX128_5 VX128_5;
+    FormatVX128_R VX128_R;
+    FormatVX128_P VX128_P;
+  };
+};
+
+}  // namespace ppc
+}  // namespace cpu
+}  // namespace xe
+
+#endif  // XENIA_CPU_PPC_PPC_DECODE_DATA_H_
diff --git a/src/xenia/cpu/ppc/ppc_disasm.cc b/src/xenia/cpu/ppc/ppc_disasm.cc
deleted file mode 100644
index 0b7555c99..000000000
--- a/src/xenia/cpu/ppc/ppc_disasm.cc
+++ /dev/null
@@ -1,529 +0,0 @@
-/*
- ******************************************************************************
- * Xenia : Xbox 360 Emulator Research Project                                 *
- ******************************************************************************
- * Copyright 2014 Ben Vanik. All rights reserved.                             *
- * Released under the BSD license - see LICENSE in the root for more details. *
- ******************************************************************************
- */
-
-#include "xenia/cpu/ppc/ppc_disasm.h"
-
-#include "xenia/base/assert.h"
-#include "xenia/base/math.h"
-#include "xenia/cpu/ppc/ppc_instr.h"
-
-namespace xe {
-namespace cpu {
-namespace ppc {
-
-void Disasm_0(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s ???", i.opcode_info->name);
-}
-
-void Disasm__(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s", i.opcode_info->name);
-}
-
-void Disasm_X_FRT_FRB(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%*s%s f%d, f%d", i.X.Rc ? -7 : -8, i.opcode_info->name,
-                    i.X.Rc ? "." : "", i.X.RT, i.X.RB);
-}
-void Disasm_A_FRT_FRB(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%*s%s f%d, f%d", i.A.Rc ? -7 : -8, i.opcode_info->name,
-                    i.A.Rc ? "." : "", i.A.FRT, i.A.FRB);
-}
-void Disasm_A_FRT_FRA_FRB(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%*s%s f%d, f%d, f%d", i.A.Rc ? -7 : -8,
-                    i.opcode_info->name, i.A.Rc ? "." : "", i.A.FRT, i.A.FRA,
-                    i.A.FRB);
-}
-void Disasm_A_FRT_FRA_FRB_FRC(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%*s%s f%d, f%d, f%d, f%d", i.A.Rc ? -7 : -8,
-                    i.opcode_info->name, i.A.Rc ? "." : "", i.A.FRT, i.A.FRA,
-                    i.A.FRB, i.A.FRC);
-}
-void Disasm_X_RT_RA_RB(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s r%d, r%d, r%d", i.opcode_info->name, i.X.RT, i.X.RA,
-                    i.X.RB);
-}
-void Disasm_X_RT_RA0_RB(const InstrData& i, StringBuffer* str) {
-  if (i.X.RA) {
-    str->AppendFormat("%-8s r%d, r%d, r%d", i.opcode_info->name, i.X.RT, i.X.RA,
-                      i.X.RB);
-  } else {
-    str->AppendFormat("%-8s r%d, 0, r%d", i.opcode_info->name, i.X.RT, i.X.RB);
-  }
-}
-void Disasm_X_FRT_RA_RB(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s f%d, r%d, r%d", i.opcode_info->name, i.X.RT, i.X.RA,
-                    i.X.RB);
-}
-void Disasm_X_FRT_RA0_RB(const InstrData& i, StringBuffer* str) {
-  if (i.X.RA) {
-    str->AppendFormat("%-8s f%d, r%d, r%d", i.opcode_info->name, i.X.RT, i.X.RA,
-                      i.X.RB);
-  } else {
-    str->AppendFormat("%-8s f%d, 0, r%d", i.opcode_info->name, i.X.RT, i.X.RB);
-  }
-}
-void Disasm_D_RT_RA_I(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s r%d, r%d, %d", i.opcode_info->name, i.D.RT, i.D.RA,
-                    (int32_t)(int16_t)XEEXTS16(i.D.DS));
-}
-void Disasm_D_RT_RA0_I(const InstrData& i, StringBuffer* str) {
-  if (i.D.RA) {
-    str->AppendFormat("%-8s r%d, r%d, %d", i.opcode_info->name, i.D.RT, i.D.RA,
-                      (int32_t)(int16_t)XEEXTS16(i.D.DS));
-  } else {
-    str->AppendFormat("%-8s r%d, 0, %d", i.opcode_info->name, i.D.RT,
-                      (int32_t)(int16_t)XEEXTS16(i.D.DS));
-  }
-}
-void Disasm_D_FRT_RA_I(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s f%d, r%d, %d", i.opcode_info->name, i.D.RT, i.D.RA,
-                    (int32_t)(int16_t)XEEXTS16(i.D.DS));
-}
-void Disasm_D_FRT_RA0_I(const InstrData& i, StringBuffer* str) {
-  if (i.D.RA) {
-    str->AppendFormat("%-8s f%d, r%d, %d", i.opcode_info->name, i.D.RT, i.D.RA,
-                      (int32_t)(int16_t)XEEXTS16(i.D.DS));
-  } else {
-    str->AppendFormat("%-8s f%d, 0, %d", i.opcode_info->name, i.D.RT,
-                      (int32_t)(int16_t)XEEXTS16(i.D.DS));
-  }
-}
-void Disasm_DS_RT_RA_I(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s r%d, r%d, %d", i.opcode_info->name, i.DS.RT, i.DS.RA,
-                    (int32_t)(int16_t)XEEXTS16(i.DS.DS << 2));
-}
-void Disasm_DS_RT_RA0_I(const InstrData& i, StringBuffer* str) {
-  if (i.DS.RA) {
-    str->AppendFormat("%-8s r%d, r%d, %d", i.opcode_info->name, i.DS.RT,
-                      i.DS.RA, (int32_t)(int16_t)XEEXTS16(i.DS.DS << 2));
-  } else {
-    str->AppendFormat("%-8s r%d, 0, %d", i.opcode_info->name, i.DS.RT,
-                      (int32_t)(int16_t)XEEXTS16(i.DS.DS << 2));
-  }
-}
-void Disasm_D_RA(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s r%d", i.opcode_info->name, i.D.RA);
-}
-void Disasm_X_RA_RB(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s r%d, r%d", i.opcode_info->name, i.X.RA, i.X.RB);
-}
-void Disasm_XO_RT_RA_RB(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%*s%s%s r%d, r%d, r%d", i.XO.Rc ? -7 : -8,
-                    i.opcode_info->name, i.XO.OE ? "o" : "", i.XO.Rc ? "." : "",
-                    i.XO.RT, i.XO.RA, i.XO.RB);
-}
-void Disasm_XO_RT_RA(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%*s%s%s r%d, r%d", i.XO.Rc ? -7 : -8, i.opcode_info->name,
-                    i.XO.OE ? "o" : "", i.XO.Rc ? "." : "", i.XO.RT, i.XO.RA);
-}
-void Disasm_X_RA_RT_RB(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%*s%s r%d, r%d, r%d", i.X.Rc ? -7 : -8,
-                    i.opcode_info->name, i.X.Rc ? "." : "", i.X.RA, i.X.RT,
-                    i.X.RB);
-}
-void Disasm_D_RA_RT_I(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-7s. r%d, r%d, %.4Xh", i.opcode_info->name, i.D.RA,
-                    i.D.RT, i.D.DS);
-}
-void Disasm_X_RA_RT(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%*s%s r%d, r%d", i.X.Rc ? -7 : -8, i.opcode_info->name,
-                    i.X.Rc ? "." : "", i.X.RA, i.X.RT);
-}
-
-#define OP(x) ((((uint32_t)(x)) & 0x3f) << 26)
-#define VX128(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x3d0))
-#define VX128_1(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x7f3))
-#define VX128_2(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x210))
-#define VX128_3(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x7f0))
-#define VX128_4(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x730))
-#define VX128_5(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x10))
-#define VX128_P(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x630))
-
-#define VX128_VD128 (i.VX128.VD128l | (i.VX128.VD128h << 5))
-#define VX128_VA128 \
-  (i.VX128.VA128l | (i.VX128.VA128h << 5) | (i.VX128.VA128H << 6))
-#define VX128_VB128 (i.VX128.VB128l | (i.VX128.VB128h << 5))
-#define VX128_1_VD128 (i.VX128_1.VD128l | (i.VX128_1.VD128h << 5))
-#define VX128_2_VD128 (i.VX128_2.VD128l | (i.VX128_2.VD128h << 5))
-#define VX128_2_VA128 \
-  (i.VX128_2.VA128l | (i.VX128_2.VA128h << 5) | (i.VX128_2.VA128H << 6))
-#define VX128_2_VB128 (i.VX128_2.VB128l | (i.VX128_2.VB128h << 5))
-#define VX128_2_VC (i.VX128_2.VC)
-#define VX128_3_VD128 (i.VX128_3.VD128l | (i.VX128_3.VD128h << 5))
-#define VX128_3_VB128 (i.VX128_3.VB128l | (i.VX128_3.VB128h << 5))
-#define VX128_3_IMM (i.VX128_3.IMM)
-#define VX128_4_VD128 (i.VX128_4.VD128l | (i.VX128_4.VD128h << 5))
-#define VX128_4_VB128 (i.VX128_4.VB128l | (i.VX128_4.VB128h << 5))
-#define VX128_5_VD128 (i.VX128_5.VD128l | (i.VX128_5.VD128h << 5))
-#define VX128_5_VA128 \
-  (i.VX128_5.VA128l | (i.VX128_5.VA128h << 5)) | (i.VX128_5.VA128H << 6)
-#define VX128_5_VB128 (i.VX128_5.VB128l | (i.VX128_5.VB128h << 5))
-#define VX128_5_SH (i.VX128_5.SH)
-#define VX128_R_VD128 (i.VX128_R.VD128l | (i.VX128_R.VD128h << 5))
-#define VX128_R_VA128 \
-  (i.VX128_R.VA128l | (i.VX128_R.VA128h << 5) | (i.VX128_R.VA128H << 6))
-#define VX128_R_VB128 (i.VX128_R.VB128l | (i.VX128_R.VB128h << 5))
-
-void Disasm_X_VX_RA0_RB(const InstrData& i, StringBuffer* str) {
-  if (i.X.RA) {
-    str->AppendFormat("%-8s v%d, r%d, r%d", i.opcode_info->name, i.X.RT, i.X.RA,
-                      i.X.RB);
-  } else {
-    str->AppendFormat("%-8s v%d, 0, r%d", i.opcode_info->name, i.X.RT, i.X.RB);
-  }
-}
-void Disasm_VX1281_VD_RA0_RB(const InstrData& i, StringBuffer* str) {
-  const uint32_t vd = VX128_1_VD128;
-  if (i.VX128_1.RA) {
-    str->AppendFormat("%-8s v%d, r%d, r%d", i.opcode_info->name, vd,
-                      i.VX128_1.RA, i.VX128_1.RB);
-  } else {
-    str->AppendFormat("%-8s v%d, 0, r%d", i.opcode_info->name, vd,
-                      i.VX128_1.RB);
-  }
-}
-void Disasm_VX1283_VD_VB(const InstrData& i, StringBuffer* str) {
-  const uint32_t vd = VX128_3_VD128;
-  const uint32_t vb = VX128_3_VB128;
-  str->AppendFormat("%-8s v%d, v%d", i.opcode_info->name, vd, vb);
-}
-void Disasm_VX1283_VD_VB_I(const InstrData& i, StringBuffer* str) {
-  const uint32_t vd = VX128_VD128;
-  const uint32_t va = VX128_VA128;
-  const uint32_t uimm = i.VX128_3.IMM;
-  str->AppendFormat("%-8s v%d, v%d, %.2Xh", i.opcode_info->name, vd, va, uimm);
-}
-void Disasm_VX_VD_VA_VB(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s v%d, v%d, v%d", i.opcode_info->name, i.VX.VD, i.VX.VA,
-                    i.VX.VB);
-}
-void Disasm_VX128_VD_VA_VB(const InstrData& i, StringBuffer* str) {
-  const uint32_t vd = VX128_VD128;
-  const uint32_t va = VX128_VA128;
-  const uint32_t vb = VX128_VB128;
-  str->AppendFormat("%-8s v%d, v%d, v%d", i.opcode_info->name, vd, va, vb);
-}
-void Disasm_VX128_VD_VA_VD_VB(const InstrData& i, StringBuffer* str) {
-  const uint32_t vd = VX128_VD128;
-  const uint32_t va = VX128_VA128;
-  const uint32_t vb = VX128_VB128;
-  str->AppendFormat("%-8s v%d, v%d, v%d, v%d", i.opcode_info->name, vd, va, vd,
-                    vb);
-}
-void Disasm_VX1282_VD_VA_VB_VC(const InstrData& i, StringBuffer* str) {
-  const uint32_t vd = VX128_2_VD128;
-  const uint32_t va = VX128_2_VA128;
-  const uint32_t vb = VX128_2_VB128;
-  const uint32_t vc = i.VX128_2.VC;
-  str->AppendFormat("%-8s v%d, v%d, v%d, v%d", i.opcode_info->name, vd, va, vb,
-                    vc);
-}
-void Disasm_VXA_VD_VA_VB_VC(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s v%d, v%d, v%d, v%d", i.opcode_info->name, i.VXA.VD,
-                    i.VXA.VA, i.VXA.VB, i.VXA.VC);
-}
-
-void Disasm_sync(const InstrData& i, StringBuffer* str) {
-  const char* name;
-  int L = i.X.RT & 3;
-  switch (L) {
-    case 0:
-      name = "hwsync";
-      break;
-    case 1:
-      name = "lwsync";
-      break;
-    default:
-    case 2:
-    case 3:
-      name = "sync";
-      break;
-  }
-  str->AppendFormat("%-8s %.2X", name, L);
-}
-
-void Disasm_dcbf(const InstrData& i, StringBuffer* str) {
-  const char* name;
-  switch (i.X.RT & 3) {
-    case 0:
-      name = "dcbf";
-      break;
-    case 1:
-      name = "dcbfl";
-      break;
-    case 2:
-      name = "dcbf.RESERVED";
-      break;
-    case 3:
-      name = "dcbflp";
-      break;
-    default:
-      name = "dcbf.??";
-      break;
-  }
-  str->AppendFormat("%-8s r%d, r%d", name, i.X.RA, i.X.RB);
-}
-
-void Disasm_dcbz(const InstrData& i, StringBuffer* str) {
-  // or dcbz128 0x7C2007EC
-  if (i.X.RA) {
-    str->AppendFormat("%-8s r%d, r%d", i.opcode_info->name, i.X.RA, i.X.RB);
-  } else {
-    str->AppendFormat("%-8s 0, r%d", i.opcode_info->name, i.X.RB);
-  }
-}
-
-void Disasm_fcmp(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s cr%d, f%d, f%d", i.opcode_info->name, i.X.RT >> 2,
-                    i.X.RA, i.X.RB);
-}
-
-void Disasm_mffsx(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%*s%s f%d, FPSCR", i.X.Rc ? -7 : -8, i.opcode_info->name,
-                    i.X.Rc ? "." : "", i.X.RT);
-}
-
-void Disasm_bx(const InstrData& i, StringBuffer* str) {
-  const char* name = i.I.LK ? "bl" : "b";
-  uint32_t nia;
-  if (i.I.AA) {
-    nia = (uint32_t)XEEXTS26(i.I.LI << 2);
-  } else {
-    nia = (uint32_t)(i.address + XEEXTS26(i.I.LI << 2));
-  }
-  str->AppendFormat("%-8s %.8X", name, nia);
-  // TODO(benvanik): resolve target name?
-}
-void Disasm_bcx(const InstrData& i, StringBuffer* str) {
-  const char* s0 = i.B.LK ? "lr, " : "";
-  const char* s1;
-  if (!select_bits(i.B.BO, 2, 2)) {
-    s1 = "ctr, ";
-  } else {
-    s1 = "";
-  }
-  char s2[8] = {0};
-  if (!select_bits(i.B.BO, 4, 4)) {
-    snprintf(s2, xe::countof(s2), "cr%d, ", i.B.BI >> 2);
-  }
-  uint32_t nia;
-  if (i.B.AA) {
-    nia = (uint32_t)XEEXTS16(i.B.BD << 2);
-  } else {
-    nia = (uint32_t)(i.address + XEEXTS16(i.B.BD << 2));
-  }
-  str->AppendFormat("%-8s %s%s%s%.8X", i.opcode_info->name, s0, s1, s2, nia);
-  // TODO(benvanik): resolve target name?
-}
-void Disasm_bcctrx(const InstrData& i, StringBuffer* str) {
-  // TODO(benvanik): mnemonics
-  const char* s0 = i.XL.LK ? "lr, " : "";
-  char s2[8] = {0};
-  if (!select_bits(i.XL.BO, 4, 4)) {
-    snprintf(s2, xe::countof(s2), "cr%d, ", i.XL.BI >> 2);
-  }
-  str->AppendFormat("%-8s %s%sctr", i.opcode_info->name, s0, s2);
-  // TODO(benvanik): resolve target name?
-}
-void Disasm_bclrx(const InstrData& i, StringBuffer* str) {
-  const char* name = "bclr";
-  if (i.code == 0x4E800020) {
-    name = "blr";
-  }
-  const char* s1;
-  if (!select_bits(i.XL.BO, 2, 2)) {
-    s1 = "ctr, ";
-  } else {
-    s1 = "";
-  }
-  char s2[8] = {0};
-  if (!select_bits(i.XL.BO, 4, 4)) {
-    snprintf(s2, xe::countof(s2), "cr%d, ", i.XL.BI >> 2);
-  }
-  str->AppendFormat("%-8s %s%s", name, s1, s2);
-}
-
-void Disasm_mfcr(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s r%d, cr", i.opcode_info->name, i.X.RT);
-}
-const char* Disasm_spr_name(uint32_t n) {
-  const char* reg = "???";
-  switch (n) {
-    case 1:
-      reg = "xer";
-      break;
-    case 8:
-      reg = "lr";
-      break;
-    case 9:
-      reg = "ctr";
-      break;
-  }
-  return reg;
-}
-void Disasm_mfspr(const InstrData& i, StringBuffer* str) {
-  const uint32_t n = ((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F);
-  const char* reg = Disasm_spr_name(n);
-  str->AppendFormat("%-8s r%d, %s", i.opcode_info->name, i.XFX.RT, reg);
-}
-void Disasm_mtspr(const InstrData& i, StringBuffer* str) {
-  const uint32_t n = ((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F);
-  const char* reg = Disasm_spr_name(n);
-  str->AppendFormat("%-8s %s, r%d", i.opcode_info->name, reg, i.XFX.RT);
-}
-void Disasm_mftb(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s r%d, tb", i.opcode_info->name, i.XFX.RT);
-}
-void Disasm_mfmsr(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s r%d", i.opcode_info->name, i.X.RT);
-}
-void Disasm_mtmsr(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s r%d, %d", i.opcode_info->name, i.X.RT,
-                    (i.X.RA & 16) ? 1 : 0);
-}
-
-void Disasm_cmp(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s cr%d, %.2X, r%d, r%d", i.opcode_info->name,
-                    i.X.RT >> 2, i.X.RT & 1, i.X.RA, i.X.RB);
-}
-void Disasm_cmpi(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s cr%d, %.2X, r%d, %d", i.opcode_info->name,
-                    i.D.RT >> 2, i.D.RT & 1, i.D.RA, XEEXTS16(i.D.DS));
-}
-void Disasm_cmpli(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s cr%d, %.2X, r%d, %.2X", i.opcode_info->name,
-                    i.D.RT >> 2, i.D.RT & 1, i.D.RA, XEEXTS16(i.D.DS));
-}
-
-void Disasm_rld(const InstrData& i, StringBuffer* str) {
-  if (i.MD.idx == 0) {
-    // XEDISASMR(rldiclx,      0x78000000, MD )
-    str->AppendFormat("%*s%s r%d, r%d, %d, %d", i.MD.Rc ? -7 : -8, "rldicl",
-                      i.MD.Rc ? "." : "", i.MD.RA, i.MD.RT,
-                      (i.MD.SH5 << 5) | i.MD.SH, (i.MD.MB5 << 5) | i.MD.MB);
-  } else if (i.MD.idx == 1) {
-    // XEDISASMR(rldicrx,      0x78000004, MD )
-    str->AppendFormat("%*s%s r%d, r%d, %d, %d", i.MD.Rc ? -7 : -8, "rldicr",
-                      i.MD.Rc ? "." : "", i.MD.RA, i.MD.RT,
-                      (i.MD.SH5 << 5) | i.MD.SH, (i.MD.MB5 << 5) | i.MD.MB);
-  } else if (i.MD.idx == 2) {
-    // XEDISASMR(rldicx,       0x78000008, MD )
-    uint32_t sh = (i.MD.SH5 << 5) | i.MD.SH;
-    uint32_t mb = (i.MD.MB5 << 5) | i.MD.MB;
-    const char* name = (mb == 0x3E) ? "sldi" : "rldic";
-    str->AppendFormat("%*s%s r%d, r%d, %d, %d", i.MD.Rc ? -7 : -8, name,
-                      i.MD.Rc ? "." : "", i.MD.RA, i.MD.RT, sh, mb);
-  } else if (i.MDS.idx == 8) {
-    // XEDISASMR(rldclx,       0x78000010, MDS)
-    str->AppendFormat("%*s%s r%d, r%d, %d, %d", i.MDS.Rc ? -7 : -8, "rldcl",
-                      i.MDS.Rc ? "." : "", i.MDS.RA, i.MDS.RT, i.MDS.RB,
-                      (i.MDS.MB5 << 5) | i.MDS.MB);
-  } else if (i.MDS.idx == 9) {
-    // XEDISASMR(rldcrx,       0x78000012, MDS)
-    str->AppendFormat("%*s%s r%d, r%d, %d, %d", i.MDS.Rc ? -7 : -8, "rldcr",
-                      i.MDS.Rc ? "." : "", i.MDS.RA, i.MDS.RT, i.MDS.RB,
-                      (i.MDS.MB5 << 5) | i.MDS.MB);
-  } else if (i.MD.idx == 3) {
-    // XEDISASMR(rldimix,      0x7800000C, MD )
-    str->AppendFormat("%*s%s r%d, r%d, %d, %d", i.MD.Rc ? -7 : -8, "rldimi",
-                      i.MD.Rc ? "." : "", i.MD.RA, i.MD.RT,
-                      (i.MD.SH5 << 5) | i.MD.SH, (i.MD.MB5 << 5) | i.MD.MB);
-  } else {
-    assert_always();
-  }
-}
-void Disasm_rlwim(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%*s%s r%d, r%d, %d, %d, %d", i.M.Rc ? -7 : -8,
-                    i.opcode_info->name, i.M.Rc ? "." : "", i.M.RA, i.M.RT,
-                    i.M.SH, i.M.MB, i.M.ME);
-}
-void Disasm_rlwnmx(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%*s%s r%d, r%d, r%d, %d, %d", i.M.Rc ? -7 : -8,
-                    i.opcode_info->name, i.M.Rc ? "." : "", i.M.RA, i.M.RT,
-                    i.M.SH, i.M.MB, i.M.ME);
-}
-void Disasm_srawix(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%*s%s r%d, r%d, %d", i.X.Rc ? -7 : -8, i.opcode_info->name,
-                    i.X.Rc ? "." : "", i.X.RA, i.X.RT, i.X.RB);
-}
-void Disasm_sradix(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%*s%s r%d, r%d, %d", i.XS.Rc ? -7 : -8,
-                    i.opcode_info->name, i.XS.Rc ? "." : "", i.XS.RA, i.XS.RT,
-                    (i.XS.SH5 << 5) | i.XS.SH);
-}
-
-void Disasm_vpermwi128(const InstrData& i, StringBuffer* str) {
-  const uint32_t vd = i.VX128_P.VD128l | (i.VX128_P.VD128h << 5);
-  const uint32_t vb = i.VX128_P.VB128l | (i.VX128_P.VB128h << 5);
-  str->AppendFormat("%-8s v%d, v%d, %.2X", i.opcode_info->name, vd, vb,
-                    i.VX128_P.PERMl | (i.VX128_P.PERMh << 5));
-}
-void Disasm_vrfin128(const InstrData& i, StringBuffer* str) {
-  const uint32_t vd = VX128_3_VD128;
-  const uint32_t vb = VX128_3_VB128;
-  str->AppendFormat("%-8s v%d, v%d", i.opcode_info->name, vd, vb);
-}
-void Disasm_vrlimi128(const InstrData& i, StringBuffer* str) {
-  const uint32_t vd = VX128_4_VD128;
-  const uint32_t vb = VX128_4_VB128;
-  str->AppendFormat("%-8s v%d, v%d, %.2X, %.2X", i.opcode_info->name, vd, vb,
-                    i.VX128_4.IMM, i.VX128_4.z);
-}
-void Disasm_vsldoi128(const InstrData& i, StringBuffer* str) {
-  const uint32_t vd = VX128_5_VD128;
-  const uint32_t va = VX128_5_VA128;
-  const uint32_t vb = VX128_5_VB128;
-  const uint32_t sh = i.VX128_5.SH;
-  str->AppendFormat("%-8s v%d, v%d, v%d, %.2X", i.opcode_info->name, vd, va, vb,
-                    sh);
-}
-void Disasm_vspltb(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s v%d, v%d, %.2X", i.opcode_info->name, i.VX.VD,
-                    i.VX.VB, i.VX.VA & 0xF);
-}
-void Disasm_vsplth(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s v%d, v%d, %.2X", i.opcode_info->name, i.VX.VD,
-                    i.VX.VB, i.VX.VA & 0x7);
-}
-void Disasm_vspltw(const InstrData& i, StringBuffer* str) {
-  str->AppendFormat("%-8s v%d, v%d, %.2X", i.opcode_info->name, i.VX.VD,
-                    i.VX.VB, i.VX.VA);
-}
-void Disasm_vspltisb(const InstrData& i, StringBuffer* str) {
-  // 5bit -> 8bit sign extend
-  int8_t simm = (i.VX.VA & 0x10) ? (i.VX.VA | 0xF0) : i.VX.VA;
-  str->AppendFormat("%-8s v%d, %.2X", i.opcode_info->name, i.VX.VD, simm);
-}
-void Disasm_vspltish(const InstrData& i, StringBuffer* str) {
-  // 5bit -> 16bit sign extend
-  int16_t simm = (i.VX.VA & 0x10) ? (i.VX.VA | 0xFFF0) : i.VX.VA;
-  str->AppendFormat("%-8s v%d, %.4X", i.opcode_info->name, i.VX.VD, simm);
-}
-void Disasm_vspltisw(const InstrData& i, StringBuffer* str) {
-  // 5bit -> 32bit sign extend
-  int32_t simm = (i.VX.VA & 0x10) ? (i.VX.VA | 0xFFFFFFF0) : i.VX.VA;
-  str->AppendFormat("%-8s v%d, %.8X", i.opcode_info->name, i.VX.VD, simm);
-}
-
-int DisasmPPC(uint32_t address, uint32_t code, StringBuffer* str) {
-  InstrData i;
-  i.address = address;
-  i.code = code;
-  i.opcode = LookupOpcode(code);
-  if (i.opcode == PPCOpcode::kInvalid) {
-    str->Append("???");
-  } else {
-    i.opcode_info = &GetOpcodeInfo(i.opcode);
-    GetInstrType(code)->disasm(i, str);
-  }
-  return 0;
-}
-
-}  // namespace ppc
-}  // namespace cpu
-}  // namespace xe
diff --git a/src/xenia/cpu/ppc/ppc_disasm.h b/src/xenia/cpu/ppc/ppc_disasm.h
deleted file mode 100644
index 2f983ee2c..000000000
--- a/src/xenia/cpu/ppc/ppc_disasm.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/**
- ******************************************************************************
- * Xenia : Xbox 360 Emulator Research Project                                 *
- ******************************************************************************
- * Copyright 2013 Ben Vanik. All rights reserved.                             *
- * Released under the BSD license - see LICENSE in the root for more details. *
- ******************************************************************************
- */
-
-#ifndef XENIA_CPU_PPC_PPC_DISASM_H_
-#define XENIA_CPU_PPC_PPC_DISASM_H_
-
-#include "xenia/base/string_buffer.h"
-
-namespace xe {
-namespace cpu {
-namespace ppc {
-
-int DisasmPPC(uint32_t address, uint32_t code, StringBuffer* str);
-
-}  // namespace ppc
-}  // namespace cpu
-}  // namespace xe
-
-#endif  // XENIA_CPU_PPC_PPC_DISASM_H_
diff --git a/src/xenia/cpu/ppc/ppc_emit-private.h b/src/xenia/cpu/ppc/ppc_emit-private.h
index 769a55f48..3e4449455 100644
--- a/src/xenia/cpu/ppc/ppc_emit-private.h
+++ b/src/xenia/cpu/ppc/ppc_emit-private.h
@@ -11,8 +11,8 @@
 #define XENIA_CPU_PPC_PPC_EMIT_PRIVATE_H_
 
 #include "xenia/base/logging.h"
+#include "xenia/cpu/ppc/ppc_decode_data.h"
 #include "xenia/cpu/ppc/ppc_emit.h"
-#include "xenia/cpu/ppc/ppc_instr.h"
 #include "xenia/cpu/ppc/ppc_opcode_info.h"
 
 namespace xe {
diff --git a/src/xenia/cpu/ppc/ppc_frontend.cc b/src/xenia/cpu/ppc/ppc_frontend.cc
index c95b63bf6..1696cadfa 100644
--- a/src/xenia/cpu/ppc/ppc_frontend.cc
+++ b/src/xenia/cpu/ppc/ppc_frontend.cc
@@ -11,8 +11,8 @@
 
 #include "xenia/base/atomic.h"
 #include "xenia/cpu/ppc/ppc_context.h"
-#include "xenia/cpu/ppc/ppc_disasm.h"
 #include "xenia/cpu/ppc/ppc_emit.h"
+#include "xenia/cpu/ppc/ppc_opcode_info.h"
 #include "xenia/cpu/ppc/ppc_translator.h"
 #include "xenia/cpu/processor.h"
 
diff --git a/src/xenia/cpu/ppc/ppc_hir_builder.cc b/src/xenia/cpu/ppc/ppc_hir_builder.cc
index 8fc221a4f..a69d80016 100644
--- a/src/xenia/cpu/ppc/ppc_hir_builder.cc
+++ b/src/xenia/cpu/ppc/ppc_hir_builder.cc
@@ -18,9 +18,8 @@
 #include "xenia/cpu/cpu_flags.h"
 #include "xenia/cpu/hir/label.h"
 #include "xenia/cpu/ppc/ppc_context.h"
-#include "xenia/cpu/ppc/ppc_disasm.h"
+#include "xenia/cpu/ppc/ppc_decode_data.h"
 #include "xenia/cpu/ppc/ppc_frontend.h"
-#include "xenia/cpu/ppc/ppc_instr.h"
 #include "xenia/cpu/ppc/ppc_opcode_info.h"
 #include "xenia/cpu/processor.h"
 
@@ -45,9 +44,10 @@ void DumpAllOpcodeCounts() {
   for (size_t i = 0; i < xe::countof(opcode_translation_counts); ++i) {
     auto opcode = static_cast<PPCOpcode>(i);
     auto& opcode_info = GetOpcodeInfo(opcode);
+    auto& disasm_info = GetOpcodeDisasmInfo(opcode);
     auto translation_count = opcode_translation_counts[i];
     if (translation_count) {
-      sb.AppendFormat("%8d : %s\n", translation_count, opcode_info.name);
+      sb.AppendFormat("%8d : %s\n", translation_count, disasm_info.name);
     }
   }
   fprintf(stdout, "%s", sb.GetString());
@@ -179,8 +179,9 @@ bool PPCHIRBuilder::Emit(GuestFunction* function, uint32_t flags) {
     i.opcode = opcode;
     i.opcode_info = &opcode_info;
     if (!opcode_info.emit || opcode_info.emit(*this, i)) {
+      auto& disasm_info = GetOpcodeDisasmInfo(opcode);
       XELOGE("Unimplemented instr %.8llX %.8X %s", address, code,
-             opcode_info.name);
+             disasm_info.name);
       Comment("UNIMPLEMENTED!");
       DebugBreak();
     }
diff --git a/src/xenia/cpu/ppc/ppc_instr.cc b/src/xenia/cpu/ppc/ppc_instr.cc
deleted file mode 100644
index 075336c19..000000000
--- a/src/xenia/cpu/ppc/ppc_instr.cc
+++ /dev/null
@@ -1,383 +0,0 @@
-/**
- ******************************************************************************
- * Xenia : Xbox 360 Emulator Research Project                                 *
- ******************************************************************************
- * Copyright 2013 Ben Vanik. All rights reserved.                             *
- * Released under the BSD license - see LICENSE in the root for more details. *
- ******************************************************************************
- */
-
-#include "xenia/cpu/ppc/ppc_instr.h"
-
-#include <cinttypes>
-#include <sstream>
-#include <vector>
-
-#include "xenia/base/assert.h"
-#include "xenia/base/math.h"
-#include "xenia/base/string_buffer.h"
-#include "xenia/cpu/ppc/ppc_instr_tables.h"
-
-namespace xe {
-namespace cpu {
-namespace ppc {
-
-void InstrOperand::Dump(std::string& out_str) {
-  if (display) {
-    out_str += display;
-    return;
-  }
-
-  char buffer[32];
-  const size_t max_count = xe::countof(buffer);
-  switch (type) {
-    case InstrOperand::kRegister:
-      switch (reg.set) {
-        case InstrRegister::kXER:
-          snprintf(buffer, max_count, "XER");
-          break;
-        case InstrRegister::kLR:
-          snprintf(buffer, max_count, "LR");
-          break;
-        case InstrRegister::kCTR:
-          snprintf(buffer, max_count, "CTR");
-          break;
-        case InstrRegister::kCR:
-          snprintf(buffer, max_count, "CR%d", reg.ordinal);
-          break;
-        case InstrRegister::kFPSCR:
-          snprintf(buffer, max_count, "FPSCR");
-          break;
-        case InstrRegister::kGPR:
-          snprintf(buffer, max_count, "r%d", reg.ordinal);
-          break;
-        case InstrRegister::kFPR:
-          snprintf(buffer, max_count, "f%d", reg.ordinal);
-          break;
-        case InstrRegister::kVMX:
-          snprintf(buffer, max_count, "vr%d", reg.ordinal);
-          break;
-      }
-      break;
-    case InstrOperand::kImmediate:
-      switch (imm.width) {
-        case 1:
-          if (imm.is_signed) {
-            snprintf(buffer, max_count, "%d", (int32_t)(int8_t)imm.value);
-          } else {
-            snprintf(buffer, max_count, "0x%.2X", (uint8_t)imm.value);
-          }
-          break;
-        case 2:
-          if (imm.is_signed) {
-            snprintf(buffer, max_count, "%d", (int32_t)(int16_t)imm.value);
-          } else {
-            snprintf(buffer, max_count, "0x%.4X", (uint16_t)imm.value);
-          }
-          break;
-        case 4:
-          if (imm.is_signed) {
-            snprintf(buffer, max_count, "%d", (int32_t)imm.value);
-          } else {
-            snprintf(buffer, max_count, "0x%.8X", (uint32_t)imm.value);
-          }
-          break;
-        case 8:
-          if (imm.is_signed) {
-            snprintf(buffer, max_count, "%" PRId64, (int64_t)imm.value);
-          } else {
-            snprintf(buffer, max_count, "0x%.16" PRIX64, imm.value);
-          }
-          break;
-      }
-      break;
-  }
-  out_str += buffer;
-}
-
-void InstrAccessBits::Clear() { spr = cr = gpr = fpr = 0; }
-
-void InstrAccessBits::Extend(InstrAccessBits& other) {
-  spr |= other.spr;
-  cr |= other.cr;
-  gpr |= other.gpr;
-  fpr |= other.fpr;
-  vr31_0 |= other.vr31_0;
-  vr63_32 |= other.vr63_32;
-  vr95_64 |= other.vr95_64;
-  vr127_96 |= other.vr127_96;
-}
-
-void InstrAccessBits::MarkAccess(InstrRegister& reg) {
-  uint64_t bits = 0;
-  if (reg.access & InstrRegister::kRead) {
-    bits |= 0x1;
-  }
-  if (reg.access & InstrRegister::kWrite) {
-    bits |= 0x2;
-  }
-
-  switch (reg.set) {
-    case InstrRegister::kXER:
-      spr |= bits << (2 * 0);
-      break;
-    case InstrRegister::kLR:
-      spr |= bits << (2 * 1);
-      break;
-    case InstrRegister::kCTR:
-      spr |= bits << (2 * 2);
-      break;
-    case InstrRegister::kCR:
-      cr |= bits << (2 * reg.ordinal);
-      break;
-    case InstrRegister::kFPSCR:
-      spr |= bits << (2 * 3);
-      break;
-    case InstrRegister::kGPR:
-      gpr |= bits << (2 * reg.ordinal);
-      break;
-    case InstrRegister::kFPR:
-      fpr |= bits << (2 * reg.ordinal);
-      break;
-    case InstrRegister::kVMX:
-      if (reg.ordinal < 32) {
-        vr31_0 |= bits << (2 * reg.ordinal);
-      } else if (reg.ordinal < 64) {
-        vr63_32 |= bits << (2 * (reg.ordinal - 32));
-      } else if (reg.ordinal < 96) {
-        vr95_64 |= bits << (2 * (reg.ordinal - 64));
-      } else {
-        vr127_96 |= bits << (2 * (reg.ordinal - 96));
-      }
-      break;
-    default:
-      assert_unhandled_case(reg.set);
-      break;
-  }
-}
-
-void InstrAccessBits::Dump(std::string& out_str) {
-  std::stringstream str;
-  if (spr) {
-    uint64_t spr_t = spr;
-    if (spr_t & 0x3) {
-      str << "XER [";
-      str << ((spr_t & 1) ? "R" : " ");
-      str << ((spr_t & 2) ? "W" : " ");
-      str << "] ";
-    }
-    spr_t >>= 2;
-    if (spr_t & 0x3) {
-      str << "LR [";
-      str << ((spr_t & 1) ? "R" : " ");
-      str << ((spr_t & 2) ? "W" : " ");
-      str << "] ";
-    }
-    spr_t >>= 2;
-    if (spr_t & 0x3) {
-      str << "CTR [";
-      str << ((spr_t & 1) ? "R" : " ");
-      str << ((spr_t & 2) ? "W" : " ");
-      str << "] ";
-    }
-    spr_t >>= 2;
-    if (spr_t & 0x3) {
-      str << "FPCSR [";
-      str << ((spr_t & 1) ? "R" : " ");
-      str << ((spr_t & 2) ? "W" : " ");
-      str << "] ";
-    }
-    spr_t >>= 2;
-  }
-
-  if (cr) {
-    uint64_t cr_t = cr;
-    for (size_t n = 0; n < 8; n++) {
-      if (cr_t & 0x3) {
-        str << "cr" << n << " [";
-        str << ((cr_t & 1) ? "R" : " ");
-        str << ((cr_t & 2) ? "W" : " ");
-        str << "] ";
-      }
-      cr_t >>= 2;
-    }
-  }
-
-  if (gpr) {
-    uint64_t gpr_t = gpr;
-    for (size_t n = 0; n < 32; n++) {
-      if (gpr_t & 0x3) {
-        str << "r" << n << " [";
-        str << ((gpr_t & 1) ? "R" : " ");
-        str << ((gpr_t & 2) ? "W" : " ");
-        str << "] ";
-      }
-      gpr_t >>= 2;
-    }
-  }
-
-  if (fpr) {
-    uint64_t fpr_t = fpr;
-    for (size_t n = 0; n < 32; n++) {
-      if (fpr_t & 0x3) {
-        str << "f" << n << " [";
-        str << ((fpr_t & 1) ? "R" : " ");
-        str << ((fpr_t & 2) ? "W" : " ");
-        str << "] ";
-      }
-      fpr_t >>= 2;
-    }
-  }
-
-  if (vr31_0) {
-    uint64_t vr31_0_t = vr31_0;
-    for (size_t n = 0; n < 32; n++) {
-      if (vr31_0_t & 0x3) {
-        str << "vr" << n << " [";
-        str << ((vr31_0_t & 1) ? "R" : " ");
-        str << ((vr31_0_t & 2) ? "W" : " ");
-        str << "] ";
-      }
-      vr31_0_t >>= 2;
-    }
-  }
-  if (vr63_32) {
-    uint64_t vr63_32_t = vr63_32;
-    for (size_t n = 0; n < 32; n++) {
-      if (vr63_32_t & 0x3) {
-        str << "vr" << (n + 32) << " [";
-        str << ((vr63_32_t & 1) ? "R" : " ");
-        str << ((vr63_32_t & 2) ? "W" : " ");
-        str << "] ";
-      }
-      vr63_32_t >>= 2;
-    }
-  }
-  if (vr95_64) {
-    uint64_t vr95_64_t = vr95_64;
-    for (size_t n = 0; n < 32; n++) {
-      if (vr95_64_t & 0x3) {
-        str << "vr" << (n + 64) << " [";
-        str << ((vr95_64_t & 1) ? "R" : " ");
-        str << ((vr95_64_t & 2) ? "W" : " ");
-        str << "] ";
-      }
-      vr95_64_t >>= 2;
-    }
-  }
-  if (vr127_96) {
-    uint64_t vr127_96_t = vr127_96;
-    for (size_t n = 0; n < 32; n++) {
-      if (vr127_96_t & 0x3) {
-        str << "vr" << (n + 96) << " [";
-        str << ((vr127_96_t & 1) ? "R" : " ");
-        str << ((vr127_96_t & 2) ? "W" : " ");
-        str << "] ";
-      }
-      vr127_96_t >>= 2;
-    }
-  }
-
-  out_str = str.str();
-}
-
-void InstrDisasm::Init(const char* new_name, const char* new_info,
-                       uint32_t new_flags) {
-  name = new_name;
-  info = new_info;
-  flags = new_flags;
-}
-
-void InstrDisasm::AddLR(InstrRegister::Access access) {}
-
-void InstrDisasm::AddCTR(InstrRegister::Access access) {}
-
-void InstrDisasm::AddCR(uint32_t bf, InstrRegister::Access access) {}
-
-void InstrDisasm::AddFPSCR(InstrRegister::Access access) {}
-
-void InstrDisasm::AddRegOperand(InstrRegister::RegisterSet set,
-                                uint32_t ordinal, InstrRegister::Access access,
-                                const char* display) {}
-
-void InstrDisasm::AddSImmOperand(uint64_t value, size_t width,
-                                 const char* display) {}
-
-void InstrDisasm::AddUImmOperand(uint64_t value, size_t width,
-                                 const char* display) {}
-
-int InstrDisasm::Finish() { return 0; }
-
-void InstrDisasm::Dump(std::string& out_str, size_t pad) {
-  out_str = name;
-  if (flags & InstrDisasm::kOE) {
-    out_str += "o";
-  }
-  if (flags & InstrDisasm::kRc) {
-    out_str += ".";
-  }
-  if (flags & InstrDisasm::kLR) {
-    out_str += "l";
-  }
-}
-
-InstrType* GetInstrType(uint32_t code) {
-  // Fast lookup via tables.
-  InstrType* slot = NULL;
-  switch (code >> 26) {
-    case 4:
-      // Opcode = 4, index = bits 10-0 (10)
-      slot = tables::instr_table_4[select_bits(code, 0, 10)];
-      break;
-    case 19:
-      // Opcode = 19, index = bits 10-1 (10)
-      slot = tables::instr_table_19[select_bits(code, 1, 10)];
-      break;
-    case 30:
-      // Opcode = 30, index = bits 4-1 (4)
-      // Special cased to an uber instruction.
-      slot = tables::instr_table_30[select_bits(code, 0, 0)];
-      break;
-    case 31:
-      // Opcode = 31, index = bits 10-1 (10)
-      slot = tables::instr_table_31[select_bits(code, 1, 10)];
-      break;
-    case 58:
-      // Opcode = 58, index = bits 1-0 (2)
-      slot = tables::instr_table_58[select_bits(code, 0, 1)];
-      break;
-    case 59:
-      // Opcode = 59, index = bits 5-1 (5)
-      slot = tables::instr_table_59[select_bits(code, 1, 5)];
-      break;
-    case 62:
-      // Opcode = 62, index = bits 1-0 (2)
-      slot = tables::instr_table_62[select_bits(code, 0, 1)];
-      break;
-    case 63:
-      // Opcode = 63, index = bits 10-1 (10)
-      slot = tables::instr_table_63[select_bits(code, 1, 10)];
-      break;
-    default:
-      slot = tables::instr_table[select_bits(code, 26, 31)];
-      break;
-  }
-  if (slot && slot->opcode) {
-    return slot;
-  }
-
-  // Slow lookup via linear scan.
-  // This is primarily due to laziness. It could be made fast like the others.
-  for (size_t n = 0; n < xe::countof(tables::instr_table_scan); n++) {
-    slot = &(tables::instr_table_scan[n]);
-    if (slot->opcode == (code & slot->opcode_mask)) {
-      return slot;
-    }
-  }
-
-  return NULL;
-}
-
-}  // namespace ppc
-}  // namespace cpu
-}  // namespace xe
diff --git a/src/xenia/cpu/ppc/ppc_instr.h b/src/xenia/cpu/ppc/ppc_instr.h
index 81753dd1d..2b76392d3 100644
--- a/src/xenia/cpu/ppc/ppc_instr.h
+++ b/src/xenia/cpu/ppc/ppc_instr.h
@@ -21,80 +21,8 @@ namespace xe {
 namespace cpu {
 namespace ppc {
 
-constexpr uint32_t make_bitmask(uint32_t a, uint32_t b) {
-  return (static_cast<uint32_t>(-1) >> (31 - b)) & ~((1u << a) - 1);
-}
-
-constexpr uint32_t select_bits(uint32_t value, uint32_t a, uint32_t b) {
-  return (value & make_bitmask(a, b)) >> a;
-}
-
-// TODO(benvanik): rename these
-typedef enum {
-  kXEPPCInstrFormatI = 0,
-  kXEPPCInstrFormatB = 1,
-  kXEPPCInstrFormatSC = 2,
-  kXEPPCInstrFormatD = 3,
-  kXEPPCInstrFormatDS = 4,
-  kXEPPCInstrFormatX = 5,
-  kXEPPCInstrFormatXL = 6,
-  kXEPPCInstrFormatXFX = 7,
-  kXEPPCInstrFormatXFL = 8,
-  kXEPPCInstrFormatXS = 9,
-  kXEPPCInstrFormatXO = 10,
-  kXEPPCInstrFormatA = 11,
-  kXEPPCInstrFormatM = 12,
-  kXEPPCInstrFormatMD = 13,
-  kXEPPCInstrFormatMDS = 14,
-  kXEPPCInstrFormatVXA = 15,
-  kXEPPCInstrFormatVX = 16,
-  kXEPPCInstrFormatVXR = 17,
-  kXEPPCInstrFormatVX128 = 18,
-  kXEPPCInstrFormatVX128_1 = 19,
-  kXEPPCInstrFormatVX128_2 = 20,
-  kXEPPCInstrFormatVX128_3 = 21,
-  kXEPPCInstrFormatVX128_4 = 22,
-  kXEPPCInstrFormatVX128_5 = 23,
-  kXEPPCInstrFormatVX128_P = 24,
-  kXEPPCInstrFormatVX128_R = 25,
-  kXEPPCInstrFormatXDSS = 26,
-} xe_ppc_instr_format_e;
-
-enum xe_ppc_instr_mask_e : uint32_t {
-  kXEPPCInstrMaskVXR = 0xFC0003FF,
-  kXEPPCInstrMaskVXA = 0xFC00003F,
-  kXEPPCInstrMaskVX128 = 0xFC0003D0,
-  kXEPPCInstrMaskVX128_1 = 0xFC0007F3,
-  kXEPPCInstrMaskVX128_2 = 0xFC000210,
-  kXEPPCInstrMaskVX128_3 = 0xFC0007F0,
-  kXEPPCInstrMaskVX128_4 = 0xFC000730,
-  kXEPPCInstrMaskVX128_5 = 0xFC000010,
-  kXEPPCInstrMaskVX128_P = 0xFC000630,
-  kXEPPCInstrMaskVX128_R = 0xFC000390,
-};
-
-class InstrType;
-
-constexpr int64_t XEEXTS16(uint32_t v) { return (int64_t)((int16_t)v); }
-constexpr int64_t XEEXTS26(uint32_t v) {
-  return (int64_t)(v & 0x02000000 ? (int32_t)v | 0xFC000000 : (int32_t)(v));
-}
-constexpr uint64_t XEEXTZ16(uint32_t v) { return (uint64_t)((uint16_t)v); }
-static inline uint64_t XEMASK(uint32_t mstart, uint32_t mstop) {
-  // if mstart ≤ mstop then
-  //   mask[mstart:mstop] = ones
-  //   mask[all other bits] = zeros
-  // else
-  //   mask[mstart:63] = ones
-  //   mask[0:mstop] = ones
-  //   mask[all other bits] = zeros
-  mstart &= 0x3F;
-  mstop &= 0x3F;
-  uint64_t value =
-      (UINT64_MAX >> mstart) ^ ((mstop >= 63) ? 0 : UINT64_MAX >> (mstop + 1));
-  return mstart <= mstop ? value : ~value;
-}
-
+// DEPRECATED
+// TODO(benvanik): move code to PPCDecodeData.
 struct InstrData {
   PPCOpcode opcode;
   const PPCOpcodeInfo* opcode_info;
@@ -235,6 +163,17 @@ struct InstrData {
       uint32_t RT : 5;
       uint32_t : 6;
     } MDS;
+    // kXEPPCInstrFormatMDSH
+    struct {
+      uint32_t Rc : 1;
+      uint32_t idx : 4;
+      uint32_t MB5 : 1;
+      uint32_t MB : 5;
+      uint32_t RB : 5;
+      uint32_t RA : 5;
+      uint32_t RT : 5;
+      uint32_t : 6;
+    } MDSH;
     // kXEPPCInstrFormatVXA
     struct {
       uint32_t : 6;
@@ -385,120 +324,6 @@ struct InstrData {
   };
 };
 
-typedef struct {
-  enum RegisterSet {
-    kXER,
-    kLR,
-    kCTR,
-    kCR,  // 0-7
-    kFPSCR,
-    kGPR,  // 0-31
-    kFPR,  // 0-31
-    kVMX,  // 0-127
-  };
-
-  enum Access {
-    kRead = 1 << 0,
-    kWrite = 1 << 1,
-    kReadWrite = kRead | kWrite,
-  };
-
-  RegisterSet set;
-  uint32_t ordinal;
-  Access access;
-} InstrRegister;
-
-typedef struct {
-  enum OperandType {
-    kRegister,
-    kImmediate,
-  };
-
-  OperandType type;
-  const char* display;
-  union {
-    InstrRegister reg;
-    struct {
-      bool is_signed;
-      uint64_t value;
-      size_t width;
-    } imm;
-  };
-
-  void Dump(std::string& out_str);
-} InstrOperand;
-
-class InstrAccessBits {
- public:
-  InstrAccessBits()
-      : spr(0),
-        cr(0),
-        gpr(0),
-        fpr(0),
-        vr31_0(0),
-        vr63_32(0),
-        vr95_64(0),
-        vr127_96(0) {}
-
-  // Bitmasks derived from the accesses to registers.
-  // Format is 2 bits for each register, even bits indicating reads and odds
-  // indicating writes.
-  uint64_t spr;  // fpcsr/ctr/lr/xer
-  uint64_t cr;   // cr7/6/5/4/3/2/1/0
-  uint64_t gpr;  // r31-0
-  uint64_t fpr;  // f31-0
-  uint64_t vr31_0;
-  uint64_t vr63_32;
-  uint64_t vr95_64;
-  uint64_t vr127_96;
-
-  void Clear();
-  void Extend(InstrAccessBits& other);
-  void MarkAccess(InstrRegister& reg);
-  void Dump(std::string& out_str);
-};
-
-class InstrDisasm {
- public:
-  enum Flags {
-    kOE = 1 << 0,
-    kRc = 1 << 1,
-    kCA = 1 << 2,
-    kLR = 1 << 4,
-    kFP = 1 << 5,
-    kVMX = 1 << 6,
-  };
-
-  const char* name;
-  const char* info;
-  uint32_t flags;
-
-  void Init(const char* new_name, const char* new_info, uint32_t new_flags);
-  void AddLR(InstrRegister::Access access);
-  void AddCTR(InstrRegister::Access access);
-  void AddCR(uint32_t bf, InstrRegister::Access access);
-  void AddFPSCR(InstrRegister::Access access);
-  void AddRegOperand(InstrRegister::RegisterSet set, uint32_t ordinal,
-                     InstrRegister::Access access, const char* display = NULL);
-  void AddSImmOperand(uint64_t value, size_t width, const char* display = NULL);
-  void AddUImmOperand(uint64_t value, size_t width, const char* display = NULL);
-  int Finish();
-
-  void Dump(std::string& out_str, size_t pad = 13);
-};
-
-typedef void (*InstrDisasmFn)(const InstrData& i, StringBuffer* str);
-
-class InstrType {
- public:
-  uint32_t opcode;
-  uint32_t opcode_mask;  // Only used for certain opcodes (altivec, etc).
-  uint32_t format;       // xe_ppc_instr_format_e
-  InstrDisasmFn disasm;
-};
-
-InstrType* GetInstrType(uint32_t code);
-
 }  // namespace ppc
 }  // namespace cpu
 }  // namespace xe
diff --git a/src/xenia/cpu/ppc/ppc_instr_tables.h b/src/xenia/cpu/ppc/ppc_instr_tables.h
deleted file mode 100644
index 01bf837d3..000000000
--- a/src/xenia/cpu/ppc/ppc_instr_tables.h
+++ /dev/null
@@ -1,1097 +0,0 @@
-/**
- ******************************************************************************
- * Xenia : Xbox 360 Emulator Research Project                                 *
- ******************************************************************************
- * Copyright 2013 Ben Vanik. All rights reserved.                             *
- * Released under the BSD license - see LICENSE in the root for more details. *
- ******************************************************************************
- */
-
-#ifndef XENIA_CPU_PPC_PPC_INSTR_TABLES_H_
-#define XENIA_CPU_PPC_PPC_INSTR_TABLES_H_
-
-#include <cmath>
-
-#include "xenia/base/math.h"
-#include "xenia/base/string_buffer.h"
-#include "xenia/cpu/ppc/ppc_instr.h"
-
-namespace xe {
-namespace cpu {
-namespace ppc {
-
-void Disasm_0(const InstrData& i, StringBuffer* str);
-void Disasm__(const InstrData& i, StringBuffer* str);
-void Disasm_X_FRT_FRB(const InstrData& i, StringBuffer* str);
-void Disasm_A_FRT_FRB(const InstrData& i, StringBuffer* str);
-void Disasm_A_FRT_FRA_FRB(const InstrData& i, StringBuffer* str);
-void Disasm_A_FRT_FRA_FRB_FRC(const InstrData& i, StringBuffer* str);
-void Disasm_X_RT_RA_RB(const InstrData& i, StringBuffer* str);
-void Disasm_X_RT_RA0_RB(const InstrData& i, StringBuffer* str);
-void Disasm_X_FRT_RA_RB(const InstrData& i, StringBuffer* str);
-void Disasm_X_FRT_RA0_RB(const InstrData& i, StringBuffer* str);
-void Disasm_D_RT_RA_I(const InstrData& i, StringBuffer* str);
-void Disasm_D_RT_RA0_I(const InstrData& i, StringBuffer* str);
-void Disasm_D_FRT_RA_I(const InstrData& i, StringBuffer* str);
-void Disasm_D_FRT_RA0_I(const InstrData& i, StringBuffer* str);
-void Disasm_DS_RT_RA_I(const InstrData& i, StringBuffer* str);
-void Disasm_DS_RT_RA0_I(const InstrData& i, StringBuffer* str);
-void Disasm_D_RA(const InstrData& i, StringBuffer* str);
-void Disasm_X_RA_RB(const InstrData& i, StringBuffer* str);
-void Disasm_XO_RT_RA_RB(const InstrData& i, StringBuffer* str);
-void Disasm_XO_RT_RA(const InstrData& i, StringBuffer* str);
-void Disasm_X_RA_RT_RB(const InstrData& i, StringBuffer* str);
-void Disasm_D_RA_RT_I(const InstrData& i, StringBuffer* str);
-void Disasm_X_RA_RT(const InstrData& i, StringBuffer* str);
-void Disasm_X_VX_RA0_RB(const InstrData& i, StringBuffer* str);
-void Disasm_VX1281_VD_RA0_RB(const InstrData& i, StringBuffer* str);
-void Disasm_VX1283_VD_VB(const InstrData& i, StringBuffer* str);
-void Disasm_VX1283_VD_VB_I(const InstrData& i, StringBuffer* str);
-void Disasm_VX_VD_VA_VB(const InstrData& i, StringBuffer* str);
-void Disasm_VX128_VD_VA_VB(const InstrData& i, StringBuffer* str);
-void Disasm_VX128_VD_VA_VD_VB(const InstrData& i, StringBuffer* str);
-void Disasm_VX1282_VD_VA_VB_VC(const InstrData& i, StringBuffer* str);
-void Disasm_VXA_VD_VA_VB_VC(const InstrData& i, StringBuffer* str);
-
-void Disasm_sync(const InstrData& i, StringBuffer* str);
-void Disasm_dcbf(const InstrData& i, StringBuffer* str);
-void Disasm_dcbz(const InstrData& i, StringBuffer* str);
-void Disasm_fcmp(const InstrData& i, StringBuffer* str);
-
-void Disasm_bx(const InstrData& i, StringBuffer* str);
-void Disasm_bcx(const InstrData& i, StringBuffer* str);
-void Disasm_bcctrx(const InstrData& i, StringBuffer* str);
-void Disasm_bclrx(const InstrData& i, StringBuffer* str);
-
-void Disasm_mfcr(const InstrData& i, StringBuffer* str);
-void Disasm_mfspr(const InstrData& i, StringBuffer* str);
-void Disasm_mtspr(const InstrData& i, StringBuffer* str);
-void Disasm_mftb(const InstrData& i, StringBuffer* str);
-void Disasm_mfmsr(const InstrData& i, StringBuffer* str);
-void Disasm_mtmsr(const InstrData& i, StringBuffer* str);
-
-void Disasm_cmp(const InstrData& i, StringBuffer* str);
-void Disasm_cmpi(const InstrData& i, StringBuffer* str);
-void Disasm_cmpli(const InstrData& i, StringBuffer* str);
-
-void Disasm_rld(const InstrData& i, StringBuffer* str);
-void Disasm_rlwim(const InstrData& i, StringBuffer* str);
-void Disasm_rlwnmx(const InstrData& i, StringBuffer* str);
-void Disasm_srawix(const InstrData& i, StringBuffer* str);
-void Disasm_sradix(const InstrData& i, StringBuffer* str);
-
-void Disasm_vpermwi128(const InstrData& i, StringBuffer* str);
-void Disasm_vrfin128(const InstrData& i, StringBuffer* str);
-void Disasm_vrlimi128(const InstrData& i, StringBuffer* str);
-void Disasm_vsldoi128(const InstrData& i, StringBuffer* str);
-void Disasm_vspltb(const InstrData& i, StringBuffer* str);
-void Disasm_vsplth(const InstrData& i, StringBuffer* str);
-void Disasm_vspltw(const InstrData& i, StringBuffer* str);
-void Disasm_vspltisb(const InstrData& i, StringBuffer* str);
-void Disasm_vspltish(const InstrData& i, StringBuffer* str);
-void Disasm_vspltisw(const InstrData& i, StringBuffer* str);
-
-namespace tables {
-
-static InstrType** instr_table_prep(InstrType* unprep, size_t unprep_count,
-                                    int a, int b) {
-  int prep_count = (int)pow(2.0, b - a + 1);
-  InstrType** prep = (InstrType**)calloc(prep_count, sizeof(void*));
-  for (int n = 0; n < unprep_count; n++) {
-    int ordinal = select_bits(unprep[n].opcode, a, b);
-    prep[ordinal] = &unprep[n];
-  }
-  return prep;
-}
-
-static InstrType** instr_table_prep_63(InstrType* unprep, size_t unprep_count,
-                                       int a, int b) {
-  // Special handling for A format instructions.
-  int prep_count = (int)pow(2.0, b - a + 1);
-  InstrType** prep = (InstrType**)calloc(prep_count, sizeof(void*));
-  for (int n = 0; n < unprep_count; n++) {
-    int ordinal = select_bits(unprep[n].opcode, a, b);
-    if (unprep[n].format == kXEPPCInstrFormatA) {
-      // Must splat this into all of the slots that it could be in.
-      for (int m = 0; m < 32; m++) {
-        prep[ordinal + (m << 5)] = &unprep[n];
-      }
-    } else {
-      prep[ordinal] = &unprep[n];
-    }
-  }
-  return prep;
-}
-
-#define EMPTY(slot) \
-  { 0 }
-#define INSTRUCTION(name, opcode, format, type, disasm_fn, descr) \
-  { opcode, 0, kXEPPCInstrFormat##format, Disasm_##disasm_fn, }
-#define FLAG(t) kXEPPCInstrFlag##t
-
-// This table set is constructed from:
-//   pem_64bit_v3.0.2005jul15.pdf, A.2
-//   PowerISA_V2.06B_V2_PUBLIC.pdf
-
-// Opcode = 4, index = bits 11-0 (6)
-static InstrType instr_table_4_unprep[] = {
-    // TODO: all of the vector ops
-    INSTRUCTION(mfvscr, 0x10000604, VX, General, 0,
-                "Move from Vector Status and Control Register"),
-    INSTRUCTION(mtvscr, 0x10000644, VX, General, 0,
-                "Move to Vector Status and Control Register"),
-    INSTRUCTION(vaddcuw, 0x10000180, VX, General, 0,
-                "Vector Add Carryout Unsigned Word"),
-    INSTRUCTION(vaddfp, 0x1000000A, VX, General, VX_VD_VA_VB,
-                "Vector Add Floating Point"),
-    INSTRUCTION(vaddsbs, 0x10000300, VX, General, 0,
-                "Vector Add Signed Byte Saturate"),
-    INSTRUCTION(vaddshs, 0x10000340, VX, General, 0,
-                "Vector Add Signed Half Word Saturate"),
-    INSTRUCTION(vaddsws, 0x10000380, VX, General, 0,
-                "Vector Add Signed Word Saturate"),
-    INSTRUCTION(vaddubm, 0x10000000, VX, General, 0,
-                "Vector Add Unsigned Byte Modulo"),
-    INSTRUCTION(vaddubs, 0x10000200, VX, General, 0,
-                "Vector Add Unsigned Byte Saturate"),
-    INSTRUCTION(vadduhm, 0x10000040, VX, General, 0,
-                "Vector Add Unsigned Half Word Modulo"),
-    INSTRUCTION(vadduhs, 0x10000240, VX, General, 0,
-                "Vector Add Unsigned Half Word Saturate"),
-    INSTRUCTION(vadduwm, 0x10000080, VX, General, 0,
-                "Vector Add Unsigned Word Modulo"),
-    INSTRUCTION(vadduws, 0x10000280, VX, General, 0,
-                "Vector Add Unsigned Word Saturate"),
-    INSTRUCTION(vand, 0x10000404, VX, General, VX_VD_VA_VB,
-                "Vector Logical AND"),
-    INSTRUCTION(vandc, 0x10000444, VX, General, VX_VD_VA_VB,
-                "Vector Logical AND with Complement"),
-    INSTRUCTION(vavgsb, 0x10000502, VX, General, 0,
-                "Vector Average Signed Byte"),
-    INSTRUCTION(vavgsh, 0x10000542, VX, General, 0,
-                "Vector Average Signed Half Word"),
-    INSTRUCTION(vavgsw, 0x10000582, VX, General, 0,
-                "Vector Average Signed Word"),
-    INSTRUCTION(vavgub, 0x10000402, VX, General, 0,
-                "Vector Average Unsigned Byte"),
-    INSTRUCTION(vavguh, 0x10000442, VX, General, 0,
-                "Vector Average Unsigned Half Word"),
-    INSTRUCTION(vavguw, 0x10000482, VX, General, 0,
-                "Vector Average Unsigned Word"),
-    INSTRUCTION(vcfsx, 0x1000034A, VX, General, 0,
-                "Vector Convert from Signed Fixed-Point Word"),
-    INSTRUCTION(vcfux, 0x1000030A, VX, General, 0,
-                "Vector Convert from Unsigned Fixed-Point Word"),
-    INSTRUCTION(vctsxs, 0x100003CA, VX, General, 0,
-                "Vector Convert to Signed Fixed-Point Word Saturate"),
-    INSTRUCTION(vctuxs, 0x1000038A, VX, General, 0,
-                "Vector Convert to Unsigned Fixed-Point Word Saturate"),
-    INSTRUCTION(vexptefp, 0x1000018A, VX, General, 0,
-                "Vector 2 Raised to the Exponent Estimate Floating Point"),
-    INSTRUCTION(vlogefp, 0x100001CA, VX, General, 0,
-                "Vector Log2 Estimate Floating Point"),
-    INSTRUCTION(vmaxfp, 0x1000040A, VX, General, 0,
-                "Vector Maximum Floating Point"),
-    INSTRUCTION(vmaxsb, 0x10000102, VX, General, 0,
-                "Vector Maximum Signed Byte"),
-    INSTRUCTION(vmaxsh, 0x10000142, VX, General, 0,
-                "Vector Maximum Signed Half Word"),
-    INSTRUCTION(vmaxsw, 0x10000182, VX, General, 0,
-                "Vector Maximum Signed Word"),
-    INSTRUCTION(vmaxub, 0x10000002, VX, General, 0,
-                "Vector Maximum Unsigned Byte"),
-    INSTRUCTION(vmaxuh, 0x10000042, VX, General, 0,
-                "Vector Maximum Unsigned Half Word"),
-    INSTRUCTION(vmaxuw, 0x10000082, VX, General, 0,
-                "Vector Maximum Unsigned Word"),
-    INSTRUCTION(vminfp, 0x1000044A, VX, General, 0,
-                "Vector Minimum Floating Point"),
-    INSTRUCTION(vminsb, 0x10000302, VX, General, 0,
-                "Vector Minimum Signed Byte"),
-    INSTRUCTION(vminsh, 0x10000342, VX, General, 0,
-                "Vector Minimum Signed Half Word"),
-    INSTRUCTION(vminsw, 0x10000382, VX, General, 0,
-                "Vector Minimum Signed Word"),
-    INSTRUCTION(vminub, 0x10000202, VX, General, 0,
-                "Vector Minimum Unsigned Byte"),
-    INSTRUCTION(vminuh, 0x10000242, VX, General, 0,
-                "Vector Minimum Unsigned Half Word"),
-    INSTRUCTION(vminuw, 0x10000282, VX, General, 0,
-                "Vector Minimum Unsigned Word"),
-    INSTRUCTION(vmrghb, 0x1000000C, VX, General, 0, "Vector Merge High Byte"),
-    INSTRUCTION(vmrghh, 0x1000004C, VX, General, 0,
-                "Vector Merge High Half Word"),
-    INSTRUCTION(vmrghw, 0x1000008C, VX, General, 0, "Vector Merge High Word"),
-    INSTRUCTION(vmrglb, 0x1000010C, VX, General, 0, "Vector Merge Low Byte"),
-    INSTRUCTION(vmrglh, 0x1000014C, VX, General, 0,
-                "Vector Merge Low Half Word"),
-    INSTRUCTION(vmrglw, 0x1000018C, VX, General, 0, "Vector Merge Low Word"),
-    INSTRUCTION(vmulesb, 0x10000308, VX, General, 0,
-                "Vector Multiply Even Signed Byte"),
-    INSTRUCTION(vmulesh, 0x10000348, VX, General, 0,
-                "Vector Multiply Even Signed Half Word"),
-    INSTRUCTION(vmuleub, 0x10000208, VX, General, 0,
-                "Vector Multiply Even Unsigned Byte"),
-    INSTRUCTION(vmuleuh, 0x10000248, VX, General, 0,
-                "Vector Multiply Even Unsigned Half Word"),
-    INSTRUCTION(vmulosb, 0x10000108, VX, General, 0,
-                "Vector Multiply Odd Signed Byte"),
-    INSTRUCTION(vmulosh, 0x10000148, VX, General, 0,
-                "Vector Multiply Odd Signed Half Word"),
-    INSTRUCTION(vmuloub, 0x10000008, VX, General, 0,
-                "Vector Multiply Odd Unsigned Byte"),
-    INSTRUCTION(vmulouh, 0x10000048, VX, General, 0,
-                "Vector Multiply Odd Unsigned Half Word"),
-    INSTRUCTION(vnor, 0x10000504, VX, General, VX_VD_VA_VB,
-                "Vector Logical NOR"),
-    INSTRUCTION(vor, 0x10000484, VX, General, VX_VD_VA_VB, "Vector Logical OR"),
-    INSTRUCTION(vpkpx, 0x1000030E, VX, General, 0, "Vector Pack Pixel"),
-    INSTRUCTION(vpkshss, 0x1000018E, VX, General, 0,
-                "Vector Pack Signed Half Word Signed Saturate"),
-    INSTRUCTION(vpkshus, 0x1000010E, VX, General, 0,
-                "Vector Pack Signed Half Word Unsigned Saturate"),
-    INSTRUCTION(vpkswss, 0x100001CE, VX, General, 0,
-                "Vector Pack Signed Word Signed Saturate"),
-    INSTRUCTION(vpkswus, 0x1000014E, VX, General, 0,
-                "Vector Pack Signed Word Unsigned Saturate"),
-    INSTRUCTION(vpkuhum, 0x1000000E, VX, General, 0,
-                "Vector Pack Unsigned Half Word Unsigned Modulo"),
-    INSTRUCTION(vpkuhus, 0x1000008E, VX, General, 0,
-                "Vector Pack Unsigned Half Word Unsigned Saturate"),
-    INSTRUCTION(vpkuwum, 0x1000004E, VX, General, 0,
-                "Vector Pack Unsigned Word Unsigned Modulo"),
-    INSTRUCTION(vpkuwus, 0x100000CE, VX, General, 0,
-                "Vector Pack Unsigned Word Unsigned Saturate"),
-    INSTRUCTION(vrefp, 0x1000010A, VX, General, 0,
-                "Vector Reciprocal Estimate Floating Point"),
-    INSTRUCTION(vrfim, 0x100002CA, VX, General, 0,
-                "Vector Round to Floating-Point Integer toward -Infinity"),
-    INSTRUCTION(vrfin, 0x1000020A, VX, General, 0,
-                "Vector Round to Floating-Point Integer Nearest"),
-    INSTRUCTION(vrfip, 0x1000028A, VX, General, 0,
-                "Vector Round to Floating-Point Integer toward +Infinity"),
-    INSTRUCTION(vrfiz, 0x1000024A, VX, General, 0,
-                "Vector Round to Floating-Point Integer toward Zero"),
-    INSTRUCTION(vrlb, 0x10000004, VX, General, 0,
-                "Vector Rotate Left Integer Byte"),
-    INSTRUCTION(vrlh, 0x10000044, VX, General, 0,
-                "Vector Rotate Left Integer Half Word"),
-    INSTRUCTION(vrlw, 0x10000084, VX, General, 0,
-                "Vector Rotate Left Integer Word"),
-    INSTRUCTION(vrsqrtefp, 0x1000014A, VX, General, 0,
-                "Vector Reciprocal Square Root Estimate Floating Point"),
-    INSTRUCTION(vsl, 0x100001C4, VX, General, 0, "Vector Shift Left"),
-    INSTRUCTION(vslb, 0x10000104, VX, General, VX_VD_VA_VB,
-                "Vector Shift Left Integer Byte"),
-    INSTRUCTION(vslh, 0x10000144, VX, General, 0,
-                "Vector Shift Left Integer Half Word"),
-    INSTRUCTION(vslo, 0x1000040C, VX, General, 0, "Vector Shift Left by Octet"),
-    INSTRUCTION(vslw, 0x10000184, VX, General, 0,
-                "Vector Shift Left Integer Word"),
-    INSTRUCTION(vspltb, 0x1000020C, VX, General, vspltb, "Vector Splat Byte"),
-    INSTRUCTION(vsplth, 0x1000024C, VX, General, vsplth,
-                "Vector Splat Half Word"),
-    INSTRUCTION(vspltisb, 0x1000030C, VX, General, vspltisb,
-                "Vector Splat Immediate Signed Byte"),
-    INSTRUCTION(vspltish, 0x1000034C, VX, General, vspltish,
-                "Vector Splat Immediate Signed Half Word"),
-    INSTRUCTION(vspltisw, 0x1000038C, VX, General, vspltisw,
-                "Vector Splat Immediate Signed Word"),
-    INSTRUCTION(vspltw, 0x1000028C, VX, General, vspltw, "Vector Splat Word"),
-    INSTRUCTION(vsr, 0x100002C4, VX, General, VX_VD_VA_VB,
-                "Vector Shift Right"),
-    INSTRUCTION(vsrab, 0x10000304, VX, General, VX_VD_VA_VB,
-                "Vector Shift Right Algebraic Byte"),
-    INSTRUCTION(vsrah, 0x10000344, VX, General, VX_VD_VA_VB,
-                "Vector Shift Right Algebraic Half Word"),
-    INSTRUCTION(vsraw, 0x10000384, VX, General, VX_VD_VA_VB,
-                "Vector Shift Right Algebraic Word"),
-    INSTRUCTION(vsrb, 0x10000204, VX, General, VX_VD_VA_VB,
-                "Vector Shift Right Byte"),
-    INSTRUCTION(vsrh, 0x10000244, VX, General, VX_VD_VA_VB,
-                "Vector Shift Right Half Word"),
-    INSTRUCTION(vsro, 0x1000044C, VX, General, VX_VD_VA_VB,
-                "Vector Shift Right Octet"),
-    INSTRUCTION(vsrw, 0x10000284, VX, General, VX_VD_VA_VB,
-                "Vector Shift Right Word"),
-    INSTRUCTION(vsubcuw, 0x10000580, VX, General, 0,
-                "Vector Subtract Carryout Unsigned Word"),
-    INSTRUCTION(vsubfp, 0x1000004A, VX, General, 0,
-                "Vector Subtract Floating Point"),
-    INSTRUCTION(vsubsbs, 0x10000700, VX, General, 0,
-                "Vector Subtract Signed Byte Saturate"),
-    INSTRUCTION(vsubshs, 0x10000740, VX, General, 0,
-                "Vector Subtract Signed Half Word Saturate"),
-    INSTRUCTION(vsubsws, 0x10000780, VX, General, 0,
-                "Vector Subtract Signed Word Saturate"),
-    INSTRUCTION(vsububm, 0x10000400, VX, General, 0,
-                "Vector Subtract Unsigned Byte Modulo"),
-    INSTRUCTION(vsububs, 0x10000600, VX, General, 0,
-                "Vector Subtract Unsigned Byte Saturate"),
-    INSTRUCTION(vsubuhm, 0x10000440, VX, General, 0,
-                "Vector Subtract Unsigned Half Word Modulo"),
-    INSTRUCTION(vsubuhs, 0x10000640, VX, General, 0,
-                "Vector Subtract Unsigned Half Word Saturate"),
-    INSTRUCTION(vsubuwm, 0x10000480, VX, General, 0,
-                "Vector Subtract Unsigned Word Modulo"),
-    INSTRUCTION(vsubuws, 0x10000680, VX, General, 0,
-                "Vector Subtract Unsigned Word Saturate"),
-    INSTRUCTION(vsumsws, 0x10000788, VX, General, 0,
-                "Vector Sum Across Signed Word Saturate"),
-    INSTRUCTION(vsum2sws, 0x10000688, VX, General, 0,
-                "Vector Sum Across Partial (1/2) Signed Word Saturate"),
-    INSTRUCTION(vsum4sbs, 0x10000708, VX, General, 0,
-                "Vector Sum Across Partial (1/4) Signed Byte Saturate"),
-    INSTRUCTION(vsum4shs, 0x10000648, VX, General, 0,
-                "Vector Sum Across Partial (1/4) Signed Half Word Saturate"),
-    INSTRUCTION(vsum4ubs, 0x10000608, VX, General, 0,
-                "Vector Sum Across Partial (1/4) Unsigned Byte Saturate"),
-    INSTRUCTION(vupkhpx, 0x1000034E, VX, General, 0,
-                "Vector Unpack High Pixel"),
-    INSTRUCTION(vupkhsb, 0x1000020E, VX, General, 0,
-                "Vector Unpack High Signed Byte"),
-    INSTRUCTION(vupkhsh, 0x1000024E, VX, General, 0,
-                "Vector Unpack High Signed Half Word"),
-    INSTRUCTION(vupklpx, 0x100003CE, VX, General, 0, "Vector Unpack Low Pixel"),
-    INSTRUCTION(vupklsb, 0x1000028E, VX, General, 0,
-                "Vector Unpack Low Signed Byte"),
-    INSTRUCTION(vupklsh, 0x100002CE, VX, General, 0,
-                "Vector Unpack Low Signed Half Word"),
-    INSTRUCTION(vxor, 0x100004C4, VX, General, VX_VD_VA_VB,
-                "Vector Logical XOR"),
-};
-static InstrType** instr_table_4 = instr_table_prep(
-    instr_table_4_unprep, xe::countof(instr_table_4_unprep), 0, 11);
-
-// Opcode = 19, index = bits 10-1 (10)
-static InstrType instr_table_19_unprep[] = {
-    INSTRUCTION(mcrf, 0x4C000000, XL, General, 0, NULL),
-    INSTRUCTION(bclrx, 0x4C000020, XL, BranchCond, bclrx,
-                "Branch Conditional to Link Register"),
-    INSTRUCTION(crnor, 0x4C000042, XL, General, 0, NULL),
-    INSTRUCTION(crandc, 0x4C000102, XL, General, 0, NULL),
-    INSTRUCTION(isync, 0x4C00012C, XL, General, 0, NULL),
-    INSTRUCTION(crxor, 0x4C000182, XL, General, 0, NULL),
-    INSTRUCTION(crnand, 0x4C0001C2, XL, General, 0, NULL),
-    INSTRUCTION(crand, 0x4C000202, XL, General, 0, NULL),
-    INSTRUCTION(creqv, 0x4C000242, XL, General, 0, NULL),
-    INSTRUCTION(crorc, 0x4C000342, XL, General, 0, NULL),
-    INSTRUCTION(cror, 0x4C000382, XL, General, 0, NULL),
-    INSTRUCTION(bcctrx, 0x4C000420, XL, BranchCond, bcctrx,
-                "Branch Conditional to Count Register"),
-};
-static InstrType** instr_table_19 = instr_table_prep(
-    instr_table_19_unprep, xe::countof(instr_table_19_unprep), 1, 10);
-
-// Opcode = 30, index = bits 4-1 (4)
-static InstrType instr_table_30_unprep[] = {
-    // Decoding these instrunctions in this table is difficult because the
-    // index bits are kind of random. This is special cased by an uber
-    // instruction handler.
-    INSTRUCTION(rld, 0x78000000, MD, General, rld, NULL),
-    // INSTRUCTION(rldiclx,        0x78000000, MD , General        , 0),
-    // INSTRUCTION(rldicrx,        0x78000004, MD , General        , 0),
-    // INSTRUCTION(rldicx,         0x78000008, MD , General        , 0),
-    // INSTRUCTION(rldimix,        0x7800000C, MD , General        , 0),
-    // INSTRUCTION(rldclx,         0x78000010, MDS, General        , 0),
-    // INSTRUCTION(rldcrx,         0x78000012, MDS, General        , 0),
-};
-static InstrType** instr_table_30 = instr_table_prep(
-    instr_table_30_unprep, xe::countof(instr_table_30_unprep), 0, 0);
-
-// Opcode = 31, index = bits 10-1 (10)
-static InstrType instr_table_31_unprep[] = {
-    INSTRUCTION(cmp, 0x7C000000, X, General, cmp, "Compare"),
-    INSTRUCTION(tw, 0x7C000008, X, General, X_RA_RB, "Trap Word"),
-    INSTRUCTION(lvsl, 0x7C00000C, X, General, X_VX_RA0_RB,
-                "Load Vector for Shift Left"),
-    INSTRUCTION(lvebx, 0x7C00000E, X, General, 0,
-                "Load Vector Element Byte Indexed"),
-    INSTRUCTION(subfcx, 0x7C000010, XO, General, XO_RT_RA_RB,
-                "Subtract From Carrying"),
-    INSTRUCTION(mulhdux, 0x7C000012, XO, General, XO_RT_RA_RB,
-                "Multiply High Doubleword Unsigned"),
-    INSTRUCTION(addcx, 0x7C000014, XO, General, XO_RT_RA_RB, "Add Carrying"),
-    INSTRUCTION(mulhwux, 0x7C000016, XO, General, XO_RT_RA_RB,
-                "Multiply High Word Unsigned"),
-    INSTRUCTION(mfcr, 0x7C000026, X, General, mfcr,
-                "Move From Condition Register"),
-    INSTRUCTION(lwarx, 0x7C000028, X, General, X_RT_RA0_RB,
-                "Load Word And Reserve Indexed"),
-    INSTRUCTION(ldx, 0x7C00002A, X, General, X_RT_RA0_RB,
-                "Load Doubleword Indexed"),
-    INSTRUCTION(lwzx, 0x7C00002E, X, General, X_RT_RA0_RB,
-                "Load Word and Zero Indexed"),
-    INSTRUCTION(slwx, 0x7C000030, X, General, X_RA_RT_RB, "Shift Left Word"),
-    INSTRUCTION(cntlzwx, 0x7C000034, X, General, X_RA_RT,
-                "Count Leading Zeros Word"),
-    INSTRUCTION(sldx, 0x7C000036, X, General, X_RA_RT_RB,
-                "Shift Left Doubleword"),
-    INSTRUCTION(andx, 0x7C000038, X, General, X_RA_RT_RB, "AND"),
-    INSTRUCTION(cmpl, 0x7C000040, X, General, cmp, "Compare Logical"),
-    INSTRUCTION(lvsr, 0x7C00004C, X, General, X_VX_RA0_RB,
-                "Load Vector for Shift Right"),
-    INSTRUCTION(lvehx, 0x7C00004E, X, General, 0,
-                "Load Vector Element Half Word Indexed"),
-    INSTRUCTION(subfx, 0x7C000050, XO, General, XO_RT_RA_RB, "Subtract From"),
-    INSTRUCTION(ldux, 0x7C00006A, X, General, X_RT_RA_RB,
-                "Load Doubleword with Update Indexed"),
-    INSTRUCTION(dcbst, 0x7C00006C, X, General, 0, NULL),
-    INSTRUCTION(lwzux, 0x7C00006E, X, General, X_RT_RA_RB,
-                "Load Word and Zero with Update Indexed"),
-    INSTRUCTION(cntlzdx, 0x7C000074, X, General, X_RA_RT,
-                "Count Leading Zeros Doubleword"),
-    INSTRUCTION(andcx, 0x7C000078, X, General, X_RA_RT_RB,
-                "AND with Complement"),
-    INSTRUCTION(td, 0x7C000088, X, General, X_RA_RB, "Trap Doubleword"),
-    INSTRUCTION(lvewx, 0x7C00008E, X, General, 0,
-                "Load Vector Element Word Indexed"),
-    INSTRUCTION(mulhdx, 0x7C000092, XO, General, XO_RT_RA_RB,
-                "Multiply High Doubleword"),
-    INSTRUCTION(mulhwx, 0x7C000096, XO, General, XO_RT_RA_RB,
-                "Multiply High Word"),
-    INSTRUCTION(mfmsr, 0x7C0000A6, X, General, mfmsr,
-                "Move From Machine State Register"),
-    INSTRUCTION(ldarx, 0x7C0000A8, X, General, X_RT_RA0_RB,
-                "Load Doubleword And Reserve Indexed"),
-    INSTRUCTION(dcbf, 0x7C0000AC, X, General, dcbf, "Data Cache Block Flush"),
-    INSTRUCTION(lbzx, 0x7C0000AE, X, General, X_RT_RA0_RB,
-                "Load Byte and Zero Indexed"),
-    INSTRUCTION(lvx, 0x7C0000CE, X, General, X_VX_RA0_RB,
-                "Load Vector Indexed"),
-    INSTRUCTION(negx, 0x7C0000D0, XO, General, XO_RT_RA, "Negate"),
-    INSTRUCTION(lbzux, 0x7C0000EE, X, General, X_RT_RA_RB,
-                "Load Byte and Zero with Update Indexed"),
-    INSTRUCTION(norx, 0x7C0000F8, X, General, X_RA_RT_RB, "NOR"),
-    INSTRUCTION(stvebx, 0x7C00010E, X, General, 0,
-                "Store Vector Element Byte Indexed"),
-    INSTRUCTION(subfex, 0x7C000110, XO, General, XO_RT_RA_RB,
-                "Subtract From Extended"),
-    INSTRUCTION(addex, 0x7C000114, XO, General, XO_RT_RA_RB, "Add Extended"),
-    INSTRUCTION(mtcrf, 0x7C000120, XFX, General, 0, NULL),
-    INSTRUCTION(mtmsr, 0x7C000124, X, General, mtmsr,
-                "Move To Machine State Register"),
-    INSTRUCTION(stdx, 0x7C00012A, X, General, X_RT_RA0_RB,
-                "Store Doubleword Indexed"),
-    INSTRUCTION(stwcx, 0x7C00012D, X, General, X_RT_RA0_RB,
-                "Store Word Conditional Indexed"),
-    INSTRUCTION(stwx, 0x7C00012E, X, General, X_RT_RA0_RB,
-                "Store Word Indexed"),
-    INSTRUCTION(stvehx, 0x7C00014E, X, General, 0,
-                "Store Vector Element Half Word Indexed"),
-    INSTRUCTION(mtmsrd, 0x7C000164, X, General, mtmsr,
-                "Move To Machine State Register Doubleword"),
-    INSTRUCTION(stdux, 0x7C00016A, X, General, X_RT_RA_RB,
-                "Store Doubleword with Update Indexed"),
-    INSTRUCTION(stwux, 0x7C00016E, X, General, X_RT_RA_RB,
-                "Store Word with Update Indexed"),
-    INSTRUCTION(stvewx, 0x7C00018E, X, General, 0,
-                "Store Vector Element Word Indexed"),
-    INSTRUCTION(subfzex, 0x7C000190, XO, General, XO_RT_RA,
-                "Subtract From Zero Extended"),
-    INSTRUCTION(addzex, 0x7C000194, XO, General, XO_RT_RA,
-                "Add to Zero Extended"),
-    INSTRUCTION(stdcx, 0x7C0001AD, X, General, X_RT_RA0_RB,
-                "Store Doubleword Conditional Indexed"),
-    INSTRUCTION(stbx, 0x7C0001AE, X, General, X_RT_RA0_RB,
-                "Store Byte Indexed"),
-    INSTRUCTION(stvx, 0x7C0001CE, X, General, 0, "Store Vector Indexed"),
-    INSTRUCTION(subfmex, 0x7C0001D0, XO, General, XO_RT_RA,
-                "Subtract From Minus One Extended"),
-    INSTRUCTION(mulldx, 0x7C0001D2, XO, General, XO_RT_RA_RB,
-                "Multiply Low Doubleword"),
-    INSTRUCTION(addmex, 0x7C0001D4, XO, General, XO_RT_RA,
-                "Add to Minus One Extended"),
-    INSTRUCTION(mullwx, 0x7C0001D6, XO, General, XO_RT_RA_RB,
-                "Multiply Low Word"),
-    INSTRUCTION(dcbtst, 0x7C0001EC, X, General, 0,
-                "Data Cache Block Touch for Store"),
-    INSTRUCTION(stbux, 0x7C0001EE, X, General, X_RT_RA_RB,
-                "Store Byte with Update Indexed"),
-    INSTRUCTION(addx, 0x7C000214, XO, General, XO_RT_RA_RB, "Add"),
-    INSTRUCTION(dcbt, 0x7C00022C, X, General, 0, "Data Cache Block Touch"),
-    INSTRUCTION(lhzx, 0x7C00022E, X, General, X_RT_RA0_RB,
-                "Load Halfword and Zero Indexed"),
-    INSTRUCTION(eqvx, 0x7C000238, X, General, X_RA_RT_RB, "Equivalent"),
-    INSTRUCTION(eciwx, 0x7C00026C, X, General, 0, NULL),
-    INSTRUCTION(lhzux, 0x7C00026E, X, General, X_RT_RA_RB,
-                "Load Halfword and Zero with Update Indexed"),
-    INSTRUCTION(xorx, 0x7C000278, X, General, X_RA_RT_RB, "XOR"),
-    INSTRUCTION(mfspr, 0x7C0002A6, XFX, General, mfspr,
-                "Move From Special Purpose Register"),
-    INSTRUCTION(lwax, 0x7C0002AA, X, General, X_RT_RA0_RB,
-                "Load Word Algebraic Indexed"),
-    INSTRUCTION(lhax, 0x7C0002AE, X, General, X_RT_RA0_RB,
-                "Load Halfword Algebraic Indexed"),
-    INSTRUCTION(lvxl, 0x7C0002CE, X, General, X_VX_RA0_RB,
-                "Load Vector Indexed LRU"),
-    INSTRUCTION(mftb, 0x7C0002E6, XFX, General, mftb, "Move From Time Base"),
-    INSTRUCTION(lwaux, 0x7C0002EA, X, General, X_RT_RA_RB,
-                "Load Word Algebraic with Update Indexed"),
-    INSTRUCTION(lhaux, 0x7C0002EE, X, General, 0, NULL),
-    INSTRUCTION(sthx, 0x7C00032E, X, General, X_RT_RA0_RB,
-                "Store Halfword Indexed"),
-    INSTRUCTION(orcx, 0x7C000338, X, General, X_RA_RT_RB, "OR with Complement"),
-    INSTRUCTION(ecowx, 0x7C00036C, X, General, 0, NULL),
-    INSTRUCTION(sthux, 0x7C00036E, X, General, X_RT_RA_RB,
-                "Store Halfword with Update Indexed"),
-    INSTRUCTION(orx, 0x7C000378, X, General, X_RA_RT_RB, "OR"),
-    INSTRUCTION(divdux, 0x7C000392, XO, General, XO_RT_RA_RB,
-                "Divide Doubleword Unsigned"),
-    INSTRUCTION(divwux, 0x7C000396, XO, General, XO_RT_RA_RB,
-                "Divide Word Unsigned"),
-    INSTRUCTION(mtspr, 0x7C0003A6, XFX, General, mtspr,
-                "Move To Special Purpose Register"),
-    INSTRUCTION(nandx, 0x7C0003B8, X, General, X_RA_RT_RB, "NAND"),
-    INSTRUCTION(stvxl, 0x7C0003CE, X, General, 0, "Store Vector Indexed LRU"),
-    INSTRUCTION(divdx, 0x7C0003D2, XO, General, XO_RT_RA_RB,
-                "Divide Doubleword"),
-    INSTRUCTION(divwx, 0x7C0003D6, XO, General, XO_RT_RA_RB, "Divide Word"),
-    INSTRUCTION(lvlx, 0x7C00040E, X, General, 0, "Load Vector Indexed"),
-    INSTRUCTION(ldbrx, 0x7C000428, X, General, X_RT_RA0_RB,
-                "Load Doubleword Byte-Reverse Indexed"),
-    INSTRUCTION(lswx, 0x7C00042A, X, General, 0, NULL),
-    INSTRUCTION(lwbrx, 0x7C00042C, X, General, X_RT_RA0_RB,
-                "Load Word Byte-Reverse Indexed"),
-    INSTRUCTION(lfsx, 0x7C00042E, X, General, X_FRT_RA0_RB,
-                "Load Floating-Point Single Indexed"),
-    INSTRUCTION(srwx, 0x7C000430, X, General, X_RA_RT_RB, "Shift Right Word"),
-    INSTRUCTION(srdx, 0x7C000436, X, General, X_RA_RT_RB,
-                "Shift Right Doubleword"),
-    INSTRUCTION(lfsux, 0x7C00046E, X, General, X_FRT_RA_RB,
-                "Load Floating-Point Single with Update Indexed"),
-    INSTRUCTION(lswi, 0x7C0004AA, X, General, 0, NULL),
-    INSTRUCTION(sync, 0x7C0004AC, X, General, sync, "Synchronize"),
-    INSTRUCTION(lfdx, 0x7C0004AE, X, General, X_FRT_RA0_RB,
-                "Load Floating-Point Double Indexed"),
-    INSTRUCTION(lfdux, 0x7C0004EE, X, General, X_FRT_RA_RB,
-                "Load Floating-Point Double with Update Indexed"),
-    INSTRUCTION(stdbrx, 0x7C000528, X, General, X_RT_RA0_RB,
-                "Store Doubleword Byte-Reverse Indexed"),
-    INSTRUCTION(stswx, 0x7C00052A, X, General, 0, NULL),
-    INSTRUCTION(stwbrx, 0x7C00052C, X, General, X_RT_RA0_RB,
-                "Store Word Byte-Reverse Indexed"),
-    INSTRUCTION(stfsx, 0x7C00052E, X, General, X_FRT_RA0_RB,
-                "Store Floating-Point Single Indexed"),
-    INSTRUCTION(stfsux, 0x7C00056E, X, General, X_FRT_RA_RB,
-                "Store Floating-Point Single with Update Indexed"),
-    INSTRUCTION(stswi, 0x7C0005AA, X, General, 0, NULL),
-    INSTRUCTION(stfdx, 0x7C0005AE, X, General, X_FRT_RA0_RB,
-                "Store Floating-Point Double Indexed"),
-    INSTRUCTION(stfdux, 0x7C0005EE, X, General, X_FRT_RA_RB,
-                "Store Floating-Point Double with Update Indexed"),
-    INSTRUCTION(lhbrx, 0x7C00062C, X, General, X_RT_RA0_RB,
-                "Load Halfword Byte-Reverse Indexed"),
-    INSTRUCTION(srawx, 0x7C000630, X, General, X_RA_RT_RB,
-                "Shift Right Algebraic Word"),
-    INSTRUCTION(sradx, 0x7C000634, X, General, X_RA_RT_RB,
-                "Shift Right Algebraic Doubleword"),
-    INSTRUCTION(srawix, 0x7C000670, X, General, srawix,
-                "Shift Right Algebraic Word Immediate"),
-    INSTRUCTION(sradix, 0x7C000674, XS, General, sradix,
-                "Shift Right Algebraic Doubleword Immediate"),
-    INSTRUCTION(sradix, 0x7C000674, XS, General, sradix,
-                "Shift Right Algebraic Doubleword Immediate"),
-    INSTRUCTION(sradix, 0x7C000676, XS, General, sradix,
-                "Shift Right Algebraic Doubleword Immediate"),  // HACK
-    INSTRUCTION(eieio, 0x7C0006AC, X, General, _,
-                "Enforce In-Order Execution of I/O Instruction"),
-    INSTRUCTION(sthbrx, 0x7C00072C, X, General, X_RT_RA0_RB,
-                "Store Halfword Byte-Reverse Indexed"),
-    INSTRUCTION(extshx, 0x7C000734, X, General, X_RA_RT,
-                "Extend Sign Halfword"),
-    INSTRUCTION(extsbx, 0x7C000774, X, General, X_RA_RT, "Extend Sign Byte"),
-    INSTRUCTION(icbi, 0x7C0007AC, X, General, 0, NULL),
-    INSTRUCTION(stfiwx, 0x7C0007AE, X, General, X_FRT_RA0_RB,
-                "Store Floating-Point as Integer Word Indexed"),
-    INSTRUCTION(extswx, 0x7C0007B4, X, General, X_RA_RT, "Extend Sign Word"),
-    INSTRUCTION(dcbz, 0x7C0007EC, X, General, dcbz,
-                "Data Cache Block set to Zero"),  // 0x7C2007EC = DCBZ128
-    INSTRUCTION(dst, 0x7C0002AC, XDSS, General, 0, NULL),
-    INSTRUCTION(dstst, 0x7C0002EC, XDSS, General, 0, NULL),
-    INSTRUCTION(dss, 0x7C00066C, XDSS, General, 0, NULL),
-    INSTRUCTION(lvebx, 0x7C00000E, X, General, 0,
-                "Load Vector Element Byte Indexed"),
-    INSTRUCTION(lvehx, 0x7C00004E, X, General, 0,
-                "Load Vector Element Half Word Indexed"),
-    INSTRUCTION(lvewx, 0x7C00008E, X, General, 0,
-                "Load Vector Element Word Indexed"),
-    INSTRUCTION(lvsl, 0x7C00000C, X, General, 0, "Load Vector for Shift Left"),
-    INSTRUCTION(lvsr, 0x7C00004C, X, General, 0, "Load Vector for Shift Right"),
-    INSTRUCTION(lvx, 0x7C0000CE, X, General, 0, "Load Vector Indexed"),
-    INSTRUCTION(lvxl, 0x7C0002CE, X, General, 0, "Load Vector Indexed LRU"),
-    INSTRUCTION(stvebx, 0x7C00010E, X, General, 0,
-                "Store Vector Element Byte Indexed"),
-    INSTRUCTION(stvehx, 0x7C00014E, X, General, 0,
-                "Store Vector Element Half Word Indexed"),
-    INSTRUCTION(stvewx, 0x7C00018E, X, General, 0,
-                "Store Vector Element Word Indexed"),
-    INSTRUCTION(stvx, 0x7C0001CE, X, General, X_VX_RA0_RB,
-                "Store Vector Indexed"),
-    INSTRUCTION(stvxl, 0x7C0003CE, X, General, X_VX_RA0_RB,
-                "Store Vector Indexed LRU"),
-    INSTRUCTION(lvlx, 0x7C00040E, X, General, X_VX_RA0_RB,
-                "Load Vector Left Indexed"),
-    INSTRUCTION(lvlxl, 0x7C00060E, X, General, X_VX_RA0_RB,
-                "Load Vector Left Indexed LRU"),
-    INSTRUCTION(lvrx, 0x7C00044E, X, General, X_VX_RA0_RB,
-                "Load Vector Right Indexed"),
-    INSTRUCTION(lvrxl, 0x7C00064E, X, General, X_VX_RA0_RB,
-                "Load Vector Right Indexed LRU"),
-    INSTRUCTION(stvlx, 0x7C00050E, X, General, X_VX_RA0_RB,
-                "Store Vector Left Indexed"),
-    INSTRUCTION(stvlxl, 0x7C00070E, X, General, X_VX_RA0_RB,
-                "Store Vector Left Indexed LRU"),
-    INSTRUCTION(stvrx, 0x7C00054E, X, General, X_VX_RA0_RB,
-                "Store Vector Right Indexed"),
-    INSTRUCTION(stvrxl, 0x7C00074E, X, General, X_VX_RA0_RB,
-                "Store Vector Right Indexed LRU"),
-};
-static InstrType** instr_table_31 = instr_table_prep(
-    instr_table_31_unprep, xe::countof(instr_table_31_unprep), 1, 10);
-
-// Opcode = 58, index = bits 1-0 (2)
-static InstrType instr_table_58_unprep[] = {
-    INSTRUCTION(ld, 0xE8000000, DS, General, DS_RT_RA0_I, "Load Doubleword"),
-    INSTRUCTION(ldu, 0xE8000001, DS, General, DS_RT_RA_I,
-                "Load Doubleword with Update"),
-    INSTRUCTION(lwa, 0xE8000002, DS, General, DS_RT_RA0_I,
-                "Load Word Algebraic"),
-};
-static InstrType** instr_table_58 = instr_table_prep(
-    instr_table_58_unprep, xe::countof(instr_table_58_unprep), 0, 1);
-
-// Opcode = 59, index = bits 5-1 (5)
-static InstrType instr_table_59_unprep[] = {
-    INSTRUCTION(fdivsx, 0xEC000024, A, General, A_FRT_FRA_FRB,
-                "Floating Divide [Single]"),
-    INSTRUCTION(fsubsx, 0xEC000028, A, General, A_FRT_FRA_FRB,
-                "Floating Subtract [Single]"),
-    INSTRUCTION(faddsx, 0xEC00002A, A, General, A_FRT_FRA_FRB,
-                "Floating Add [Single]"),
-    INSTRUCTION(fsqrtsx, 0xEC00002C, A, General, A_FRT_FRB,
-                "Floating Square Root [Single]"),
-    INSTRUCTION(fresx, 0xEC000030, A, General, A_FRT_FRB,
-                "Floating Reciprocal Estimate [Single]"),
-    INSTRUCTION(fmulsx, 0xEC000032, A, General, A_FRT_FRA_FRB,
-                "Floating Multiply [Single]"),
-    INSTRUCTION(fmsubsx, 0xEC000038, A, General, A_FRT_FRA_FRB_FRC,
-                "Floating Multiply-Subtract [Single]"),
-    INSTRUCTION(fmaddsx, 0xEC00003A, A, General, A_FRT_FRA_FRB_FRC,
-                "Floating Multiply-Add [Single]"),
-    INSTRUCTION(fnmsubsx, 0xEC00003C, A, General, A_FRT_FRA_FRB_FRC,
-                "Floating Negative Multiply-Subtract [Single]"),
-    INSTRUCTION(fnmaddsx, 0xEC00003E, A, General, A_FRT_FRA_FRB_FRC,
-                "Floating Negative Multiply-Add [Single]"),
-};
-static InstrType** instr_table_59 = instr_table_prep(
-    instr_table_59_unprep, xe::countof(instr_table_59_unprep), 1, 5);
-
-// Opcode = 62, index = bits 1-0 (2)
-static InstrType instr_table_62_unprep[] = {
-    INSTRUCTION(std, 0xF8000000, DS, General, DS_RT_RA0_I, "Store Doubleword"),
-    INSTRUCTION(stdu, 0xF8000001, DS, General, DS_RT_RA_I,
-                "Store Doubleword with Update"),
-};
-static InstrType** instr_table_62 = instr_table_prep(
-    instr_table_62_unprep, xe::countof(instr_table_62_unprep), 0, 1);
-
-// Opcode = 63, index = bits 10-1 (10)
-// NOTE: the A format instructions need some special handling because
-//       they only use 6bits to identify their index.
-static InstrType instr_table_63_unprep[] = {
-    INSTRUCTION(fcmpu, 0xFC000000, X, General, fcmp,
-                "Floating Compare Unordered"),
-    INSTRUCTION(frspx, 0xFC000018, X, General, X_FRT_FRB,
-                "Floating Round to Single-Precision"),
-    INSTRUCTION(fctiwx, 0xFC00001C, X, General, X_FRT_FRB,
-                "Floating Convert To Integer Word"),
-    INSTRUCTION(fctiwzx, 0xFC00001E, X, General, X_FRT_FRB,
-                "Floating Convert To Integer Word with round toward Zero"),
-    INSTRUCTION(fdivx, 0xFC000024, A, General, A_FRT_FRA_FRB,
-                "Floating Divide [Single]"),
-    INSTRUCTION(fsubx, 0xFC000028, A, General, A_FRT_FRA_FRB,
-                "Floating Subtract [Single]"),
-    INSTRUCTION(faddx, 0xFC00002A, A, General, A_FRT_FRA_FRB,
-                "Floating Add [Single]"),
-    INSTRUCTION(fsqrtx, 0xFC00002C, A, General, A_FRT_FRB,
-                "Floating Square Root [Single]"),
-    INSTRUCTION(fselx, 0xFC00002E, A, General, A_FRT_FRA_FRB_FRC,
-                "Floating Select"),
-    INSTRUCTION(fmulx, 0xFC000032, A, General, A_FRT_FRA_FRB,
-                "Floating Multiply [Single]"),
-    INSTRUCTION(frsqrtex, 0xFC000034, A, General, A_FRT_FRB,
-                "Floating Reciprocal Square Root Estimate [Single]"),
-    INSTRUCTION(fmsubx, 0xFC000038, A, General, 0,
-                "Floating Multiply-Subtract [Single]"),
-    INSTRUCTION(fmaddx, 0xFC00003A, A, General, A_FRT_FRA_FRB_FRC,
-                "Floating Multiply-Add [Single]"),
-    INSTRUCTION(fnmsubx, 0xFC00003C, A, General, A_FRT_FRA_FRB_FRC,
-                "Floating Negative Multiply-Subtract [Single]"),
-    INSTRUCTION(fnmaddx, 0xFC00003E, A, General, A_FRT_FRA_FRB_FRC,
-                "Floating Negative Multiply-Add [Single]"),
-    INSTRUCTION(fcmpo, 0xFC000040, X, General, fcmp,
-                "Floating Compare Ordered"),
-    INSTRUCTION(mtfsb1x, 0xFC00004C, X, General, 0, NULL),
-    INSTRUCTION(fnegx, 0xFC000050, X, General, X_FRT_FRB, "Floating Negate"),
-    INSTRUCTION(mcrfs, 0xFC000080, X, General, 0, NULL),
-    INSTRUCTION(mtfsb0x, 0xFC00008C, X, General, 0, NULL),
-    INSTRUCTION(fmrx, 0xFC000090, X, General, X_FRT_FRB,
-                "Floating Move Register"),
-    INSTRUCTION(mtfsfix, 0xFC00010C, X, General, 0, NULL),
-    INSTRUCTION(fnabsx, 0xFC000110, X, General, X_FRT_FRB,
-                "Floating Negative Absolute Value"),
-    INSTRUCTION(fabsx, 0xFC000210, X, General, X_FRT_FRB,
-                "Floating Absolute Value"),
-    INSTRUCTION(mffsx, 0xFC00048E, X, General, 0, "Move from FPSCR"),
-    INSTRUCTION(mtfsfx, 0xFC00058E, XFL, General, 0, "Move to FPSCR Fields"),
-    INSTRUCTION(fctidx, 0xFC00065C, X, General, X_FRT_FRB,
-                "Floating Convert To Integer Doubleword"),
-    INSTRUCTION(
-        fctidzx, 0xFC00065E, X, General, X_FRT_FRB,
-        "Floating Convert To Integer Doubleword with round toward Zero"),
-    INSTRUCTION(fcfidx, 0xFC00069C, X, General, X_FRT_FRB,
-                "Floating Convert From Integer Doubleword"),
-};
-static InstrType** instr_table_63 = instr_table_prep_63(
-    instr_table_63_unprep, xe::countof(instr_table_63_unprep), 1, 10);
-
-// Main table, index = bits 31-26 (6) : (code >> 26)
-static InstrType instr_table_unprep[64] = {
-    INSTRUCTION(tdi, 0x08000000, D, General, D_RA, "Trap Doubleword Immediate"),
-    INSTRUCTION(twi, 0x0C000000, D, General, D_RA, "Trap Word Immediate"),
-    INSTRUCTION(mulli, 0x1C000000, D, General, D_RT_RA_I,
-                "Multiply Low Immediate"),
-    INSTRUCTION(subficx, 0x20000000, D, General, D_RT_RA_I,
-                "Subtract From Immediate Carrying"),
-    INSTRUCTION(cmpli, 0x28000000, D, General, cmpli,
-                "Compare Logical Immediate"),
-    INSTRUCTION(cmpi, 0x2C000000, D, General, cmpi, "Compare Immediate"),
-    INSTRUCTION(addic, 0x30000000, D, General, D_RT_RA_I,
-                "Add Immediate Carrying"),
-    INSTRUCTION(addicx, 0x34000000, D, General, D_RT_RA_I,
-                "Add Immediate Carrying and Record"),
-    INSTRUCTION(addi, 0x38000000, D, General, D_RT_RA0_I, "Add Immediate"),
-    INSTRUCTION(addis, 0x3C000000, D, General, D_RT_RA0_I,
-                "Add Immediate Shifted"),
-    INSTRUCTION(bcx, 0x40000000, B, BranchCond, bcx, "Branch Conditional"),
-    INSTRUCTION(sc, 0x44000002, SC, Syscall, 0, NULL),
-    INSTRUCTION(bx, 0x48000000, I, BranchAlways, bx, "Branch"),
-    INSTRUCTION(rlwimix, 0x50000000, M, General, rlwim,
-                "Rotate Left Word Immediate then Mask Insert"),
-    INSTRUCTION(rlwinmx, 0x54000000, M, General, rlwim,
-                "Rotate Left Word Immediate then AND with Mask"),
-    INSTRUCTION(rlwnmx, 0x5C000000, M, General, rlwnmx,
-                "Rotate Left Word then AND with Mask"),
-    INSTRUCTION(ori, 0x60000000, D, General, D_RA_RT_I, "OR Immediate"),
-    INSTRUCTION(oris, 0x64000000, D, General, D_RA_RT_I,
-                "OR Immediate Shifted"),
-    INSTRUCTION(xori, 0x68000000, D, General, D_RA_RT_I, "XOR Immediate"),
-    INSTRUCTION(xoris, 0x6C000000, D, General, D_RA_RT_I,
-                "XOR Immediate Shifted"),
-    INSTRUCTION(andix, 0x70000000, D, General, D_RA_RT_I, "AND Immediate"),
-    INSTRUCTION(andisx, 0x74000000, D, General, D_RA_RT_I,
-                "AND Immediate Shifted"),
-    INSTRUCTION(lwz, 0x80000000, D, General, D_RT_RA0_I, "Load Word and Zero"),
-    INSTRUCTION(lwzu, 0x84000000, D, General, D_RT_RA_I,
-                "Load Word and Zero with Udpate"),
-    INSTRUCTION(lbz, 0x88000000, D, General, D_RT_RA0_I, "Load Byte and Zero"),
-    INSTRUCTION(lbzu, 0x8C000000, D, General, D_RT_RA_I,
-                "Load Byte and Zero with Update"),
-    INSTRUCTION(stw, 0x90000000, D, General, D_RT_RA0_I, "Store Word"),
-    INSTRUCTION(stwu, 0x94000000, D, General, D_RT_RA_I,
-                "Store Word with Update"),
-    INSTRUCTION(stb, 0x98000000, D, General, D_RT_RA0_I, "Store Byte"),
-    INSTRUCTION(stbu, 0x9C000000, D, General, D_RT_RA_I,
-                "Store Byte with Update"),
-    INSTRUCTION(lhz, 0xA0000000, D, General, D_RT_RA0_I,
-                "Load Halfword and Zero"),
-    INSTRUCTION(lhzu, 0xA4000000, D, General, D_RT_RA_I,
-                "Load Halfword and Zero with Update"),
-    INSTRUCTION(lha, 0xA8000000, D, General, D_RT_RA0_I,
-                "Load Halfword Algebraic"),
-    INSTRUCTION(lhau, 0xAC000000, D, General, D_RT_RA_I, NULL),
-    INSTRUCTION(sth, 0xB0000000, D, General, D_RT_RA0_I, "Store Halfword"),
-    INSTRUCTION(sthu, 0xB4000000, D, General, D_RT_RA_I,
-                "Store Halfword with Update"),
-    INSTRUCTION(lmw, 0xB8000000, D, General, 0, NULL),
-    INSTRUCTION(stmw, 0xBC000000, D, General, 0, NULL),
-    INSTRUCTION(lfs, 0xC0000000, D, General, D_FRT_RA0_I,
-                "Load Floating-Point Single"),
-    INSTRUCTION(lfsu, 0xC4000000, D, General, D_FRT_RA_I,
-                "Load Floating-Point Single with Update"),
-    INSTRUCTION(lfd, 0xC8000000, D, General, D_FRT_RA0_I,
-                "Load Floating-Point Double"),
-    INSTRUCTION(lfdu, 0xCC000000, D, General, D_FRT_RA_I,
-                "Load Floating-Point Double with Update"),
-    INSTRUCTION(stfs, 0xD0000000, D, General, D_FRT_RA0_I,
-                "Store Floating-Point Single"),
-    INSTRUCTION(stfsu, 0xD4000000, D, General, D_FRT_RA_I,
-                "Store Floating-Point Single with Update"),
-    INSTRUCTION(stfd, 0xD8000000, D, General, D_FRT_RA0_I,
-                "Store Floating-Point Double"),
-    INSTRUCTION(stfdu, 0xDC000000, D, General, D_FRT_RA_I,
-                "Store Floating-Point Double with Update"),
-};
-static InstrType** instr_table = instr_table_prep(
-    instr_table_unprep, xe::countof(instr_table_unprep), 26, 31);
-
-// Altivec instructions.
-// TODO(benvanik): build a table like the other instructions.
-// This table is looked up via linear scan of opcodes.
-#define SCAN_INSTRUCTION(name, opcode, format, type, disasm_fn, descr) \
-  {                                                                    \
-    opcode, kXEPPCInstrMask##format, kXEPPCInstrFormat##format,        \
-        Disasm_##disasm_fn,                                            \
-  }
-#define OP(x) ((((uint32_t)(x)) & 0x3f) << 26)
-#define VX128(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x3d0))
-#define VX128_1(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x7f3))
-#define VX128_2(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x210))
-#define VX128_3(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x7f0))
-#define VX128_4(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x730))
-#define VX128_5(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x10))
-#define VX128_P(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x630))
-#define VX128_R(op, xop) (OP(op) | (((uint32_t)(xop)) & 0x390))
-static InstrType instr_table_scan[] = {
-    SCAN_INSTRUCTION(vcmpbfp, 0x100003C6, VXR, General, 0,
-                     "Vector Compare Bounds Floating Point"),
-    SCAN_INSTRUCTION(vcmpeqfp, 0x100000C6, VXR, General, 0,
-                     "Vector Compare Equal-to Floating Point"),
-    SCAN_INSTRUCTION(vcmpequb, 0x10000006, VXR, General, 0,
-                     "Vector Compare Equal-to Unsigned Byte"),
-    SCAN_INSTRUCTION(vcmpequh, 0x10000046, VXR, General, 0,
-                     "Vector Compare Equal-to Unsigned Half Word"),
-    SCAN_INSTRUCTION(vcmpequw, 0x10000086, VXR, General, 0,
-                     "Vector Compare Equal-to Unsigned Word"),
-    SCAN_INSTRUCTION(vcmpgefp, 0x100001C6, VXR, General, 0,
-                     "Vector Compare Greater-Than-or-Equal-to Floating Point"),
-    SCAN_INSTRUCTION(vcmpgtfp, 0x100002C6, VXR, General, 0,
-                     "Vector Compare Greater-Than Floating Point"),
-    SCAN_INSTRUCTION(vcmpgtsb, 0x10000306, VXR, General, 0,
-                     "Vector Compare Greater-Than Signed Byte"),
-    SCAN_INSTRUCTION(vcmpgtsh, 0x10000346, VXR, General, 0,
-                     "Vector Compare Greater-Than Signed Half Word"),
-    SCAN_INSTRUCTION(vcmpgtsw, 0x10000386, VXR, General, 0,
-                     "Vector Compare Greater-Than Signed Word"),
-    SCAN_INSTRUCTION(vcmpgtub, 0x10000206, VXR, General, 0,
-                     "Vector Compare Greater-Than Unsigned Byte"),
-    SCAN_INSTRUCTION(vcmpgtuh, 0x10000246, VXR, General, 0,
-                     "Vector Compare Greater-Than Unsigned Half Word"),
-    SCAN_INSTRUCTION(vcmpgtuw, 0x10000286, VXR, General, 0,
-                     "Vector Compare Greater-Than Unsigned Word"),
-    SCAN_INSTRUCTION(vmaddfp, 0x1000002E, VXA, General, VXA_VD_VA_VB_VC,
-                     "Vector Multiply-Add Floating Point"),
-    SCAN_INSTRUCTION(
-        vmhaddshs, 0x10000020, VXA, General, VXA_VD_VA_VB_VC,
-        "Vector Multiply-High and Add Signed Signed Half Word Saturate"),
-    SCAN_INSTRUCTION(
-        vmhraddshs, 0x10000021, VXA, General, VXA_VD_VA_VB_VC,
-        "Vector Multiply-High Round and Add Signed Signed Half Word Saturate"),
-    SCAN_INSTRUCTION(vmladduhm, 0x10000022, VXA, General, VXA_VD_VA_VB_VC,
-                     "Vector Multiply-Low and Add Unsigned Half Word Modulo"),
-    SCAN_INSTRUCTION(vmsummbm, 0x10000025, VXA, General, VXA_VD_VA_VB_VC,
-                     "Vector Multiply-Sum Mixed-Sign Byte Modulo"),
-    SCAN_INSTRUCTION(vmsumshm, 0x10000028, VXA, General, VXA_VD_VA_VB_VC,
-                     "Vector Multiply-Sum Signed Half Word Modulo"),
-    SCAN_INSTRUCTION(vmsumshs, 0x10000029, VXA, General, VXA_VD_VA_VB_VC,
-                     "Vector Multiply-Sum Signed Half Word Saturate"),
-    SCAN_INSTRUCTION(vmsumubm, 0x10000024, VXA, General, VXA_VD_VA_VB_VC,
-                     "Vector Multiply-Sum Unsigned Byte Modulo"),
-    SCAN_INSTRUCTION(vmsumuhm, 0x10000026, VXA, General, VXA_VD_VA_VB_VC,
-                     "Vector Multiply-Sum Unsigned Half Word Modulo"),
-    SCAN_INSTRUCTION(vmsumuhs, 0x10000027, VXA, General, VXA_VD_VA_VB_VC,
-                     "Vector Multiply-Sum Unsigned Half Word Saturate"),
-    SCAN_INSTRUCTION(vnmsubfp, 0x1000002F, VXA, General, VXA_VD_VA_VB_VC,
-                     "Vector Negative Multiply-Subtract Floating Point"),
-    SCAN_INSTRUCTION(vperm, 0x1000002B, VXA, General, VXA_VD_VA_VB_VC,
-                     "Vector Permute"),
-    SCAN_INSTRUCTION(vsel, 0x1000002A, VXA, General, VXA_VD_VA_VB_VC,
-                     "Vector Conditional Select"),
-    SCAN_INSTRUCTION(vsldoi, 0x1000002C, VXA, General, VXA_VD_VA_VB_VC,
-                     "Vector Shift Left Double by Octet Immediate"),
-    SCAN_INSTRUCTION(lvsl128, VX128_1(4, 3), VX128_1, General, VX1281_VD_RA0_RB,
-                     "Load Vector128 for Shift Left"),
-    SCAN_INSTRUCTION(lvsr128, VX128_1(4, 67), VX128_1, General,
-                     VX1281_VD_RA0_RB, "Load Vector128 for Shift Right"),
-    SCAN_INSTRUCTION(lvewx128, VX128_1(4, 131), VX128_1, General,
-                     VX1281_VD_RA0_RB, "Load Vector128 Element Word Indexed"),
-    SCAN_INSTRUCTION(lvx128, VX128_1(4, 195), VX128_1, General,
-                     VX1281_VD_RA0_RB, "Load Vector128 Indexed"),
-    SCAN_INSTRUCTION(stvewx128, VX128_1(4, 387), VX128_1, General,
-                     VX1281_VD_RA0_RB, "Store Vector128 Element Word Indexed"),
-    SCAN_INSTRUCTION(stvx128, VX128_1(4, 451), VX128_1, General,
-                     VX1281_VD_RA0_RB, "Store Vector128 Indexed"),
-    SCAN_INSTRUCTION(lvxl128, VX128_1(4, 707), VX128_1, General,
-                     VX1281_VD_RA0_RB, "Load Vector128 Left Indexed"),
-    SCAN_INSTRUCTION(stvxl128, VX128_1(4, 963), VX128_1, General,
-                     VX1281_VD_RA0_RB, "Store Vector128 Indexed LRU"),
-    SCAN_INSTRUCTION(lvlx128, VX128_1(4, 1027), VX128_1, General,
-                     VX1281_VD_RA0_RB, "Load Vector128 Left Indexed LRU"),
-    SCAN_INSTRUCTION(lvrx128, VX128_1(4, 1091), VX128_1, General,
-                     VX1281_VD_RA0_RB, "Load Vector128 Right Indexed"),
-    SCAN_INSTRUCTION(stvlx128, VX128_1(4, 1283), VX128_1, General,
-                     VX1281_VD_RA0_RB, "Store Vector128 Left Indexed"),
-    SCAN_INSTRUCTION(stvrx128, VX128_1(4, 1347), VX128_1, General,
-                     VX1281_VD_RA0_RB, "Store Vector128 Right Indexed"),
-    SCAN_INSTRUCTION(lvlxl128, VX128_1(4, 1539), VX128_1, General,
-                     VX1281_VD_RA0_RB, "Load Vector128 Indexed LRU"),
-    SCAN_INSTRUCTION(lvrxl128, VX128_1(4, 1603), VX128_1, General,
-                     VX1281_VD_RA0_RB, "Load Vector128 Right Indexed LRU"),
-    SCAN_INSTRUCTION(stvlxl128, VX128_1(4, 1795), VX128_1, General,
-                     VX1281_VD_RA0_RB, "Store Vector128 Left Indexed LRU"),
-    SCAN_INSTRUCTION(stvrxl128, VX128_1(4, 1859), VX128_1, General,
-                     VX1281_VD_RA0_RB, "Store Vector128 Right Indexed LRU"),
-    SCAN_INSTRUCTION(vsldoi128, VX128_5(4, 16), VX128_5, General, vsldoi128,
-                     "Vector128 Shift Left Double by Octet Immediate"),
-    SCAN_INSTRUCTION(vperm128, VX128_2(5, 0), VX128_2, General,
-                     VX1282_VD_VA_VB_VC, "Vector128 Permute"),
-    SCAN_INSTRUCTION(vaddfp128, VX128(5, 16), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Add Floating Point"),
-    SCAN_INSTRUCTION(vsubfp128, VX128(5, 80), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Subtract Floating Point"),
-    SCAN_INSTRUCTION(vmulfp128, VX128(5, 144), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Multiply Floating-Point"),
-    SCAN_INSTRUCTION(vmaddfp128, VX128(5, 208), VX128, General,
-                     VX128_VD_VA_VD_VB,
-                     "Vector128 Multiply Add Floating Point"),
-    SCAN_INSTRUCTION(vmaddcfp128, VX128(5, 272), VX128, General,
-                     VX128_VD_VA_VD_VB,
-                     "Vector128 Multiply Add Floating Point"),
-    SCAN_INSTRUCTION(vnmsubfp128, VX128(5, 336), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Negative Multiply-Subtract Floating Point"),
-    SCAN_INSTRUCTION(vmsum3fp128, VX128(5, 400), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Multiply Sum 3-way Floating Point"),
-    SCAN_INSTRUCTION(vmsum4fp128, VX128(5, 464), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Multiply Sum 4-way Floating-Point"),
-    SCAN_INSTRUCTION(vpkshss128, VX128(5, 512), VX128, General, 0,
-                     "Vector128 Pack Signed Half Word Signed Saturate"),
-    SCAN_INSTRUCTION(vand128, VX128(5, 528), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Logical AND"),
-    SCAN_INSTRUCTION(vpkshus128, VX128(5, 576), VX128, General, 0,
-                     "Vector128 Pack Signed Half Word Unsigned Saturate"),
-    SCAN_INSTRUCTION(vandc128, VX128(5, 592), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Logical AND with Complement"),
-    SCAN_INSTRUCTION(vpkswss128, VX128(5, 640), VX128, General, 0,
-                     "Vector128 Pack Signed Word Signed Saturate"),
-    SCAN_INSTRUCTION(vnor128, VX128(5, 656), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Logical NOR"),
-    SCAN_INSTRUCTION(vpkswus128, VX128(5, 704), VX128, General, 0,
-                     "Vector128 Pack Signed Word Unsigned Saturate"),
-    SCAN_INSTRUCTION(vor128, VX128(5, 720), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Logical OR"),
-    SCAN_INSTRUCTION(vpkuhum128, VX128(5, 768), VX128, General, 0,
-                     "Vector128 Pack Unsigned Half Word Unsigned Modulo"),
-    SCAN_INSTRUCTION(vxor128, VX128(5, 784), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Logical XOR"),
-    SCAN_INSTRUCTION(vpkuhus128, VX128(5, 832), VX128, General, 0,
-                     "Vector128 Pack Unsigned Half Word Unsigned Saturate"),
-    SCAN_INSTRUCTION(vsel128, VX128(5, 848), VX128, General, 0,
-                     "Vector128 Conditional Select"),
-    SCAN_INSTRUCTION(vpkuwum128, VX128(5, 896), VX128, General, 0,
-                     "Vector128 Pack Unsigned Word Unsigned Modulo"),
-    SCAN_INSTRUCTION(vslo128, VX128(5, 912), VX128, General, 0,
-                     "Vector128 Shift Left Octet"),
-    SCAN_INSTRUCTION(vpkuwus128, VX128(5, 960), VX128, General, 0,
-                     "Vector128 Pack Unsigned Word Unsigned Saturate"),
-    SCAN_INSTRUCTION(vsro128, VX128(5, 976), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Shift Right Octet"),
-    SCAN_INSTRUCTION(vpermwi128, VX128_P(6, 528), VX128_P, General, vpermwi128,
-                     "Vector128 Permutate Word Immediate"),
-    SCAN_INSTRUCTION(vcfpsxws128, VX128_3(6, 560), VX128_3, General,
-                     VX1283_VD_VB_I,
-                     "Vector128 Convert From Floating-Point to Signed "
-                     "Fixed-Point Word Saturate"),
-    SCAN_INSTRUCTION(vcfpuxws128, VX128_3(6, 624), VX128_3, General, 0,
-                     "Vector128 Convert From Floating-Point to Unsigned "
-                     "Fixed-Point Word Saturate"),
-    SCAN_INSTRUCTION(
-        vcsxwfp128, VX128_3(6, 688), VX128_3, General, VX1283_VD_VB_I,
-        "Vector128 Convert From Signed Fixed-Point Word to Floating-Point"),
-    SCAN_INSTRUCTION(
-        vcuxwfp128, VX128_3(6, 752), VX128_3, General, 0,
-        "Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point"),
-    SCAN_INSTRUCTION(
-        vrfim128, VX128_3(6, 816), VX128_3, General, 0,
-        "Vector128 Round to Floating-Point Integer toward -Infinity"),
-    SCAN_INSTRUCTION(vrfin128, VX128_3(6, 880), VX128_3, General, vrfin128,
-                     "Vector128 Round to Floating-Point Integer Nearest"),
-    SCAN_INSTRUCTION(
-        vrfip128, VX128_3(6, 944), VX128_3, General, 0,
-        "Vector128 Round to Floating-Point Integer toward +Infinity"),
-    SCAN_INSTRUCTION(vrfiz128, VX128_3(6, 1008), VX128_3, General, 0,
-                     "Vector128 Round to Floating-Point Integer toward Zero"),
-    SCAN_INSTRUCTION(
-        vpkd3d128, VX128_4(6, 1552), VX128_4, General, 0,
-        "Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert"),
-    SCAN_INSTRUCTION(vrefp128, VX128_3(6, 1584), VX128_3, General, 0,
-                     "Vector128 Reciprocal Estimate Floating Point"),
-    SCAN_INSTRUCTION(
-        vrsqrtefp128, VX128_3(6, 1648), VX128_3, General, VX1283_VD_VB,
-        "Vector128 Reciprocal Square Root Estimate Floating Point"),
-    SCAN_INSTRUCTION(vexptefp128, VX128_3(6, 1712), VX128_3, General, 0,
-                     "Vector128 Log2 Estimate Floating Point"),
-    SCAN_INSTRUCTION(vlogefp128, VX128_3(6, 1776), VX128_3, General, 0,
-                     "Vector128 Log2 Estimate Floating Point"),
-    SCAN_INSTRUCTION(vrlimi128, VX128_4(6, 1808), VX128_4, General, vrlimi128,
-                     "Vector128 Rotate Left Immediate and Mask Insert"),
-    SCAN_INSTRUCTION(vspltw128, VX128_3(6, 1840), VX128_3, General,
-                     VX1283_VD_VB_I, "Vector128 Splat Word"),
-    SCAN_INSTRUCTION(vspltisw128, VX128_3(6, 1904), VX128_3, General,
-                     VX1283_VD_VB_I, "Vector128 Splat Immediate Signed Word"),
-    SCAN_INSTRUCTION(vupkd3d128, VX128_3(6, 2032), VX128_3, General,
-                     VX1283_VD_VB_I, "Vector128 Unpack D3Dtype"),
-    SCAN_INSTRUCTION(vcmpeqfp128, VX128_R(6, 0), VX128_R, General,
-                     VX128_VD_VA_VB,
-                     "Vector128 Compare Equal-to Floating Point"),
-    SCAN_INSTRUCTION(vrlw128, VX128(6, 80), VX128, General, 0,
-                     "Vector128 Rotate Left Word"),
-    SCAN_INSTRUCTION(
-        vcmpgefp128,
-        VX128_R(6, 128), VX128_R, General, 0,
-        "Vector128 Compare Greater-Than-or-Equal-to Floating Point"),
-    SCAN_INSTRUCTION(vslw128, VX128(6, 208), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Shift Left Integer Word"),
-    SCAN_INSTRUCTION(vcmpgtfp128, VX128_R(6, 256), VX128_R, General, 0,
-                     "Vector128 Compare Greater-Than Floating-Point"),
-    SCAN_INSTRUCTION(vsraw128, VX128(6, 336), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Shift Right Arithmetic Word"),
-    SCAN_INSTRUCTION(vcmpbfp128, VX128_R(6, 384), VX128_R, General, 0,
-                     "Vector128 Compare Bounds Floating Point"),
-    SCAN_INSTRUCTION(vsrw128, VX128(6, 464), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Shift Right Word"),
-    SCAN_INSTRUCTION(vcmpequw128, VX128_R(6, 512), VX128_R, General,
-                     VX128_VD_VA_VB,
-                     "Vector128 Compare Equal-to Unsigned Word"),
-    SCAN_INSTRUCTION(vmaxfp128, VX128(6, 640), VX128, General, 0,
-                     "Vector128 Maximum Floating Point"),
-    SCAN_INSTRUCTION(vminfp128, VX128(6, 704), VX128, General, 0,
-                     "Vector128 Minimum Floating Point"),
-    SCAN_INSTRUCTION(vmrghw128, VX128(6, 768), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Merge High Word"),
-    SCAN_INSTRUCTION(vmrglw128, VX128(6, 832), VX128, General, VX128_VD_VA_VB,
-                     "Vector128 Merge Low Word"),
-    SCAN_INSTRUCTION(vupkhsb128, VX128(6, 896), VX128, General, 0,
-                     "Vector128 Unpack High Signed Byte"),
-    SCAN_INSTRUCTION(vupklsb128, VX128(6, 960), VX128, General, 0,
-                     "Vector128 Unpack Low Signed Byte"),
-};
-#undef OP
-#undef VX128
-#undef VX128_1
-#undef VX128_2
-#undef VX128_3
-#undef VX128_4
-#undef VX128_5
-#undef VX128_P
-
-#undef FLAG
-#undef INSTRUCTION
-#undef EMPTY
-
-}  // namespace tables
-}  // namespace ppc
-}  // namespace cpu
-}  // namespace xe
-
-#endif  // XENIA_CPU_PPC_PPC_INSTR_TABLES_H_
diff --git a/src/xenia/cpu/ppc/ppc_opcode.h b/src/xenia/cpu/ppc/ppc_opcode.h
index ad333260f..7bda98615 100644
--- a/src/xenia/cpu/ppc/ppc_opcode.h
+++ b/src/xenia/cpu/ppc/ppc_opcode.h
@@ -9,7 +9,7 @@ namespace xe {
 namespace cpu {
 namespace ppc {
 
-// All PPC opcodes in the same order they appear in ppc_instr_table.h:
+// All PPC opcodes in the same order they appear in ppc_opcode_table.h:
 enum class PPCOpcode : uint32_t {
   addcx,
   addex,
@@ -54,8 +54,6 @@ enum class PPCOpcode : uint32_t {
   divdx,
   divwux,
   divwx,
-  eciwx,
-  ecowx,
   eieio,
   eqvx,
   extsbx,
diff --git a/src/xenia/cpu/ppc/ppc_opcode_disasm.cc b/src/xenia/cpu/ppc/ppc_opcode_disasm.cc
new file mode 100644
index 000000000..7dc36bd90
--- /dev/null
+++ b/src/xenia/cpu/ppc/ppc_opcode_disasm.cc
@@ -0,0 +1,5449 @@
+// This code was autogenerated by tools/ppc-table-gen.py. Do not modify!
+// clang-format off
+#include <cstdint>
+
+#include "xenia/base/assert.h"
+#include "xenia/cpu/ppc/ppc_decode_data.h"
+#include "xenia/cpu/ppc/ppc_opcode.h"
+#include "xenia/cpu/ppc/ppc_opcode_info.h"
+
+namespace xe {
+namespace cpu {
+namespace ppc {
+
+constexpr size_t kNamePad = 11;
+const uint8_t kSpaces[kNamePad] = {0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20};
+void PadStringBuffer(StringBuffer* str, size_t base, size_t pad) {
+  size_t added_len = str->length() - base;
+  if (added_len < pad) str->AppendBytes(kSpaces, kNamePad - added_len);
+}
+
+void PrintDisasm_addcx(const PPCDecodeData& d, StringBuffer* str) {
+  // addc[OE][Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("addc");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_addex(const PPCDecodeData& d, StringBuffer* str) {
+  // adde[OE][Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("adde");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_addi(const PPCDecodeData& d, StringBuffer* str) {
+  // addi [RD], [RA0], [SIMM]
+  size_t str_start = str->length();
+  str->Append("addi");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RA0());
+  str->Append(", ");
+  str->AppendFormat(d.D.SIMM() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.SIMM()));
+}
+void PrintDisasm_addic(const PPCDecodeData& d, StringBuffer* str) {
+  // addic [RD], [RA], [SIMM]
+  size_t str_start = str->length();
+  str->Append("addic");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(", ");
+  str->AppendFormat(d.D.SIMM() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.SIMM()));
+}
+void PrintDisasm_addicx(const PPCDecodeData& d, StringBuffer* str) {
+  // addic. [RD], [RA], [SIMM]
+  size_t str_start = str->length();
+  str->Append("addic.");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(", ");
+  str->AppendFormat(d.D.SIMM() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.SIMM()));
+}
+void PrintDisasm_addis(const PPCDecodeData& d, StringBuffer* str) {
+  // addis [RD], [RA0], [SIMM]
+  size_t str_start = str->length();
+  str->Append("addis");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RA0());
+  str->Append(", ");
+  str->AppendFormat(d.D.SIMM() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.SIMM()));
+}
+void PrintDisasm_addmex(const PPCDecodeData& d, StringBuffer* str) {
+  // addme[OE][Rc] [RD], [RA]
+  size_t str_start = str->length();
+  str->Append("addme");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+}
+void PrintDisasm_addx(const PPCDecodeData& d, StringBuffer* str) {
+  // add[OE][Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("add");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_addzex(const PPCDecodeData& d, StringBuffer* str) {
+  // addze[OE][Rc] [RD], [RA]
+  size_t str_start = str->length();
+  str->Append("addze");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+}
+void PrintDisasm_andcx(const PPCDecodeData& d, StringBuffer* str) {
+  // andc[Rc] [RA], [RS], [RB]
+  size_t str_start = str->length();
+  str->Append("andc");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_andisx(const PPCDecodeData& d, StringBuffer* str) {
+  // andis. [RA], [RS], [UIMM]
+  size_t str_start = str->length();
+  str->Append("andis.");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RS());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.D.UIMM());
+}
+void PrintDisasm_andix(const PPCDecodeData& d, StringBuffer* str) {
+  // andi. [RA], [RS], [UIMM]
+  size_t str_start = str->length();
+  str->Append("andi.");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RS());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.D.UIMM());
+}
+void PrintDisasm_andx(const PPCDecodeData& d, StringBuffer* str) {
+  // and[Rc] [RA], [RS], [RB]
+  size_t str_start = str->length();
+  str->Append("and");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_bcctrx(const PPCDecodeData& d, StringBuffer* str) {
+  // bcctr[LK] [BO], [BI]
+  size_t str_start = str->length();
+  str->Append("bcctr");
+  if (d.XL.LK()) str->Append('l');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("%d", d.XL.BO());
+  str->Append(", ");
+  str->AppendFormat("%d", d.XL.BI());
+}
+void PrintDisasm_bclrx(const PPCDecodeData& d, StringBuffer* str) {
+  // bclr[LK] [BO], [BI]
+  size_t str_start = str->length();
+  str->Append("bclr");
+  if (d.XL.LK()) str->Append('l');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("%d", d.XL.BO());
+  str->Append(", ");
+  str->AppendFormat("%d", d.XL.BI());
+}
+void PrintDisasm_bcx(const PPCDecodeData& d, StringBuffer* str) {
+  // bc[LK][AA] [BO], [BI], [ADDR]
+  size_t str_start = str->length();
+  str->Append("bc");
+  if (d.B.LK()) str->Append('l');
+  if (d.B.AA()) str->Append('a');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("%d", d.B.BO());
+  str->Append(", ");
+  str->AppendFormat("%d", d.B.BI());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.B.ADDR());
+}
+void PrintDisasm_bx(const PPCDecodeData& d, StringBuffer* str) {
+  // b[LK][AA] [ADDR]
+  size_t str_start = str->length();
+  str->Append("b");
+  if (d.I.LK()) str->Append('l');
+  if (d.I.AA()) str->Append('a');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("0x%X", d.I.ADDR());
+}
+void PrintDisasm_cmp(const PPCDecodeData& d, StringBuffer* str) {
+  // cmp [CRFD], [L], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("cmp");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crf%d", d.X.CRFD());
+  str->Append(", ");
+  str->AppendFormat("%d", d.X.L());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_cmpi(const PPCDecodeData& d, StringBuffer* str) {
+  // cmpi [CRFD], [L], [RA], [SIMM]
+  size_t str_start = str->length();
+  str->Append("cmpi");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crf%d", d.D.CRFD());
+  str->Append(", ");
+  str->AppendFormat("%d", d.D.L());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(", ");
+  str->AppendFormat(d.D.SIMM() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.SIMM()));
+}
+void PrintDisasm_cmpl(const PPCDecodeData& d, StringBuffer* str) {
+  // cmpl [CRFD], [L], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("cmpl");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crf%d", d.X.CRFD());
+  str->Append(", ");
+  str->AppendFormat("%d", d.X.L());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_cmpli(const PPCDecodeData& d, StringBuffer* str) {
+  // cmpli [CRFD], [L], [RA], [UIMM]
+  size_t str_start = str->length();
+  str->Append("cmpli");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crf%d", d.D.CRFD());
+  str->Append(", ");
+  str->AppendFormat("%d", d.D.L());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.D.UIMM());
+}
+void PrintDisasm_cntlzdx(const PPCDecodeData& d, StringBuffer* str) {
+  // cntlzd[Rc] [RA], [RS]
+  size_t str_start = str->length();
+  str->Append("cntlzd");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+}
+void PrintDisasm_cntlzwx(const PPCDecodeData& d, StringBuffer* str) {
+  // cntlzw[Rc] [RA], [RS]
+  size_t str_start = str->length();
+  str->Append("cntlzw");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+}
+void PrintDisasm_crand(const PPCDecodeData& d, StringBuffer* str) {
+  // crand [CRBD], [CRBA], [CRBB]
+  size_t str_start = str->length();
+  str->Append("crand");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crb%d", d.XL.CRBD());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBA());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBB());
+}
+void PrintDisasm_crandc(const PPCDecodeData& d, StringBuffer* str) {
+  // crandc [CRBD], [CRBA], [CRBB]
+  size_t str_start = str->length();
+  str->Append("crandc");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crb%d", d.XL.CRBD());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBA());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBB());
+}
+void PrintDisasm_creqv(const PPCDecodeData& d, StringBuffer* str) {
+  // creqv [CRBD], [CRBA], [CRBB]
+  size_t str_start = str->length();
+  str->Append("creqv");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crb%d", d.XL.CRBD());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBA());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBB());
+}
+void PrintDisasm_crnand(const PPCDecodeData& d, StringBuffer* str) {
+  // crnand [CRBD], [CRBA], [CRBB]
+  size_t str_start = str->length();
+  str->Append("crnand");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crb%d", d.XL.CRBD());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBA());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBB());
+}
+void PrintDisasm_crnor(const PPCDecodeData& d, StringBuffer* str) {
+  // crnor [CRBD], [CRBA], [CRBB]
+  size_t str_start = str->length();
+  str->Append("crnor");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crb%d", d.XL.CRBD());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBA());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBB());
+}
+void PrintDisasm_cror(const PPCDecodeData& d, StringBuffer* str) {
+  // cror [CRBD], [CRBA], [CRBB]
+  size_t str_start = str->length();
+  str->Append("cror");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crb%d", d.XL.CRBD());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBA());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBB());
+}
+void PrintDisasm_crorc(const PPCDecodeData& d, StringBuffer* str) {
+  // crorc [CRBD], [CRBA], [CRBB]
+  size_t str_start = str->length();
+  str->Append("crorc");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crb%d", d.XL.CRBD());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBA());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBB());
+}
+void PrintDisasm_crxor(const PPCDecodeData& d, StringBuffer* str) {
+  // crxor [CRBD], [CRBA], [CRBB]
+  size_t str_start = str->length();
+  str->Append("crxor");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crb%d", d.XL.CRBD());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBA());
+  str->Append(", ");
+  str->AppendFormat("crb%d", d.XL.CRBB());
+}
+void PrintDisasm_dcba(const PPCDecodeData& d, StringBuffer* str) {
+  // dcba [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("dcba");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_dcbf(const PPCDecodeData& d, StringBuffer* str) {
+  // dcbf [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("dcbf");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_dcbi(const PPCDecodeData& d, StringBuffer* str) {
+  // dcbi [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("dcbi");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_dcbst(const PPCDecodeData& d, StringBuffer* str) {
+  // dcbst [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("dcbst");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_dcbt(const PPCDecodeData& d, StringBuffer* str) {
+  // dcbt [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("dcbt");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_dcbtst(const PPCDecodeData& d, StringBuffer* str) {
+  // dcbtst [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("dcbtst");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_dcbz(const PPCDecodeData& d, StringBuffer* str) {
+  // dcbz [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("dcbz");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.DCBZ.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.DCBZ.RB());
+}
+void PrintDisasm_dcbz128(const PPCDecodeData& d, StringBuffer* str) {
+  // dcbz128 [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("dcbz128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.DCBZ.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.DCBZ.RB());
+}
+void PrintDisasm_divdux(const PPCDecodeData& d, StringBuffer* str) {
+  // divdu[OE][Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("divdu");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_divdx(const PPCDecodeData& d, StringBuffer* str) {
+  // divd[OE][Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("divd");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_divwux(const PPCDecodeData& d, StringBuffer* str) {
+  // divwu[OE][Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("divwu");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_divwx(const PPCDecodeData& d, StringBuffer* str) {
+  // divw[OE][Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("divw");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_eieio(const PPCDecodeData& d, StringBuffer* str) {
+  // eieio
+  size_t str_start = str->length();
+  str->Append("eieio");
+  PadStringBuffer(str, str_start, kNamePad);
+}
+void PrintDisasm_eqvx(const PPCDecodeData& d, StringBuffer* str) {
+  // eqv[Rc] [RA], [RS], [RB]
+  size_t str_start = str->length();
+  str->Append("eqv");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_extsbx(const PPCDecodeData& d, StringBuffer* str) {
+  // extsb[Rc] [RA], [RS]
+  size_t str_start = str->length();
+  str->Append("extsb");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+}
+void PrintDisasm_extshx(const PPCDecodeData& d, StringBuffer* str) {
+  // extsh[Rc] [RA], [RS]
+  size_t str_start = str->length();
+  str->Append("extsh");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+}
+void PrintDisasm_extswx(const PPCDecodeData& d, StringBuffer* str) {
+  // extsw[Rc] [RA], [RS]
+  size_t str_start = str->length();
+  str->Append("extsw");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+}
+void PrintDisasm_fabsx(const PPCDecodeData& d, StringBuffer* str) {
+  // fabs[Rc] [FD], [FB]
+  size_t str_start = str->length();
+  str->Append("fabs");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.X.FB());
+}
+void PrintDisasm_faddsx(const PPCDecodeData& d, StringBuffer* str) {
+  // fadds[Rc] [FD], [FA], [FB]
+  size_t str_start = str->length();
+  str->Append("fadds");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_faddx(const PPCDecodeData& d, StringBuffer* str) {
+  // fadd[Rc] [FD], [FA], [FB]
+  size_t str_start = str->length();
+  str->Append("fadd");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fcfidx(const PPCDecodeData& d, StringBuffer* str) {
+  // fcfid[Rc] [FD], [FB]
+  size_t str_start = str->length();
+  str->Append("fcfid");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.X.FB());
+}
+void PrintDisasm_fcmpo(const PPCDecodeData& d, StringBuffer* str) {
+  // fcmpo [CRFD], [FA], [FB]
+  size_t str_start = str->length();
+  str->Append("fcmpo");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crf%d", d.X.CRFD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.X.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.X.FB());
+}
+void PrintDisasm_fcmpu(const PPCDecodeData& d, StringBuffer* str) {
+  // fcmpu [CRFD], [FA], [FB]
+  size_t str_start = str->length();
+  str->Append("fcmpu");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crf%d", d.X.CRFD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.X.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.X.FB());
+}
+void PrintDisasm_fctidx(const PPCDecodeData& d, StringBuffer* str) {
+  // fctid[Rc] [FD], [FB]
+  size_t str_start = str->length();
+  str->Append("fctid");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.X.FB());
+}
+void PrintDisasm_fctidzx(const PPCDecodeData& d, StringBuffer* str) {
+  // fctidz[Rc] [FD], [FB]
+  size_t str_start = str->length();
+  str->Append("fctidz");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.X.FB());
+}
+void PrintDisasm_fctiwx(const PPCDecodeData& d, StringBuffer* str) {
+  // fctiw[Rc] [FD], [FB]
+  size_t str_start = str->length();
+  str->Append("fctiw");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.X.FB());
+}
+void PrintDisasm_fctiwzx(const PPCDecodeData& d, StringBuffer* str) {
+  // fctiwz[Rc] [FD], [FB]
+  size_t str_start = str->length();
+  str->Append("fctiwz");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.X.FB());
+}
+void PrintDisasm_fdivsx(const PPCDecodeData& d, StringBuffer* str) {
+  // fdivs[Rc] [FD], [FA], [FB]
+  size_t str_start = str->length();
+  str->Append("fdivs");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fdivx(const PPCDecodeData& d, StringBuffer* str) {
+  // fdiv[Rc] [FD], [FA], [FB]
+  size_t str_start = str->length();
+  str->Append("fdiv");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fmaddsx(const PPCDecodeData& d, StringBuffer* str) {
+  // fmadds[Rc] [FD], [FA], [FC], [FB]
+  size_t str_start = str->length();
+  str->Append("fmadds");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FC());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fmaddx(const PPCDecodeData& d, StringBuffer* str) {
+  // fmadd[Rc] [FD], [FA], [FC], [FB]
+  size_t str_start = str->length();
+  str->Append("fmadd");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FC());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fmrx(const PPCDecodeData& d, StringBuffer* str) {
+  // fmr[Rc] [FD], [FB]
+  size_t str_start = str->length();
+  str->Append("fmr");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.X.FB());
+}
+void PrintDisasm_fmsubsx(const PPCDecodeData& d, StringBuffer* str) {
+  // fmsubs[Rc] [FD], [FA], [FC], [FB]
+  size_t str_start = str->length();
+  str->Append("fmsubs");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FC());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fmsubx(const PPCDecodeData& d, StringBuffer* str) {
+  // fmsub[Rc] [FD], [FA], [FC], [FB]
+  size_t str_start = str->length();
+  str->Append("fmsub");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FC());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fmulsx(const PPCDecodeData& d, StringBuffer* str) {
+  // fmuls[Rc] [FD], [FA], [FC]
+  size_t str_start = str->length();
+  str->Append("fmuls");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FC());
+}
+void PrintDisasm_fmulx(const PPCDecodeData& d, StringBuffer* str) {
+  // fmul[Rc] [FD], [FA], [FC]
+  size_t str_start = str->length();
+  str->Append("fmul");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FC());
+}
+void PrintDisasm_fnabsx(const PPCDecodeData& d, StringBuffer* str) {
+  // fnabs[Rc] [FD], [FB]
+  size_t str_start = str->length();
+  str->Append("fnabs");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.X.FB());
+}
+void PrintDisasm_fnegx(const PPCDecodeData& d, StringBuffer* str) {
+  // fneg[Rc] [FD], [FB]
+  size_t str_start = str->length();
+  str->Append("fneg");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.X.FB());
+}
+void PrintDisasm_fnmaddsx(const PPCDecodeData& d, StringBuffer* str) {
+  // fnmadds[Rc] [FD], [FA], [FC], [FB]
+  size_t str_start = str->length();
+  str->Append("fnmadds");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FC());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fnmaddx(const PPCDecodeData& d, StringBuffer* str) {
+  // fnmadd[Rc] [FD], [FA], [FC], [FB]
+  size_t str_start = str->length();
+  str->Append("fnmadd");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FC());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fnmsubsx(const PPCDecodeData& d, StringBuffer* str) {
+  // fnmsubs[Rc] [FD], [FA], [FC], [FB]
+  size_t str_start = str->length();
+  str->Append("fnmsubs");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FC());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fnmsubx(const PPCDecodeData& d, StringBuffer* str) {
+  // fnmsub[Rc] [FD], [FA], [FC], [FB]
+  size_t str_start = str->length();
+  str->Append("fnmsub");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FC());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fresx(const PPCDecodeData& d, StringBuffer* str) {
+  // fres[Rc] [FD], [FB]
+  size_t str_start = str->length();
+  str->Append("fres");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_frspx(const PPCDecodeData& d, StringBuffer* str) {
+  // frsp[Rc] [FD], [FB]
+  size_t str_start = str->length();
+  str->Append("frsp");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.X.FB());
+}
+void PrintDisasm_frsqrtex(const PPCDecodeData& d, StringBuffer* str) {
+  // frsqrte[Rc] [FD], [FB]
+  size_t str_start = str->length();
+  str->Append("frsqrte");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fselx(const PPCDecodeData& d, StringBuffer* str) {
+  // fsel[Rc] [FD], [FA], [FC], [FB]
+  size_t str_start = str->length();
+  str->Append("fsel");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FC());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fsqrtsx(const PPCDecodeData& d, StringBuffer* str) {
+  // fsqrts[Rc] [FD], [FB]
+  size_t str_start = str->length();
+  str->Append("fsqrts");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fsqrtx(const PPCDecodeData& d, StringBuffer* str) {
+  // fsqrt[Rc] [FD], [FB]
+  size_t str_start = str->length();
+  str->Append("fsqrt");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fsubsx(const PPCDecodeData& d, StringBuffer* str) {
+  // fsubs[Rc] [FD], [FA], [FB]
+  size_t str_start = str->length();
+  str->Append("fsubs");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_fsubx(const PPCDecodeData& d, StringBuffer* str) {
+  // fsub[Rc] [FD], [FA], [FB]
+  size_t str_start = str->length();
+  str->Append("fsub");
+  if (d.A.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.A.FD());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FA());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.A.FB());
+}
+void PrintDisasm_icbi(const PPCDecodeData& d, StringBuffer* str) {
+  // icbi [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("icbi");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_isync(const PPCDecodeData& d, StringBuffer* str) {
+  // isync
+  size_t str_start = str->length();
+  str->Append("isync");
+  PadStringBuffer(str, str_start, kNamePad);
+}
+void PrintDisasm_lbz(const PPCDecodeData& d, StringBuffer* str) {
+  // lbz [RD], [d]([RA0])
+  size_t str_start = str->length();
+  str->Append("lbz");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RD());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA0());
+  str->Append(")");
+}
+void PrintDisasm_lbzu(const PPCDecodeData& d, StringBuffer* str) {
+  // lbzu [RD], [d]([RA])
+  size_t str_start = str->length();
+  str->Append("lbzu");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RD());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(")");
+}
+void PrintDisasm_lbzux(const PPCDecodeData& d, StringBuffer* str) {
+  // lbzux [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("lbzux");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lbzx(const PPCDecodeData& d, StringBuffer* str) {
+  // lbzx [RD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lbzx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_ld(const PPCDecodeData& d, StringBuffer* str) {
+  // ld [RD], [ds]([RA0])
+  size_t str_start = str->length();
+  str->Append("ld");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.DS.RD());
+  str->Append(", ");
+  str->AppendFormat(d.DS.ds() < 0 ? "-0x%X" : "0x%X", std::abs(d.DS.ds()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.DS.RA0());
+  str->Append(")");
+}
+void PrintDisasm_ldarx(const PPCDecodeData& d, StringBuffer* str) {
+  // ldarx [RD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("ldarx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_ldbrx(const PPCDecodeData& d, StringBuffer* str) {
+  // ldbrx [RD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("ldbrx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_ldu(const PPCDecodeData& d, StringBuffer* str) {
+  // ldu [RD], [ds]([RA])
+  size_t str_start = str->length();
+  str->Append("ldu");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.DS.RD());
+  str->Append(", ");
+  str->AppendFormat(d.DS.ds() < 0 ? "-0x%X" : "0x%X", std::abs(d.DS.ds()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.DS.RA());
+  str->Append(")");
+}
+void PrintDisasm_ldux(const PPCDecodeData& d, StringBuffer* str) {
+  // ldux [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("ldux");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_ldx(const PPCDecodeData& d, StringBuffer* str) {
+  // ldx [RD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("ldx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lfd(const PPCDecodeData& d, StringBuffer* str) {
+  // lfd [FD], [d]([RA0])
+  size_t str_start = str->length();
+  str->Append("lfd");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.D.FD());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA0());
+  str->Append(")");
+}
+void PrintDisasm_lfdu(const PPCDecodeData& d, StringBuffer* str) {
+  // lfdu [FD], [d]([RA])
+  size_t str_start = str->length();
+  str->Append("lfdu");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.D.FD());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(")");
+}
+void PrintDisasm_lfdux(const PPCDecodeData& d, StringBuffer* str) {
+  // lfdux [FD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("lfdux");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lfdx(const PPCDecodeData& d, StringBuffer* str) {
+  // lfdx [FD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lfdx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lfs(const PPCDecodeData& d, StringBuffer* str) {
+  // lfs [FD], [d]([RA0])
+  size_t str_start = str->length();
+  str->Append("lfs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.D.FD());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA0());
+  str->Append(")");
+}
+void PrintDisasm_lfsu(const PPCDecodeData& d, StringBuffer* str) {
+  // lfsu [FD], [d]([RA])
+  size_t str_start = str->length();
+  str->Append("lfsu");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.D.FD());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(")");
+}
+void PrintDisasm_lfsux(const PPCDecodeData& d, StringBuffer* str) {
+  // lfsux [FD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("lfsux");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lfsx(const PPCDecodeData& d, StringBuffer* str) {
+  // lfsx [FD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lfsx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lha(const PPCDecodeData& d, StringBuffer* str) {
+  // lha [RD], [d]([RA0])
+  size_t str_start = str->length();
+  str->Append("lha");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RD());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA0());
+  str->Append(")");
+}
+void PrintDisasm_lhau(const PPCDecodeData& d, StringBuffer* str) {
+  // lhau [RD], [d]([RA])
+  size_t str_start = str->length();
+  str->Append("lhau");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RD());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(")");
+}
+void PrintDisasm_lhaux(const PPCDecodeData& d, StringBuffer* str) {
+  // lhaux [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("lhaux");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lhax(const PPCDecodeData& d, StringBuffer* str) {
+  // lhax [RD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lhax");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lhbrx(const PPCDecodeData& d, StringBuffer* str) {
+  // lhbrx [RD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lhbrx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lhz(const PPCDecodeData& d, StringBuffer* str) {
+  // lhz [RD], [d]([RA0])
+  size_t str_start = str->length();
+  str->Append("lhz");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RD());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA0());
+  str->Append(")");
+}
+void PrintDisasm_lhzu(const PPCDecodeData& d, StringBuffer* str) {
+  // lhzu [RD], [d]([RA])
+  size_t str_start = str->length();
+  str->Append("lhzu");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RD());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(")");
+}
+void PrintDisasm_lhzux(const PPCDecodeData& d, StringBuffer* str) {
+  // lhzux [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("lhzux");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lhzx(const PPCDecodeData& d, StringBuffer* str) {
+  // lhzx [RD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lhzx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lvebx(const PPCDecodeData& d, StringBuffer* str) {
+  // lvebx [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvebx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lvehx(const PPCDecodeData& d, StringBuffer* str) {
+  // lvehx [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvehx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lvewx(const PPCDecodeData& d, StringBuffer* str) {
+  // lvewx [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvewx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lvewx128(const PPCDecodeData& d, StringBuffer* str) {
+  // lvewx128 [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvewx128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_lvlx(const PPCDecodeData& d, StringBuffer* str) {
+  // lvlx [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvlx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lvlx128(const PPCDecodeData& d, StringBuffer* str) {
+  // lvlx128 [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvlx128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_lvlxl(const PPCDecodeData& d, StringBuffer* str) {
+  // lvlxl [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvlxl");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lvlxl128(const PPCDecodeData& d, StringBuffer* str) {
+  // lvlxl128 [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvlxl128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_lvrx(const PPCDecodeData& d, StringBuffer* str) {
+  // lvrx [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvrx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lvrx128(const PPCDecodeData& d, StringBuffer* str) {
+  // lvrx128 [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvrx128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_lvrxl(const PPCDecodeData& d, StringBuffer* str) {
+  // lvrxl [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvrxl");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lvrxl128(const PPCDecodeData& d, StringBuffer* str) {
+  // lvrxl128 [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvrxl128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_lvsl(const PPCDecodeData& d, StringBuffer* str) {
+  // lvsl [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvsl");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lvsl128(const PPCDecodeData& d, StringBuffer* str) {
+  // lvsl128 [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvsl128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_lvsr(const PPCDecodeData& d, StringBuffer* str) {
+  // lvsr [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvsr");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lvsr128(const PPCDecodeData& d, StringBuffer* str) {
+  // lvsr128 [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvsr128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_lvx(const PPCDecodeData& d, StringBuffer* str) {
+  // lvx [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lvx128(const PPCDecodeData& d, StringBuffer* str) {
+  // lvx128 [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvx128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_lvxl(const PPCDecodeData& d, StringBuffer* str) {
+  // lvslx [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvslx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lvxl128(const PPCDecodeData& d, StringBuffer* str) {
+  // lvxl128 [VD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lvxl128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_lwa(const PPCDecodeData& d, StringBuffer* str) {
+  // lwa [RD], [ds]([RA0])
+  size_t str_start = str->length();
+  str->Append("lwa");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.DS.RD());
+  str->Append(", ");
+  str->AppendFormat(d.DS.ds() < 0 ? "-0x%X" : "0x%X", std::abs(d.DS.ds()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.DS.RA0());
+  str->Append(")");
+}
+void PrintDisasm_lwarx(const PPCDecodeData& d, StringBuffer* str) {
+  // lwarx [RD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lwarx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lwaux(const PPCDecodeData& d, StringBuffer* str) {
+  // lwaux [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("lwaux");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lwax(const PPCDecodeData& d, StringBuffer* str) {
+  // lwax [RD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lwax");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lwbrx(const PPCDecodeData& d, StringBuffer* str) {
+  // lwbrx [RD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lwbrx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lwz(const PPCDecodeData& d, StringBuffer* str) {
+  // lwz [RD], [d]([RA0])
+  size_t str_start = str->length();
+  str->Append("lwz");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RD());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA0());
+  str->Append(")");
+}
+void PrintDisasm_lwzu(const PPCDecodeData& d, StringBuffer* str) {
+  // lwzu [RD], [d]([RA])
+  size_t str_start = str->length();
+  str->Append("lwzu");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RD());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(")");
+}
+void PrintDisasm_lwzux(const PPCDecodeData& d, StringBuffer* str) {
+  // lwzux [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("lwzux");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_lwzx(const PPCDecodeData& d, StringBuffer* str) {
+  // lwzx [RD], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("lwzx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_mcrf(const PPCDecodeData& d, StringBuffer* str) {
+  // mcrf [CRFD], [CRFS]
+  size_t str_start = str->length();
+  str->Append("mcrf");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crf%d", d.XL.CRFD());
+  str->Append(", ");
+  str->AppendFormat("crf%d", d.XL.CRFS());
+}
+void PrintDisasm_mcrfs(const PPCDecodeData& d, StringBuffer* str) {
+  // mcrfs [CRFD], [CRFS]
+  size_t str_start = str->length();
+  str->Append("mcrfs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crf%d", d.X.CRFD());
+  str->Append(", ");
+  str->AppendFormat("crf%d", d.X.CRFS());
+}
+void PrintDisasm_mcrxr(const PPCDecodeData& d, StringBuffer* str) {
+  // mcrxr [CRFD]
+  size_t str_start = str->length();
+  str->Append("mcrxr");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crf%d", d.X.CRFD());
+}
+void PrintDisasm_mfcr(const PPCDecodeData& d, StringBuffer* str) {
+  // mfcr [RD]
+  size_t str_start = str->length();
+  str->Append("mfcr");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+}
+void PrintDisasm_mffsx(const PPCDecodeData& d, StringBuffer* str) {
+  // mffs[Rc] [RD]
+  size_t str_start = str->length();
+  str->Append("mffs");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+}
+void PrintDisasm_mfmsr(const PPCDecodeData& d, StringBuffer* str) {
+  // mfmsr [RD]
+  size_t str_start = str->length();
+  str->Append("mfmsr");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RD());
+}
+void PrintDisasm_mfspr(const PPCDecodeData& d, StringBuffer* str) {
+  // mfspr [RD], [SPR]
+  size_t str_start = str->length();
+  str->Append("mfspr");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XFX.RD());
+  str->Append(", ");
+  str->AppendFormat("%d", d.XFX.SPR());
+}
+void PrintDisasm_mftb(const PPCDecodeData& d, StringBuffer* str) {
+  // mftb [RD], [TBR]
+  size_t str_start = str->length();
+  str->Append("mftb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XFX.RD());
+  str->Append(", ");
+  str->AppendFormat("%d", d.XFX.TBR());
+}
+void PrintDisasm_mtcrf(const PPCDecodeData& d, StringBuffer* str) {
+  // mtcrf [CRM], [RS]
+  size_t str_start = str->length();
+  str->Append("mtcrf");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("(UNHANDLED CRM)");
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XFX.RS());
+}
+void PrintDisasm_mtfsb0x(const PPCDecodeData& d, StringBuffer* str) {
+  // mtfsb0[Rc] [FPSCRD]
+  size_t str_start = str->length();
+  str->Append("mtfsb0");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("(UNHANDLED FPSCRD)");
+}
+void PrintDisasm_mtfsb1x(const PPCDecodeData& d, StringBuffer* str) {
+  // mtfsb1[Rc] [FPSCRD]
+  size_t str_start = str->length();
+  str->Append("mtfsb1");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("(UNHANDLED FPSCRD)");
+}
+void PrintDisasm_mtfsfix(const PPCDecodeData& d, StringBuffer* str) {
+  // mtfsfi[Rc] [CRFD], [IMM]
+  size_t str_start = str->length();
+  str->Append("mtfsfi");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("crf%d", d.X.CRFD());
+  str->Append(", ");
+  str->AppendFormat("%d", d.X.IMM());
+}
+void PrintDisasm_mtfsfx(const PPCDecodeData& d, StringBuffer* str) {
+  // mtfsf[Rc] [FM], [FB]
+  size_t str_start = str->length();
+  str->Append("mtfsf");
+  if (d.XFL.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("%d", d.XFL.FM());
+  str->Append(", ");
+  str->AppendFormat("fr%d", d.XFL.FB());
+}
+void PrintDisasm_mtmsr(const PPCDecodeData& d, StringBuffer* str) {
+  // mtmsr [RS]
+  size_t str_start = str->length();
+  str->Append("mtmsr");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RS());
+}
+void PrintDisasm_mtmsrd(const PPCDecodeData& d, StringBuffer* str) {
+  // mtmsrd [RS]
+  size_t str_start = str->length();
+  str->Append("mtmsrd");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RS());
+}
+void PrintDisasm_mtspr(const PPCDecodeData& d, StringBuffer* str) {
+  // mtmspr [SPR], [RS]
+  size_t str_start = str->length();
+  str->Append("mtmspr");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("%d", d.XFX.SPR());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XFX.RS());
+}
+void PrintDisasm_mulhdux(const PPCDecodeData& d, StringBuffer* str) {
+  // mulhdu[Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("mulhdu");
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_mulhdx(const PPCDecodeData& d, StringBuffer* str) {
+  // mulhd[Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("mulhd");
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_mulhwux(const PPCDecodeData& d, StringBuffer* str) {
+  // mulhwu[Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("mulhwu");
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_mulhwx(const PPCDecodeData& d, StringBuffer* str) {
+  // mulhw[Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("mulhw");
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_mulldx(const PPCDecodeData& d, StringBuffer* str) {
+  // mulld[OE][Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("mulld");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_mulli(const PPCDecodeData& d, StringBuffer* str) {
+  // mulli [RD], [RA], [SIMM]
+  size_t str_start = str->length();
+  str->Append("mulli");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(", ");
+  str->AppendFormat(d.D.SIMM() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.SIMM()));
+}
+void PrintDisasm_mullwx(const PPCDecodeData& d, StringBuffer* str) {
+  // mullw[OE][Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("mullw");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_nandx(const PPCDecodeData& d, StringBuffer* str) {
+  // nand[Rc] [RA], [RS], [RB]
+  size_t str_start = str->length();
+  str->Append("nand");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_negx(const PPCDecodeData& d, StringBuffer* str) {
+  // neg[OE][Rc] [RD], [RA]
+  size_t str_start = str->length();
+  str->Append("neg");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+}
+void PrintDisasm_norx(const PPCDecodeData& d, StringBuffer* str) {
+  // nor[Rc] [RA], [RS], [RB]
+  size_t str_start = str->length();
+  str->Append("nor");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_orcx(const PPCDecodeData& d, StringBuffer* str) {
+  // orc[Rc] [RA], [RS], [RB]
+  size_t str_start = str->length();
+  str->Append("orc");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_ori(const PPCDecodeData& d, StringBuffer* str) {
+  // ori [RA], [RS], [UIMM]
+  size_t str_start = str->length();
+  str->Append("ori");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RS());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.D.UIMM());
+}
+void PrintDisasm_oris(const PPCDecodeData& d, StringBuffer* str) {
+  // oris [RA], [RS], [UIMM]
+  size_t str_start = str->length();
+  str->Append("oris");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RS());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.D.UIMM());
+}
+void PrintDisasm_orx(const PPCDecodeData& d, StringBuffer* str) {
+  // or[Rc] [RA], [RS], [RB]
+  size_t str_start = str->length();
+  str->Append("or");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_rldclx(const PPCDecodeData& d, StringBuffer* str) {
+  // rldcl[Rc] [RA], [RS], [RB], [MB]
+  size_t str_start = str->length();
+  str->Append("rldcl");
+  if (d.MDS.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.MDS.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.MDS.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.MDS.RB());
+  str->Append(", ");
+  str->AppendFormat("%d", d.MDS.MB());
+}
+void PrintDisasm_rldcrx(const PPCDecodeData& d, StringBuffer* str) {
+  // rldcr[Rc] [RA], [RS], [RB], [ME]
+  size_t str_start = str->length();
+  str->Append("rldcr");
+  if (d.MDS.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.MDS.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.MDS.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.MDS.RB());
+  str->Append(", ");
+  str->AppendFormat("%d", d.MDS.ME());
+}
+void PrintDisasm_rldiclx(const PPCDecodeData& d, StringBuffer* str) {
+  // rldicl[Rc] [RA], [RS], [SH], [MB]
+  size_t str_start = str->length();
+  str->Append("rldicl");
+  if (d.MD.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.MD.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.MD.RS());
+  str->Append(", ");
+  str->AppendFormat("%d", d.MD.SH());
+  str->Append(", ");
+  str->AppendFormat("%d", d.MD.MB());
+}
+void PrintDisasm_rldicrx(const PPCDecodeData& d, StringBuffer* str) {
+  // rldicr[Rc] [RA], [RS], [SH], [ME]
+  size_t str_start = str->length();
+  str->Append("rldicr");
+  if (d.MD.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.MD.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.MD.RS());
+  str->Append(", ");
+  str->AppendFormat("%d", d.MD.SH());
+  str->Append(", ");
+  str->AppendFormat("%d", d.MD.ME());
+}
+void PrintDisasm_rldicx(const PPCDecodeData& d, StringBuffer* str) {
+  // rldic[Rc] [RA], [RS], [SH], [MB]
+  size_t str_start = str->length();
+  str->Append("rldic");
+  if (d.MD.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.MD.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.MD.RS());
+  str->Append(", ");
+  str->AppendFormat("%d", d.MD.SH());
+  str->Append(", ");
+  str->AppendFormat("%d", d.MD.MB());
+}
+void PrintDisasm_rldimix(const PPCDecodeData& d, StringBuffer* str) {
+  // rldimi[Rc] [RA], [RS], [SH], [MB]
+  size_t str_start = str->length();
+  str->Append("rldimi");
+  if (d.MD.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.MD.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.MD.RS());
+  str->Append(", ");
+  str->AppendFormat("%d", d.MD.SH());
+  str->Append(", ");
+  str->AppendFormat("%d", d.MD.MB());
+}
+void PrintDisasm_rlwimix(const PPCDecodeData& d, StringBuffer* str) {
+  // rlwimi[Rc] [RA], [RS], [SH], [MB], [ME]
+  size_t str_start = str->length();
+  str->Append("rlwimi");
+  if (d.M.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.M.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.M.RS());
+  str->Append(", ");
+  str->AppendFormat("%d", d.M.SH());
+  str->Append(", ");
+  str->AppendFormat("%d", d.M.MB());
+  str->Append(", ");
+  str->AppendFormat("%d", d.M.ME());
+}
+void PrintDisasm_rlwinmx(const PPCDecodeData& d, StringBuffer* str) {
+  // rlwinm[Rc] [RA], [RS], [SH], [MB], [ME]
+  size_t str_start = str->length();
+  str->Append("rlwinm");
+  if (d.M.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.M.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.M.RS());
+  str->Append(", ");
+  str->AppendFormat("%d", d.M.SH());
+  str->Append(", ");
+  str->AppendFormat("%d", d.M.MB());
+  str->Append(", ");
+  str->AppendFormat("%d", d.M.ME());
+}
+void PrintDisasm_rlwnmx(const PPCDecodeData& d, StringBuffer* str) {
+  // rlwnm[Rc] [RA], [RS], [RB], [MB], [ME]
+  size_t str_start = str->length();
+  str->Append("rlwnm");
+  if (d.M.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.M.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.M.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.M.RB());
+  str->Append(", ");
+  str->AppendFormat("%d", d.M.MB());
+  str->Append(", ");
+  str->AppendFormat("%d", d.M.ME());
+}
+void PrintDisasm_sc(const PPCDecodeData& d, StringBuffer* str) {
+  // sc
+  size_t str_start = str->length();
+  str->Append("sc");
+  PadStringBuffer(str, str_start, kNamePad);
+}
+void PrintDisasm_sldx(const PPCDecodeData& d, StringBuffer* str) {
+  // sld[Rc] [RA], [RS], [RB]
+  size_t str_start = str->length();
+  str->Append("sld");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_slwx(const PPCDecodeData& d, StringBuffer* str) {
+  // slw[Rc] [RA], [RS], [RB]
+  size_t str_start = str->length();
+  str->Append("slw");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_sradix(const PPCDecodeData& d, StringBuffer* str) {
+  // sradi[Rc] [RA], [RS], [SH]
+  size_t str_start = str->length();
+  str->Append("sradi");
+  if (d.XS.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XS.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XS.RS());
+  str->Append(", ");
+  str->AppendFormat("%d", d.XS.SH());
+}
+void PrintDisasm_sradx(const PPCDecodeData& d, StringBuffer* str) {
+  // srad[Rc] [RA], [RS], [RB]
+  size_t str_start = str->length();
+  str->Append("srad");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_srawix(const PPCDecodeData& d, StringBuffer* str) {
+  // srawi[Rc] [RA], [RS], [SH]
+  size_t str_start = str->length();
+  str->Append("srawi");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("%d", d.X.SH());
+}
+void PrintDisasm_srawx(const PPCDecodeData& d, StringBuffer* str) {
+  // sraw[Rc] [RA], [RS], [RB]
+  size_t str_start = str->length();
+  str->Append("sraw");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_srdx(const PPCDecodeData& d, StringBuffer* str) {
+  // srd[Rc] [RA], [RS], [RB]
+  size_t str_start = str->length();
+  str->Append("srd");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_srwx(const PPCDecodeData& d, StringBuffer* str) {
+  // srw[Rc] [RA], [RS], [RB]
+  size_t str_start = str->length();
+  str->Append("srw");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stb(const PPCDecodeData& d, StringBuffer* str) {
+  // stb [RS], [d]([RA0])
+  size_t str_start = str->length();
+  str->Append("stb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RS());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA0());
+  str->Append(")");
+}
+void PrintDisasm_stbu(const PPCDecodeData& d, StringBuffer* str) {
+  // stbu [RS], [d]([RA])
+  size_t str_start = str->length();
+  str->Append("stbu");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RS());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(")");
+}
+void PrintDisasm_stbux(const PPCDecodeData& d, StringBuffer* str) {
+  // stbux [RS], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("stbux");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stbx(const PPCDecodeData& d, StringBuffer* str) {
+  // stbx [RS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stbx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_std(const PPCDecodeData& d, StringBuffer* str) {
+  // std [RS], [ds]([RA0])
+  size_t str_start = str->length();
+  str->Append("std");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.DS.RS());
+  str->Append(", ");
+  str->AppendFormat(d.DS.ds() < 0 ? "-0x%X" : "0x%X", std::abs(d.DS.ds()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.DS.RA0());
+  str->Append(")");
+}
+void PrintDisasm_stdbrx(const PPCDecodeData& d, StringBuffer* str) {
+  // stdbrx [RS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stdbrx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stdcx(const PPCDecodeData& d, StringBuffer* str) {
+  // stdcx. [RS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stdcx.");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stdu(const PPCDecodeData& d, StringBuffer* str) {
+  // stdu [RS], [ds]([RA])
+  size_t str_start = str->length();
+  str->Append("stdu");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.DS.RS());
+  str->Append(", ");
+  str->AppendFormat(d.DS.ds() < 0 ? "-0x%X" : "0x%X", std::abs(d.DS.ds()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.DS.RA());
+  str->Append(")");
+}
+void PrintDisasm_stdux(const PPCDecodeData& d, StringBuffer* str) {
+  // stdux [RS], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("stdux");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stdx(const PPCDecodeData& d, StringBuffer* str) {
+  // stdx [RS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stdx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stfd(const PPCDecodeData& d, StringBuffer* str) {
+  // stfd [FS], [d]([RA0])
+  size_t str_start = str->length();
+  str->Append("stfd");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.D.FS());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA0());
+  str->Append(")");
+}
+void PrintDisasm_stfdu(const PPCDecodeData& d, StringBuffer* str) {
+  // stfdu [FS], [d]([RA])
+  size_t str_start = str->length();
+  str->Append("stfdu");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.D.FS());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(")");
+}
+void PrintDisasm_stfdux(const PPCDecodeData& d, StringBuffer* str) {
+  // stfdux [FS], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("stfdux");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stfdx(const PPCDecodeData& d, StringBuffer* str) {
+  // stfdx [FS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stfdx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stfiwx(const PPCDecodeData& d, StringBuffer* str) {
+  // stfiwx [FS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stfiwx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stfs(const PPCDecodeData& d, StringBuffer* str) {
+  // stfs [FS], [d]([RA0])
+  size_t str_start = str->length();
+  str->Append("stfs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.D.FS());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA0());
+  str->Append(")");
+}
+void PrintDisasm_stfsu(const PPCDecodeData& d, StringBuffer* str) {
+  // stfsu [FS], [d]([RA])
+  size_t str_start = str->length();
+  str->Append("stfsu");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.D.FS());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(")");
+}
+void PrintDisasm_stfsux(const PPCDecodeData& d, StringBuffer* str) {
+  // stfsux [FS], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("stfsux");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stfsx(const PPCDecodeData& d, StringBuffer* str) {
+  // stfsx [FS], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("stfsx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("fr%d", d.X.FS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_sth(const PPCDecodeData& d, StringBuffer* str) {
+  // sth [RS], [d]([RA0])
+  size_t str_start = str->length();
+  str->Append("sth");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RS());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA0());
+  str->Append(")");
+}
+void PrintDisasm_sthbrx(const PPCDecodeData& d, StringBuffer* str) {
+  // sthbrx [RS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("sthbrx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_sthu(const PPCDecodeData& d, StringBuffer* str) {
+  // sthu [RS], [d]([RA])
+  size_t str_start = str->length();
+  str->Append("sthu");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RS());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(")");
+}
+void PrintDisasm_sthux(const PPCDecodeData& d, StringBuffer* str) {
+  // sthux [RS], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("sthux");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_sthx(const PPCDecodeData& d, StringBuffer* str) {
+  // sthx [RS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("sthx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stvebx(const PPCDecodeData& d, StringBuffer* str) {
+  // stvebx [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvebx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stvehx(const PPCDecodeData& d, StringBuffer* str) {
+  // stvehx [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvehx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stvewx(const PPCDecodeData& d, StringBuffer* str) {
+  // stvewx [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvewx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stvewx128(const PPCDecodeData& d, StringBuffer* str) {
+  // stvewx128 [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvewx128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_stvlx(const PPCDecodeData& d, StringBuffer* str) {
+  // stvlx [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvlx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stvlx128(const PPCDecodeData& d, StringBuffer* str) {
+  // stvlx128 [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvlx128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_stvlxl(const PPCDecodeData& d, StringBuffer* str) {
+  // stvlxl [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvlxl");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stvlxl128(const PPCDecodeData& d, StringBuffer* str) {
+  // stvlxl128 [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvlxl128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_stvrx(const PPCDecodeData& d, StringBuffer* str) {
+  // stvrx [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvrx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stvrx128(const PPCDecodeData& d, StringBuffer* str) {
+  // stvrx128 [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvrx128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_stvrxl(const PPCDecodeData& d, StringBuffer* str) {
+  // stvrxl [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvrxl");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stvrxl128(const PPCDecodeData& d, StringBuffer* str) {
+  // stvrxl128 [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvrxl128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_stvx(const PPCDecodeData& d, StringBuffer* str) {
+  // stvx [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stvx128(const PPCDecodeData& d, StringBuffer* str) {
+  // stvx128 [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvx128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_stvxl(const PPCDecodeData& d, StringBuffer* str) {
+  // stvxl [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvxl");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.X.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stvxl128(const PPCDecodeData& d, StringBuffer* str) {
+  // stvxl128 [VS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stvxl128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_1.VS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.VX128_1.RB());
+}
+void PrintDisasm_stw(const PPCDecodeData& d, StringBuffer* str) {
+  // stw [RS], [d]([RA0])
+  size_t str_start = str->length();
+  str->Append("stw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RS());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA0());
+  str->Append(")");
+}
+void PrintDisasm_stwbrx(const PPCDecodeData& d, StringBuffer* str) {
+  // stwbrx [RS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stwbrx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stwcx(const PPCDecodeData& d, StringBuffer* str) {
+  // stwcx. [RS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stwcx.");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stwu(const PPCDecodeData& d, StringBuffer* str) {
+  // stwu [RS], [d]([RA])
+  size_t str_start = str->length();
+  str->Append("stwu");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RS());
+  str->Append(", ");
+  str->AppendFormat(d.D.d() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.d()));
+  str->Append("(");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(")");
+}
+void PrintDisasm_stwux(const PPCDecodeData& d, StringBuffer* str) {
+  // stwux [RS], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("stwux");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_stwx(const PPCDecodeData& d, StringBuffer* str) {
+  // stwx [RS], [RA0], [RB]
+  size_t str_start = str->length();
+  str->Append("stwx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA0());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_subfcx(const PPCDecodeData& d, StringBuffer* str) {
+  // subfc[OE][Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("subfc");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_subfex(const PPCDecodeData& d, StringBuffer* str) {
+  // subfe[OE][Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("subfe");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_subficx(const PPCDecodeData& d, StringBuffer* str) {
+  // subfic [RD], [RA], [SIMM]
+  size_t str_start = str->length();
+  str->Append("subfic");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(", ");
+  str->AppendFormat(d.D.SIMM() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.SIMM()));
+}
+void PrintDisasm_subfmex(const PPCDecodeData& d, StringBuffer* str) {
+  // subfme[OE][Rc] [RD], [RA]
+  size_t str_start = str->length();
+  str->Append("subfme");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+}
+void PrintDisasm_subfx(const PPCDecodeData& d, StringBuffer* str) {
+  // subf[OE][Rc] [RD], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("subf");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RB());
+}
+void PrintDisasm_subfzex(const PPCDecodeData& d, StringBuffer* str) {
+  // subfze[OE][Rc] [RD], [RA]
+  size_t str_start = str->length();
+  str->Append("subfze");
+  if (d.XO.OE()) str->Append('o');
+  if (d.XO.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.XO.RD());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.XO.RA());
+}
+void PrintDisasm_sync(const PPCDecodeData& d, StringBuffer* str) {
+  // sync
+  size_t str_start = str->length();
+  str->Append("sync");
+  PadStringBuffer(str, str_start, kNamePad);
+}
+void PrintDisasm_td(const PPCDecodeData& d, StringBuffer* str) {
+  // td [TO], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("td");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("%d", d.X.TO());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_tdi(const PPCDecodeData& d, StringBuffer* str) {
+  // tdi [TO], [RA], [SIMM]
+  size_t str_start = str->length();
+  str->Append("tdi");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("%d", d.D.TO());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(", ");
+  str->AppendFormat(d.D.SIMM() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.SIMM()));
+}
+void PrintDisasm_tw(const PPCDecodeData& d, StringBuffer* str) {
+  // tw [TO], [RA], [RB]
+  size_t str_start = str->length();
+  str->Append("tw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("%d", d.X.TO());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+void PrintDisasm_twi(const PPCDecodeData& d, StringBuffer* str) {
+  // tw [TO], [RA], [SIMM]
+  size_t str_start = str->length();
+  str->Append("tw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("%d", d.D.TO());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(", ");
+  str->AppendFormat(d.D.SIMM() < 0 ? "-0x%X" : "0x%X", std::abs(d.D.SIMM()));
+}
+void PrintDisasm_vaddcuw(const PPCDecodeData& d, StringBuffer* str) {
+  // vaddcuw [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vaddcuw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vaddfp(const PPCDecodeData& d, StringBuffer* str) {
+  // vaddfp [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vaddfp");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vaddfp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vaddfp128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vaddfp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vaddsbs(const PPCDecodeData& d, StringBuffer* str) {
+  // vaddsbs [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vaddsbs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vaddshs(const PPCDecodeData& d, StringBuffer* str) {
+  // vaddshs [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vaddshs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vaddsws(const PPCDecodeData& d, StringBuffer* str) {
+  // vaddsws [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vaddsws");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vaddubm(const PPCDecodeData& d, StringBuffer* str) {
+  // vaddubm [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vaddubm");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vaddubs(const PPCDecodeData& d, StringBuffer* str) {
+  // vaddubs [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vaddubs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vadduhm(const PPCDecodeData& d, StringBuffer* str) {
+  // vadduhm [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vadduhm");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vadduhs(const PPCDecodeData& d, StringBuffer* str) {
+  // vadduhs [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vadduhs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vadduwm(const PPCDecodeData& d, StringBuffer* str) {
+  // vadduwm [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vadduwm");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vadduws(const PPCDecodeData& d, StringBuffer* str) {
+  // vadduws [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vadduws");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vand(const PPCDecodeData& d, StringBuffer* str) {
+  // vand [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vand");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vand128(const PPCDecodeData& d, StringBuffer* str) {
+  // vand128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vand128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vandc(const PPCDecodeData& d, StringBuffer* str) {
+  // vandc [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vandc");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vandc128(const PPCDecodeData& d, StringBuffer* str) {
+  // vandc128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vandc128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vavgsb(const PPCDecodeData& d, StringBuffer* str) {
+  // vavgsb [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vavgsb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vavgsh(const PPCDecodeData& d, StringBuffer* str) {
+  // vavgsh [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vavgsh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vavgsw(const PPCDecodeData& d, StringBuffer* str) {
+  // vavgsw [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vavgsw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vavgub(const PPCDecodeData& d, StringBuffer* str) {
+  // vavgub [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vavgub");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vavguh(const PPCDecodeData& d, StringBuffer* str) {
+  // vavguh [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vavguh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vavguw(const PPCDecodeData& d, StringBuffer* str) {
+  // vavguw [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vavguw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vcfpsxws128(const PPCDecodeData& d, StringBuffer* str) {
+  // vcfpsxws128 [VD], [VB], [UIMM]
+  size_t str_start = str->length();
+  str->Append("vcfpsxws128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_3.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_3.VB());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.VX128_3.UIMM());
+}
+void PrintDisasm_vcfpuxws128(const PPCDecodeData& d, StringBuffer* str) {
+  // vcfpuxws128 [VD], [VB], [UIMM]
+  size_t str_start = str->length();
+  str->Append("vcfpuxws128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_3.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_3.VB());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.VX128_3.UIMM());
+}
+void PrintDisasm_vcfsx(const PPCDecodeData& d, StringBuffer* str) {
+  // vcfsx [VD], [VB], [UIMM]
+  size_t str_start = str->length();
+  str->Append("vcfsx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.VX.UIMM());
+}
+void PrintDisasm_vcfux(const PPCDecodeData& d, StringBuffer* str) {
+  // vcfux [VD], [VB], [UIMM]
+  size_t str_start = str->length();
+  str->Append("vcfux");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.VX.UIMM());
+}
+void PrintDisasm_vcmpbfp(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpbfp[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpbfp");
+  if (d.VC.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VC.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VB());
+}
+void PrintDisasm_vcmpbfp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpbfp128[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpbfp128");
+  if (d.VX128_R.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_R.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_R.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_R.VB());
+}
+void PrintDisasm_vcmpeqfp(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpeqfp[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpeqfp");
+  if (d.VC.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VC.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VB());
+}
+void PrintDisasm_vcmpeqfp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpeqfp128[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpeqfp128");
+  if (d.VX128_R.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_R.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_R.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_R.VB());
+}
+void PrintDisasm_vcmpequb(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpequb[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpequb");
+  if (d.VC.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VC.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VB());
+}
+void PrintDisasm_vcmpequh(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpequh[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpequh");
+  if (d.VC.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VC.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VB());
+}
+void PrintDisasm_vcmpequw(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpequw[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpequw");
+  if (d.VC.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VC.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VB());
+}
+void PrintDisasm_vcmpequw128(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpequw128[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpequw128");
+  if (d.VX128_R.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_R.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_R.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_R.VB());
+}
+void PrintDisasm_vcmpgefp(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpgefp[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpgefp");
+  if (d.VC.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VC.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VB());
+}
+void PrintDisasm_vcmpgefp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpgefp128[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpgefp128");
+  if (d.VX128_R.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_R.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_R.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_R.VB());
+}
+void PrintDisasm_vcmpgtfp(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpgtfp[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpgtfp");
+  if (d.VC.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VC.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VB());
+}
+void PrintDisasm_vcmpgtfp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpgtfp128[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpgtfp128");
+  if (d.VX128_R.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_R.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_R.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_R.VB());
+}
+void PrintDisasm_vcmpgtsb(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpgtsb[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpgtsb");
+  if (d.VC.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VC.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VB());
+}
+void PrintDisasm_vcmpgtsh(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpgtsh[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpgtsh");
+  if (d.VC.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VC.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VB());
+}
+void PrintDisasm_vcmpgtsw(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpgtsw[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpgtsw");
+  if (d.VC.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VC.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VB());
+}
+void PrintDisasm_vcmpgtub(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpgtub[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpgtub");
+  if (d.VC.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VC.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VB());
+}
+void PrintDisasm_vcmpgtuh(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpgtuh[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpgtuh");
+  if (d.VC.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VC.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VB());
+}
+void PrintDisasm_vcmpgtuw(const PPCDecodeData& d, StringBuffer* str) {
+  // vcmpgtuw[Rc] [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vcmpgtuw");
+  if (d.VC.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VC.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VC.VB());
+}
+void PrintDisasm_vcsxwfp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vcsxwfp128 [VD], [VB], [UIMM]
+  size_t str_start = str->length();
+  str->Append("vcsxwfp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_3.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_3.VB());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.VX128_3.UIMM());
+}
+void PrintDisasm_vctsxs(const PPCDecodeData& d, StringBuffer* str) {
+  // vctsxs [VD], [VB], [UIMM]
+  size_t str_start = str->length();
+  str->Append("vctsxs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.VX.UIMM());
+}
+void PrintDisasm_vctuxs(const PPCDecodeData& d, StringBuffer* str) {
+  // vctuxs [VD], [VB], [UIMM]
+  size_t str_start = str->length();
+  str->Append("vctuxs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.VX.UIMM());
+}
+void PrintDisasm_vcuxwfp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vcuxwfp128 [VD], [VB], [UIMM]
+  size_t str_start = str->length();
+  str->Append("vcuxwfp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_3.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_3.VB());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.VX128_3.UIMM());
+}
+void PrintDisasm_vexptefp(const PPCDecodeData& d, StringBuffer* str) {
+  // vexptefp [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vexptefp");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vexptefp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vexptefp128 [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vexptefp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_3.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_3.VB());
+}
+void PrintDisasm_vlogefp(const PPCDecodeData& d, StringBuffer* str) {
+  // vlogefp [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vlogefp");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vlogefp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vlogefp128 [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vlogefp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_3.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_3.VB());
+}
+void PrintDisasm_vmaddcfp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vmaddcfp128 [VD], [VA], [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vmaddcfp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vmaddfp(const PPCDecodeData& d, StringBuffer* str) {
+  // vmaddfp [VD], [VA], [VC], [VB]
+  size_t str_start = str->length();
+  str->Append("vmaddfp");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VA.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VC());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VB());
+}
+void PrintDisasm_vmaddfp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vmaddfp128 [VD], [VA], [VB], [VD]
+  size_t str_start = str->length();
+  str->Append("vmaddfp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VD());
+}
+void PrintDisasm_vmaxfp(const PPCDecodeData& d, StringBuffer* str) {
+  // vmaxfp [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmaxfp");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmaxfp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vmaxfp128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmaxfp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vmaxsb(const PPCDecodeData& d, StringBuffer* str) {
+  // vmaxsb [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmaxsb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmaxsh(const PPCDecodeData& d, StringBuffer* str) {
+  // vmaxsh [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmaxsh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmaxsw(const PPCDecodeData& d, StringBuffer* str) {
+  // vmaxsw [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmaxsw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmaxub(const PPCDecodeData& d, StringBuffer* str) {
+  // vmaxub [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmaxub");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmaxuh(const PPCDecodeData& d, StringBuffer* str) {
+  // vmaxuh [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmaxuh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmaxuw(const PPCDecodeData& d, StringBuffer* str) {
+  // vmaxuw [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmaxuw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmhaddshs(const PPCDecodeData& d, StringBuffer* str) {
+  // vmhaddshs [VD], [VA], [VB], [VC]
+  size_t str_start = str->length();
+  str->Append("vmhaddshs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VA.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VB());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VC());
+}
+void PrintDisasm_vmhraddshs(const PPCDecodeData& d, StringBuffer* str) {
+  // vmhraddshs [VD], [VA], [VB], [VC]
+  size_t str_start = str->length();
+  str->Append("vmhraddshs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VA.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VB());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VC());
+}
+void PrintDisasm_vminfp(const PPCDecodeData& d, StringBuffer* str) {
+  // vminfp [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vminfp");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vminfp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vminfp128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vminfp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vminsb(const PPCDecodeData& d, StringBuffer* str) {
+  // vminsb [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vminsb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vminsh(const PPCDecodeData& d, StringBuffer* str) {
+  // vminsh [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vminsh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vminsw(const PPCDecodeData& d, StringBuffer* str) {
+  // vminsw [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vminsw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vminub(const PPCDecodeData& d, StringBuffer* str) {
+  // vminub [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vminub");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vminuh(const PPCDecodeData& d, StringBuffer* str) {
+  // vminuh [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vminuh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vminuw(const PPCDecodeData& d, StringBuffer* str) {
+  // vminuw [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vminuw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmladduhm(const PPCDecodeData& d, StringBuffer* str) {
+  // vmladduhm [VD], [VA], [VB], [VC]
+  size_t str_start = str->length();
+  str->Append("vmladduhm");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VA.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VB());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VC());
+}
+void PrintDisasm_vmrghb(const PPCDecodeData& d, StringBuffer* str) {
+  // vmrghb [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmrghb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmrghh(const PPCDecodeData& d, StringBuffer* str) {
+  // vmrghh [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmrghh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmrghw(const PPCDecodeData& d, StringBuffer* str) {
+  // vmrghw [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmrghw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmrghw128(const PPCDecodeData& d, StringBuffer* str) {
+  // vmrghw128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmrghw128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vmrglb(const PPCDecodeData& d, StringBuffer* str) {
+  // vmrglb [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmrglb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmrglh(const PPCDecodeData& d, StringBuffer* str) {
+  // vmrglh [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmrglh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmrglw(const PPCDecodeData& d, StringBuffer* str) {
+  // vmrglw [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmrglw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmrglw128(const PPCDecodeData& d, StringBuffer* str) {
+  // vmrglw128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmrglw128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vmsum3fp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vmsum3fp128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmsum3fp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vmsum4fp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vmsum4fp128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmsum4fp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vmsummbm(const PPCDecodeData& d, StringBuffer* str) {
+  // vmsummbm [VD], [VA], [VB], [VC]
+  size_t str_start = str->length();
+  str->Append("vmsummbm");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VA.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VB());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VC());
+}
+void PrintDisasm_vmsumshm(const PPCDecodeData& d, StringBuffer* str) {
+  // vmsumshm [VD], [VA], [VB], [VC]
+  size_t str_start = str->length();
+  str->Append("vmsumshm");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VA.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VB());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VC());
+}
+void PrintDisasm_vmsumshs(const PPCDecodeData& d, StringBuffer* str) {
+  // vmsumshs [VD], [VA], [VB], [VC]
+  size_t str_start = str->length();
+  str->Append("vmsumshs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VA.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VB());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VC());
+}
+void PrintDisasm_vmsumubm(const PPCDecodeData& d, StringBuffer* str) {
+  // vmsumubm [VD], [VA], [VB], [VC]
+  size_t str_start = str->length();
+  str->Append("vmsumubm");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VA.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VB());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VC());
+}
+void PrintDisasm_vmsumuhm(const PPCDecodeData& d, StringBuffer* str) {
+  // vmsumuhm [VD], [VA], [VB], [VC]
+  size_t str_start = str->length();
+  str->Append("vmsumuhm");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VA.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VB());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VC());
+}
+void PrintDisasm_vmsumuhs(const PPCDecodeData& d, StringBuffer* str) {
+  // vmsumuhs [VD], [VA], [VB], [VC]
+  size_t str_start = str->length();
+  str->Append("vmsumuhs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VA.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VB());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VC());
+}
+void PrintDisasm_vmulesb(const PPCDecodeData& d, StringBuffer* str) {
+  // vmulesb [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmulesb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmulesh(const PPCDecodeData& d, StringBuffer* str) {
+  // vmulesh [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmulesh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmuleub(const PPCDecodeData& d, StringBuffer* str) {
+  // vmuleub [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmuleub");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmuleuh(const PPCDecodeData& d, StringBuffer* str) {
+  // vmuleuh [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmuleuh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmulfp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vmulfp128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmulfp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vmulosb(const PPCDecodeData& d, StringBuffer* str) {
+  // vmulosb [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmulosb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmulosh(const PPCDecodeData& d, StringBuffer* str) {
+  // vmulosh [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmulosh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmuloub(const PPCDecodeData& d, StringBuffer* str) {
+  // vmuloub [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmuloub");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vmulouh(const PPCDecodeData& d, StringBuffer* str) {
+  // vmulouh [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vmulouh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vnmsubfp(const PPCDecodeData& d, StringBuffer* str) {
+  // vnmsubfp [VD], [VA], [VC], [VB]
+  size_t str_start = str->length();
+  str->Append("vnmsubfp");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VA.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VC());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VB());
+}
+void PrintDisasm_vnmsubfp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vnmsubfp128 [VD], [VA], [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vnmsubfp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vnor(const PPCDecodeData& d, StringBuffer* str) {
+  // vnor [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vnor");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vnor128(const PPCDecodeData& d, StringBuffer* str) {
+  // vnor128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vnor128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vor(const PPCDecodeData& d, StringBuffer* str) {
+  // vor [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vor");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vor128(const PPCDecodeData& d, StringBuffer* str) {
+  // vor128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vor128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vperm(const PPCDecodeData& d, StringBuffer* str) {
+  // vperm [VD], [VA], [VB], [VC]
+  size_t str_start = str->length();
+  str->Append("vperm");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VA.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VB());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VC());
+}
+void PrintDisasm_vperm128(const PPCDecodeData& d, StringBuffer* str) {
+  // vperm128 [VD], [VA], [VB], [VC]
+  size_t str_start = str->length();
+  str->Append("vperm128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_2.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_2.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_2.VB());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_2.VC());
+}
+void PrintDisasm_vpermwi128(const PPCDecodeData& d, StringBuffer* str) {
+  // vpermwi128 [VD], [VB], [UIMM]
+  size_t str_start = str->length();
+  str->Append("vpermwi128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_P.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_P.VB());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.VX128_P.UIMM());
+}
+void PrintDisasm_vpkpx(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkpx [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkpx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vpkshss(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkshss [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkshss");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vpkshss128(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkshss128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkshss128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vpkshus(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkshus [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkshus");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vpkshus128(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkshus128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkshus128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vpkswss(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkswss [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkswss");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vpkswss128(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkswss128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkswss128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vpkswus(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkswus [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkswus");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vpkswus128(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkswus128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkswus128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vpkuhum(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkuhum [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkuhum");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vpkuhum128(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkuhum128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkuhum128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vpkuhus(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkuhus [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkuhus");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vpkuhus128(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkuhus128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkuhus128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vpkuwum(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkuwum [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkuwum");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vpkuwum128(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkuwum128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkuwum128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vpkuwus(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkuwus [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkuwus");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vpkuwus128(const PPCDecodeData& d, StringBuffer* str) {
+  // vpkuwus128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vpkuwus128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vrefp(const PPCDecodeData& d, StringBuffer* str) {
+  // vrefp [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vrefp");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vrefp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vrefp128 [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vrefp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_3.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_3.VB());
+}
+void PrintDisasm_vrfim(const PPCDecodeData& d, StringBuffer* str) {
+  // vrfim [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vrfim");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vrfim128(const PPCDecodeData& d, StringBuffer* str) {
+  // vrfim128 [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vrfim128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_3.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_3.VB());
+}
+void PrintDisasm_vrfin(const PPCDecodeData& d, StringBuffer* str) {
+  // vrfin [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vrfin");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vrfin128(const PPCDecodeData& d, StringBuffer* str) {
+  // vrfin128 [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vrfin128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_3.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_3.VB());
+}
+void PrintDisasm_vrfip(const PPCDecodeData& d, StringBuffer* str) {
+  // vrfip [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vrfip");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vrfip128(const PPCDecodeData& d, StringBuffer* str) {
+  // vrfip128 [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vrfip128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_3.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_3.VB());
+}
+void PrintDisasm_vrfiz(const PPCDecodeData& d, StringBuffer* str) {
+  // vrfiz [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vrfiz");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vrfiz128(const PPCDecodeData& d, StringBuffer* str) {
+  // vrfiz128 [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vrfiz128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_3.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_3.VB());
+}
+void PrintDisasm_vrlb(const PPCDecodeData& d, StringBuffer* str) {
+  // vrlb [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vrlb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vrlh(const PPCDecodeData& d, StringBuffer* str) {
+  // vrlh [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vrlh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vrlimi128(const PPCDecodeData& d, StringBuffer* str) {
+  // vrlimi128 [VD], [VB], [IMM], [z]
+  size_t str_start = str->length();
+  str->Append("vrlimi128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_4.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_4.VB());
+  str->Append(", ");
+  str->AppendFormat("%d", d.VX128_4.IMM());
+  str->Append(", ");
+  str->AppendFormat("%d", d.VX128_4.z());
+}
+void PrintDisasm_vrlw(const PPCDecodeData& d, StringBuffer* str) {
+  // vrlw [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vrlw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vrlw128(const PPCDecodeData& d, StringBuffer* str) {
+  // vrlw128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vrlw128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vrsqrtefp(const PPCDecodeData& d, StringBuffer* str) {
+  // vrsqrtefp [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vrsqrtefp");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vrsqrtefp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vrsqrtefp128 [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vrsqrtefp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_3.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_3.VB());
+}
+void PrintDisasm_vsel(const PPCDecodeData& d, StringBuffer* str) {
+  // vsel [VD], [VA], [VB], [VC]
+  size_t str_start = str->length();
+  str->Append("vsel");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VA.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VB());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VC());
+}
+void PrintDisasm_vsel128(const PPCDecodeData& d, StringBuffer* str) {
+  // vsel128 [VD], [VA], [VB], [VD]
+  size_t str_start = str->length();
+  str->Append("vsel128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VD());
+}
+void PrintDisasm_vsl(const PPCDecodeData& d, StringBuffer* str) {
+  // vsl [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsl");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vslb(const PPCDecodeData& d, StringBuffer* str) {
+  // vslb [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vslb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsldoi(const PPCDecodeData& d, StringBuffer* str) {
+  // vsldoi [VD], [VA], [VB], [SHB]
+  size_t str_start = str->length();
+  str->Append("vsldoi");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VA.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VA.VB());
+  str->Append(", ");
+  str->AppendFormat("(UNHANDLED SHB)");
+}
+void PrintDisasm_vsldoi128(const PPCDecodeData& d, StringBuffer* str) {
+  // vsldoi128 [VD], [VA], [VB], [SHB]
+  size_t str_start = str->length();
+  str->Append("vsldoi128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_5.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_5.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_5.VB());
+  str->Append(", ");
+  str->AppendFormat("(UNHANDLED SHB)");
+}
+void PrintDisasm_vslh(const PPCDecodeData& d, StringBuffer* str) {
+  // vslh [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vslh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vslo(const PPCDecodeData& d, StringBuffer* str) {
+  // vslo [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vslo");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vslo128(const PPCDecodeData& d, StringBuffer* str) {
+  // vslo128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vslo128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vslw(const PPCDecodeData& d, StringBuffer* str) {
+  // vslw [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vslw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vslw128(const PPCDecodeData& d, StringBuffer* str) {
+  // vslw128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vslw128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vspltb(const PPCDecodeData& d, StringBuffer* str) {
+  // vspltb [VD], [VB], [UIMM]
+  size_t str_start = str->length();
+  str->Append("vspltb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.VX.UIMM());
+}
+void PrintDisasm_vsplth(const PPCDecodeData& d, StringBuffer* str) {
+  // vsplth [VD], [VB], [UIMM]
+  size_t str_start = str->length();
+  str->Append("vsplth");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.VX.UIMM());
+}
+void PrintDisasm_vspltisb(const PPCDecodeData& d, StringBuffer* str) {
+  // vspltisb [VD], [SIMM]
+  size_t str_start = str->length();
+  str->Append("vspltisb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat(d.VX.SIMM() < 0 ? "-0x%X" : "0x%X", std::abs(d.VX.SIMM()));
+}
+void PrintDisasm_vspltish(const PPCDecodeData& d, StringBuffer* str) {
+  // vspltish [VD], [SIMM]
+  size_t str_start = str->length();
+  str->Append("vspltish");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat(d.VX.SIMM() < 0 ? "-0x%X" : "0x%X", std::abs(d.VX.SIMM()));
+}
+void PrintDisasm_vspltisw(const PPCDecodeData& d, StringBuffer* str) {
+  // vspltisw [VD], [SIMM]
+  size_t str_start = str->length();
+  str->Append("vspltisw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat(d.VX.SIMM() < 0 ? "-0x%X" : "0x%X", std::abs(d.VX.SIMM()));
+}
+void PrintDisasm_vspltisw128(const PPCDecodeData& d, StringBuffer* str) {
+  // vspltisw128 [VD], [SIMM]
+  size_t str_start = str->length();
+  str->Append("vspltisw128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_3.VD());
+  str->Append(", ");
+  str->AppendFormat(d.VX128_3.SIMM() < 0 ? "-0x%X" : "0x%X", std::abs(d.VX128_3.SIMM()));
+}
+void PrintDisasm_vspltw(const PPCDecodeData& d, StringBuffer* str) {
+  // vspltw [VD], [VB], [UIMM]
+  size_t str_start = str->length();
+  str->Append("vspltw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.VX.UIMM());
+}
+void PrintDisasm_vspltw128(const PPCDecodeData& d, StringBuffer* str) {
+  // vspltw128 [VD], [VB], [UIMM]
+  size_t str_start = str->length();
+  str->Append("vspltw128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128_3.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128_3.VB());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.VX128_3.UIMM());
+}
+void PrintDisasm_vsr(const PPCDecodeData& d, StringBuffer* str) {
+  // vsr [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsr");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsrab(const PPCDecodeData& d, StringBuffer* str) {
+  // vsrab [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsrab");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsrah(const PPCDecodeData& d, StringBuffer* str) {
+  // vsrah [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsrah");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsraw(const PPCDecodeData& d, StringBuffer* str) {
+  // vsraw [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsraw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsraw128(const PPCDecodeData& d, StringBuffer* str) {
+  // vsraw128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsraw128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vsrb(const PPCDecodeData& d, StringBuffer* str) {
+  // vsrb [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsrb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsrh(const PPCDecodeData& d, StringBuffer* str) {
+  // vsrh [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsrh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsro(const PPCDecodeData& d, StringBuffer* str) {
+  // vsro [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsro");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsro128(const PPCDecodeData& d, StringBuffer* str) {
+  // vsro128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsro128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vsrw(const PPCDecodeData& d, StringBuffer* str) {
+  // vsrw [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsrw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsrw128(const PPCDecodeData& d, StringBuffer* str) {
+  // vsrw128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsrw128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vsubcuw(const PPCDecodeData& d, StringBuffer* str) {
+  // vsubcuw [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsubcuw");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsubfp(const PPCDecodeData& d, StringBuffer* str) {
+  // vsubfp [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsubfp");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsubfp128(const PPCDecodeData& d, StringBuffer* str) {
+  // vsubfp128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsubfp128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vsubsbs(const PPCDecodeData& d, StringBuffer* str) {
+  // vsubsbs [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsubsbs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsubshs(const PPCDecodeData& d, StringBuffer* str) {
+  // vsubshs [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsubshs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsubsws(const PPCDecodeData& d, StringBuffer* str) {
+  // vsubsws [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsubsws");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsububm(const PPCDecodeData& d, StringBuffer* str) {
+  // vsububm [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsububm");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsububs(const PPCDecodeData& d, StringBuffer* str) {
+  // vsububs [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsububs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsubuhm(const PPCDecodeData& d, StringBuffer* str) {
+  // vsubuhm [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsubuhm");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsubuhs(const PPCDecodeData& d, StringBuffer* str) {
+  // vsubuhs [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsubuhs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsubuwm(const PPCDecodeData& d, StringBuffer* str) {
+  // vsubuwm [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsubuwm");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsubuws(const PPCDecodeData& d, StringBuffer* str) {
+  // vsubuws [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsubuws");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsum2sws(const PPCDecodeData& d, StringBuffer* str) {
+  // vsum2sws [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsum2sws");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsum4sbs(const PPCDecodeData& d, StringBuffer* str) {
+  // vsum4sbs [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsum4sbs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsum4shs(const PPCDecodeData& d, StringBuffer* str) {
+  // vsum4shs [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsum4shs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsum4ubs(const PPCDecodeData& d, StringBuffer* str) {
+  // vsum4ubs [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsum4ubs");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vsumsws(const PPCDecodeData& d, StringBuffer* str) {
+  // vsumsws [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vsumsws");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vupkhpx(const PPCDecodeData& d, StringBuffer* str) {
+  // vupkhpx [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vupkhpx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vupkhsb(const PPCDecodeData& d, StringBuffer* str) {
+  // vupkhsb [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vupkhsb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vupkhsb128(const PPCDecodeData& d, StringBuffer* str) {
+  // vupkhsb128 [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vupkhsb128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vupkhsh(const PPCDecodeData& d, StringBuffer* str) {
+  // vupkhsh [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vupkhsh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vupklpx(const PPCDecodeData& d, StringBuffer* str) {
+  // vupklpx [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vupklpx");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vupklsb(const PPCDecodeData& d, StringBuffer* str) {
+  // vupklsb [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vupklsb");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vupklsb128(const PPCDecodeData& d, StringBuffer* str) {
+  // vupklsb128 [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vupklsb128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_vupklsh(const PPCDecodeData& d, StringBuffer* str) {
+  // vupklsh [VD], [VB]
+  size_t str_start = str->length();
+  str->Append("vupklsh");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vxor(const PPCDecodeData& d, StringBuffer* str) {
+  // vxor [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vxor");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX.VB());
+}
+void PrintDisasm_vxor128(const PPCDecodeData& d, StringBuffer* str) {
+  // vxor128 [VD], [VA], [VB]
+  size_t str_start = str->length();
+  str->Append("vxor128");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("vr%d", d.VX128.VD());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VA());
+  str->Append(", ");
+  str->AppendFormat("vr%d", d.VX128.VB());
+}
+void PrintDisasm_xori(const PPCDecodeData& d, StringBuffer* str) {
+  // xori [RA], [RS], [UIMM]
+  size_t str_start = str->length();
+  str->Append("xori");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RS());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.D.UIMM());
+}
+void PrintDisasm_xoris(const PPCDecodeData& d, StringBuffer* str) {
+  // xoris [RA], [RS], [UIMM]
+  size_t str_start = str->length();
+  str->Append("xoris");
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.D.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.D.RS());
+  str->Append(", ");
+  str->AppendFormat("0x%X", d.D.UIMM());
+}
+void PrintDisasm_xorx(const PPCDecodeData& d, StringBuffer* str) {
+  // xor[Rc] [RA], [RS], [RB]
+  size_t str_start = str->length();
+  str->Append("xor");
+  if (d.X.Rc()) str->Append('.');
+  PadStringBuffer(str, str_start, kNamePad);
+  str->AppendFormat("r%d", d.X.RA());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RS());
+  str->Append(", ");
+  str->AppendFormat("r%d", d.X.RB());
+}
+#define INIT_LIST(...) {__VA_ARGS__}
+#define INSTRUCTION(opcode, mnem, form, group, type, desc, reads, writes, fn) \
+    {PPCOpcodeGroup::group, PPCOpcodeFormat::form, opcode, mnem, desc, INIT_LIST reads, INIT_LIST writes, fn}
+PPCOpcodeDisasmInfo ppc_opcode_disasm_table[] = {
+  INSTRUCTION(0x7c000014, "addcx"       , kXO     , kI, kGeneral, "Add Carrying"                                                               , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kOEcond,PPCOpcodeField::kCRcond), PrintDisasm_addcx),
+  INSTRUCTION(0x7c000114, "addex"       , kXO     , kI, kGeneral, "Add Extended"                                                               , (PPCOpcodeField::kRA,PPCOpcodeField::kRB,PPCOpcodeField::kCR), (PPCOpcodeField::kRD,PPCOpcodeField::kOEcond,PPCOpcodeField::kCRcond), PrintDisasm_addex),
+  INSTRUCTION(0x38000000, "addi"        , kD      , kI, kGeneral, "Add Immediate"                                                              , (PPCOpcodeField::kRA0,PPCOpcodeField::kSIMM), (PPCOpcodeField::kRD), PrintDisasm_addi),
+  INSTRUCTION(0x30000000, "addic"       , kD      , kI, kGeneral, "Add Immediate Carrying"                                                     , (PPCOpcodeField::kRA,PPCOpcodeField::kSIMM), (PPCOpcodeField::kRD,PPCOpcodeField::kCA), PrintDisasm_addic),
+  INSTRUCTION(0x34000000, "addicx"      , kD      , kI, kGeneral, "Add Immediate Carrying and Record"                                          , (PPCOpcodeField::kRA,PPCOpcodeField::kSIMM), (PPCOpcodeField::kRD,PPCOpcodeField::kCA,PPCOpcodeField::kCR), PrintDisasm_addicx),
+  INSTRUCTION(0x3c000000, "addis"       , kD      , kI, kGeneral, "Add Immediate Shifted"                                                      , (PPCOpcodeField::kRA0,PPCOpcodeField::kSIMM), (PPCOpcodeField::kRD), PrintDisasm_addis),
+  INSTRUCTION(0x7c0001d4, "addmex"      , kXO     , kI, kGeneral, "Add to Minus One Extended"                                                  , (PPCOpcodeField::kRA,PPCOpcodeField::kCA), (PPCOpcodeField::kRD,PPCOpcodeField::kCA,PPCOpcodeField::kOEcond,PPCOpcodeField::kCRcond), PrintDisasm_addmex),
+  INSTRUCTION(0x7c000214, "addx"        , kXO     , kI, kGeneral, "Add"                                                                        , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kOEcond,PPCOpcodeField::kCRcond), PrintDisasm_addx),
+  INSTRUCTION(0x7c000194, "addzex"      , kXO     , kI, kGeneral, "Add to Zero Extended"                                                       , (PPCOpcodeField::kRA,PPCOpcodeField::kCA), (PPCOpcodeField::kRD,PPCOpcodeField::kCA,PPCOpcodeField::kOEcond,PPCOpcodeField::kCRcond), PrintDisasm_addzex),
+  INSTRUCTION(0x7c000078, "andcx"       , kX      , kI, kGeneral, "AND with Complement"                                                        , (PPCOpcodeField::kRS,PPCOpcodeField::kRB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_andcx),
+  INSTRUCTION(0x74000000, "andisx"      , kD      , kI, kGeneral, "AND Immediate Shifted"                                                      , (PPCOpcodeField::kRS,PPCOpcodeField::kUIMM), (PPCOpcodeField::kRA,PPCOpcodeField::kCR), PrintDisasm_andisx),
+  INSTRUCTION(0x70000000, "andix"       , kD      , kI, kGeneral, "AND Immediate"                                                              , (PPCOpcodeField::kRS,PPCOpcodeField::kUIMM), (PPCOpcodeField::kRA,PPCOpcodeField::kCR), PrintDisasm_andix),
+  INSTRUCTION(0x7c000038, "andx"        , kX      , kI, kGeneral, "AND"                                                                        , (PPCOpcodeField::kRS,PPCOpcodeField::kRB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_andx),
+  INSTRUCTION(0x4c000420, "bcctrx"      , kXL     , kI, kSync   , "Branch Conditional to Count Register"                                       , (PPCOpcodeField::kLK,PPCOpcodeField::kBO,PPCOpcodeField::kBI,PPCOpcodeField::kCR,PPCOpcodeField::kCTR), (PPCOpcodeField::kLRcond), PrintDisasm_bcctrx),
+  INSTRUCTION(0x4c000020, "bclrx"       , kXL     , kI, kSync   , "Branch Conditional to Link Register"                                        , (PPCOpcodeField::kLK,PPCOpcodeField::kBO,PPCOpcodeField::kBI,PPCOpcodeField::kCRcond,PPCOpcodeField::kCTRcond), (PPCOpcodeField::kCTRcond,PPCOpcodeField::kLRcond), PrintDisasm_bclrx),
+  INSTRUCTION(0x40000000, "bcx"         , kB      , kI, kSync   , "Branch Conditional"                                                         , (PPCOpcodeField::kLK,PPCOpcodeField::kAA,PPCOpcodeField::kBO,PPCOpcodeField::kBI,PPCOpcodeField::kADDR,PPCOpcodeField::kCRcond,PPCOpcodeField::kCTRcond), (PPCOpcodeField::kCTRcond,PPCOpcodeField::kLRcond), PrintDisasm_bcx),
+  INSTRUCTION(0x48000000, "bx"          , kI      , kI, kSync   , "Branch"                                                                     , (PPCOpcodeField::kLK,PPCOpcodeField::kAA,PPCOpcodeField::kADDR), (PPCOpcodeField::kLRcond), PrintDisasm_bx),
+  INSTRUCTION(0x7c000000, "cmp"         , kX      , kI, kGeneral, "Compare"                                                                    , (PPCOpcodeField::kL,PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kCRFD), PrintDisasm_cmp),
+  INSTRUCTION(0x2c000000, "cmpi"        , kD      , kI, kGeneral, "Compare Immediate"                                                          , (PPCOpcodeField::kL,PPCOpcodeField::kRA,PPCOpcodeField::kSIMM), (PPCOpcodeField::kRD,PPCOpcodeField::kCRFD), PrintDisasm_cmpi),
+  INSTRUCTION(0x7c000040, "cmpl"        , kX      , kI, kGeneral, "Compare Logical"                                                            , (PPCOpcodeField::kL,PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kCRFD), PrintDisasm_cmpl),
+  INSTRUCTION(0x28000000, "cmpli"       , kD      , kI, kGeneral, "Compare Logical Immediate"                                                  , (PPCOpcodeField::kL,PPCOpcodeField::kRA,PPCOpcodeField::kUIMM), (PPCOpcodeField::kCRFD), PrintDisasm_cmpli),
+  INSTRUCTION(0x7c000074, "cntlzdx"     , kX      , kI, kGeneral, "Count Leading Zeros Doubleword"                                             , (PPCOpcodeField::kRS), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_cntlzdx),
+  INSTRUCTION(0x7c000034, "cntlzwx"     , kX      , kI, kGeneral, "Count Leading Zeros Word"                                                   , (PPCOpcodeField::kRS), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_cntlzwx),
+  INSTRUCTION(0x4c000202, "crand"       , kXL     , kI, kGeneral, "Condition Register AND"                                                     , (PPCOpcodeField::kCRBA,PPCOpcodeField::kCRBB), (PPCOpcodeField::kCRBD), PrintDisasm_crand),
+  INSTRUCTION(0x4c000102, "crandc"      , kXL     , kI, kGeneral, "Condition Register AND with Complement"                                     , (PPCOpcodeField::kCRBA,PPCOpcodeField::kCRBB), (PPCOpcodeField::kCRBD), PrintDisasm_crandc),
+  INSTRUCTION(0x4c000242, "creqv"       , kXL     , kI, kGeneral, "Condition Register Equivalent"                                              , (PPCOpcodeField::kCRBA,PPCOpcodeField::kCRBB), (PPCOpcodeField::kCRBD), PrintDisasm_creqv),
+  INSTRUCTION(0x4c0001c2, "crnand"      , kXL     , kI, kGeneral, "Condition Register NAND"                                                    , (PPCOpcodeField::kCRBA,PPCOpcodeField::kCRBB), (PPCOpcodeField::kCRBD), PrintDisasm_crnand),
+  INSTRUCTION(0x4c000042, "crnor"       , kXL     , kI, kGeneral, "Condition Register NOR"                                                     , (PPCOpcodeField::kCRBA,PPCOpcodeField::kCRBB), (PPCOpcodeField::kCRBD), PrintDisasm_crnor),
+  INSTRUCTION(0x4c000382, "cror"        , kXL     , kI, kGeneral, "Condition Register OR"                                                      , (PPCOpcodeField::kCRBA,PPCOpcodeField::kCRBB), (PPCOpcodeField::kCRBD), PrintDisasm_cror),
+  INSTRUCTION(0x4c000342, "crorc"       , kXL     , kI, kGeneral, "Condition Register OR with Complement"                                      , (PPCOpcodeField::kCRBA,PPCOpcodeField::kCRBB), (PPCOpcodeField::kCRBD), PrintDisasm_crorc),
+  INSTRUCTION(0x4c000182, "crxor"       , kXL     , kI, kGeneral, "Condition Register XOR"                                                     , (PPCOpcodeField::kCRBA,PPCOpcodeField::kCRBB), (PPCOpcodeField::kCRBD), PrintDisasm_crxor),
+  INSTRUCTION(0x7c0005ec, "dcba"        , kX      , kI, kGeneral, "Data Cache Block Allocate"                                                  , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcba),
+  INSTRUCTION(0x7c0000ac, "dcbf"        , kX      , kI, kGeneral, "Data Cache Block Flush"                                                     , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbf),
+  INSTRUCTION(0x7c0003ac, "dcbi"        , kX      , kI, kGeneral, "Data Cache Block Invalidate"                                                , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbi),
+  INSTRUCTION(0x7c00006c, "dcbst"       , kX      , kI, kGeneral, "Data Cache Block Store"                                                     , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbst),
+  INSTRUCTION(0x7c00022c, "dcbt"        , kX      , kI, kGeneral, "Data Cache Block Touch"                                                     , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbt),
+  INSTRUCTION(0x7c0001ec, "dcbtst"      , kX      , kI, kGeneral, "Data Cache Block Touch for Store"                                           , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbtst),
+  INSTRUCTION(0x7c0007ec, "dcbz"        , kDCBZ   , kI, kGeneral, "Data Cache Block Clear to Zero"                                             , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbz),
+  INSTRUCTION(0x7c2007ec, "dcbz128"     , kDCBZ   , kI, kGeneral, "Data Cache Block Clear to Zero 128"                                         , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_dcbz128),
+  INSTRUCTION(0x7c000392, "divdux"      , kXO     , kI, kGeneral, "Divide Doubleword Unsigned"                                                 , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kOEcond,PPCOpcodeField::kCRcond), PrintDisasm_divdux),
+  INSTRUCTION(0x7c0003d2, "divdx"       , kXO     , kI, kGeneral, "Divide Doubleword"                                                          , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kOEcond,PPCOpcodeField::kCRcond), PrintDisasm_divdx),
+  INSTRUCTION(0x7c000396, "divwux"      , kXO     , kI, kGeneral, "Divide Word Unsigned"                                                       , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kOEcond,PPCOpcodeField::kCRcond), PrintDisasm_divwux),
+  INSTRUCTION(0x7c0003d6, "divwx"       , kXO     , kI, kGeneral, "Divide Word"                                                                , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kOEcond,PPCOpcodeField::kCRcond), PrintDisasm_divwx),
+  INSTRUCTION(0x7c0006ac, "eieio"       , kX      , kI, kGeneral, "Enforce In-Order Execution of I/O"                                          , (), (), PrintDisasm_eieio),
+  INSTRUCTION(0x7c000238, "eqvx"        , kX      , kI, kGeneral, "Equivalent"                                                                 , (PPCOpcodeField::kRS,PPCOpcodeField::kRB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_eqvx),
+  INSTRUCTION(0x7c000774, "extsbx"      , kX      , kI, kGeneral, "Extend Sign Byte"                                                           , (PPCOpcodeField::kRS), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_extsbx),
+  INSTRUCTION(0x7c000734, "extshx"      , kX      , kI, kGeneral, "Extend Sign Half Word"                                                      , (PPCOpcodeField::kRS), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_extshx),
+  INSTRUCTION(0x7c0007b4, "extswx"      , kX      , kI, kGeneral, "Extend Sign Word"                                                           , (PPCOpcodeField::kRS), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_extswx),
+  INSTRUCTION(0xfc000210, "fabsx"       , kX      , kF, kGeneral, "Floating Absolute Value"                                                    , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond), PrintDisasm_fabsx),
+  INSTRUCTION(0xec00002a, "faddsx"      , kA      , kF, kGeneral, "Floating Add Single"                                                        , (PPCOpcodeField::kFA,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_faddsx),
+  INSTRUCTION(0xfc00002a, "faddx"       , kA      , kF, kGeneral, "Floating Add"                                                               , (PPCOpcodeField::kFA,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_faddx),
+  INSTRUCTION(0xfc00069c, "fcfidx"      , kX      , kF, kGeneral, "Floating Convert From Integer Doubleword"                                   , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fcfidx),
+  INSTRUCTION(0xfc000040, "fcmpo"       , kX      , kF, kGeneral, "Floating Compare Ordered"                                                   , (PPCOpcodeField::kFA,PPCOpcodeField::kFB), (PPCOpcodeField::kCRFD,PPCOpcodeField::kFPSCR), PrintDisasm_fcmpo),
+  INSTRUCTION(0xfc000000, "fcmpu"       , kX      , kF, kGeneral, "Floating Compare Unordered"                                                 , (PPCOpcodeField::kFA,PPCOpcodeField::kFB), (PPCOpcodeField::kCRFD,PPCOpcodeField::kFPSCR), PrintDisasm_fcmpu),
+  INSTRUCTION(0xfc00065c, "fctidx"      , kX      , kF, kGeneral, "Floating Convert to Integer Doubleword"                                     , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fctidx),
+  INSTRUCTION(0xfc00065e, "fctidzx"     , kX      , kF, kGeneral, "Floating Convert to Integer Doubleword with Round Toward Zero"              , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fctidzx),
+  INSTRUCTION(0xfc00001c, "fctiwx"      , kX      , kF, kGeneral, "Floating Convert to Integer Word"                                           , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fctiwx),
+  INSTRUCTION(0xfc00001e, "fctiwzx"     , kX      , kF, kGeneral, "Floating Convert to Integer Word with Round Toward Zero"                    , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fctiwzx),
+  INSTRUCTION(0xec000024, "fdivsx"      , kA      , kF, kGeneral, "Floating Divide Single"                                                     , (PPCOpcodeField::kFA,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fdivsx),
+  INSTRUCTION(0xfc000024, "fdivx"       , kA      , kF, kGeneral, "Floating Divide"                                                            , (PPCOpcodeField::kFA,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fdivx),
+  INSTRUCTION(0xec00003a, "fmaddsx"     , kA      , kF, kGeneral, "Floating Multiply-Add Single"                                               , (PPCOpcodeField::kFA,PPCOpcodeField::kFC,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fmaddsx),
+  INSTRUCTION(0xfc00003a, "fmaddx"      , kA      , kF, kGeneral, "Floating Multiply-Add"                                                      , (PPCOpcodeField::kFA,PPCOpcodeField::kFC,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fmaddx),
+  INSTRUCTION(0xfc000090, "fmrx"        , kX      , kF, kGeneral, "Floating Move Register"                                                     , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond), PrintDisasm_fmrx),
+  INSTRUCTION(0xec000038, "fmsubsx"     , kA      , kF, kGeneral, "Floating Multiply-Subtract Single"                                          , (PPCOpcodeField::kFA,PPCOpcodeField::kFC,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fmsubsx),
+  INSTRUCTION(0xfc000038, "fmsubx"      , kA      , kF, kGeneral, "Floating Multiply-Subtract"                                                 , (PPCOpcodeField::kFA,PPCOpcodeField::kFC,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fmsubx),
+  INSTRUCTION(0xec000032, "fmulsx"      , kA      , kF, kGeneral, "Floating Multiply Single"                                                   , (PPCOpcodeField::kFA,PPCOpcodeField::kFC), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fmulsx),
+  INSTRUCTION(0xfc000032, "fmulx"       , kA      , kF, kGeneral, "Floating Multiply"                                                          , (PPCOpcodeField::kFA,PPCOpcodeField::kFC), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fmulx),
+  INSTRUCTION(0xfc000110, "fnabsx"      , kX      , kF, kGeneral, "Floating Negative Absolute Value"                                           , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond), PrintDisasm_fnabsx),
+  INSTRUCTION(0xfc000050, "fnegx"       , kX      , kF, kGeneral, "Floating Negate"                                                            , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond), PrintDisasm_fnegx),
+  INSTRUCTION(0xec00003e, "fnmaddsx"    , kA      , kF, kGeneral, "Floating Negative Multiply-Add Single"                                      , (PPCOpcodeField::kFA,PPCOpcodeField::kFC,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fnmaddsx),
+  INSTRUCTION(0xfc00003e, "fnmaddx"     , kA      , kF, kGeneral, "Floating Negative Multiply-Add"                                             , (PPCOpcodeField::kFA,PPCOpcodeField::kFC,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fnmaddx),
+  INSTRUCTION(0xec00003c, "fnmsubsx"    , kA      , kF, kGeneral, "Floating Negative Multiply-Subtract Single"                                 , (PPCOpcodeField::kFA,PPCOpcodeField::kFC,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fnmsubsx),
+  INSTRUCTION(0xfc00003c, "fnmsubx"     , kA      , kF, kGeneral, "Floating Negative Multiply-Subtract"                                        , (PPCOpcodeField::kFA,PPCOpcodeField::kFC,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fnmsubx),
+  INSTRUCTION(0xec000030, "fresx"       , kA      , kF, kGeneral, "Floating Reciprocal Estimate Single"                                        , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fresx),
+  INSTRUCTION(0xfc000018, "frspx"       , kX      , kF, kGeneral, "Floating Round to Single"                                                   , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_frspx),
+  INSTRUCTION(0xfc000034, "frsqrtex"    , kA      , kF, kGeneral, "Floating Reciprocal Square Root Estimate"                                   , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_frsqrtex),
+  INSTRUCTION(0xfc00002e, "fselx"       , kA      , kF, kGeneral, "Floating Select"                                                            , (PPCOpcodeField::kFA,PPCOpcodeField::kFC,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond), PrintDisasm_fselx),
+  INSTRUCTION(0xec00002c, "fsqrtsx"     , kA      , kF, kGeneral, "Floating Square Root Single"                                                , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fsqrtsx),
+  INSTRUCTION(0xfc00002c, "fsqrtx"      , kA      , kF, kGeneral, "Floating Square Root"                                                       , (PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fsqrtx),
+  INSTRUCTION(0xec000028, "fsubsx"      , kA      , kF, kGeneral, "Floating Subtract Single"                                                   , (PPCOpcodeField::kFA,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fsubsx),
+  INSTRUCTION(0xfc000028, "fsubx"       , kA      , kF, kGeneral, "Floating Subtract"                                                          , (PPCOpcodeField::kFA,PPCOpcodeField::kFB), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond,PPCOpcodeField::kFPSCR), PrintDisasm_fsubx),
+  INSTRUCTION(0x7c0007ac, "icbi"        , kX      , kI, kGeneral, "Instruction Cache Block Invalidate"                                         , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_icbi),
+  INSTRUCTION(0x4c00012c, "isync"       , kXL     , kI, kGeneral, "Instruction Synchronize"                                                    , (), (), PrintDisasm_isync),
+  INSTRUCTION(0x88000000, "lbz"         , kD      , kI, kGeneral, "Load Byte and Zero"                                                         , (PPCOpcodeField::kRA0,PPCOpcodeField::kd), (PPCOpcodeField::kRD), PrintDisasm_lbz),
+  INSTRUCTION(0x8c000000, "lbzu"        , kD      , kI, kGeneral, "Load Byte and Zero with Update"                                             , (PPCOpcodeField::kRA,PPCOpcodeField::kd), (PPCOpcodeField::kRD,PPCOpcodeField::kRA), PrintDisasm_lbzu),
+  INSTRUCTION(0x7c0000ee, "lbzux"       , kX      , kI, kGeneral, "Load Byte and Zero with Update Indexed"                                     , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kRA), PrintDisasm_lbzux),
+  INSTRUCTION(0x7c0000ae, "lbzx"        , kX      , kI, kGeneral, "Load Byte and Zero Indexed"                                                 , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kRD), PrintDisasm_lbzx),
+  INSTRUCTION(0xe8000000, "ld"          , kDS     , kI, kGeneral, "Load Doubleword"                                                            , (PPCOpcodeField::kRA0,PPCOpcodeField::kds), (PPCOpcodeField::kRD), PrintDisasm_ld),
+  INSTRUCTION(0x7c0000a8, "ldarx"       , kX      , kI, kGeneral, "Load Doubleword and Reserve Indexed"                                        , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kRD), PrintDisasm_ldarx),
+  INSTRUCTION(0x7c000428, "ldbrx"       , kX      , kI, kGeneral, "Load Doubleword Byte-Reverse Indexed"                                       , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kRD), PrintDisasm_ldbrx),
+  INSTRUCTION(0xe8000001, "ldu"         , kDS     , kI, kGeneral, "Load Doubleword with Update"                                                , (PPCOpcodeField::kRA,PPCOpcodeField::kds), (PPCOpcodeField::kRD,PPCOpcodeField::kRA), PrintDisasm_ldu),
+  INSTRUCTION(0x7c00006a, "ldux"        , kX      , kI, kGeneral, "Load Doubleword with Update Indexed"                                        , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kRA), PrintDisasm_ldux),
+  INSTRUCTION(0x7c00002a, "ldx"         , kX      , kI, kGeneral, "Load Doubleword Indexed"                                                    , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kRD), PrintDisasm_ldx),
+  INSTRUCTION(0xc8000000, "lfd"         , kD      , kF, kGeneral, "Load Floating-Point Double"                                                 , (PPCOpcodeField::kRA0,PPCOpcodeField::kd), (PPCOpcodeField::kFD), PrintDisasm_lfd),
+  INSTRUCTION(0xcc000000, "lfdu"        , kD      , kF, kGeneral, "Load Floating-Point Double with Update"                                     , (PPCOpcodeField::kRA,PPCOpcodeField::kd), (PPCOpcodeField::kFD,PPCOpcodeField::kRA), PrintDisasm_lfdu),
+  INSTRUCTION(0x7c0004ee, "lfdux"       , kX      , kF, kGeneral, "Load Floating-Point Double with Update Indexed"                             , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kFD,PPCOpcodeField::kRA), PrintDisasm_lfdux),
+  INSTRUCTION(0x7c0004ae, "lfdx"        , kX      , kF, kGeneral, "Load Floating-Point Double Indexed"                                         , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kFD), PrintDisasm_lfdx),
+  INSTRUCTION(0xc0000000, "lfs"         , kD      , kF, kGeneral, "Load Floating-Point Single"                                                 , (PPCOpcodeField::kRA0,PPCOpcodeField::kd), (PPCOpcodeField::kFD), PrintDisasm_lfs),
+  INSTRUCTION(0xc4000000, "lfsu"        , kD      , kF, kGeneral, "Load Floating-Point Single with Update"                                     , (PPCOpcodeField::kRA,PPCOpcodeField::kd), (PPCOpcodeField::kFD,PPCOpcodeField::kRA), PrintDisasm_lfsu),
+  INSTRUCTION(0x7c00046e, "lfsux"       , kX      , kF, kGeneral, "Load Floating-Point Single with Update Indexed"                             , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kFD,PPCOpcodeField::kRA), PrintDisasm_lfsux),
+  INSTRUCTION(0x7c00042e, "lfsx"        , kX      , kF, kGeneral, "Load Floating-Point Single Indexed"                                         , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kFD), PrintDisasm_lfsx),
+  INSTRUCTION(0xa8000000, "lha"         , kD      , kI, kGeneral, "Load Half Word Algebraic"                                                   , (PPCOpcodeField::kRA0,PPCOpcodeField::kd), (PPCOpcodeField::kRD), PrintDisasm_lha),
+  INSTRUCTION(0xac000000, "lhau"        , kD      , kI, kGeneral, "Load Half Word Algebraic with Update"                                       , (PPCOpcodeField::kRA,PPCOpcodeField::kd), (PPCOpcodeField::kRD,PPCOpcodeField::kRA), PrintDisasm_lhau),
+  INSTRUCTION(0x7c0002ee, "lhaux"       , kX      , kI, kGeneral, "Load Half Word Algebraic with Update Indexed"                               , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kRA), PrintDisasm_lhaux),
+  INSTRUCTION(0x7c0002ae, "lhax"        , kX      , kI, kGeneral, "Load Half Word Algebraic Indexed"                                           , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kRD), PrintDisasm_lhax),
+  INSTRUCTION(0x7c00062c, "lhbrx"       , kX      , kI, kGeneral, "Load Half Word Byte-Reverse Indexed"                                        , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kRD), PrintDisasm_lhbrx),
+  INSTRUCTION(0xa0000000, "lhz"         , kD      , kI, kGeneral, "Load Half Word and Zero"                                                    , (PPCOpcodeField::kRA0,PPCOpcodeField::kd), (PPCOpcodeField::kRD), PrintDisasm_lhz),
+  INSTRUCTION(0xa4000000, "lhzu"        , kD      , kI, kGeneral, "Load Half Word and Zero with Update"                                        , (PPCOpcodeField::kRA,PPCOpcodeField::kd), (PPCOpcodeField::kRD,PPCOpcodeField::kRA), PrintDisasm_lhzu),
+  INSTRUCTION(0x7c00026e, "lhzux"       , kX      , kI, kGeneral, "Load Half Word and Zero with Update Indexed"                                , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kRA), PrintDisasm_lhzux),
+  INSTRUCTION(0x7c00022e, "lhzx"        , kX      , kI, kGeneral, "Load Half Word and Zero Indexed"                                            , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kRD), PrintDisasm_lhzx),
+  INSTRUCTION(0xb8000000, "lmw"         , kD      , kI, kGeneral, "Load Multiple Word"                                                         , (), (), nullptr),
+  INSTRUCTION(0x7c0004aa, "lswi"        , kX      , kI, kGeneral, "Load String Word Immediate"                                                 , (), (), nullptr),
+  INSTRUCTION(0x7c00042a, "lswx"        , kX      , kI, kGeneral, "Load String Word Indexed"                                                   , (), (), nullptr),
+  INSTRUCTION(0x7c00000e, "lvebx"       , kX      , kV, kGeneral, "Load Vector Element Byte Indexed"                                           , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvebx),
+  INSTRUCTION(0x7c00004e, "lvehx"       , kX      , kV, kGeneral, "Load Vector Element Half Word Indexed"                                      , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvehx),
+  INSTRUCTION(0x7c00008e, "lvewx"       , kX      , kV, kGeneral, "Load Vector Element Word Indexed"                                           , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvewx),
+  INSTRUCTION(0x10000083, "lvewx128"    , kVX128_1, kV, kGeneral, "Load Vector Element Word Indexed 128"                                       , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvewx128),
+  INSTRUCTION(0x7c00040e, "lvlx"        , kX      , kV, kGeneral, "Load Vector Left Indexed"                                                   , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvlx),
+  INSTRUCTION(0x10000403, "lvlx128"     , kVX128_1, kV, kGeneral, "Load Vector Left Indexed 128"                                               , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvlx128),
+  INSTRUCTION(0x7c00060e, "lvlxl"       , kX      , kV, kGeneral, "Load Vector Left Indexed LRU"                                               , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvlxl),
+  INSTRUCTION(0x10000603, "lvlxl128"    , kVX128_1, kV, kGeneral, "Load Vector Left Indexed LRU 128"                                           , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvlxl128),
+  INSTRUCTION(0x7c00044e, "lvrx"        , kX      , kV, kGeneral, "Load Vector Right Indexed"                                                  , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvrx),
+  INSTRUCTION(0x10000443, "lvrx128"     , kVX128_1, kV, kGeneral, "Load Vector Right Indexed 128"                                              , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvrx128),
+  INSTRUCTION(0x7c00064e, "lvrxl"       , kX      , kV, kGeneral, "Load Vector Right Indexed LRU"                                              , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvrxl),
+  INSTRUCTION(0x10000643, "lvrxl128"    , kVX128_1, kV, kGeneral, "Load Vector Right Indexed LRU 128"                                          , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvrxl128),
+  INSTRUCTION(0x7c00000c, "lvsl"        , kX      , kV, kGeneral, "Load Vector for Shift Left Indexed"                                         , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvsl),
+  INSTRUCTION(0x10000003, "lvsl128"     , kVX128_1, kV, kGeneral, "Load Vector for Shift Left Indexed 128"                                     , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvsl128),
+  INSTRUCTION(0x7c00004c, "lvsr"        , kX      , kV, kGeneral, "Load Vector for Shift Right Indexed"                                        , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvsr),
+  INSTRUCTION(0x10000043, "lvsr128"     , kVX128_1, kV, kGeneral, "Load Vector for Shift Right Indexed 128"                                    , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvsr128),
+  INSTRUCTION(0x7c0000ce, "lvx"         , kX      , kV, kGeneral, "Load Vector Indexed"                                                        , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvx),
+  INSTRUCTION(0x100000c3, "lvx128"      , kVX128_1, kV, kGeneral, "Load Vector Indexed 128"                                                    , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvx128),
+  INSTRUCTION(0x7c0002ce, "lvxl"        , kX      , kV, kGeneral, "Load Vector Indexed LRU"                                                    , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvxl),
+  INSTRUCTION(0x100002c3, "lvxl128"     , kVX128_1, kV, kGeneral, "Load Vector Indexed LRU 128"                                                , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kVD), PrintDisasm_lvxl128),
+  INSTRUCTION(0xe8000002, "lwa"         , kDS     , kI, kGeneral, "Load Word Algebraic"                                                        , (PPCOpcodeField::kRA0,PPCOpcodeField::kds), (PPCOpcodeField::kRD), PrintDisasm_lwa),
+  INSTRUCTION(0x7c000028, "lwarx"       , kX      , kI, kGeneral, "Load Word and Reserve Indexed"                                              , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kRD), PrintDisasm_lwarx),
+  INSTRUCTION(0x7c0002ea, "lwaux"       , kX      , kI, kGeneral, "Load Word Algebraic with Update Indexed"                                    , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kRA), PrintDisasm_lwaux),
+  INSTRUCTION(0x7c0002aa, "lwax"        , kX      , kI, kGeneral, "Load Word Algebraic Indexed"                                                , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kRD), PrintDisasm_lwax),
+  INSTRUCTION(0x7c00042c, "lwbrx"       , kX      , kI, kGeneral, "Load Word Byte-Reverse Indexed"                                             , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kRD), PrintDisasm_lwbrx),
+  INSTRUCTION(0x80000000, "lwz"         , kD      , kI, kGeneral, "Load Word and Zero"                                                         , (PPCOpcodeField::kRA0,PPCOpcodeField::kd), (PPCOpcodeField::kRD), PrintDisasm_lwz),
+  INSTRUCTION(0x84000000, "lwzu"        , kD      , kI, kGeneral, "Load Word and Zero with Update"                                             , (PPCOpcodeField::kRA,PPCOpcodeField::kd), (PPCOpcodeField::kRD,PPCOpcodeField::kRA), PrintDisasm_lwzu),
+  INSTRUCTION(0x7c00006e, "lwzux"       , kX      , kI, kGeneral, "Load Word and Zero with Update Indexed"                                     , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kRA), PrintDisasm_lwzux),
+  INSTRUCTION(0x7c00002e, "lwzx"        , kX      , kI, kGeneral, "Load Word and Zero Indexed"                                                 , (PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kRD), PrintDisasm_lwzx),
+  INSTRUCTION(0x4c000000, "mcrf"        , kXL     , kI, kGeneral, "Move Condition Register Field"                                              , (PPCOpcodeField::kCRFS), (PPCOpcodeField::kCRFD), PrintDisasm_mcrf),
+  INSTRUCTION(0xfc000080, "mcrfs"       , kX      , kF, kGeneral, "Move to Condition Register from FPSCR"                                      , (PPCOpcodeField::kCRFS,PPCOpcodeField::kFPSCR), (PPCOpcodeField::kCRFD,PPCOpcodeField::kFPSCR), PrintDisasm_mcrfs),
+  INSTRUCTION(0x7c000400, "mcrxr"       , kX      , kI, kGeneral, "Move to Condition Register from XER"                                        , (PPCOpcodeField::kCR), (PPCOpcodeField::kCRFD), PrintDisasm_mcrxr),
+  INSTRUCTION(0x7c000026, "mfcr"        , kX      , kI, kGeneral, "Move from Condition Register"                                               , (PPCOpcodeField::kCR), (PPCOpcodeField::kRD), PrintDisasm_mfcr),
+  INSTRUCTION(0xfc00048e, "mffsx"       , kX      , kF, kGeneral, "Move from FPSCR"                                                            , (PPCOpcodeField::kFPSCR), (PPCOpcodeField::kFD,PPCOpcodeField::kCRcond), PrintDisasm_mffsx),
+  INSTRUCTION(0x7c0000a6, "mfmsr"       , kX      , kI, kGeneral, "Move from Machine State Register"                                           , (PPCOpcodeField::kMSR), (PPCOpcodeField::kRD), PrintDisasm_mfmsr),
+  INSTRUCTION(0x7c0002a6, "mfspr"       , kXFX    , kI, kGeneral, "Move from Special-Purpose Register"                                         , (PPCOpcodeField::kSPR), (PPCOpcodeField::kRD), PrintDisasm_mfspr),
+  INSTRUCTION(0x7c0002e6, "mftb"        , kXFX    , kI, kGeneral, "Move from Time Base"                                                        , (PPCOpcodeField::kTBR), (PPCOpcodeField::kRD), PrintDisasm_mftb),
+  INSTRUCTION(0x10000604, "mfvscr"      , kVX     , kV, kGeneral, "Move from VSCR"                                                             , (PPCOpcodeField::kVSCR), (PPCOpcodeField::kVD), nullptr),
+  INSTRUCTION(0x7c000120, "mtcrf"       , kXFX    , kI, kGeneral, "Move to Condition Register Fields"                                          , (PPCOpcodeField::kRS), (PPCOpcodeField::kCRM), PrintDisasm_mtcrf),
+  INSTRUCTION(0xfc00008c, "mtfsb0x"     , kX      , kF, kGeneral, "Move to FPSCR Bit 0"                                                        , (), (PPCOpcodeField::kFPSCRD,PPCOpcodeField::kCRcond), PrintDisasm_mtfsb0x),
+  INSTRUCTION(0xfc00004c, "mtfsb1x"     , kX      , kF, kGeneral, "Move to FPSCR Bit 1"                                                        , (), (PPCOpcodeField::kFPSCRD,PPCOpcodeField::kCRcond), PrintDisasm_mtfsb1x),
+  INSTRUCTION(0xfc00010c, "mtfsfix"     , kX      , kF, kGeneral, "Move to FPSCR Field Immediate"                                              , (PPCOpcodeField::kIMM), (PPCOpcodeField::kCRFD,PPCOpcodeField::kCRcond), PrintDisasm_mtfsfix),
+  INSTRUCTION(0xfc00058e, "mtfsfx"      , kXFL    , kF, kGeneral, "Move to FPSCR Fields"                                                       , (PPCOpcodeField::kFM,PPCOpcodeField::kFB), (PPCOpcodeField::kFPSCR,PPCOpcodeField::kCRcond), PrintDisasm_mtfsfx),
+  INSTRUCTION(0x7c000124, "mtmsr"       , kX      , kI, kGeneral, "Move to Machine State Register"                                             , (PPCOpcodeField::kRS), (PPCOpcodeField::kMSR), PrintDisasm_mtmsr),
+  INSTRUCTION(0x7c000164, "mtmsrd"      , kX      , kI, kGeneral, "Move to Machine State Register Doubleword"                                  , (PPCOpcodeField::kRS), (PPCOpcodeField::kMSR), PrintDisasm_mtmsrd),
+  INSTRUCTION(0x7c0003a6, "mtspr"       , kXFX    , kI, kGeneral, "Move to Special-Purpose Register"                                           , (PPCOpcodeField::kRS), (PPCOpcodeField::kSPR), PrintDisasm_mtspr),
+  INSTRUCTION(0x10000644, "mtvscr"      , kVX     , kV, kGeneral, "Move to VSCR"                                                               , (PPCOpcodeField::kVB), (PPCOpcodeField::kVSCR), nullptr),
+  INSTRUCTION(0x7c000012, "mulhdux"     , kXO     , kI, kGeneral, "Multiply High Doubleword Unsigned"                                          , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kCRcond), PrintDisasm_mulhdux),
+  INSTRUCTION(0x7c000092, "mulhdx"      , kXO     , kI, kGeneral, "Multiply High Doubleword"                                                   , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kCRcond), PrintDisasm_mulhdx),
+  INSTRUCTION(0x7c000016, "mulhwux"     , kXO     , kI, kGeneral, "Multiply High Word Unsigned"                                                , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kCRcond), PrintDisasm_mulhwux),
+  INSTRUCTION(0x7c000096, "mulhwx"      , kXO     , kI, kGeneral, "Multiply High Word"                                                         , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kCRcond), PrintDisasm_mulhwx),
+  INSTRUCTION(0x7c0001d2, "mulldx"      , kXO     , kI, kGeneral, "Multiply Low Doubleword"                                                    , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kCRcond,PPCOpcodeField::kOEcond), PrintDisasm_mulldx),
+  INSTRUCTION(0x1c000000, "mulli"       , kD      , kI, kGeneral, "Multiply Low Immediate"                                                     , (PPCOpcodeField::kRA,PPCOpcodeField::kSIMM), (PPCOpcodeField::kRD), PrintDisasm_mulli),
+  INSTRUCTION(0x7c0001d6, "mullwx"      , kXO     , kI, kGeneral, "Multiply Low Word"                                                          , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kCRcond,PPCOpcodeField::kOEcond), PrintDisasm_mullwx),
+  INSTRUCTION(0x7c0003b8, "nandx"       , kX      , kI, kGeneral, "NAND"                                                                       , (PPCOpcodeField::kRS,PPCOpcodeField::kRB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_nandx),
+  INSTRUCTION(0x7c0000d0, "negx"        , kXO     , kI, kGeneral, "Negate"                                                                     , (PPCOpcodeField::kRA), (PPCOpcodeField::kRD,PPCOpcodeField::kCRcond,PPCOpcodeField::kOEcond), PrintDisasm_negx),
+  INSTRUCTION(0x7c0000f8, "norx"        , kX      , kI, kGeneral, "NOR"                                                                        , (PPCOpcodeField::kRS,PPCOpcodeField::kRB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_norx),
+  INSTRUCTION(0x7c000338, "orcx"        , kX      , kI, kGeneral, "OR with Complement"                                                         , (PPCOpcodeField::kRS,PPCOpcodeField::kRB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_orcx),
+  INSTRUCTION(0x60000000, "ori"         , kD      , kI, kGeneral, "OR Immediate"                                                               , (PPCOpcodeField::kRS,PPCOpcodeField::kUIMM), (PPCOpcodeField::kRA), PrintDisasm_ori),
+  INSTRUCTION(0x64000000, "oris"        , kD      , kI, kGeneral, "OR Immediate Shifted"                                                       , (PPCOpcodeField::kRS,PPCOpcodeField::kUIMM), (PPCOpcodeField::kRA), PrintDisasm_oris),
+  INSTRUCTION(0x7c000378, "orx"         , kX      , kI, kGeneral, "OR"                                                                         , (PPCOpcodeField::kRS,PPCOpcodeField::kRB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_orx),
+  INSTRUCTION(0x78000010, "rldclx"      , kMDS    , kI, kGeneral, "Rotate Left Doubleword then Clear Left"                                     , (PPCOpcodeField::kRS,PPCOpcodeField::kRB,PPCOpcodeField::kMB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_rldclx),
+  INSTRUCTION(0x78000012, "rldcrx"      , kMDS    , kI, kGeneral, "Rotate Left Doubleword then Clear Right"                                    , (PPCOpcodeField::kRS,PPCOpcodeField::kRB,PPCOpcodeField::kME), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_rldcrx),
+  INSTRUCTION(0x78000000, "rldiclx"     , kMD     , kI, kGeneral, "Rotate Left Doubleword Immediate then Clear Left"                           , (PPCOpcodeField::kRS,PPCOpcodeField::kSH,PPCOpcodeField::kMB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_rldiclx),
+  INSTRUCTION(0x78000004, "rldicrx"     , kMD     , kI, kGeneral, "Rotate Left Doubleword Immediate then Clear Right"                          , (PPCOpcodeField::kRS,PPCOpcodeField::kSH,PPCOpcodeField::kME), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_rldicrx),
+  INSTRUCTION(0x78000008, "rldicx"      , kMD     , kI, kGeneral, "Rotate Left Doubleword Immediate then Clear"                                , (PPCOpcodeField::kRS,PPCOpcodeField::kSH,PPCOpcodeField::kMB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_rldicx),
+  INSTRUCTION(0x7800000c, "rldimix"     , kMD     , kI, kGeneral, "Rotate Left Doubleword Immediate then Mask Insert"                          , (PPCOpcodeField::kRS,PPCOpcodeField::kSH,PPCOpcodeField::kMB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_rldimix),
+  INSTRUCTION(0x50000000, "rlwimix"     , kM      , kI, kGeneral, "Rotate Left Word Immediate then Mask Insert"                                , (PPCOpcodeField::kRS,PPCOpcodeField::kSH,PPCOpcodeField::kMB,PPCOpcodeField::kME), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_rlwimix),
+  INSTRUCTION(0x54000000, "rlwinmx"     , kM      , kI, kGeneral, "Rotate Left Word Immediate then AND with Mask"                              , (PPCOpcodeField::kRS,PPCOpcodeField::kSH,PPCOpcodeField::kMB,PPCOpcodeField::kME), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_rlwinmx),
+  INSTRUCTION(0x5c000000, "rlwnmx"      , kM      , kI, kGeneral, "Rotate Left Word then AND with Mask"                                        , (PPCOpcodeField::kRS,PPCOpcodeField::kRB,PPCOpcodeField::kMB,PPCOpcodeField::kME), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_rlwnmx),
+  INSTRUCTION(0x44000002, "sc"          , kSC     , kI, kSync   , "System Call"                                                                , (), (), PrintDisasm_sc),
+  INSTRUCTION(0x7c000036, "sldx"        , kX      , kI, kGeneral, "Shift Left Doubleword"                                                      , (PPCOpcodeField::kRS,PPCOpcodeField::kRB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_sldx),
+  INSTRUCTION(0x7c000030, "slwx"        , kX      , kI, kGeneral, "Shift Left Word"                                                            , (PPCOpcodeField::kRS,PPCOpcodeField::kRB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_slwx),
+  INSTRUCTION(0x7c000674, "sradix"      , kXS     , kI, kGeneral, "Shift Right Algebraic Doubleword Immediate"                                 , (PPCOpcodeField::kRS,PPCOpcodeField::kSH), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond,PPCOpcodeField::kCA), PrintDisasm_sradix),
+  INSTRUCTION(0x7c000634, "sradx"       , kX      , kI, kGeneral, "Shift Right Algebraic Doubleword"                                           , (PPCOpcodeField::kRS,PPCOpcodeField::kRB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond,PPCOpcodeField::kCA), PrintDisasm_sradx),
+  INSTRUCTION(0x7c000670, "srawix"      , kX      , kI, kGeneral, "Shift Right Algebraic Word Immediate"                                       , (PPCOpcodeField::kRS,PPCOpcodeField::kSH), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond,PPCOpcodeField::kCA), PrintDisasm_srawix),
+  INSTRUCTION(0x7c000630, "srawx"       , kX      , kI, kGeneral, "Shift Right Algebraic Word"                                                 , (PPCOpcodeField::kRS,PPCOpcodeField::kRB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond,PPCOpcodeField::kCA), PrintDisasm_srawx),
+  INSTRUCTION(0x7c000436, "srdx"        , kX      , kI, kGeneral, "Shift Right Doubleword"                                                     , (PPCOpcodeField::kRS,PPCOpcodeField::kRB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_srdx),
+  INSTRUCTION(0x7c000430, "srwx"        , kX      , kI, kGeneral, "Shift Right Word"                                                           , (PPCOpcodeField::kRS,PPCOpcodeField::kRB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_srwx),
+  INSTRUCTION(0x98000000, "stb"         , kD      , kI, kGeneral, "Store Byte"                                                                 , (PPCOpcodeField::kRS,PPCOpcodeField::kRA0,PPCOpcodeField::kd), (), PrintDisasm_stb),
+  INSTRUCTION(0x9c000000, "stbu"        , kD      , kI, kGeneral, "Store Byte with Update"                                                     , (PPCOpcodeField::kRS,PPCOpcodeField::kRA,PPCOpcodeField::kd), (PPCOpcodeField::kRA), PrintDisasm_stbu),
+  INSTRUCTION(0x7c0001ee, "stbux"       , kX      , kI, kGeneral, "Store Byte with Update Indexed"                                             , (PPCOpcodeField::kRS,PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRA), PrintDisasm_stbux),
+  INSTRUCTION(0x7c0001ae, "stbx"        , kX      , kI, kGeneral, "Store Byte Indexed"                                                         , (PPCOpcodeField::kRS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stbx),
+  INSTRUCTION(0xf8000000, "std"         , kDS     , kI, kGeneral, "Store Doubleword"                                                           , (PPCOpcodeField::kRS,PPCOpcodeField::kRA,PPCOpcodeField::kds), (), PrintDisasm_std),
+  INSTRUCTION(0x7c000528, "stdbrx"      , kX      , kI, kGeneral, "Store Doubleword Byte-Reverse Indexed"                                      , (PPCOpcodeField::kRS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stdbrx),
+  INSTRUCTION(0x7c0001ad, "stdcx"       , kX      , kI, kGeneral, "Store Doubleword Conditional Indexed"                                       , (PPCOpcodeField::kRS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kCR), PrintDisasm_stdcx),
+  INSTRUCTION(0xf8000001, "stdu"        , kDS     , kI, kGeneral, "Store Doubleword with Update"                                               , (PPCOpcodeField::kRS,PPCOpcodeField::kRA,PPCOpcodeField::kds), (PPCOpcodeField::kRA), PrintDisasm_stdu),
+  INSTRUCTION(0x7c00016a, "stdux"       , kX      , kI, kGeneral, "Store Doubleword with Update Indexed"                                       , (PPCOpcodeField::kRS,PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRA), PrintDisasm_stdux),
+  INSTRUCTION(0x7c00012a, "stdx"        , kX      , kI, kGeneral, "Store Doubleword Indexed"                                                   , (PPCOpcodeField::kRS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stdx),
+  INSTRUCTION(0xd8000000, "stfd"        , kD      , kF, kGeneral, "Store Floating-Point Double"                                                , (PPCOpcodeField::kFS,PPCOpcodeField::kRA0,PPCOpcodeField::kd), (), PrintDisasm_stfd),
+  INSTRUCTION(0xdc000000, "stfdu"       , kD      , kF, kGeneral, "Store Floating-Point Double with Update"                                    , (PPCOpcodeField::kFS,PPCOpcodeField::kRA,PPCOpcodeField::kd), (PPCOpcodeField::kRA), PrintDisasm_stfdu),
+  INSTRUCTION(0x7c0005ee, "stfdux"      , kX      , kF, kGeneral, "Store Floating-Point Double with Update Indexed"                            , (PPCOpcodeField::kFS,PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRA), PrintDisasm_stfdux),
+  INSTRUCTION(0x7c0005ae, "stfdx"       , kX      , kF, kGeneral, "Store Floating-Point Double Indexed"                                        , (PPCOpcodeField::kFS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stfdx),
+  INSTRUCTION(0x7c0007ae, "stfiwx"      , kX      , kF, kGeneral, "Store Floating-Point as Integer Word Indexed"                               , (PPCOpcodeField::kFS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stfiwx),
+  INSTRUCTION(0xd0000000, "stfs"        , kD      , kF, kGeneral, "Store Floating-Point Single"                                                , (PPCOpcodeField::kFS,PPCOpcodeField::kRA0,PPCOpcodeField::kd), (), PrintDisasm_stfs),
+  INSTRUCTION(0xd4000000, "stfsu"       , kD      , kF, kGeneral, "Store Floating-Point Single with Update"                                    , (PPCOpcodeField::kFS,PPCOpcodeField::kRA,PPCOpcodeField::kd), (PPCOpcodeField::kRA), PrintDisasm_stfsu),
+  INSTRUCTION(0x7c00056e, "stfsux"      , kX      , kF, kGeneral, "Store Floating-Point Single with Update Indexed"                            , (PPCOpcodeField::kFS,PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRA), PrintDisasm_stfsux),
+  INSTRUCTION(0x7c00052e, "stfsx"       , kX      , kF, kGeneral, "Store Floating-Point Single Indexed"                                        , (PPCOpcodeField::kFS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stfsx),
+  INSTRUCTION(0xb0000000, "sth"         , kD      , kI, kGeneral, "Store Half Word"                                                            , (PPCOpcodeField::kRS,PPCOpcodeField::kRA0,PPCOpcodeField::kd), (), PrintDisasm_sth),
+  INSTRUCTION(0x7c00072c, "sthbrx"      , kX      , kI, kGeneral, "Store Half Word Byte-Reverse Indexed"                                       , (PPCOpcodeField::kRS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_sthbrx),
+  INSTRUCTION(0xb4000000, "sthu"        , kD      , kI, kGeneral, "Store Half Word with Update"                                                , (PPCOpcodeField::kRS,PPCOpcodeField::kRA,PPCOpcodeField::kd), (PPCOpcodeField::kRA), PrintDisasm_sthu),
+  INSTRUCTION(0x7c00036e, "sthux"       , kX      , kI, kGeneral, "Store Half Word with Update Indexed"                                        , (PPCOpcodeField::kRS,PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRA), PrintDisasm_sthux),
+  INSTRUCTION(0x7c00032e, "sthx"        , kX      , kI, kGeneral, "Store Half Word Indexed"                                                    , (PPCOpcodeField::kRS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_sthx),
+  INSTRUCTION(0xbc000000, "stmw"        , kD      , kI, kGeneral, "Store Multiple Word"                                                        , (), (), nullptr),
+  INSTRUCTION(0x7c0005aa, "stswi"       , kX      , kI, kGeneral, "Store String Word Immediate"                                                , (), (), nullptr),
+  INSTRUCTION(0x7c00052a, "stswx"       , kX      , kI, kGeneral, "Store String Word Indexed"                                                  , (), (), nullptr),
+  INSTRUCTION(0x7c00010e, "stvebx"      , kX      , kV, kGeneral, "Store Vector Element Byte Indexed"                                          , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvebx),
+  INSTRUCTION(0x7c00014e, "stvehx"      , kX      , kV, kGeneral, "Store Vector Element Half Word Indexed"                                     , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvehx),
+  INSTRUCTION(0x7c00018e, "stvewx"      , kX      , kV, kGeneral, "Store Vector Element Word Indexed"                                          , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvewx),
+  INSTRUCTION(0x10000183, "stvewx128"   , kVX128_1, kV, kGeneral, "Store Vector Element Word Indexed 128"                                      , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvewx128),
+  INSTRUCTION(0x7c00050e, "stvlx"       , kX      , kV, kGeneral, "Store Vector Left Indexed"                                                  , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvlx),
+  INSTRUCTION(0x10000503, "stvlx128"    , kVX128_1, kV, kGeneral, "Store Vector Left Indexed 128"                                              , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvlx128),
+  INSTRUCTION(0x7c00070e, "stvlxl"      , kX      , kV, kGeneral, "Store Vector Left Indexed LRU"                                              , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvlxl),
+  INSTRUCTION(0x10000703, "stvlxl128"   , kVX128_1, kV, kGeneral, "Store Vector Left Indexed LRU 128"                                          , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvlxl128),
+  INSTRUCTION(0x7c00054e, "stvrx"       , kX      , kV, kGeneral, "Store Vector Right Indexed"                                                 , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvrx),
+  INSTRUCTION(0x10000543, "stvrx128"    , kVX128_1, kV, kGeneral, "Store Vector Right Indexed 128"                                             , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvrx128),
+  INSTRUCTION(0x7c00074e, "stvrxl"      , kX      , kV, kGeneral, "Store Vector Right Indexed LRU"                                             , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvrxl),
+  INSTRUCTION(0x10000743, "stvrxl128"   , kVX128_1, kV, kGeneral, "Store Vector Right Indexed LRU 128"                                         , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvrxl128),
+  INSTRUCTION(0x7c0001ce, "stvx"        , kX      , kV, kGeneral, "Store Vector Indexed"                                                       , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvx),
+  INSTRUCTION(0x100001c3, "stvx128"     , kVX128_1, kV, kGeneral, "Store Vector Indexed 128"                                                   , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvx128),
+  INSTRUCTION(0x7c0003ce, "stvxl"       , kX      , kV, kGeneral, "Store Vector Indexed LRU"                                                   , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvxl),
+  INSTRUCTION(0x100003c3, "stvxl128"    , kVX128_1, kV, kGeneral, "Store Vector Indexed LRU 128"                                               , (PPCOpcodeField::kVS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stvxl128),
+  INSTRUCTION(0x90000000, "stw"         , kD      , kI, kGeneral, "Store Word"                                                                 , (PPCOpcodeField::kRS,PPCOpcodeField::kRA0,PPCOpcodeField::kd), (), PrintDisasm_stw),
+  INSTRUCTION(0x7c00052c, "stwbrx"      , kX      , kI, kGeneral, "Store Word Byte-Reverse Indexed"                                            , (PPCOpcodeField::kRS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stwbrx),
+  INSTRUCTION(0x7c00012d, "stwcx"       , kX      , kI, kGeneral, "Store Word Conditional Indexed"                                             , (PPCOpcodeField::kRS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (PPCOpcodeField::kCR), PrintDisasm_stwcx),
+  INSTRUCTION(0x94000000, "stwu"        , kD      , kI, kGeneral, "Store Word with Update"                                                     , (PPCOpcodeField::kRS,PPCOpcodeField::kRA,PPCOpcodeField::kd), (PPCOpcodeField::kRA), PrintDisasm_stwu),
+  INSTRUCTION(0x7c00016e, "stwux"       , kX      , kI, kGeneral, "Store Word with Update Indexed"                                             , (PPCOpcodeField::kRS,PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRA), PrintDisasm_stwux),
+  INSTRUCTION(0x7c00012e, "stwx"        , kX      , kI, kGeneral, "Store Word Indexed"                                                         , (PPCOpcodeField::kRS,PPCOpcodeField::kRA0,PPCOpcodeField::kRB), (), PrintDisasm_stwx),
+  INSTRUCTION(0x7c000010, "subfcx"      , kXO     , kI, kGeneral, "Subtract From Carrying"                                                     , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kCRcond,PPCOpcodeField::kOEcond), PrintDisasm_subfcx),
+  INSTRUCTION(0x7c000110, "subfex"      , kXO     , kI, kGeneral, "Subtract From Extended"                                                     , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kCRcond,PPCOpcodeField::kOEcond), PrintDisasm_subfex),
+  INSTRUCTION(0x20000000, "subficx"     , kD      , kI, kGeneral, "Subtract From Immediate Carrying"                                           , (PPCOpcodeField::kRA,PPCOpcodeField::kSIMM), (PPCOpcodeField::kRD,PPCOpcodeField::kCA), PrintDisasm_subficx),
+  INSTRUCTION(0x7c0001d0, "subfmex"     , kXO     , kI, kGeneral, "Subtract From Minus One Extended"                                           , (PPCOpcodeField::kRA,PPCOpcodeField::kCA), (PPCOpcodeField::kRD,PPCOpcodeField::kCRcond,PPCOpcodeField::kOEcond,PPCOpcodeField::kCA), PrintDisasm_subfmex),
+  INSTRUCTION(0x7c000050, "subfx"       , kXO     , kI, kGeneral, "Subtract From"                                                              , (PPCOpcodeField::kRA,PPCOpcodeField::kRB), (PPCOpcodeField::kRD,PPCOpcodeField::kCRcond,PPCOpcodeField::kOEcond), PrintDisasm_subfx),
+  INSTRUCTION(0x7c000190, "subfzex"     , kXO     , kI, kGeneral, "Subtract From Zero Extended"                                                , (PPCOpcodeField::kRA,PPCOpcodeField::kCA), (PPCOpcodeField::kRD,PPCOpcodeField::kCRcond,PPCOpcodeField::kOEcond,PPCOpcodeField::kCA), PrintDisasm_subfzex),
+  INSTRUCTION(0x7c0004ac, "sync"        , kX      , kI, kGeneral, "Synchronize"                                                                , (), (), PrintDisasm_sync),
+  INSTRUCTION(0x7c000088, "td"          , kX      , kI, kGeneral, "Trap Doubleword"                                                            , (PPCOpcodeField::kTO,PPCOpcodeField::kRA,PPCOpcodeField::kRB), (), PrintDisasm_td),
+  INSTRUCTION(0x08000000, "tdi"         , kD      , kI, kGeneral, "Trap Doubleword Immediate"                                                  , (PPCOpcodeField::kTO,PPCOpcodeField::kRA,PPCOpcodeField::kSIMM), (), PrintDisasm_tdi),
+  INSTRUCTION(0x7c000008, "tw"          , kX      , kI, kGeneral, "Trap Word"                                                                  , (PPCOpcodeField::kTO,PPCOpcodeField::kRA,PPCOpcodeField::kRB), (), PrintDisasm_tw),
+  INSTRUCTION(0x0c000000, "twi"         , kD      , kI, kGeneral, "Trap Word Immediate"                                                        , (PPCOpcodeField::kTO,PPCOpcodeField::kRA,PPCOpcodeField::kSIMM), (), PrintDisasm_twi),
+  INSTRUCTION(0x10000180, "vaddcuw"     , kVX     , kV, kGeneral, "Vector Add Carryout Unsigned Word"                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vaddcuw),
+  INSTRUCTION(0x1000000a, "vaddfp"      , kVX     , kV, kGeneral, "Vector Add Floating Point"                                                  , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vaddfp),
+  INSTRUCTION(0x14000010, "vaddfp128"   , kVX128  , kV, kGeneral, "Vector128 Add Floating Point"                                               , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vaddfp128),
+  INSTRUCTION(0x10000300, "vaddsbs"     , kVX     , kV, kGeneral, "Vector Add Signed Byte Saturate"                                            , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vaddsbs),
+  INSTRUCTION(0x10000340, "vaddshs"     , kVX     , kV, kGeneral, "Vector Add Signed Half Word Saturate"                                       , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vaddshs),
+  INSTRUCTION(0x10000380, "vaddsws"     , kVX     , kV, kGeneral, "Vector Add Signed Word Saturate"                                            , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vaddsws),
+  INSTRUCTION(0x10000000, "vaddubm"     , kVX     , kV, kGeneral, "Vector Add Unsigned Byte Modulo"                                            , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vaddubm),
+  INSTRUCTION(0x10000200, "vaddubs"     , kVX     , kV, kGeneral, "Vector Add Unsigned Byte Saturate"                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vaddubs),
+  INSTRUCTION(0x10000040, "vadduhm"     , kVX     , kV, kGeneral, "Vector Add Unsigned Half Word Modulo"                                       , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vadduhm),
+  INSTRUCTION(0x10000240, "vadduhs"     , kVX     , kV, kGeneral, "Vector Add Unsigned Half Word Saturate"                                     , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vadduhs),
+  INSTRUCTION(0x10000080, "vadduwm"     , kVX     , kV, kGeneral, "Vector Add Unsigned Word Modulo"                                            , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vadduwm),
+  INSTRUCTION(0x10000280, "vadduws"     , kVX     , kV, kGeneral, "Vector Add Unsigned Word Saturate"                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vadduws),
+  INSTRUCTION(0x10000404, "vand"        , kVX     , kV, kGeneral, "Vector Logical AND"                                                         , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vand),
+  INSTRUCTION(0x14000210, "vand128"     , kVX128  , kV, kGeneral, "Vector128 Logical AND"                                                      , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vand128),
+  INSTRUCTION(0x10000444, "vandc"       , kVX     , kV, kGeneral, "Vector Logical AND with Complement"                                         , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vandc),
+  INSTRUCTION(0x14000250, "vandc128"    , kVX128  , kV, kGeneral, "Vector128 Logical AND with Complement"                                      , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vandc128),
+  INSTRUCTION(0x10000502, "vavgsb"      , kVX     , kV, kGeneral, "Vector Average Signed Byte"                                                 , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vavgsb),
+  INSTRUCTION(0x10000542, "vavgsh"      , kVX     , kV, kGeneral, "Vector Average Signed Half Word"                                            , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vavgsh),
+  INSTRUCTION(0x10000582, "vavgsw"      , kVX     , kV, kGeneral, "Vector Average Signed Word"                                                 , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vavgsw),
+  INSTRUCTION(0x10000402, "vavgub"      , kVX     , kV, kGeneral, "Vector Average Unsigned Byte"                                               , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vavgub),
+  INSTRUCTION(0x10000442, "vavguh"      , kVX     , kV, kGeneral, "Vector Average Unsigned Half Word"                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vavguh),
+  INSTRUCTION(0x10000482, "vavguw"      , kVX     , kV, kGeneral, "Vector Average Unsigned Word"                                               , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vavguw),
+  INSTRUCTION(0x18000230, "vcfpsxws128" , kVX128_3, kV, kGeneral, "Vector128 Convert From Floating-Point to Signed Fixed-Point Word Saturate"  , (PPCOpcodeField::kVB,PPCOpcodeField::kUIMM), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vcfpsxws128),
+  INSTRUCTION(0x18000270, "vcfpuxws128" , kVX128_3, kV, kGeneral, "Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate", (PPCOpcodeField::kVB,PPCOpcodeField::kUIMM), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vcfpuxws128),
+  INSTRUCTION(0x1000034a, "vcfsx"       , kVX     , kV, kGeneral, "Vector Convert from Signed Fixed-Point Word"                                , (PPCOpcodeField::kVB,PPCOpcodeField::kUIMM), (PPCOpcodeField::kVD), PrintDisasm_vcfsx),
+  INSTRUCTION(0x1000030a, "vcfux"       , kVX     , kV, kGeneral, "Vector Convert from Unsigned Fixed-Point Word"                              , (PPCOpcodeField::kVB,PPCOpcodeField::kUIMM), (PPCOpcodeField::kVD), PrintDisasm_vcfux),
+  INSTRUCTION(0x100003c6, "vcmpbfp"     , kVC     , kV, kGeneral, "Vector Compare Bounds Floating Point"                                       , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpbfp),
+  INSTRUCTION(0x18000180, "vcmpbfp128"  , kVX128_R, kV, kGeneral, "Vector128 Compare Bounds Floating Point"                                    , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpbfp128),
+  INSTRUCTION(0x100000c6, "vcmpeqfp"    , kVC     , kV, kGeneral, "Vector Compare Equal-to Floating Point"                                     , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpeqfp),
+  INSTRUCTION(0x18000000, "vcmpeqfp128" , kVX128_R, kV, kGeneral, "Vector128 Compare Equal-to Floating Point"                                  , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpeqfp128),
+  INSTRUCTION(0x10000006, "vcmpequb"    , kVC     , kV, kGeneral, "Vector Compare Equal-to Unsigned Byte"                                      , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpequb),
+  INSTRUCTION(0x10000046, "vcmpequh"    , kVC     , kV, kGeneral, "Vector Compare Equal-to Unsigned Half Word"                                 , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpequh),
+  INSTRUCTION(0x10000086, "vcmpequw"    , kVC     , kV, kGeneral, "Vector Compare Equal-to Unsigned Word"                                      , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpequw),
+  INSTRUCTION(0x18000200, "vcmpequw128" , kVX128_R, kV, kGeneral, "Vector128 Compare Equal-to Unsigned Word"                                   , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpequw128),
+  INSTRUCTION(0x100001c6, "vcmpgefp"    , kVC     , kV, kGeneral, "Vector Compare Greater-Than-or-Equal-to Floating Point"                     , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpgefp),
+  INSTRUCTION(0x18000080, "vcmpgefp128" , kVX128_R, kV, kGeneral, "Vector128 Compare Greater-Than-or-Equal-to Floating Point"                  , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpgefp128),
+  INSTRUCTION(0x100002c6, "vcmpgtfp"    , kVC     , kV, kGeneral, "Vector Compare Greater-Than Floating Point"                                 , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpgtfp),
+  INSTRUCTION(0x18000100, "vcmpgtfp128" , kVX128_R, kV, kGeneral, "Vector128 Compare Greater-Than Floating-Point"                              , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpgtfp128),
+  INSTRUCTION(0x10000306, "vcmpgtsb"    , kVC     , kV, kGeneral, "Vector Compare Greater-Than Signed Byte"                                    , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpgtsb),
+  INSTRUCTION(0x10000346, "vcmpgtsh"    , kVC     , kV, kGeneral, "Vector Compare Greater-Than Signed Half Word"                               , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpgtsh),
+  INSTRUCTION(0x10000386, "vcmpgtsw"    , kVC     , kV, kGeneral, "Vector Compare Greater-Than Signed Word"                                    , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpgtsw),
+  INSTRUCTION(0x10000206, "vcmpgtub"    , kVC     , kV, kGeneral, "Vector Compare Greater-Than Unsigned Byte"                                  , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpgtub),
+  INSTRUCTION(0x10000246, "vcmpgtuh"    , kVC     , kV, kGeneral, "Vector Compare Greater-Than Unsigned Half Word"                             , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpgtuh),
+  INSTRUCTION(0x10000286, "vcmpgtuw"    , kVC     , kV, kGeneral, "Vector Compare Greater-Than Unsigned Word"                                  , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kCRcond), PrintDisasm_vcmpgtuw),
+  INSTRUCTION(0x180002b0, "vcsxwfp128"  , kVX128_3, kV, kGeneral, "Vector128 Convert From Signed Fixed-Point Word to Floating-Point"           , (PPCOpcodeField::kVB,PPCOpcodeField::kUIMM), (PPCOpcodeField::kVD), PrintDisasm_vcsxwfp128),
+  INSTRUCTION(0x100003ca, "vctsxs"      , kVX     , kV, kGeneral, "Vector Convert to Signed Fixed-Point Word Saturate"                         , (PPCOpcodeField::kVB,PPCOpcodeField::kUIMM), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vctsxs),
+  INSTRUCTION(0x1000038a, "vctuxs"      , kVX     , kV, kGeneral, "Vector Convert to Unsigned Fixed-Point Word Saturate"                       , (PPCOpcodeField::kVB,PPCOpcodeField::kUIMM), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vctuxs),
+  INSTRUCTION(0x180002f0, "vcuxwfp128"  , kVX128_3, kV, kGeneral, "Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point"         , (PPCOpcodeField::kVB,PPCOpcodeField::kUIMM), (PPCOpcodeField::kVD), PrintDisasm_vcuxwfp128),
+  INSTRUCTION(0x1000018a, "vexptefp"    , kVX     , kV, kGeneral, "Vector 2 Raised to the Exponent Estimate Floating Point"                    , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vexptefp),
+  INSTRUCTION(0x180006b0, "vexptefp128" , kVX128_3, kV, kGeneral, "Vector128 Log2 Estimate Floating Point"                                     , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vexptefp128),
+  INSTRUCTION(0x100001ca, "vlogefp"     , kVX     , kV, kGeneral, "Vector Log2 Estimate Floating Point"                                        , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vlogefp),
+  INSTRUCTION(0x180006f0, "vlogefp128"  , kVX128_3, kV, kGeneral, "Vector128 Log2 Estimate Floating Point"                                     , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vlogefp128),
+  INSTRUCTION(0x14000110, "vmaddcfp128" , kVX128  , kV, kGeneral, "Vector128 Multiply Add Floating Point"                                      , (PPCOpcodeField::kVA,PPCOpcodeField::kVD,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmaddcfp128),
+  INSTRUCTION(0x1000002e, "vmaddfp"     , kVA     , kV, kGeneral, "Vector Multiply-Add Floating Point"                                         , (PPCOpcodeField::kVA,PPCOpcodeField::kVC,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmaddfp),
+  INSTRUCTION(0x140000d0, "vmaddfp128"  , kVX128  , kV, kGeneral, "Vector128 Multiply Add Floating Point"                                      , (PPCOpcodeField::kVA,PPCOpcodeField::kVC,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmaddfp128),
+  INSTRUCTION(0x1000040a, "vmaxfp"      , kVX     , kV, kGeneral, "Vector Maximum Floating Point"                                              , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmaxfp),
+  INSTRUCTION(0x18000280, "vmaxfp128"   , kVX128  , kV, kGeneral, "Vector128 Maximum Floating Point"                                           , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmaxfp128),
+  INSTRUCTION(0x10000102, "vmaxsb"      , kVX     , kV, kGeneral, "Vector Maximum Signed Byte"                                                 , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmaxsb),
+  INSTRUCTION(0x10000142, "vmaxsh"      , kVX     , kV, kGeneral, "Vector Maximum Signed Half Word"                                            , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmaxsh),
+  INSTRUCTION(0x10000182, "vmaxsw"      , kVX     , kV, kGeneral, "Vector Maximum Signed Word"                                                 , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmaxsw),
+  INSTRUCTION(0x10000002, "vmaxub"      , kVX     , kV, kGeneral, "Vector Maximum Unsigned Byte"                                               , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmaxub),
+  INSTRUCTION(0x10000042, "vmaxuh"      , kVX     , kV, kGeneral, "Vector Maximum Unsigned Half Word"                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmaxuh),
+  INSTRUCTION(0x10000082, "vmaxuw"      , kVX     , kV, kGeneral, "Vector Maximum Unsigned Word"                                               , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmaxuw),
+  INSTRUCTION(0x10000020, "vmhaddshs"   , kVA     , kV, kGeneral, "Vector Multiply-High and Add Signed Signed Half Word Saturate"              , (PPCOpcodeField::kVA,PPCOpcodeField::kVB,PPCOpcodeField::kVC), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vmhaddshs),
+  INSTRUCTION(0x10000021, "vmhraddshs"  , kVA     , kV, kGeneral, "Vector Multiply-High Round and Add Signed Signed Half Word Saturate"        , (PPCOpcodeField::kVA,PPCOpcodeField::kVB,PPCOpcodeField::kVC), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vmhraddshs),
+  INSTRUCTION(0x1000044a, "vminfp"      , kVX     , kV, kGeneral, "Vector Minimum Floating Point"                                              , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vminfp),
+  INSTRUCTION(0x180002c0, "vminfp128"   , kVX128  , kV, kGeneral, "Vector128 Minimum Floating Point"                                           , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vminfp128),
+  INSTRUCTION(0x10000302, "vminsb"      , kVX     , kV, kGeneral, "Vector Minimum Signed Byte"                                                 , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vminsb),
+  INSTRUCTION(0x10000342, "vminsh"      , kVX     , kV, kGeneral, "Vector Minimum Signed Half Word"                                            , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vminsh),
+  INSTRUCTION(0x10000382, "vminsw"      , kVX     , kV, kGeneral, "Vector Minimum Signed Word"                                                 , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vminsw),
+  INSTRUCTION(0x10000202, "vminub"      , kVX     , kV, kGeneral, "Vector Minimum Unsigned Byte"                                               , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vminub),
+  INSTRUCTION(0x10000242, "vminuh"      , kVX     , kV, kGeneral, "Vector Minimum Unsigned Half Word"                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vminuh),
+  INSTRUCTION(0x10000282, "vminuw"      , kVX     , kV, kGeneral, "Vector Minimum Unsigned Word"                                               , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vminuw),
+  INSTRUCTION(0x10000022, "vmladduhm"   , kVA     , kV, kGeneral, "Vector Multiply-Low and Add Unsigned Half Word Modulo"                      , (PPCOpcodeField::kVA,PPCOpcodeField::kVB,PPCOpcodeField::kVC), (PPCOpcodeField::kVD), PrintDisasm_vmladduhm),
+  INSTRUCTION(0x1000000c, "vmrghb"      , kVX     , kV, kGeneral, "Vector Merge High Byte"                                                     , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmrghb),
+  INSTRUCTION(0x1000004c, "vmrghh"      , kVX     , kV, kGeneral, "Vector Merge High Half Word"                                                , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmrghh),
+  INSTRUCTION(0x1000008c, "vmrghw"      , kVX     , kV, kGeneral, "Vector Merge High Word"                                                     , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmrghw),
+  INSTRUCTION(0x18000300, "vmrghw128"   , kVX128  , kV, kGeneral, "Vector128 Merge High Word"                                                  , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmrghw128),
+  INSTRUCTION(0x1000010c, "vmrglb"      , kVX     , kV, kGeneral, "Vector Merge Low Byte"                                                      , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmrglb),
+  INSTRUCTION(0x1000014c, "vmrglh"      , kVX     , kV, kGeneral, "Vector Merge Low Half Word"                                                 , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmrglh),
+  INSTRUCTION(0x1000018c, "vmrglw"      , kVX     , kV, kGeneral, "Vector Merge Low Word"                                                      , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmrglw),
+  INSTRUCTION(0x18000340, "vmrglw128"   , kVX128  , kV, kGeneral, "Vector128 Merge Low Word"                                                   , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmrglw128),
+  INSTRUCTION(0x14000190, "vmsum3fp128" , kVX128  , kV, kGeneral, "Vector128 Multiply Sum 3-way Floating Point"                                , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmsum3fp128),
+  INSTRUCTION(0x140001d0, "vmsum4fp128" , kVX128  , kV, kGeneral, "Vector128 Multiply Sum 4-way Floating-Point"                                , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmsum4fp128),
+  INSTRUCTION(0x10000025, "vmsummbm"    , kVA     , kV, kGeneral, "Vector Multiply-Sum Mixed-Sign Byte Modulo"                                 , (PPCOpcodeField::kVA,PPCOpcodeField::kVB,PPCOpcodeField::kVC), (PPCOpcodeField::kVD), PrintDisasm_vmsummbm),
+  INSTRUCTION(0x10000028, "vmsumshm"    , kVA     , kV, kGeneral, "Vector Multiply-Sum Signed Half Word Modulo"                                , (PPCOpcodeField::kVA,PPCOpcodeField::kVB,PPCOpcodeField::kVC), (PPCOpcodeField::kVD), PrintDisasm_vmsumshm),
+  INSTRUCTION(0x10000029, "vmsumshs"    , kVA     , kV, kGeneral, "Vector Multiply-Sum Signed Half Word Saturate"                              , (PPCOpcodeField::kVA,PPCOpcodeField::kVB,PPCOpcodeField::kVC), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vmsumshs),
+  INSTRUCTION(0x10000024, "vmsumubm"    , kVA     , kV, kGeneral, "Vector Multiply-Sum Unsigned Byte Modulo"                                   , (PPCOpcodeField::kVA,PPCOpcodeField::kVB,PPCOpcodeField::kVC), (PPCOpcodeField::kVD), PrintDisasm_vmsumubm),
+  INSTRUCTION(0x10000026, "vmsumuhm"    , kVA     , kV, kGeneral, "Vector Multiply-Sum Unsigned Half Word Modulo"                              , (PPCOpcodeField::kVA,PPCOpcodeField::kVB,PPCOpcodeField::kVC), (PPCOpcodeField::kVD), PrintDisasm_vmsumuhm),
+  INSTRUCTION(0x10000027, "vmsumuhs"    , kVA     , kV, kGeneral, "Vector Multiply-Sum Unsigned Half Word Saturate"                            , (PPCOpcodeField::kVA,PPCOpcodeField::kVB,PPCOpcodeField::kVC), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vmsumuhs),
+  INSTRUCTION(0x10000308, "vmulesb"     , kVX     , kV, kGeneral, "Vector Multiply Even Signed Byte"                                           , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmulesb),
+  INSTRUCTION(0x10000348, "vmulesh"     , kVX     , kV, kGeneral, "Vector Multiply Even Signed Half Word"                                      , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmulesh),
+  INSTRUCTION(0x10000208, "vmuleub"     , kVX     , kV, kGeneral, "Vector Multiply Even Unsigned Byte"                                         , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmuleub),
+  INSTRUCTION(0x10000248, "vmuleuh"     , kVX     , kV, kGeneral, "Vector Multiply Even Unsigned Half Word"                                    , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmuleuh),
+  INSTRUCTION(0x14000090, "vmulfp128"   , kVX128  , kV, kGeneral, "Vector128 Multiply Floating-Point"                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmulfp128),
+  INSTRUCTION(0x10000108, "vmulosb"     , kVX     , kV, kGeneral, "Vector Multiply Odd Signed Byte"                                            , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmulosb),
+  INSTRUCTION(0x10000148, "vmulosh"     , kVX     , kV, kGeneral, "Vector Multiply Odd Signed Half Word"                                       , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmulosh),
+  INSTRUCTION(0x10000008, "vmuloub"     , kVX     , kV, kGeneral, "Vector Multiply Odd Unsigned Byte"                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmuloub),
+  INSTRUCTION(0x10000048, "vmulouh"     , kVX     , kV, kGeneral, "Vector Multiply Odd Unsigned Half Word"                                     , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vmulouh),
+  INSTRUCTION(0x1000002f, "vnmsubfp"    , kVA     , kV, kGeneral, "Vector Negative Multiply-Subtract Floating Point"                           , (PPCOpcodeField::kVA,PPCOpcodeField::kVC,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vnmsubfp),
+  INSTRUCTION(0x14000150, "vnmsubfp128" , kVX128  , kV, kGeneral, "Vector128 Negative Multiply-Subtract Floating Point"                        , (PPCOpcodeField::kVA,PPCOpcodeField::kVD,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vnmsubfp128),
+  INSTRUCTION(0x10000504, "vnor"        , kVX     , kV, kGeneral, "Vector Logical NOR"                                                         , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vnor),
+  INSTRUCTION(0x14000290, "vnor128"     , kVX128  , kV, kGeneral, "Vector128 Logical NOR"                                                      , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vnor128),
+  INSTRUCTION(0x10000484, "vor"         , kVX     , kV, kGeneral, "Vector Logical OR"                                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vor),
+  INSTRUCTION(0x140002d0, "vor128"      , kVX128  , kV, kGeneral, "Vector128 Logical OR"                                                       , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vor128),
+  INSTRUCTION(0x1000002b, "vperm"       , kVA     , kV, kGeneral, "Vector Permute"                                                             , (PPCOpcodeField::kVA,PPCOpcodeField::kVB,PPCOpcodeField::kVC), (PPCOpcodeField::kVD), PrintDisasm_vperm),
+  INSTRUCTION(0x14000000, "vperm128"    , kVX128_2, kV, kGeneral, "Vector128 Permute"                                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB,PPCOpcodeField::kVC), (PPCOpcodeField::kVD), PrintDisasm_vperm128),
+  INSTRUCTION(0x18000210, "vpermwi128"  , kVX128_P, kV, kGeneral, "Vector128 Permutate Word Immediate"                                         , (PPCOpcodeField::kVB,PPCOpcodeField::kUIMM), (PPCOpcodeField::kVD), PrintDisasm_vpermwi128),
+  INSTRUCTION(0x18000610, "vpkd3d128"   , kVX128_4, kV, kGeneral, "Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert"              , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), nullptr),
+  INSTRUCTION(0x1000030e, "vpkpx"       , kVX     , kV, kGeneral, "Vector Pack Pixel"                                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vpkpx),
+  INSTRUCTION(0x1000018e, "vpkshss"     , kVX     , kV, kGeneral, "Vector Pack Signed Half Word Signed Saturate"                               , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vpkshss),
+  INSTRUCTION(0x14000200, "vpkshss128"  , kVX128  , kV, kGeneral, "Vector128 Pack Signed Half Word Signed Saturate"                            , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vpkshss128),
+  INSTRUCTION(0x1000010e, "vpkshus"     , kVX     , kV, kGeneral, "Vector Pack Signed Half Word Unsigned Saturate"                             , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vpkshus),
+  INSTRUCTION(0x14000240, "vpkshus128"  , kVX128  , kV, kGeneral, "Vector128 Pack Signed Half Word Unsigned Saturate"                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vpkshus128),
+  INSTRUCTION(0x100001ce, "vpkswss"     , kVX     , kV, kGeneral, "Vector Pack Signed Word Signed Saturate"                                    , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vpkswss),
+  INSTRUCTION(0x14000280, "vpkswss128"  , kVX128  , kV, kGeneral, "Vector128 Pack Signed Word Signed Saturate"                                 , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vpkswss128),
+  INSTRUCTION(0x1000014e, "vpkswus"     , kVX     , kV, kGeneral, "Vector Pack Signed Word Unsigned Saturate"                                  , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vpkswus),
+  INSTRUCTION(0x140002c0, "vpkswus128"  , kVX128  , kV, kGeneral, "Vector128 Pack Signed Word Unsigned Saturate"                               , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vpkswus128),
+  INSTRUCTION(0x1000000e, "vpkuhum"     , kVX     , kV, kGeneral, "Vector Pack Unsigned Half Word Unsigned Modulo"                             , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vpkuhum),
+  INSTRUCTION(0x14000300, "vpkuhum128"  , kVX128  , kV, kGeneral, "Vector128 Pack Unsigned Half Word Unsigned Modulo"                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vpkuhum128),
+  INSTRUCTION(0x1000008e, "vpkuhus"     , kVX     , kV, kGeneral, "Vector Pack Unsigned Half Word Unsigned Saturate"                           , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vpkuhus),
+  INSTRUCTION(0x14000340, "vpkuhus128"  , kVX128  , kV, kGeneral, "Vector128 Pack Unsigned Half Word Unsigned Saturate"                        , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vpkuhus128),
+  INSTRUCTION(0x1000004e, "vpkuwum"     , kVX     , kV, kGeneral, "Vector Pack Unsigned Word Unsigned Modulo"                                  , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vpkuwum),
+  INSTRUCTION(0x14000380, "vpkuwum128"  , kVX128  , kV, kGeneral, "Vector128 Pack Unsigned Word Unsigned Modulo"                               , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vpkuwum128),
+  INSTRUCTION(0x100000ce, "vpkuwus"     , kVX     , kV, kGeneral, "Vector Pack Unsigned Word Unsigned Saturate"                                , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vpkuwus),
+  INSTRUCTION(0x140003c0, "vpkuwus128"  , kVX128  , kV, kGeneral, "Vector128 Pack Unsigned Word Unsigned Saturate"                             , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vpkuwus128),
+  INSTRUCTION(0x1000010a, "vrefp"       , kVX     , kV, kGeneral, "Vector Reciprocal Estimate Floating Point"                                  , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrefp),
+  INSTRUCTION(0x18000630, "vrefp128"    , kVX128_3, kV, kGeneral, "Vector128 Reciprocal Estimate Floating Point"                               , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrefp128),
+  INSTRUCTION(0x100002ca, "vrfim"       , kVX     , kV, kGeneral, "Vector Round to Floating-Point Integer toward -Infinity"                    , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrfim),
+  INSTRUCTION(0x18000330, "vrfim128"    , kVX128_3, kV, kGeneral, "Vector128 Round to Floating-Point Integer toward -Infinity"                 , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrfim128),
+  INSTRUCTION(0x1000020a, "vrfin"       , kVX     , kV, kGeneral, "Vector Round to Floating-Point Integer Nearest"                             , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrfin),
+  INSTRUCTION(0x18000370, "vrfin128"    , kVX128_3, kV, kGeneral, "Vector128 Round to Floating-Point Integer Nearest"                          , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrfin128),
+  INSTRUCTION(0x1000028a, "vrfip"       , kVX     , kV, kGeneral, "Vector Round to Floating-Point Integer toward +Infinity"                    , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrfip),
+  INSTRUCTION(0x180003b0, "vrfip128"    , kVX128_3, kV, kGeneral, "Vector128 Round to Floating-Point Integer toward +Infinity"                 , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrfip128),
+  INSTRUCTION(0x1000024a, "vrfiz"       , kVX     , kV, kGeneral, "Vector Round to Floating-Point Integer toward Zero"                         , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrfiz),
+  INSTRUCTION(0x180003f0, "vrfiz128"    , kVX128_3, kV, kGeneral, "Vector128 Round to Floating-Point Integer toward Zero"                      , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrfiz128),
+  INSTRUCTION(0x10000004, "vrlb"        , kVX     , kV, kGeneral, "Vector Rotate Left Integer Byte"                                            , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrlb),
+  INSTRUCTION(0x10000044, "vrlh"        , kVX     , kV, kGeneral, "Vector Rotate Left Integer Half Word"                                       , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrlh),
+  INSTRUCTION(0x18000710, "vrlimi128"   , kVX128_4, kV, kGeneral, "Vector128 Rotate Left Immediate and Mask Insert"                            , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrlimi128),
+  INSTRUCTION(0x10000084, "vrlw"        , kVX     , kV, kGeneral, "Vector Rotate Left Integer Word"                                            , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrlw),
+  INSTRUCTION(0x18000050, "vrlw128"     , kVX128  , kV, kGeneral, "Vector128 Rotate Left Word"                                                 , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrlw128),
+  INSTRUCTION(0x1000014a, "vrsqrtefp"   , kVX     , kV, kGeneral, "Vector Reciprocal Square Root Estimate Floating Point"                      , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrsqrtefp),
+  INSTRUCTION(0x18000670, "vrsqrtefp128", kVX128_3, kV, kGeneral, "Vector128 Reciprocal Square Root Estimate Floating Point"                   , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vrsqrtefp128),
+  INSTRUCTION(0x1000002a, "vsel"        , kVA     , kV, kGeneral, "Vector Conditional Select"                                                  , (PPCOpcodeField::kVA,PPCOpcodeField::kVB,PPCOpcodeField::kVC), (PPCOpcodeField::kVD), PrintDisasm_vsel),
+  INSTRUCTION(0x14000350, "vsel128"     , kVX128  , kV, kGeneral, "Vector128 Conditional Select"                                               , (PPCOpcodeField::kVA,PPCOpcodeField::kVB,PPCOpcodeField::kVD), (PPCOpcodeField::kVD), PrintDisasm_vsel128),
+  INSTRUCTION(0x100001c4, "vsl"         , kVX     , kV, kGeneral, "Vector Shift Left"                                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsl),
+  INSTRUCTION(0x10000104, "vslb"        , kVX     , kV, kGeneral, "Vector Shift Left Integer Byte"                                             , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vslb),
+  INSTRUCTION(0x1000002c, "vsldoi"      , kVA     , kV, kGeneral, "Vector Shift Left Double by Octet Immediate"                                , (PPCOpcodeField::kVA,PPCOpcodeField::kVB,PPCOpcodeField::kSHB), (PPCOpcodeField::kVD), PrintDisasm_vsldoi),
+  INSTRUCTION(0x10000010, "vsldoi128"   , kVX128_5, kV, kGeneral, "Vector128 Shift Left Double by Octet Immediate"                             , (PPCOpcodeField::kVA,PPCOpcodeField::kVB,PPCOpcodeField::kSHB), (PPCOpcodeField::kVD), PrintDisasm_vsldoi128),
+  INSTRUCTION(0x10000144, "vslh"        , kVX     , kV, kGeneral, "Vector Shift Left Integer Half Word"                                        , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vslh),
+  INSTRUCTION(0x1000040c, "vslo"        , kVX     , kV, kGeneral, "Vector Shift Left by Octet"                                                 , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vslo),
+  INSTRUCTION(0x14000390, "vslo128"     , kVX128  , kV, kGeneral, "Vector128 Shift Left Octet"                                                 , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vslo128),
+  INSTRUCTION(0x10000184, "vslw"        , kVX     , kV, kGeneral, "Vector Shift Left Integer Word"                                             , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vslw),
+  INSTRUCTION(0x180000d0, "vslw128"     , kVX128  , kV, kGeneral, "Vector128 Shift Left Integer Word"                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vslw128),
+  INSTRUCTION(0x1000020c, "vspltb"      , kVX     , kV, kGeneral, "Vector Splat Byte"                                                          , (PPCOpcodeField::kVB,PPCOpcodeField::kUIMM), (PPCOpcodeField::kVD), PrintDisasm_vspltb),
+  INSTRUCTION(0x1000024c, "vsplth"      , kVX     , kV, kGeneral, "Vector Splat Half Word"                                                     , (PPCOpcodeField::kVB,PPCOpcodeField::kUIMM), (PPCOpcodeField::kVD), PrintDisasm_vsplth),
+  INSTRUCTION(0x1000030c, "vspltisb"    , kVX     , kV, kGeneral, "Vector Splat Immediate Signed Byte"                                         , (PPCOpcodeField::kSIMM), (PPCOpcodeField::kVD), PrintDisasm_vspltisb),
+  INSTRUCTION(0x1000034c, "vspltish"    , kVX     , kV, kGeneral, "Vector Splat Immediate Signed Half Word"                                    , (PPCOpcodeField::kSIMM), (PPCOpcodeField::kVD), PrintDisasm_vspltish),
+  INSTRUCTION(0x1000038c, "vspltisw"    , kVX     , kV, kGeneral, "Vector Splat Immediate Signed Word"                                         , (PPCOpcodeField::kSIMM), (PPCOpcodeField::kVD), PrintDisasm_vspltisw),
+  INSTRUCTION(0x18000770, "vspltisw128" , kVX128_3, kV, kGeneral, "Vector128 Splat Immediate Signed Word"                                      , (PPCOpcodeField::kSIMM), (PPCOpcodeField::kVD), PrintDisasm_vspltisw128),
+  INSTRUCTION(0x1000028c, "vspltw"      , kVX     , kV, kGeneral, "Vector Splat Word"                                                          , (PPCOpcodeField::kVB,PPCOpcodeField::kUIMM), (PPCOpcodeField::kVD), PrintDisasm_vspltw),
+  INSTRUCTION(0x18000730, "vspltw128"   , kVX128_3, kV, kGeneral, "Vector128 Splat Word"                                                       , (PPCOpcodeField::kVB,PPCOpcodeField::kUIMM), (PPCOpcodeField::kVD), PrintDisasm_vspltw128),
+  INSTRUCTION(0x100002c4, "vsr"         , kVX     , kV, kGeneral, "Vector Shift Right"                                                         , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsr),
+  INSTRUCTION(0x10000304, "vsrab"       , kVX     , kV, kGeneral, "Vector Shift Right Algebraic Byte"                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsrab),
+  INSTRUCTION(0x10000344, "vsrah"       , kVX     , kV, kGeneral, "Vector Shift Right Algebraic Half Word"                                     , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsrah),
+  INSTRUCTION(0x10000384, "vsraw"       , kVX     , kV, kGeneral, "Vector Shift Right Algebraic Word"                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsraw),
+  INSTRUCTION(0x18000150, "vsraw128"    , kVX128  , kV, kGeneral, "Vector128 Shift Right Arithmetic Word"                                      , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsraw128),
+  INSTRUCTION(0x10000204, "vsrb"        , kVX     , kV, kGeneral, "Vector Shift Right Byte"                                                    , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsrb),
+  INSTRUCTION(0x10000244, "vsrh"        , kVX     , kV, kGeneral, "Vector Shift Right Half Word"                                               , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsrh),
+  INSTRUCTION(0x1000044c, "vsro"        , kVX     , kV, kGeneral, "Vector Shift Right Octet"                                                   , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsro),
+  INSTRUCTION(0x140003d0, "vsro128"     , kVX128  , kV, kGeneral, "Vector128 Shift Right Octet"                                                , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsro128),
+  INSTRUCTION(0x10000284, "vsrw"        , kVX     , kV, kGeneral, "Vector Shift Right Word"                                                    , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsrw),
+  INSTRUCTION(0x180001d0, "vsrw128"     , kVX128  , kV, kGeneral, "Vector128 Shift Right Word"                                                 , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsrw128),
+  INSTRUCTION(0x10000580, "vsubcuw"     , kVX     , kV, kGeneral, "Vector Subtract Carryout Unsigned Word"                                     , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsubcuw),
+  INSTRUCTION(0x1000004a, "vsubfp"      , kVX     , kV, kGeneral, "Vector Subtract Floating Point"                                             , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsubfp),
+  INSTRUCTION(0x14000050, "vsubfp128"   , kVX128  , kV, kGeneral, "Vector128 Subtract Floating Point"                                          , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsubfp128),
+  INSTRUCTION(0x10000700, "vsubsbs"     , kVX     , kV, kGeneral, "Vector Subtract Signed Byte Saturate"                                       , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vsubsbs),
+  INSTRUCTION(0x10000740, "vsubshs"     , kVX     , kV, kGeneral, "Vector Subtract Signed Half Word Saturate"                                  , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vsubshs),
+  INSTRUCTION(0x10000780, "vsubsws"     , kVX     , kV, kGeneral, "Vector Subtract Signed Word Saturate"                                       , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vsubsws),
+  INSTRUCTION(0x10000400, "vsububm"     , kVX     , kV, kGeneral, "Vector Subtract Unsigned Byte Modulo"                                       , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsububm),
+  INSTRUCTION(0x10000600, "vsububs"     , kVX     , kV, kGeneral, "Vector Subtract Unsigned Byte Saturate"                                     , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vsububs),
+  INSTRUCTION(0x10000440, "vsubuhm"     , kVX     , kV, kGeneral, "Vector Subtract Unsigned Half Word Modulo"                                  , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsubuhm),
+  INSTRUCTION(0x10000640, "vsubuhs"     , kVX     , kV, kGeneral, "Vector Subtract Unsigned Half Word Saturate"                                , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vsubuhs),
+  INSTRUCTION(0x10000480, "vsubuwm"     , kVX     , kV, kGeneral, "Vector Subtract Unsigned Word Modulo"                                       , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vsubuwm),
+  INSTRUCTION(0x10000680, "vsubuws"     , kVX     , kV, kGeneral, "Vector Subtract Unsigned Word Saturate"                                     , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vsubuws),
+  INSTRUCTION(0x10000688, "vsum2sws"    , kVX     , kV, kGeneral, "Vector Sum Across Partial (1/2) Signed Word Saturate"                       , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vsum2sws),
+  INSTRUCTION(0x10000708, "vsum4sbs"    , kVX     , kV, kGeneral, "Vector Sum Across Partial (1/4) Signed Byte Saturate"                       , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vsum4sbs),
+  INSTRUCTION(0x10000648, "vsum4shs"    , kVX     , kV, kGeneral, "Vector Sum Across Partial (1/4) Signed Half Word Saturate"                  , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vsum4shs),
+  INSTRUCTION(0x10000608, "vsum4ubs"    , kVX     , kV, kGeneral, "Vector Sum Across Partial (1/4) Unsigned Byte Saturate"                     , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vsum4ubs),
+  INSTRUCTION(0x10000788, "vsumsws"     , kVX     , kV, kGeneral, "Vector Sum Across Signed Word Saturate"                                     , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD,PPCOpcodeField::kVSCR), PrintDisasm_vsumsws),
+  INSTRUCTION(0x180007f0, "vupkd3d128"  , kVX128_3, kV, kGeneral, "Vector128 Unpack D3Dtype"                                                   , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), nullptr),
+  INSTRUCTION(0x1000034e, "vupkhpx"     , kVX     , kV, kGeneral, "Vector Unpack High Pixel"                                                   , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vupkhpx),
+  INSTRUCTION(0x1000020e, "vupkhsb"     , kVX     , kV, kGeneral, "Vector Unpack High Signed Byte"                                             , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vupkhsb),
+  INSTRUCTION(0x18000380, "vupkhsb128"  , kVX128  , kV, kGeneral, "Vector128 Unpack High Signed Byte"                                          , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vupkhsb128),
+  INSTRUCTION(0x1000024e, "vupkhsh"     , kVX     , kV, kGeneral, "Vector Unpack High Signed Half Word"                                        , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vupkhsh),
+  INSTRUCTION(0x100003ce, "vupklpx"     , kVX     , kV, kGeneral, "Vector Unpack Low Pixel"                                                    , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vupklpx),
+  INSTRUCTION(0x1000028e, "vupklsb"     , kVX     , kV, kGeneral, "Vector Unpack Low Signed Byte"                                              , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vupklsb),
+  INSTRUCTION(0x180003c0, "vupklsb128"  , kVX128  , kV, kGeneral, "Vector128 Unpack Low Signed Byte"                                           , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vupklsb128),
+  INSTRUCTION(0x100002ce, "vupklsh"     , kVX     , kV, kGeneral, "Vector Unpack Low Signed Half Word"                                         , (PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vupklsh),
+  INSTRUCTION(0x100004c4, "vxor"        , kVX     , kV, kGeneral, "Vector Logical XOR"                                                         , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vxor),
+  INSTRUCTION(0x14000310, "vxor128"     , kVX128  , kV, kGeneral, "Vector128 Logical XOR"                                                      , (PPCOpcodeField::kVA,PPCOpcodeField::kVB), (PPCOpcodeField::kVD), PrintDisasm_vxor128),
+  INSTRUCTION(0x68000000, "xori"        , kD      , kI, kGeneral, "XOR Immediate"                                                              , (PPCOpcodeField::kRS,PPCOpcodeField::kUIMM), (PPCOpcodeField::kRA), PrintDisasm_xori),
+  INSTRUCTION(0x6c000000, "xoris"       , kD      , kI, kGeneral, "XOR Immediate Shifted"                                                      , (PPCOpcodeField::kRS,PPCOpcodeField::kUIMM), (PPCOpcodeField::kRA), PrintDisasm_xoris),
+  INSTRUCTION(0x7c000278, "xorx"        , kX      , kI, kGeneral, "XOR"                                                                        , (PPCOpcodeField::kRS,PPCOpcodeField::kRB), (PPCOpcodeField::kRA,PPCOpcodeField::kCRcond), PrintDisasm_xorx),
+};
+static_assert(sizeof(ppc_opcode_disasm_table) / sizeof(PPCOpcodeDisasmInfo) == static_cast<int>(PPCOpcode::kInvalid), "PPC table mismatch - rerun ppc-table-gen");
+
+const PPCOpcodeDisasmInfo& GetOpcodeDisasmInfo(PPCOpcode opcode) {
+  return ppc_opcode_disasm_table[static_cast<int>(opcode)];
+}
+void RegisterOpcodeDisasm(PPCOpcode opcode, InstrDisasmFn fn) {
+  assert_null(ppc_opcode_disasm_table[static_cast<int>(opcode)].disasm);
+  ppc_opcode_disasm_table[static_cast<int>(opcode)].disasm = fn;
+}
+
+}  // namespace ppc
+}  // namespace cpu
+}  // namespace xe
diff --git a/src/xenia/cpu/ppc/ppc_opcode_info.cc b/src/xenia/cpu/ppc/ppc_opcode_info.cc
new file mode 100644
index 000000000..00b90a6bc
--- /dev/null
+++ b/src/xenia/cpu/ppc/ppc_opcode_info.cc
@@ -0,0 +1,38 @@
+/**
+ ******************************************************************************
+ * Xenia : Xbox 360 Emulator Research Project                                 *
+ ******************************************************************************
+ * Copyright 2015 Ben Vanik. All rights reserved.                             *
+ * Released under the BSD license - see LICENSE in the root for more details. *
+ ******************************************************************************
+ */
+
+#include "xenia/cpu/ppc/ppc_opcode_info.h"
+
+#include "xenia/cpu/ppc/ppc_decode_data.h"
+
+namespace xe {
+namespace cpu {
+namespace ppc {
+
+bool DisasmPPC(uint32_t address, uint32_t code, StringBuffer* str) {
+  auto opcode = LookupOpcode(code);
+  if (opcode == PPCOpcode::kInvalid) {
+    str->Append("DISASM ERROR");
+    return false;
+  }
+  auto& disasm_info = GetOpcodeDisasmInfo(opcode);
+  if (disasm_info.disasm) {
+    PPCDecodeData d;
+    d.address = address;
+    d.code = code;
+    disasm_info.disasm(d, str);
+  } else {
+    str->AppendFormat("%-8s", disasm_info.name);
+  }
+  return true;
+}
+
+}  // namespace ppc
+}  // namespace cpu
+}  // namespace xe
diff --git a/src/xenia/cpu/ppc/ppc_opcode_info.h b/src/xenia/cpu/ppc/ppc_opcode_info.h
index 9ba6868a6..4bf99eb1a 100644
--- a/src/xenia/cpu/ppc/ppc_opcode_info.h
+++ b/src/xenia/cpu/ppc/ppc_opcode_info.h
@@ -1,4 +1,4 @@
-/**
+/**
  ******************************************************************************
  * Xenia : Xbox 360 Emulator Research Project                                 *
  ******************************************************************************
@@ -25,13 +25,23 @@ class PPCHIRBuilder;
 enum class PPCOpcodeFormat {
   kSC,
   kD,
+  kDS,
   kB,
   kI,
   kX,
   kXL,
   kXFX,
   kXFL,
+  kXS,
+  kXO,
+  kA,
+  kM,
+  kMD,
+  kMDS,
+  kDCBZ,
   kVX,
+  kVC,
+  kVA,
   kVX128,
   kVX128_1,
   kVX128_2,
@@ -40,18 +50,6 @@ enum class PPCOpcodeFormat {
   kVX128_5,
   kVX128_R,
   kVX128_P,
-  kVC,
-  kVA,
-  kXO,
-  kXW,
-  kA,
-  kDS,
-  kM,
-  kMD,
-  kMDS,
-  kMDSH,
-  kXS,
-  kDCBZ,
 };
 
 enum class PPCOpcodeGroup {
@@ -65,32 +63,97 @@ enum class PPCOpcodeType {
   kSync,
 };
 
-typedef void (*InstrDisasmFn1)(const InstrData* i, StringBuffer* str);
 typedef int (*InstrEmitFn)(PPCHIRBuilder& f, const InstrData& i);
 
 struct PPCOpcodeInfo {
+  PPCOpcodeType type;
+  InstrEmitFn emit;
+};
+
+struct PPCDecodeData;
+typedef void (*InstrDisasmFn)(const PPCDecodeData& d, StringBuffer* str);
+
+enum class PPCOpcodeField : uint32_t {
+  kRA,
+  kRA0,  // 0 if RA==0 else RA
+  kRB,
+  kRD,
+  kRS,  // alias for RD
+  kOE,
+  kOEcond,  // iff OE=1
+  kCR,
+  kCRcond,  // iff Rc=1
+  kCA,
+  kCRM,
+  kIMM,
+  kSIMM,
+  kUIMM,
+  kd,  // displacement
+  kds,
+  kLR,
+  kLRcond,
+  kADDR,
+  kBI,
+  kBO,
+  kCTR,
+  kCTRcond,
+  kL,
+  kLK,
+  kAA,
+  kCRFD,
+  kCRFS,
+  kCRBA,
+  kCRBB,
+  kCRBD,
+  kFPSCR,
+  kFPSCRD,
+  kMSR,
+  kSPR,
+  kVSCR,
+  kTBR,
+  kFM,
+  kFA,
+  kFB,
+  kFC,
+  kFD,
+  kFS,
+  kVA,
+  kVB,
+  kVC,
+  kVD,
+  kVS,
+  kSH,
+  kSHB,
+  kME,
+  kMB,
+  kTO,
+};
+
+struct PPCOpcodeDisasmInfo {
+  PPCOpcodeGroup group;
+  PPCOpcodeFormat format;
   uint32_t opcode;
   const char* name;
-  PPCOpcodeFormat format;
-  PPCOpcodeGroup group;
-  PPCOpcodeType type;
   const char* description;
-
-  InstrDisasmFn1 disasm;
-  InstrEmitFn emit;
+  std::vector<PPCOpcodeField> reads;
+  std::vector<PPCOpcodeField> writes;
+  InstrDisasmFn disasm;
 };
 
 PPCOpcode LookupOpcode(uint32_t code);
 
 const PPCOpcodeInfo& GetOpcodeInfo(PPCOpcode opcode);
+const PPCOpcodeDisasmInfo& GetOpcodeDisasmInfo(PPCOpcode opcode);
 
-void RegisterOpcodeDisasm(PPCOpcode opcode, InstrDisasmFn1 fn);
 void RegisterOpcodeEmitter(PPCOpcode opcode, InstrEmitFn fn);
+void RegisterOpcodeDisasm(PPCOpcode opcode, InstrDisasmFn fn);
 
 inline const PPCOpcodeInfo& LookupOpcodeInfo(uint32_t code) {
   return GetOpcodeInfo(LookupOpcode(code));
 }
 
+bool DisasmPPC(uint32_t address, uint32_t code, StringBuffer* str);
+
 }  // namespace ppc
 }  // namespace cpu
 }  // namespace xe
diff --git a/src/xenia/cpu/ppc/ppc_opcode_lookup.cc b/src/xenia/cpu/ppc/ppc_opcode_lookup.cc
index 27857665e..7591c3e62 100644
--- a/src/xenia/cpu/ppc/ppc_opcode_lookup.cc
+++ b/src/xenia/cpu/ppc/ppc_opcode_lookup.cc
@@ -371,7 +371,6 @@ PPCOpcode LookupOpcode(uint32_t code) {
       case 0b0100010110: PPC_DECODER_HIT(dcbt);
       case 0b0100010111: PPC_DECODER_HIT(lhzx);
       case 0b0100011100: PPC_DECODER_HIT(eqvx);
-      case 0b0100110110: PPC_DECODER_HIT(eciwx);
       case 0b0100110111: PPC_DECODER_HIT(lhzux);
       case 0b0100111100: PPC_DECODER_HIT(xorx);
       case 0b0101010011: PPC_DECODER_HIT(mfspr);
@@ -383,7 +382,6 @@ PPCOpcode LookupOpcode(uint32_t code) {
       case 0b0101110111: PPC_DECODER_HIT(lhaux);
       case 0b0110010111: PPC_DECODER_HIT(sthx);
       case 0b0110011100: PPC_DECODER_HIT(orcx);
-      case 0b0110110110: PPC_DECODER_HIT(ecowx);
       case 0b0110110111: PPC_DECODER_HIT(sthux);
       case 0b0110111100: PPC_DECODER_HIT(orx);
       case 0b0111010011: PPC_DECODER_HIT(mtspr);
diff --git a/src/xenia/cpu/ppc/ppc_opcode_table.cc b/src/xenia/cpu/ppc/ppc_opcode_table.cc
index 73245d029..1982d9161 100644
--- a/src/xenia/cpu/ppc/ppc_opcode_table.cc
+++ b/src/xenia/cpu/ppc/ppc_opcode_table.cc
@@ -10,477 +10,471 @@ namespace xe {
 namespace cpu {
 namespace ppc {
 
-#define INSTRUCTION(opcode, mnem, form, subform, group, type, desc) \
-    {opcode, mnem, PPCOpcodeFormat::form, PPCOpcodeGroup::group, PPCOpcodeType::type, desc, nullptr, nullptr}
+#define INSTRUCTION(opcode, mnem, form, group, type) \
+    {PPCOpcodeType::type, nullptr}
 PPCOpcodeInfo ppc_opcode_table[] = {
-  INSTRUCTION(0x7c000014, "addcx"       , kXO     , D_A_B_OE_Rc    , kI, kGeneral, "Add Carrying"                                                               ),
-  INSTRUCTION(0x7c000114, "addex"       , kXO     , D_A_B_OE_Rc    , kI, kGeneral, "Add Extended"                                                               ),
-  INSTRUCTION(0x38000000, "addi"        , kD      , D_A_SIMM       , kI, kGeneral, "Add Immediate"                                                              ),
-  INSTRUCTION(0x30000000, "addic"       , kD      , D_A_SIMM       , kI, kGeneral, "Add Immediate Carrying"                                                     ),
-  INSTRUCTION(0x34000000, "addicx"      , kD      , D_A_SIMM       , kI, kGeneral, "Add Immediate Carrying and Record"                                          ),
-  INSTRUCTION(0x3c000000, "addis"       , kD      , D_A_SIMM       , kI, kGeneral, "Add Immediate Shifted"                                                      ),
-  INSTRUCTION(0x7c0001d4, "addmex"      , kXO     , D_A_0_OE_Rc    , kI, kGeneral, "Add to Minus One Extended"                                                  ),
-  INSTRUCTION(0x7c000214, "addx"        , kXO     , D_A_B_OE_Rc    , kI, kGeneral, "Add"                                                                        ),
-  INSTRUCTION(0x7c000194, "addzex"      , kXO     , D_A_0_OE_Rc    , kI, kGeneral, "Add to Zero Extended"                                                       ),
-  INSTRUCTION(0x7c000078, "andcx"       , kX      , S_A_B_Rc       , kI, kGeneral, "AND with Complement"                                                        ),
-  INSTRUCTION(0x74000000, "andisx"      , kD      , S_A_UIMM       , kI, kGeneral, "AND Immediate Shifted"                                                      ),
-  INSTRUCTION(0x70000000, "andix"       , kD      , S_A_UIMM       , kI, kGeneral, "AND Immediate"                                                              ),
-  INSTRUCTION(0x7c000038, "andx"        , kX      , S_A_B_Rc       , kI, kGeneral, "AND"                                                                        ),
-  INSTRUCTION(0x4c000420, "bcctrx"      , kXL     , BO_BI_0_LK     , kI, kSync   , "Branch Conditional to Count Register"                                       ),
-  INSTRUCTION(0x4c000020, "bclrx"       , kXL     , BO_BI_0_LK     , kI, kSync   , "Branch Conditional to Link Register"                                        ),
-  INSTRUCTION(0x40000000, "bcx"         , kB      , BO_BI_BD_AA_LK , kI, kSync   , "Branch Conditional"                                                         ),
-  INSTRUCTION(0x48000000, "bx"          , kI      , LI_AA_LK       , kI, kSync   , "Branch"                                                                     ),
-  INSTRUCTION(0x7c000000, "cmp"         , kX      , crfD_L_A_B     , kI, kGeneral, "Compare"                                                                    ),
-  INSTRUCTION(0x2c000000, "cmpi"        , kD      , crfD_L_A_SIMM  , kI, kGeneral, "Compare Immediate"                                                          ),
-  INSTRUCTION(0x7c000040, "cmpl"        , kX      , crfD_L_A_B     , kI, kGeneral, "Compare Logical"                                                            ),
-  INSTRUCTION(0x28000000, "cmpli"       , kD      , crfD_L_A_UIMM  , kI, kGeneral, "Compare Logical Immediate"                                                  ),
-  INSTRUCTION(0x7c000074, "cntlzdx"     , kX      , S_A_0_Rc       , kI, kGeneral, "Count Leading Zeros Doubleword"                                             ),
-  INSTRUCTION(0x7c000034, "cntlzwx"     , kX      , S_A_0_Rc       , kI, kGeneral, "Count Leading Zeros Word"                                                   ),
-  INSTRUCTION(0x4c000202, "crand"       , kXL     , crbD_crbA_crbB , kI, kGeneral, "Condition Register AND"                                                     ),
-  INSTRUCTION(0x4c000102, "crandc"      , kXL     , crbD_crbA_crbB , kI, kGeneral, "Condition Register AND with Complement"                                     ),
-  INSTRUCTION(0x4c000242, "creqv"       , kXL     , crbD_crbA_crbB , kI, kGeneral, "Condition Register Equivalent"                                              ),
-  INSTRUCTION(0x4c0001c2, "crnand"      , kXL     , crbD_crbA_crbB , kI, kGeneral, "Condition Register NAND"                                                    ),
-  INSTRUCTION(0x4c000042, "crnor"       , kXL     , crbD_crbA_crbB , kI, kGeneral, "Condition Register NOR"                                                     ),
-  INSTRUCTION(0x4c000382, "cror"        , kXL     , crbD_crbA_crbB , kI, kGeneral, "Condition Register OR"                                                      ),
-  INSTRUCTION(0x4c000342, "crorc"       , kXL     , crbD_crbA_crbB , kI, kGeneral, "Condition Register OR with Complement"                                      ),
-  INSTRUCTION(0x4c000182, "crxor"       , kXL     , crbD_crbA_crbB , kI, kGeneral, "Condition Register XOR"                                                     ),
-  INSTRUCTION(0x7c0005ec, "dcba"        , kX      , _0_A_B         , kI, kGeneral, "Data Cache Block Allocate"                                                  ),
-  INSTRUCTION(0x7c0000ac, "dcbf"        , kX      , _0_A_B         , kI, kGeneral, "Data Cache Block Flush"                                                     ),
-  INSTRUCTION(0x7c0003ac, "dcbi"        , kX      , _0_A_B         , kI, kGeneral, "Data Cache Block Invalidate"                                                ),
-  INSTRUCTION(0x7c00006c, "dcbst"       , kX      , _0_A_B         , kI, kGeneral, "Data Cache Block Store"                                                     ),
-  INSTRUCTION(0x7c00022c, "dcbt"        , kX      , _0_A_B         , kI, kGeneral, "Data Cache Block Touch"                                                     ),
-  INSTRUCTION(0x7c0001ec, "dcbtst"      , kX      , _0_A_B         , kI, kGeneral, "Data Cache Block Touch for Store"                                           ),
-  INSTRUCTION(0x7c0007ec, "dcbz"        , kDCBZ   , _0_A_B         , kI, kGeneral, "Data Cache Block Clear to Zero"                                             ),
-  INSTRUCTION(0x7c2007ec, "dcbz128"     , kDCBZ   , _0_A_B         , kI, kGeneral, "Data Cache Block Clear to Zero 128"                                         ),
-  INSTRUCTION(0x7c000392, "divdux"      , kXO     , D_A_B_OE_Rc    , kI, kGeneral, "Divide Doubleword Unsigned"                                                 ),
-  INSTRUCTION(0x7c0003d2, "divdx"       , kXO     , D_A_B_OE_Rc    , kI, kGeneral, "Divide Doubleword"                                                          ),
-  INSTRUCTION(0x7c000396, "divwux"      , kXO     , D_A_B_OE_Rc    , kI, kGeneral, "Divide Word Unsigned"                                                       ),
-  INSTRUCTION(0x7c0003d6, "divwx"       , kXO     , D_A_B_OE_Rc    , kI, kGeneral, "Divide Word"                                                                ),
-  INSTRUCTION(0x7c00026c, "eciwx"       , kX      , D_A_B          , kI, kGeneral, "External Control In Word Indexed"                                           ),
-  INSTRUCTION(0x7c00036c, "ecowx"       , kX      , S_A_B          , kI, kGeneral, "External Control Out Word Indexed"                                          ),
-  INSTRUCTION(0x7c0006ac, "eieio"       , kX      , _0_0_0         , kI, kGeneral, "Enforce In-Order Execution of I/O"                                          ),
-  INSTRUCTION(0x7c000238, "eqvx"        , kX      , S_A_B_Rc       , kI, kGeneral, "Equivalent"                                                                 ),
-  INSTRUCTION(0x7c000774, "extsbx"      , kX      , S_A_0_Rc       , kI, kGeneral, "Extend Sign Byte"                                                           ),
-  INSTRUCTION(0x7c000734, "extshx"      , kX      , S_A_0_Rc       , kI, kGeneral, "Extend Sign Half Word"                                                      ),
-  INSTRUCTION(0x7c0007b4, "extswx"      , kX      , S_A_0_Rc       , kI, kGeneral, "Extend Sign Word"                                                           ),
-  INSTRUCTION(0xfc000210, "fabsx"       , kX      , D_0_B_Rc       , kF, kGeneral, "Floating Absolute Value"                                                    ),
-  INSTRUCTION(0xec00002a, "faddsx"      , kA      , D_A_B_0_Rc     , kF, kGeneral, "Floating Add Single"                                                        ),
-  INSTRUCTION(0xfc00002a, "faddx"       , kA      , D_A_B_0_Rc     , kF, kGeneral, "Floating Add"                                                               ),
-  INSTRUCTION(0xfc00069c, "fcfidx"      , kX      , D_A_B_Rc       , kF, kGeneral, "Floating Convert From Integer Doubleword"                                   ),
-  INSTRUCTION(0xfc000040, "fcmpo"       , kX      , crfD_A_B       , kF, kGeneral, "Floating Compare Ordered"                                                   ),
-  INSTRUCTION(0xfc000000, "fcmpu"       , kX      , crfD_A_B       , kF, kGeneral, "Floating Compare Unordered"                                                 ),
-  INSTRUCTION(0xfc00065c, "fctidx"      , kX      , D_0_B_Rc       , kF, kGeneral, "Floating Convert to Integer Doubleword"                                     ),
-  INSTRUCTION(0xfc00065e, "fctidzx"     , kX      , D_0_B_Rc       , kF, kGeneral, "Floating Convert to Integer Doubleword with Round Toward Zero"              ),
-  INSTRUCTION(0xfc00001c, "fctiwx"      , kX      , D_0_B_Rc       , kF, kGeneral, "Floating Convert to Integer Word"                                           ),
-  INSTRUCTION(0xfc00001e, "fctiwzx"     , kX      , D_0_B_Rc       , kF, kGeneral, "Floating Convert to Integer Word with Round Toward Zero"                    ),
-  INSTRUCTION(0xec000024, "fdivsx"      , kA      , D_A_B_0_Rc     , kF, kGeneral, "Floating Divide Single"                                                     ),
-  INSTRUCTION(0xfc000024, "fdivx"       , kA      , D_A_B_0_Rc     , kF, kGeneral, "Floating Divide"                                                            ),
-  INSTRUCTION(0xec00003a, "fmaddsx"     , kA      , D_A_B_C_Rc     , kF, kGeneral, "Floating Multiply-Add Single"                                               ),
-  INSTRUCTION(0xfc00003a, "fmaddx"      , kA      , D_A_B_C_Rc     , kF, kGeneral, "Floating Multiply-Add"                                                      ),
-  INSTRUCTION(0xfc000090, "fmrx"        , kX      , D_0_B_Rc       , kF, kGeneral, "Floating Move Register"                                                     ),
-  INSTRUCTION(0xec000038, "fmsubsx"     , kA      , D_A_B_C_Rc     , kF, kGeneral, "Floating Multiply-Subtract Single"                                          ),
-  INSTRUCTION(0xfc000038, "fmsubx"      , kA      , D_A_B_C_Rc     , kF, kGeneral, "Floating Multiply-Subtract"                                                 ),
-  INSTRUCTION(0xec000032, "fmulsx"      , kA      , D_A_0_C_Rc     , kF, kGeneral, "Floating Multiply Single"                                                   ),
-  INSTRUCTION(0xfc000032, "fmulx"       , kA      , D_A_0_C_Rc     , kF, kGeneral, "Floating Multiply"                                                          ),
-  INSTRUCTION(0xfc000110, "fnabsx"      , kX      , D_0_B_Rc       , kF, kGeneral, "Floating Negative Absolute Value"                                           ),
-  INSTRUCTION(0xfc000050, "fnegx"       , kX      , D_0_B_Rc       , kF, kGeneral, "Floating Negate"                                                            ),
-  INSTRUCTION(0xec00003e, "fnmaddsx"    , kA      , D_A_B_C_Rc     , kF, kGeneral, "Floating Negative Multiply-Add Single"                                      ),
-  INSTRUCTION(0xfc00003e, "fnmaddx"     , kA      , D_A_B_C_Rc     , kF, kGeneral, "Floating Negative Multiply-Add"                                             ),
-  INSTRUCTION(0xec00003c, "fnmsubsx"    , kA      , D_A_B_C_Rc     , kF, kGeneral, "Floating Negative Multiply-Subtract Single"                                 ),
-  INSTRUCTION(0xfc00003c, "fnmsubx"     , kA      , D_A_B_C_Rc     , kF, kGeneral, "Floating Negative Multiply-Subtract"                                        ),
-  INSTRUCTION(0xec000030, "fresx"       , kA      , D_0_B_0_Rc     , kF, kGeneral, "Floating Reciprocal Estimate Single"                                        ),
-  INSTRUCTION(0xfc000018, "frspx"       , kX      , D_0_B_Rc       , kF, kGeneral, "Floating Round to Single"                                                   ),
-  INSTRUCTION(0xfc000034, "frsqrtex"    , kA      , D_0_B_0_Rc     , kF, kGeneral, "Floating Reciprocal Square Root Estimate"                                   ),
-  INSTRUCTION(0xfc00002e, "fselx"       , kA      , D_A_B_C_Rc     , kF, kGeneral, "Floating Select"                                                            ),
-  INSTRUCTION(0xec00002c, "fsqrtsx"     , kA      , D_0_B_0_Rc     , kF, kGeneral, "Floating Square Root Single"                                                ),
-  INSTRUCTION(0xfc00002c, "fsqrtx"      , kA      , D_0_B_0_Rc     , kF, kGeneral, "Floating Square Root"                                                       ),
-  INSTRUCTION(0xec000028, "fsubsx"      , kA      , D_A_B_0_Rc     , kF, kGeneral, "Floating Subtract Single"                                                   ),
-  INSTRUCTION(0xfc000028, "fsubx"       , kA      , D_A_B_0_Rc     , kF, kGeneral, "Floating Subtract"                                                          ),
-  INSTRUCTION(0x7c0007ac, "icbi"        , kX      , _0_A_B         , kI, kGeneral, "Instruction Cache Block Invalidate"                                         ),
-  INSTRUCTION(0x4c00012c, "isync"       , kXL     , _0_0_0         , kI, kGeneral, "Instruction Synchronize"                                                    ),
-  INSTRUCTION(0x88000000, "lbz"         , kD      , D_A_d          , kI, kGeneral, "Load Byte and Zero"                                                         ),
-  INSTRUCTION(0x8c000000, "lbzu"        , kD      , D_A_d          , kI, kGeneral, "Load Byte and Zero with Update"                                             ),
-  INSTRUCTION(0x7c0000ee, "lbzux"       , kX      , D_A_B          , kI, kGeneral, "Load Byte and Zero with Update Indexed"                                     ),
-  INSTRUCTION(0x7c0000ae, "lbzx"        , kX      , D_A_B          , kI, kGeneral, "Load Byte and Zero Indexed"                                                 ),
-  INSTRUCTION(0xe8000000, "ld"          , kDS     , D_A_d          , kI, kGeneral, "Load Doubleword"                                                            ),
-  INSTRUCTION(0x7c0000a8, "ldarx"       , kX      , D_A_B          , kI, kGeneral, "Load Doubleword and Reserve Indexed"                                        ),
-  INSTRUCTION(0x7c000428, "ldbrx"       , kX      , D_A_B          , kI, kGeneral, "Load Doubleword Byte-Reverse Indexed"                                       ),
-  INSTRUCTION(0xe8000001, "ldu"         , kDS     , D_A_d          , kI, kGeneral, "Load Doubleword with Update"                                                ),
-  INSTRUCTION(0x7c00006a, "ldux"        , kX      , D_A_B          , kI, kGeneral, "Load Doubleword with Update Indexed"                                        ),
-  INSTRUCTION(0x7c00002a, "ldx"         , kX      , D_A_B          , kI, kGeneral, "Load Doubleword Indexed"                                                    ),
-  INSTRUCTION(0xc8000000, "lfd"         , kD      , D_A_d          , kF, kGeneral, "Load Floating-Point Double"                                                 ),
-  INSTRUCTION(0xcc000000, "lfdu"        , kD      , D_A_d          , kF, kGeneral, "Load Floating-Point Double with Update"                                     ),
-  INSTRUCTION(0x7c0004ee, "lfdux"       , kX      , D_A_B          , kF, kGeneral, "Load Floating-Point Double with Update Indexed"                             ),
-  INSTRUCTION(0x7c0004ae, "lfdx"        , kX      , D_A_B          , kF, kGeneral, "Load Floating-Point Double Indexed"                                         ),
-  INSTRUCTION(0xc0000000, "lfs"         , kD      , D_A_d          , kF, kGeneral, "Load Floating-Point Single"                                                 ),
-  INSTRUCTION(0xc4000000, "lfsu"        , kD      , D_A_d          , kF, kGeneral, "Load Floating-Point Single with Update"                                     ),
-  INSTRUCTION(0x7c00046e, "lfsux"       , kX      , D_A_B          , kF, kGeneral, "Load Floating-Point Single with Update Indexed"                             ),
-  INSTRUCTION(0x7c00042e, "lfsx"        , kX      , D_A_B          , kF, kGeneral, "Load Floating-Point Single Indexed"                                         ),
-  INSTRUCTION(0xa8000000, "lha"         , kD      , D_A_d          , kI, kGeneral, "Load Half Word Algebraic"                                                   ),
-  INSTRUCTION(0xac000000, "lhau"        , kD      , D_A_d          , kI, kGeneral, "Load Half Word Algebraic with Update"                                       ),
-  INSTRUCTION(0x7c0002ee, "lhaux"       , kX      , D_A_B          , kI, kGeneral, "Load Half Word Algebraic with Update Indexed"                               ),
-  INSTRUCTION(0x7c0002ae, "lhax"        , kX      , D_A_B          , kI, kGeneral, "Load Half Word Algebraic Indexed"                                           ),
-  INSTRUCTION(0x7c00062c, "lhbrx"       , kX      , D_A_B          , kI, kGeneral, "Load Half Word Byte-Reverse Indexed"                                        ),
-  INSTRUCTION(0xa0000000, "lhz"         , kD      , D_A_d          , kI, kGeneral, "Load Half Word and Zero"                                                    ),
-  INSTRUCTION(0xa4000000, "lhzu"        , kD      , D_A_d          , kI, kGeneral, "Load Half Word and Zero with Update"                                        ),
-  INSTRUCTION(0x7c00026e, "lhzux"       , kX      , D_A_B          , kI, kGeneral, "Load Half Word and Zero with Update Indexed"                                ),
-  INSTRUCTION(0x7c00022e, "lhzx"        , kX      , D_A_B          , kI, kGeneral, "Load Half Word and Zero Indexed"                                            ),
-  INSTRUCTION(0xb8000000, "lmw"         , kD      , D_A_d          , kI, kGeneral, "Load Multiple Word"                                                         ),
-  INSTRUCTION(0x7c0004aa, "lswi"        , kX      , D_A_NB         , kI, kGeneral, "Load String Word Immediate"                                                 ),
-  INSTRUCTION(0x7c00042a, "lswx"        , kX      , D_A_B          , kI, kGeneral, "Load String Word Indexed"                                                   ),
-  INSTRUCTION(0x7c00000e, "lvebx"       , kX      , D_A_B          , kV, kGeneral, "Load Vector Element Byte Indexed"                                           ),
-  INSTRUCTION(0x7c00004e, "lvehx"       , kX      , D_A_B          , kV, kGeneral, "Load Vector Element Half Word Indexed"                                      ),
-  INSTRUCTION(0x7c00008e, "lvewx"       , kX      , D_A_B          , kV, kGeneral, "Load Vector Element Word Indexed"                                           ),
-  INSTRUCTION(0x10000083, "lvewx128"    , kVX128_1, D_A_B          , kV, kGeneral, "Load Vector Element Word Indexed 128"                                       ),
-  INSTRUCTION(0x7c00040e, "lvlx"        , kX      , D_A_B          , kV, kGeneral, "Load Vector Left Indexed"                                                   ),
-  INSTRUCTION(0x10000403, "lvlx128"     , kVX128_1, D_A_B          , kV, kGeneral, "Load Vector Left Indexed 128"                                               ),
-  INSTRUCTION(0x7c00060e, "lvlxl"       , kX      , D_A_B          , kV, kGeneral, "Load Vector Left Indexed LRU"                                               ),
-  INSTRUCTION(0x10000603, "lvlxl128"    , kVX128_1, D_A_B          , kV, kGeneral, "Load Vector Left Indexed LRU 128"                                           ),
-  INSTRUCTION(0x7c00044e, "lvrx"        , kX      , D_A_B          , kV, kGeneral, "Load Vector Right Indexed"                                                  ),
-  INSTRUCTION(0x10000443, "lvrx128"     , kVX128_1, D_A_B          , kV, kGeneral, "Load Vector Right Indexed 128"                                              ),
-  INSTRUCTION(0x7c00064e, "lvrxl"       , kX      , D_A_B          , kV, kGeneral, "Load Vector Right Indexed LRU"                                              ),
-  INSTRUCTION(0x10000643, "lvrxl128"    , kVX128_1, D_A_B          , kV, kGeneral, "Load Vector Right Indexed LRU 128"                                          ),
-  INSTRUCTION(0x7c00000c, "lvsl"        , kX      , D_A_B          , kV, kGeneral, "Load Vector for Shift Left Indexed"                                         ),
-  INSTRUCTION(0x10000003, "lvsl128"     , kVX128_1, D_A_B          , kV, kGeneral, "Load Vector for Shift Left Indexed 128"                                     ),
-  INSTRUCTION(0x7c00004c, "lvsr"        , kX      , D_A_B          , kV, kGeneral, "Load Vector for Shift Right Indexed"                                        ),
-  INSTRUCTION(0x10000043, "lvsr128"     , kVX128_1, D_A_B          , kV, kGeneral, "Load Vector for Shift Right Indexed 128"                                    ),
-  INSTRUCTION(0x7c0000ce, "lvx"         , kX      , D_A_B          , kV, kGeneral, "Load Vector Indexed"                                                        ),
-  INSTRUCTION(0x100000c3, "lvx128"      , kVX128_1, D_A_B          , kV, kGeneral, "Load Vector Indexed 128"                                                    ),
-  INSTRUCTION(0x7c0002ce, "lvxl"        , kX      , D_A_B          , kV, kGeneral, "Load Vector Indexed LRU"                                                    ),
-  INSTRUCTION(0x100002c3, "lvxl128"     , kVX128_1, D_A_B          , kV, kGeneral, "Load Vector Indexed LRU 128"                                                ),
-  INSTRUCTION(0xe8000002, "lwa"         , kDS     , D_A_d          , kI, kGeneral, "Load Word Algebraic"                                                        ),
-  INSTRUCTION(0x7c000028, "lwarx"       , kX      , D_A_B          , kI, kGeneral, "Load Word and Reserve Indexed"                                              ),
-  INSTRUCTION(0x7c0002ea, "lwaux"       , kX      , D_A_B          , kI, kGeneral, "Load Word Algebraic with Update Indexed"                                    ),
-  INSTRUCTION(0x7c0002aa, "lwax"        , kX      , D_A_B          , kI, kGeneral, "Load Word Algebraic Indexed"                                                ),
-  INSTRUCTION(0x7c00042c, "lwbrx"       , kX      , D_A_B          , kI, kGeneral, "Load Word Byte-Reverse Indexed"                                             ),
-  INSTRUCTION(0x80000000, "lwz"         , kD      , D_A_d          , kI, kGeneral, "Load Word and Zero"                                                         ),
-  INSTRUCTION(0x84000000, "lwzu"        , kD      , D_A_d          , kI, kGeneral, "Load Word and Zero with Update"                                             ),
-  INSTRUCTION(0x7c00006e, "lwzux"       , kX      , D_A_B          , kI, kGeneral, "Load Word and Zero with Update Indexed"                                     ),
-  INSTRUCTION(0x7c00002e, "lwzx"        , kX      , D_A_B          , kI, kGeneral, "Load Word and Zero Indexed"                                                 ),
-  INSTRUCTION(0x4c000000, "mcrf"        , kXL     , crfD_crfS_0    , kI, kGeneral, "Move Condition Register Field"                                              ),
-  INSTRUCTION(0xfc000080, "mcrfs"       , kX      , crfD_crfS_0    , kF, kGeneral, "Move to Condition Register from FPSCR"                                      ),
-  INSTRUCTION(0x7c000400, "mcrxr"       , kX      , crfD_0_0       , kI, kGeneral, "Move to Condition Register from XER"                                        ),
-  INSTRUCTION(0x7c000026, "mfcr"        , kX      , D_0_0          , kI, kGeneral, "Move from Condition Register"                                               ),
-  INSTRUCTION(0xfc00048e, "mffsx"       , kX      , D_0_0_Rc       , kF, kGeneral, "Move from FPSCR"                                                            ),
-  INSTRUCTION(0x7c0000a6, "mfmsr"       , kX      , D_0_0          , kI, kGeneral, "Move from Machine State Register"                                           ),
-  INSTRUCTION(0x7c0002a6, "mfspr"       , kXFX    , D_spr          , kI, kGeneral, "Move from Special-Purpose Register"                                         ),
-  INSTRUCTION(0x7c0002e6, "mftb"        , kXFX    , D_tbr          , kI, kGeneral, "Move from Time Base"                                                        ),
-  INSTRUCTION(0x10000604, "mfvscr"      , kVX     , D_0_0          , kI, kGeneral, "Move from VSCR"                                                             ),
-  INSTRUCTION(0x7c000120, "mtcrf"       , kXFX    , S_CRM          , kI, kGeneral, "Move to Condition Register Fields"                                          ),
-  INSTRUCTION(0xfc00008c, "mtfsb0x"     , kX      , crbD_0_0_Rc    , kF, kGeneral, "Move to FPSCR Bit 0"                                                        ),
-  INSTRUCTION(0xfc00004c, "mtfsb1x"     , kX      , crbD_0_0_Rc    , kF, kGeneral, "Move to FPSCR Bit 1"                                                        ),
-  INSTRUCTION(0xfc00010c, "mtfsfix"     , kX      , crfD_0_IMM_Rc  , kF, kGeneral, "Move to FPSCR Field Immediate"                                              ),
-  INSTRUCTION(0xfc00058e, "mtfsfx"      , kXFL    , FM_B_Rc        , kF, kGeneral, "Move to FPSCR Fields"                                                       ),
-  INSTRUCTION(0x7c000124, "mtmsr"       , kX      , S_0_0          , kI, kGeneral, "Move to Machine State Register"                                             ),
-  INSTRUCTION(0x7c000164, "mtmsrd"      , kX      , S_0_0          , kI, kGeneral, "Move to Machine State Register Doubleword"                                  ),
-  INSTRUCTION(0x7c0003a6, "mtspr"       , kXFX    , S_spr          , kI, kGeneral, "Move to Special-Purpose Register"                                           ),
-  INSTRUCTION(0x10000644, "mtvscr"      , kVX     , S_0_0          , kI, kGeneral, "Move to VSCR"                                                               ),
-  INSTRUCTION(0x7c000012, "mulhdux"     , kXO     , D_A_B_Rc       , kI, kGeneral, "Multiply High Doubleword Unsigned"                                          ),
-  INSTRUCTION(0x7c000092, "mulhdx"      , kXO     , D_A_B_Rc       , kI, kGeneral, "Multiply High Doubleword"                                                   ),
-  INSTRUCTION(0x7c000016, "mulhwux"     , kXO     , D_A_B_Rc       , kI, kGeneral, "Multiply High Word Unsigned"                                                ),
-  INSTRUCTION(0x7c000096, "mulhwx"      , kXO     , D_A_B_Rc       , kI, kGeneral, "Multiply High Word"                                                         ),
-  INSTRUCTION(0x7c0001d2, "mulldx"      , kXO     , D_A_B_OE_Rc    , kI, kGeneral, "Multiply Low Doubleword"                                                    ),
-  INSTRUCTION(0x1c000000, "mulli"       , kD      , D_A_SIMM       , kI, kGeneral, "Multiply Low Immediate"                                                     ),
-  INSTRUCTION(0x7c0001d6, "mullwx"      , kXO     , D_A_B_OE_Rc    , kI, kGeneral, "Multiply Low Word"                                                          ),
-  INSTRUCTION(0x7c0003b8, "nandx"       , kX      , S_A_B_Rc       , kI, kGeneral, "NAND"                                                                       ),
-  INSTRUCTION(0x7c0000d0, "negx"        , kXO     , D_A_0_OE_Rc    , kI, kGeneral, "Negate"                                                                     ),
-  INSTRUCTION(0x7c0000f8, "norx"        , kX      , S_A_B_Rc       , kI, kGeneral, "NOR"                                                                        ),
-  INSTRUCTION(0x7c000338, "orcx"        , kX      , S_A_B_Rc       , kI, kGeneral, "OR with Complement"                                                         ),
-  INSTRUCTION(0x60000000, "ori"         , kD      , S_A_UIMM       , kI, kGeneral, "OR Immediate"                                                               ),
-  INSTRUCTION(0x64000000, "oris"        , kD      , S_A_UIMM       , kI, kGeneral, "OR Immediate Shifted"                                                       ),
-  INSTRUCTION(0x7c000378, "orx"         , kX      , S_A_B_Rc       , kI, kGeneral, "OR"                                                                         ),
-  INSTRUCTION(0x78000010, "rldclx"      , kMDS    , S_A_B_MB_ME_Rc , kI, kGeneral, "Rotate Left Doubleword then Clear Left"                                     ),
-  INSTRUCTION(0x78000012, "rldcrx"      , kMDS    , S_A_B_MB_ME_Rc , kI, kGeneral, "Rotate Left Doubleword then Clear Right"                                    ),
-  INSTRUCTION(0x78000000, "rldiclx"     , kMDSH   , S_A_SH_MB_ME_Rc, kI, kGeneral, "Rotate Left Doubleword Immediate then Clear Left"                           ),
-  INSTRUCTION(0x78000004, "rldicrx"     , kMDSH   , S_A_SH_MB_ME_Rc, kI, kGeneral, "Rotate Left Doubleword Immediate then Clear Right"                          ),
-  INSTRUCTION(0x78000008, "rldicx"      , kMDSH   , S_A_SH_MB_ME_Rc, kI, kGeneral, "Rotate Left Doubleword Immediate then Clear"                                ),
-  INSTRUCTION(0x7800000c, "rldimix"     , kMDSH   , S_A_SH_MB_ME_Rc, kI, kGeneral, "Rotate Left Doubleword Immediate then Mask Insert"                          ),
-  INSTRUCTION(0x50000000, "rlwimix"     , kM      , S_A_SH_MB_ME_Rc, kI, kGeneral, "Rotate Left Word Immediate then Mask Insert"                                ),
-  INSTRUCTION(0x54000000, "rlwinmx"     , kM      , S_A_SH_MB_ME_Rc, kI, kGeneral, "Rotate Left Word Immediate then AND with Mask"                              ),
-  INSTRUCTION(0x5c000000, "rlwnmx"      , kM      , S_A_SH_MB_ME_Rc, kI, kGeneral, "Rotate Left Word then AND with Mask"                                        ),
-  INSTRUCTION(0x44000002, "sc"          , kSC     , sc             , kI, kSync   , "System Call"                                                                ),
-  INSTRUCTION(0x7c000036, "sldx"        , kX      , S_A_B_Rc       , kI, kGeneral, "Shift Left Doubleword"                                                      ),
-  INSTRUCTION(0x7c000030, "slwx"        , kX      , S_A_B_Rc       , kI, kGeneral, "Shift Left Word"                                                            ),
-  INSTRUCTION(0x7c000674, "sradix"      , kXS     , S_A_SH_Rc      , kI, kGeneral, "Shift Right Algebraic Doubleword Immediate"                                 ),
-  INSTRUCTION(0x7c000634, "sradx"       , kX      , S_A_B_Rc       , kI, kGeneral, "Shift Right Algebraic Doubleword"                                           ),
-  INSTRUCTION(0x7c000670, "srawix"      , kX      , S_A_SH_Rc      , kI, kGeneral, "Shift Right Algebraic Word Immediate"                                       ),
-  INSTRUCTION(0x7c000630, "srawx"       , kX      , S_A_B_Rc       , kI, kGeneral, "Shift Right Algebraic Word"                                                 ),
-  INSTRUCTION(0x7c000436, "srdx"        , kX      , S_A_B_Rc       , kI, kGeneral, "Shift Right Doubleword"                                                     ),
-  INSTRUCTION(0x7c000430, "srwx"        , kX      , S_A_B_Rc       , kI, kGeneral, "Shift Right Word"                                                           ),
-  INSTRUCTION(0x98000000, "stb"         , kD      , S_A_d          , kI, kGeneral, "Store Byte"                                                                 ),
-  INSTRUCTION(0x9c000000, "stbu"        , kD      , S_A_d          , kI, kGeneral, "Store Byte with Update"                                                     ),
-  INSTRUCTION(0x7c0001ee, "stbux"       , kX      , S_A_B          , kI, kGeneral, "Store Byte with Update Indexed"                                             ),
-  INSTRUCTION(0x7c0001ae, "stbx"        , kX      , S_A_B          , kI, kGeneral, "Store Byte Indexed"                                                         ),
-  INSTRUCTION(0xf8000000, "std"         , kDS     , S_A_d          , kI, kGeneral, "Store Doubleword"                                                           ),
-  INSTRUCTION(0x7c000528, "stdbrx"      , kX      , S_A_B          , kI, kGeneral, "Store Doubleword Byte-Reverse Indexed"                                      ),
-  INSTRUCTION(0x7c0001ad, "stdcx"       , kX      , S_A_B_1        , kI, kGeneral, "Store Doubleword Conditional Indexed"                                       ),
-  INSTRUCTION(0xf8000001, "stdu"        , kDS     , S_A_d          , kI, kGeneral, "Store Doubleword with Update"                                               ),
-  INSTRUCTION(0x7c00016a, "stdux"       , kX      , S_A_B          , kI, kGeneral, "Store Doubleword with Update Indexed"                                       ),
-  INSTRUCTION(0x7c00012a, "stdx"        , kX      , S_A_B          , kI, kGeneral, "Store Doubleword Indexed"                                                   ),
-  INSTRUCTION(0xd8000000, "stfd"        , kD      , S_A_d          , kF, kGeneral, "Store Floating-Point Double"                                                ),
-  INSTRUCTION(0xdc000000, "stfdu"       , kD      , S_A_d          , kF, kGeneral, "Store Floating-Point Double with Update"                                    ),
-  INSTRUCTION(0x7c0005ee, "stfdux"      , kX      , S_A_B          , kF, kGeneral, "Store Floating-Point Double with Update Indexed"                            ),
-  INSTRUCTION(0x7c0005ae, "stfdx"       , kX      , S_A_B          , kF, kGeneral, "Store Floating-Point Double Indexed"                                        ),
-  INSTRUCTION(0x7c0007ae, "stfiwx"      , kX      , S_A_B          , kF, kGeneral, "Store Floating-Point as Integer Word Indexed"                               ),
-  INSTRUCTION(0xd0000000, "stfs"        , kD      , S_A_d          , kF, kGeneral, "Store Floating-Point Single"                                                ),
-  INSTRUCTION(0xd4000000, "stfsu"       , kD      , S_A_d          , kF, kGeneral, "Store Floating-Point Single with Update"                                    ),
-  INSTRUCTION(0x7c00056e, "stfsux"      , kX      , S_A_B          , kF, kGeneral, "Store Floating-Point Single with Update Indexed"                            ),
-  INSTRUCTION(0x7c00052e, "stfsx"       , kX      , S_A_B          , kF, kGeneral, "Store Floating-Point Single Indexed"                                        ),
-  INSTRUCTION(0xb0000000, "sth"         , kD      , S_A_d          , kI, kGeneral, "Store Half Word"                                                            ),
-  INSTRUCTION(0x7c00072c, "sthbrx"      , kX      , S_A_B          , kI, kGeneral, "Store Half Word Byte-Reverse Indexed"                                       ),
-  INSTRUCTION(0xb4000000, "sthu"        , kD      , S_A_d          , kI, kGeneral, "Store Half Word with Update"                                                ),
-  INSTRUCTION(0x7c00036e, "sthux"       , kX      , S_A_B          , kI, kGeneral, "Store Half Word with Update Indexed"                                        ),
-  INSTRUCTION(0x7c00032e, "sthx"        , kX      , S_A_B          , kI, kGeneral, "Store Half Word Indexed"                                                    ),
-  INSTRUCTION(0xbc000000, "stmw"        , kD      , S_A_d          , kI, kGeneral, "Store Multiple Word"                                                        ),
-  INSTRUCTION(0x7c0005aa, "stswi"       , kX      , S_A_NB         , kI, kGeneral, "Store String Word Immediate"                                                ),
-  INSTRUCTION(0x7c00052a, "stswx"       , kX      , S_A_B          , kI, kGeneral, "Store String Word Indexed"                                                  ),
-  INSTRUCTION(0x7c00010e, "stvebx"      , kX      , S_A_B          , kV, kGeneral, "Store Vector Element Byte Indexed"                                          ),
-  INSTRUCTION(0x7c00014e, "stvehx"      , kX      , S_A_B          , kV, kGeneral, "Store Vector Element Half Word Indexed"                                     ),
-  INSTRUCTION(0x7c00018e, "stvewx"      , kX      , S_A_B          , kV, kGeneral, "Store Vector Element Word Indexed"                                          ),
-  INSTRUCTION(0x10000183, "stvewx128"   , kVX128_1, S_A_B          , kV, kGeneral, "Store Vector Element Word Indexed 128"                                      ),
-  INSTRUCTION(0x7c00050e, "stvlx"       , kX      , S_A_B          , kV, kGeneral, "Store Vector Left Indexed"                                                  ),
-  INSTRUCTION(0x10000503, "stvlx128"    , kVX128_1, S_A_B          , kV, kGeneral, "Store Vector Left Indexed 128"                                              ),
-  INSTRUCTION(0x7c00070e, "stvlxl"      , kX      , S_A_B          , kV, kGeneral, "Store Vector Left Indexed LRU"                                              ),
-  INSTRUCTION(0x10000703, "stvlxl128"   , kVX128_1, S_A_B          , kV, kGeneral, "Store Vector Left Indexed LRU 128"                                          ),
-  INSTRUCTION(0x7c00054e, "stvrx"       , kX      , S_A_B          , kV, kGeneral, "Store Vector Right Indexed"                                                 ),
-  INSTRUCTION(0x10000543, "stvrx128"    , kVX128_1, S_A_B          , kV, kGeneral, "Store Vector Right Indexed 128"                                             ),
-  INSTRUCTION(0x7c00074e, "stvrxl"      , kX      , S_A_B          , kV, kGeneral, "Store Vector Right Indexed LRU"                                             ),
-  INSTRUCTION(0x10000743, "stvrxl128"   , kVX128_1, S_A_B          , kV, kGeneral, "Store Vector Right Indexed LRU 128"                                         ),
-  INSTRUCTION(0x7c0001ce, "stvx"        , kX      , S_A_B          , kV, kGeneral, "Store Vector Indexed"                                                       ),
-  INSTRUCTION(0x100001c3, "stvx128"     , kVX128_1, S_A_B          , kV, kGeneral, "Store Vector Indexed 128"                                                   ),
-  INSTRUCTION(0x7c0003ce, "stvxl"       , kX      , S_A_B          , kV, kGeneral, "Store Vector Indexed LRU"                                                   ),
-  INSTRUCTION(0x100003c3, "stvxl128"    , kVX128_1, S_A_B          , kV, kGeneral, "Store Vector Indexed LRU 128"                                               ),
-  INSTRUCTION(0x90000000, "stw"         , kD      , S_A_d          , kI, kGeneral, "Store Word"                                                                 ),
-  INSTRUCTION(0x7c00052c, "stwbrx"      , kX      , S_A_B          , kI, kGeneral, "Store Word Byte-Reverse Indexed"                                            ),
-  INSTRUCTION(0x7c00012d, "stwcx"       , kX      , S_A_B_1        , kI, kGeneral, "Store Word Conditional Indexed"                                             ),
-  INSTRUCTION(0x94000000, "stwu"        , kD      , S_A_d          , kI, kGeneral, "Store Word with Update"                                                     ),
-  INSTRUCTION(0x7c00016e, "stwux"       , kX      , S_A_B          , kI, kGeneral, "Store Word with Update Indexed"                                             ),
-  INSTRUCTION(0x7c00012e, "stwx"        , kX      , S_A_B          , kI, kGeneral, "Store Word Indexed"                                                         ),
-  INSTRUCTION(0x7c000010, "subfcx"      , kXO     , D_A_B_OE_Rc    , kI, kGeneral, "Subtract From Carrying"                                                     ),
-  INSTRUCTION(0x7c000110, "subfex"      , kXO     , D_A_B_OE_Rc    , kI, kGeneral, "Subtract From Extended"                                                     ),
-  INSTRUCTION(0x20000000, "subficx"     , kD      , D_A_SIMM       , kI, kGeneral, "Subtract From Immediate Carrying"                                           ),
-  INSTRUCTION(0x7c0001d0, "subfmex"     , kXO     , D_A_0_OE_Rc    , kI, kGeneral, "Subtract From Minus One Extended"                                           ),
-  INSTRUCTION(0x7c000050, "subfx"       , kXO     , D_A_B_OE_Rc    , kI, kGeneral, "Subtract From"                                                              ),
-  INSTRUCTION(0x7c000190, "subfzex"     , kXO     , D_A_0_OE_Rc    , kI, kGeneral, "Subtract From Zero Extended"                                                ),
-  INSTRUCTION(0x7c0004ac, "sync"        , kX      , _0_0_0         , kI, kGeneral, "Synchronize"                                                                ),
-  INSTRUCTION(0x7c000088, "td"          , kX      , TO_A_B         , kI, kGeneral, "Trap Doubleword"                                                            ),
-  INSTRUCTION(0x08000000, "tdi"         , kD      , TO_A_SIMM      , kI, kGeneral, "Trap Doubleword Immediate"                                                  ),
-  INSTRUCTION(0x7c000008, "tw"          , kX      , TO_A_B         , kI, kGeneral, "Trap Word"                                                                  ),
-  INSTRUCTION(0x0c000000, "twi"         , kD      , TO_A_SIMM      , kI, kGeneral, "Trap Word Immediate"                                                        ),
-  INSTRUCTION(0x10000180, "vaddcuw"     , kVX     , D_A_B          , kV, kGeneral, "Vector Add Carryout Unsigned Word"                                          ),
-  INSTRUCTION(0x1000000a, "vaddfp"      , kVX     , D_A_B          , kV, kGeneral, "Vector Add Floating Point"                                                  ),
-  INSTRUCTION(0x14000010, "vaddfp128"   , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Add Floating Point"                                               ),
-  INSTRUCTION(0x10000300, "vaddsbs"     , kVX     , D_A_B          , kV, kGeneral, "Vector Add Signed Byte Saturate"                                            ),
-  INSTRUCTION(0x10000340, "vaddshs"     , kVX     , D_A_B          , kV, kGeneral, "Vector Add Signed Half Word Saturate"                                       ),
-  INSTRUCTION(0x10000380, "vaddsws"     , kVX     , D_A_B          , kV, kGeneral, "Vector Add Signed Word Saturate"                                            ),
-  INSTRUCTION(0x10000000, "vaddubm"     , kVX     , D_A_B          , kV, kGeneral, "Vector Add Unsigned Byte Modulo"                                            ),
-  INSTRUCTION(0x10000200, "vaddubs"     , kVX     , D_A_B          , kV, kGeneral, "Vector Add Unsigned Byte Saturate"                                          ),
-  INSTRUCTION(0x10000040, "vadduhm"     , kVX     , D_A_B          , kV, kGeneral, "Vector Add Unsigned Half Word Modulo"                                       ),
-  INSTRUCTION(0x10000240, "vadduhs"     , kVX     , D_A_B          , kV, kGeneral, "Vector Add Unsigned Half Word Saturate"                                     ),
-  INSTRUCTION(0x10000080, "vadduwm"     , kVX     , D_A_B          , kV, kGeneral, "Vector Add Unsigned Word Modulo"                                            ),
-  INSTRUCTION(0x10000280, "vadduws"     , kVX     , D_A_B          , kV, kGeneral, "Vector Add Unsigned Word Saturate"                                          ),
-  INSTRUCTION(0x10000404, "vand"        , kVX     , D_A_B          , kV, kGeneral, "Vector Logical AND"                                                         ),
-  INSTRUCTION(0x14000210, "vand128"     , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Logical AND"                                                      ),
-  INSTRUCTION(0x10000444, "vandc"       , kVX     , D_A_B          , kV, kGeneral, "Vector Logical AND with Complement"                                         ),
-  INSTRUCTION(0x14000250, "vandc128"    , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Logical AND with Complement"                                      ),
-  INSTRUCTION(0x10000502, "vavgsb"      , kVX     , D_A_B          , kV, kGeneral, "Vector Average Signed Byte"                                                 ),
-  INSTRUCTION(0x10000542, "vavgsh"      , kVX     , D_A_B          , kV, kGeneral, "Vector Average Signed Half Word"                                            ),
-  INSTRUCTION(0x10000582, "vavgsw"      , kVX     , D_A_B          , kV, kGeneral, "Vector Average Signed Word"                                                 ),
-  INSTRUCTION(0x10000402, "vavgub"      , kVX     , D_A_B          , kV, kGeneral, "Vector Average Unsigned Byte"                                               ),
-  INSTRUCTION(0x10000442, "vavguh"      , kVX     , D_A_B          , kV, kGeneral, "Vector Average Unsigned Half Word"                                          ),
-  INSTRUCTION(0x10000482, "vavguw"      , kVX     , D_A_B          , kV, kGeneral, "Vector Average Unsigned Word"                                               ),
-  INSTRUCTION(0x18000230, "vcfpsxws128" , kVX128_3, D_B_SIMM       , kV, kGeneral, "Vector128 Convert From Floating-Point to Signed Fixed-Point Word Saturate"  ),
-  INSTRUCTION(0x18000270, "vcfpuxws128" , kVX128_3, D_B_UIMM       , kV, kGeneral, "Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate"),
-  INSTRUCTION(0x1000034a, "vcfsx"       , kVX     , D_A_B          , kV, kGeneral, "Vector Convert from Signed Fixed-Point Word"                                ),
-  INSTRUCTION(0x1000030a, "vcfux"       , kVX     , D_A_B          , kV, kGeneral, "Vector Convert from Unsigned Fixed-Point Word"                              ),
-  INSTRUCTION(0x100003c6, "vcmpbfp"     , kVC     , D_A_B          , kV, kGeneral, "Vector Compare Bounds Floating Point"                                       ),
-  INSTRUCTION(0x18000180, "vcmpbfp128"  , kVX128_R, D_A_B          , kV, kGeneral, "Vector128 Compare Bounds Floating Point"                                    ),
-  INSTRUCTION(0x100000c6, "vcmpeqfp"    , kVC     , D_A_B          , kV, kGeneral, "Vector Compare Equal-to Floating Point"                                     ),
-  INSTRUCTION(0x18000000, "vcmpeqfp128" , kVX128_R, D_A_B          , kV, kGeneral, "Vector128 Compare Equal-to Floating Point"                                  ),
-  INSTRUCTION(0x10000006, "vcmpequb"    , kVC     , D_A_B          , kV, kGeneral, "Vector Compare Equal-to Unsigned Byte"                                      ),
-  INSTRUCTION(0x10000046, "vcmpequh"    , kVC     , D_A_B          , kV, kGeneral, "Vector Compare Equal-to Unsigned Half Word"                                 ),
-  INSTRUCTION(0x10000086, "vcmpequw"    , kVC     , D_A_B          , kV, kGeneral, "Vector Compare Equal-to Unsigned Word"                                      ),
-  INSTRUCTION(0x18000200, "vcmpequw128" , kVX128_R, D_A_B          , kV, kGeneral, "Vector128 Compare Equal-to Unsigned Word"                                   ),
-  INSTRUCTION(0x100001c6, "vcmpgefp"    , kVC     , D_A_B          , kV, kGeneral, "Vector Compare Greater-Than-or-Equal-to Floating Point"                     ),
-  INSTRUCTION(0x18000080, "vcmpgefp128" , kVX128_R, D_A_B          , kV, kGeneral, "Vector128 Compare Greater-Than-or-Equal-to Floating Point"                  ),
-  INSTRUCTION(0x100002c6, "vcmpgtfp"    , kVC     , D_A_B          , kV, kGeneral, "Vector Compare Greater-Than Floating Point"                                 ),
-  INSTRUCTION(0x18000100, "vcmpgtfp128" , kVX128_R, D_A_B          , kV, kGeneral, "Vector128 Compare Greater-Than Floating-Point"                              ),
-  INSTRUCTION(0x10000306, "vcmpgtsb"    , kVC     , D_A_B          , kV, kGeneral, "Vector Compare Greater-Than Signed Byte"                                    ),
-  INSTRUCTION(0x10000346, "vcmpgtsh"    , kVC     , D_A_B          , kV, kGeneral, "Vector Compare Greater-Than Signed Half Word"                               ),
-  INSTRUCTION(0x10000386, "vcmpgtsw"    , kVC     , D_A_B          , kV, kGeneral, "Vector Compare Greater-Than Signed Word"                                    ),
-  INSTRUCTION(0x10000206, "vcmpgtub"    , kVC     , D_A_B          , kV, kGeneral, "Vector Compare Greater-Than Unsigned Byte"                                  ),
-  INSTRUCTION(0x10000246, "vcmpgtuh"    , kVC     , D_A_B          , kV, kGeneral, "Vector Compare Greater-Than Unsigned Half Word"                             ),
-  INSTRUCTION(0x10000286, "vcmpgtuw"    , kVC     , D_A_B          , kV, kGeneral, "Vector Compare Greater-Than Unsigned Word"                                  ),
-  INSTRUCTION(0x180002b0, "vcsxwfp128"  , kVX128_3, D_B_SIMM       , kV, kGeneral, "Vector128 Convert From Signed Fixed-Point Word to Floating-Point"           ),
-  INSTRUCTION(0x100003ca, "vctsxs"      , kVX     , D_A_B          , kV, kGeneral, "Vector Convert to Signed Fixed-Point Word Saturate"                         ),
-  INSTRUCTION(0x1000038a, "vctuxs"      , kVX     , D_A_B          , kV, kGeneral, "Vector Convert to Unsigned Fixed-Point Word Saturate"                       ),
-  INSTRUCTION(0x180002f0, "vcuxwfp128"  , kVX128_3, D_B_SIMM       , kV, kGeneral, "Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point"         ),
-  INSTRUCTION(0x1000018a, "vexptefp"    , kVX     , D_A_B          , kV, kGeneral, "Vector 2 Raised to the Exponent Estimate Floating Point"                    ),
-  INSTRUCTION(0x180006b0, "vexptefp128" , kVX128_3, D_B            , kV, kGeneral, "Vector128 Log2 Estimate Floating Point"                                     ),
-  INSTRUCTION(0x100001ca, "vlogefp"     , kVX     , D_A_B          , kV, kGeneral, "Vector Log2 Estimate Floating Point"                                        ),
-  INSTRUCTION(0x180006f0, "vlogefp128"  , kVX128_3, D_B            , kV, kGeneral, "Vector128 Log2 Estimate Floating Point"                                     ),
-  INSTRUCTION(0x14000110, "vmaddcfp128" , kVX128  , D_A_D_B        , kV, kGeneral, "Vector128 Multiply Add Floating Point"                                      ),
-  INSTRUCTION(0x1000002e, "vmaddfp"     , kVA     , D_A_B_C        , kV, kGeneral, "Vector Multiply-Add Floating Point"                                         ),
-  INSTRUCTION(0x140000d0, "vmaddfp128"  , kVX128  , D_A_D_B        , kV, kGeneral, "Vector128 Multiply Add Floating Point"                                      ),
-  INSTRUCTION(0x1000040a, "vmaxfp"      , kVX     , D_A_B          , kV, kGeneral, "Vector Maximum Floating Point"                                              ),
-  INSTRUCTION(0x18000280, "vmaxfp128"   , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Maximum Floating Point"                                           ),
-  INSTRUCTION(0x10000102, "vmaxsb"      , kVX     , D_A_B          , kV, kGeneral, "Vector Maximum Signed Byte"                                                 ),
-  INSTRUCTION(0x10000142, "vmaxsh"      , kVX     , D_A_B          , kV, kGeneral, "Vector Maximum Signed Half Word"                                            ),
-  INSTRUCTION(0x10000182, "vmaxsw"      , kVX     , D_A_B          , kV, kGeneral, "Vector Maximum Signed Word"                                                 ),
-  INSTRUCTION(0x10000002, "vmaxub"      , kVX     , D_A_B          , kV, kGeneral, "Vector Maximum Unsigned Byte"                                               ),
-  INSTRUCTION(0x10000042, "vmaxuh"      , kVX     , D_A_B          , kV, kGeneral, "Vector Maximum Unsigned Half Word"                                          ),
-  INSTRUCTION(0x10000082, "vmaxuw"      , kVX     , D_A_B          , kV, kGeneral, "Vector Maximum Unsigned Word"                                               ),
-  INSTRUCTION(0x10000020, "vmhaddshs"   , kVA     , D_A_B_C        , kV, kGeneral, "Vector Multiply-High and Add Signed Signed Half Word Saturate"              ),
-  INSTRUCTION(0x10000021, "vmhraddshs"  , kVA     , D_A_B_C        , kV, kGeneral, "Vector Multiply-High Round and Add Signed Signed Half Word Saturate"        ),
-  INSTRUCTION(0x1000044a, "vminfp"      , kVX     , D_A_B          , kV, kGeneral, "Vector Minimum Floating Point"                                              ),
-  INSTRUCTION(0x180002c0, "vminfp128"   , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Minimum Floating Point"                                           ),
-  INSTRUCTION(0x10000302, "vminsb"      , kVX     , D_A_B          , kV, kGeneral, "Vector Minimum Signed Byte"                                                 ),
-  INSTRUCTION(0x10000342, "vminsh"      , kVX     , D_A_B          , kV, kGeneral, "Vector Minimum Signed Half Word"                                            ),
-  INSTRUCTION(0x10000382, "vminsw"      , kVX     , D_A_B          , kV, kGeneral, "Vector Minimum Signed Word"                                                 ),
-  INSTRUCTION(0x10000202, "vminub"      , kVX     , D_A_B          , kV, kGeneral, "Vector Minimum Unsigned Byte"                                               ),
-  INSTRUCTION(0x10000242, "vminuh"      , kVX     , D_A_B          , kV, kGeneral, "Vector Minimum Unsigned Half Word"                                          ),
-  INSTRUCTION(0x10000282, "vminuw"      , kVX     , D_A_B          , kV, kGeneral, "Vector Minimum Unsigned Word"                                               ),
-  INSTRUCTION(0x10000022, "vmladduhm"   , kVA     , D_A_B_C        , kV, kGeneral, "Vector Multiply-Low and Add Unsigned Half Word Modulo"                      ),
-  INSTRUCTION(0x1000000c, "vmrghb"      , kVX     , D_A_B          , kV, kGeneral, "Vector Merge High Byte"                                                     ),
-  INSTRUCTION(0x1000004c, "vmrghh"      , kVX     , D_A_B          , kV, kGeneral, "Vector Merge High Half Word"                                                ),
-  INSTRUCTION(0x1000008c, "vmrghw"      , kVX     , D_A_B          , kV, kGeneral, "Vector Merge High Word"                                                     ),
-  INSTRUCTION(0x18000300, "vmrghw128"   , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Merge High Word"                                                  ),
-  INSTRUCTION(0x1000010c, "vmrglb"      , kVX     , D_A_B          , kV, kGeneral, "Vector Merge Low Byte"                                                      ),
-  INSTRUCTION(0x1000014c, "vmrglh"      , kVX     , D_A_B          , kV, kGeneral, "Vector Merge Low Half Word"                                                 ),
-  INSTRUCTION(0x1000018c, "vmrglw"      , kVX     , D_A_B          , kV, kGeneral, "Vector Merge Low Word"                                                      ),
-  INSTRUCTION(0x18000340, "vmrglw128"   , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Merge Low Word"                                                   ),
-  INSTRUCTION(0x14000190, "vmsum3fp128" , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Multiply Sum 3-way Floating Point"                                ),
-  INSTRUCTION(0x140001d0, "vmsum4fp128" , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Multiply Sum 4-way Floating-Point"                                ),
-  INSTRUCTION(0x10000025, "vmsummbm"    , kVA     , D_A_B_C        , kV, kGeneral, "Vector Multiply-Sum Mixed-Sign Byte Modulo"                                 ),
-  INSTRUCTION(0x10000028, "vmsumshm"    , kVA     , D_A_B_C        , kV, kGeneral, "Vector Multiply-Sum Signed Half Word Modulo"                                ),
-  INSTRUCTION(0x10000029, "vmsumshs"    , kVA     , D_A_B_C        , kV, kGeneral, "Vector Multiply-Sum Signed Half Word Saturate"                              ),
-  INSTRUCTION(0x10000024, "vmsumubm"    , kVA     , D_A_B_C        , kV, kGeneral, "Vector Multiply-Sum Unsigned Byte Modulo"                                   ),
-  INSTRUCTION(0x10000026, "vmsumuhm"    , kVA     , D_A_B_C        , kV, kGeneral, "Vector Multiply-Sum Unsigned Half Word Modulo"                              ),
-  INSTRUCTION(0x10000027, "vmsumuhs"    , kVA     , D_A_B_C        , kV, kGeneral, "Vector Multiply-Sum Unsigned Half Word Saturate"                            ),
-  INSTRUCTION(0x10000308, "vmulesb"     , kVX     , D_A_B          , kV, kGeneral, "Vector Multiply Even Signed Byte"                                           ),
-  INSTRUCTION(0x10000348, "vmulesh"     , kVX     , D_A_B          , kV, kGeneral, "Vector Multiply Even Signed Half Word"                                      ),
-  INSTRUCTION(0x10000208, "vmuleub"     , kVX     , D_A_B          , kV, kGeneral, "Vector Multiply Even Unsigned Byte"                                         ),
-  INSTRUCTION(0x10000248, "vmuleuh"     , kVX     , D_A_B          , kV, kGeneral, "Vector Multiply Even Unsigned Half Word"                                    ),
-  INSTRUCTION(0x14000090, "vmulfp128"   , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Multiply Floating-Point"                                          ),
-  INSTRUCTION(0x10000108, "vmulosb"     , kVX     , D_A_B          , kV, kGeneral, "Vector Multiply Odd Signed Byte"                                            ),
-  INSTRUCTION(0x10000148, "vmulosh"     , kVX     , D_A_B          , kV, kGeneral, "Vector Multiply Odd Signed Half Word"                                       ),
-  INSTRUCTION(0x10000008, "vmuloub"     , kVX     , D_A_B          , kV, kGeneral, "Vector Multiply Odd Unsigned Byte"                                          ),
-  INSTRUCTION(0x10000048, "vmulouh"     , kVX     , D_A_B          , kV, kGeneral, "Vector Multiply Odd Unsigned Half Word"                                     ),
-  INSTRUCTION(0x1000002f, "vnmsubfp"    , kVA     , D_A_B_C        , kV, kGeneral, "Vector Negative Multiply-Subtract Floating Point"                           ),
-  INSTRUCTION(0x14000150, "vnmsubfp128" , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Negative Multiply-Subtract Floating Point"                        ),
-  INSTRUCTION(0x10000504, "vnor"        , kVX     , D_A_B          , kV, kGeneral, "Vector Logical NOR"                                                         ),
-  INSTRUCTION(0x14000290, "vnor128"     , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Logical NOR"                                                      ),
-  INSTRUCTION(0x10000484, "vor"         , kVX     , D_A_B          , kV, kGeneral, "Vector Logical OR"                                                          ),
-  INSTRUCTION(0x140002d0, "vor128"      , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Logical OR"                                                       ),
-  INSTRUCTION(0x1000002b, "vperm"       , kVA     , D_A_B_C        , kV, kGeneral, "Vector Permute"                                                             ),
-  INSTRUCTION(0x14000000, "vperm128"    , kVX128_2, D_A_B_C        , kV, kGeneral, "Vector128 Permute"                                                          ),
-  INSTRUCTION(0x18000210, "vpermwi128"  , kVX128_P, D_A_B_C        , kV, kGeneral, "Vector128 Permutate Word Immediate"                                         ),
-  INSTRUCTION(0x18000610, "vpkd3d128"   , kVX128_4, D_B            , kV, kGeneral, "Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert"              ),
-  INSTRUCTION(0x1000030e, "vpkpx"       , kVX     , D_A_B          , kV, kGeneral, "Vector Pack Pixel"                                                          ),
-  INSTRUCTION(0x1000018e, "vpkshss"     , kVX     , D_A_B          , kV, kGeneral, "Vector Pack Signed Half Word Signed Saturate"                               ),
-  INSTRUCTION(0x14000200, "vpkshss128"  , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Pack Signed Half Word Signed Saturate"                            ),
-  INSTRUCTION(0x1000010e, "vpkshus"     , kVX     , D_A_B          , kV, kGeneral, "Vector Pack Signed Half Word Unsigned Saturate"                             ),
-  INSTRUCTION(0x14000240, "vpkshus128"  , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Pack Signed Half Word Unsigned Saturate"                          ),
-  INSTRUCTION(0x100001ce, "vpkswss"     , kVX     , D_A_B          , kV, kGeneral, "Vector Pack Signed Word Signed Saturate"                                    ),
-  INSTRUCTION(0x14000280, "vpkswss128"  , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Pack Signed Word Signed Saturate"                                 ),
-  INSTRUCTION(0x1000014e, "vpkswus"     , kVX     , D_A_B          , kV, kGeneral, "Vector Pack Signed Word Unsigned Saturate"                                  ),
-  INSTRUCTION(0x140002c0, "vpkswus128"  , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Pack Signed Word Unsigned Saturate"                               ),
-  INSTRUCTION(0x1000000e, "vpkuhum"     , kVX     , D_A_B          , kV, kGeneral, "Vector Pack Unsigned Half Word Unsigned Modulo"                             ),
-  INSTRUCTION(0x14000300, "vpkuhum128"  , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Pack Unsigned Half Word Unsigned Modulo"                          ),
-  INSTRUCTION(0x1000008e, "vpkuhus"     , kVX     , D_A_B          , kV, kGeneral, "Vector Pack Unsigned Half Word Unsigned Saturate"                           ),
-  INSTRUCTION(0x14000340, "vpkuhus128"  , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Pack Unsigned Half Word Unsigned Saturate"                        ),
-  INSTRUCTION(0x1000004e, "vpkuwum"     , kVX     , D_A_B          , kV, kGeneral, "Vector Pack Unsigned Word Unsigned Modulo"                                  ),
-  INSTRUCTION(0x14000380, "vpkuwum128"  , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Pack Unsigned Word Unsigned Modulo"                               ),
-  INSTRUCTION(0x100000ce, "vpkuwus"     , kVX     , D_A_B          , kV, kGeneral, "Vector Pack Unsigned Word Unsigned Saturate"                                ),
-  INSTRUCTION(0x140003c0, "vpkuwus128"  , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Pack Unsigned Word Unsigned Saturate"                             ),
-  INSTRUCTION(0x1000010a, "vrefp"       , kVX     , D_A_B          , kV, kGeneral, "Vector Reciprocal Estimate Floating Point"                                  ),
-  INSTRUCTION(0x18000630, "vrefp128"    , kVX128_3, D_B            , kV, kGeneral, "Vector128 Reciprocal Estimate Floating Point"                               ),
-  INSTRUCTION(0x100002ca, "vrfim"       , kVX     , D_A_B          , kV, kGeneral, "Vector Round to Floating-Point Integer toward -Infinity"                    ),
-  INSTRUCTION(0x18000330, "vrfim128"    , kVX128_3, D_B            , kV, kGeneral, "Vector128 Round to Floating-Point Integer toward -Infinity"                 ),
-  INSTRUCTION(0x1000020a, "vrfin"       , kVX     , D_A_B          , kV, kGeneral, "Vector Round to Floating-Point Integer Nearest"                             ),
-  INSTRUCTION(0x18000370, "vrfin128"    , kVX128_3, D_B            , kV, kGeneral, "Vector128 Round to Floating-Point Integer Nearest"                          ),
-  INSTRUCTION(0x1000028a, "vrfip"       , kVX     , D_A_B          , kV, kGeneral, "Vector Round to Floating-Point Integer toward +Infinity"                    ),
-  INSTRUCTION(0x180003b0, "vrfip128"    , kVX128_3, D_B            , kV, kGeneral, "Vector128 Round to Floating-Point Integer toward +Infinity"                 ),
-  INSTRUCTION(0x1000024a, "vrfiz"       , kVX     , D_A_B          , kV, kGeneral, "Vector Round to Floating-Point Integer toward Zero"                         ),
-  INSTRUCTION(0x180003f0, "vrfiz128"    , kVX128_3, D_B            , kV, kGeneral, "Vector128 Round to Floating-Point Integer toward Zero"                      ),
-  INSTRUCTION(0x10000004, "vrlb"        , kVX     , D_A_B          , kV, kGeneral, "Vector Rotate Left Integer Byte"                                            ),
-  INSTRUCTION(0x10000044, "vrlh"        , kVX     , D_A_B          , kV, kGeneral, "Vector Rotate Left Integer Half Word"                                       ),
-  INSTRUCTION(0x18000710, "vrlimi128"   , kVX128_4, D_B_UIMM       , kV, kGeneral, "Vector128 Rotate Left Immediate and Mask Insert"                            ),
-  INSTRUCTION(0x10000084, "vrlw"        , kVX     , D_A_B          , kV, kGeneral, "Vector Rotate Left Integer Word"                                            ),
-  INSTRUCTION(0x18000050, "vrlw128"     , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Rotate Left Word"                                                 ),
-  INSTRUCTION(0x1000014a, "vrsqrtefp"   , kVX     , D_A_B          , kV, kGeneral, "Vector Reciprocal Square Root Estimate Floating Point"                      ),
-  INSTRUCTION(0x18000670, "vrsqrtefp128", kVX128_3, D_B            , kV, kGeneral, "Vector128 Reciprocal Square Root Estimate Floating Point"                   ),
-  INSTRUCTION(0x1000002a, "vsel"        , kVA     , D_A_B_C        , kV, kGeneral, "Vector Conditional Select"                                                  ),
-  INSTRUCTION(0x14000350, "vsel128"     , kVX128  , D_A_B_D        , kV, kGeneral, "Vector128 Conditional Select"                                               ),
-  INSTRUCTION(0x100001c4, "vsl"         , kVX     , D_A_B          , kV, kGeneral, "Vector Shift Left"                                                          ),
-  INSTRUCTION(0x10000104, "vslb"        , kVX     , D_A_B          , kV, kGeneral, "Vector Shift Left Integer Byte"                                             ),
-  INSTRUCTION(0x1000002c, "vsldoi"      , kVA     , D_A_B_C        , kV, kGeneral, "Vector Shift Left Double by Octet Immediate"                                ),
-  INSTRUCTION(0x10000010, "vsldoi128"   , kVX128_5, D_A_B_I        , kV, kGeneral, "Vector128 Shift Left Double by Octet Immediate"                             ),
-  INSTRUCTION(0x10000144, "vslh"        , kVX     , D_A_B          , kV, kGeneral, "Vector Shift Left Integer Half Word"                                        ),
-  INSTRUCTION(0x1000040c, "vslo"        , kVX     , D_A_B          , kV, kGeneral, "Vector Shift Left by Octet"                                                 ),
-  INSTRUCTION(0x14000390, "vslo128"     , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Shift Left Octet"                                                 ),
-  INSTRUCTION(0x10000184, "vslw"        , kVX     , D_A_B          , kV, kGeneral, "Vector Shift Left Integer Word"                                             ),
-  INSTRUCTION(0x180000d0, "vslw128"     , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Shift Left Integer Word"                                          ),
-  INSTRUCTION(0x1000020c, "vspltb"      , kVX     , D_A_B          , kV, kGeneral, "Vector Splat Byte"                                                          ),
-  INSTRUCTION(0x1000024c, "vsplth"      , kVX     , D_A_B          , kV, kGeneral, "Vector Splat Half Word"                                                     ),
-  INSTRUCTION(0x1000030c, "vspltisb"    , kVX     , D_A_B          , kV, kGeneral, "Vector Splat Immediate Signed Byte"                                         ),
-  INSTRUCTION(0x1000034c, "vspltish"    , kVX     , D_A_B          , kV, kGeneral, "Vector Splat Immediate Signed Half Word"                                    ),
-  INSTRUCTION(0x1000038c, "vspltisw"    , kVX     , D_A_B          , kV, kGeneral, "Vector Splat Immediate Signed Word"                                         ),
-  INSTRUCTION(0x18000770, "vspltisw128" , kVX128_3, D_B_SIMM       , kV, kGeneral, "Vector128 Splat Immediate Signed Word"                                      ),
-  INSTRUCTION(0x1000028c, "vspltw"      , kVX     , D_A_B          , kV, kGeneral, "Vector Splat Word"                                                          ),
-  INSTRUCTION(0x18000730, "vspltw128"   , kVX128_3, D_B_SIMM       , kV, kGeneral, "Vector128 Splat Word"                                                       ),
-  INSTRUCTION(0x100002c4, "vsr"         , kVX     , D_A_B          , kV, kGeneral, "Vector Shift Right"                                                         ),
-  INSTRUCTION(0x10000304, "vsrab"       , kVX     , D_A_B          , kV, kGeneral, "Vector Shift Right Algebraic Byte"                                          ),
-  INSTRUCTION(0x10000344, "vsrah"       , kVX     , D_A_B          , kV, kGeneral, "Vector Shift Right Algebraic Half Word"                                     ),
-  INSTRUCTION(0x10000384, "vsraw"       , kVX     , D_A_B          , kV, kGeneral, "Vector Shift Right Algebraic Word"                                          ),
-  INSTRUCTION(0x18000150, "vsraw128"    , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Shift Right Arithmetic Word"                                      ),
-  INSTRUCTION(0x10000204, "vsrb"        , kVX     , D_A_B          , kV, kGeneral, "Vector Shift Right Byte"                                                    ),
-  INSTRUCTION(0x10000244, "vsrh"        , kVX     , D_A_B          , kV, kGeneral, "Vector Shift Right Half Word"                                               ),
-  INSTRUCTION(0x1000044c, "vsro"        , kVX     , D_A_B          , kV, kGeneral, "Vector Shift Right Octet"                                                   ),
-  INSTRUCTION(0x140003d0, "vsro128"     , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Shift Right Octet"                                                ),
-  INSTRUCTION(0x10000284, "vsrw"        , kVX     , D_A_B          , kV, kGeneral, "Vector Shift Right Word"                                                    ),
-  INSTRUCTION(0x180001d0, "vsrw128"     , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Shift Right Word"                                                 ),
-  INSTRUCTION(0x10000580, "vsubcuw"     , kVX     , D_A_B          , kV, kGeneral, "Vector Subtract Carryout Unsigned Word"                                     ),
-  INSTRUCTION(0x1000004a, "vsubfp"      , kVX     , D_A_B          , kV, kGeneral, "Vector Subtract Floating Point"                                             ),
-  INSTRUCTION(0x14000050, "vsubfp128"   , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Subtract Floating Point"                                          ),
-  INSTRUCTION(0x10000700, "vsubsbs"     , kVX     , D_A_B          , kV, kGeneral, "Vector Subtract Signed Byte Saturate"                                       ),
-  INSTRUCTION(0x10000740, "vsubshs"     , kVX     , D_A_B          , kV, kGeneral, "Vector Subtract Signed Half Word Saturate"                                  ),
-  INSTRUCTION(0x10000780, "vsubsws"     , kVX     , D_A_B          , kV, kGeneral, "Vector Subtract Signed Word Saturate"                                       ),
-  INSTRUCTION(0x10000400, "vsububm"     , kVX     , D_A_B          , kV, kGeneral, "Vector Subtract Unsigned Byte Modulo"                                       ),
-  INSTRUCTION(0x10000600, "vsububs"     , kVX     , D_A_B          , kV, kGeneral, "Vector Subtract Unsigned Byte Saturate"                                     ),
-  INSTRUCTION(0x10000440, "vsubuhm"     , kVX     , D_A_B          , kV, kGeneral, "Vector Subtract Unsigned Half Word Modulo"                                  ),
-  INSTRUCTION(0x10000640, "vsubuhs"     , kVX     , D_A_B          , kV, kGeneral, "Vector Subtract Unsigned Half Word Saturate"                                ),
-  INSTRUCTION(0x10000480, "vsubuwm"     , kVX     , D_A_B          , kV, kGeneral, "Vector Subtract Unsigned Word Modulo"                                       ),
-  INSTRUCTION(0x10000680, "vsubuws"     , kVX     , D_A_B          , kV, kGeneral, "Vector Subtract Unsigned Word Saturate"                                     ),
-  INSTRUCTION(0x10000688, "vsum2sws"    , kVX     , D_A_B          , kV, kGeneral, "Vector Sum Across Partial (1/2) Signed Word Saturate"                       ),
-  INSTRUCTION(0x10000708, "vsum4sbs"    , kVX     , D_A_B          , kV, kGeneral, "Vector Sum Across Partial (1/4) Signed Byte Saturate"                       ),
-  INSTRUCTION(0x10000648, "vsum4shs"    , kVX     , D_A_B          , kV, kGeneral, "Vector Sum Across Partial (1/4) Signed Half Word Saturate"                  ),
-  INSTRUCTION(0x10000608, "vsum4ubs"    , kVX     , D_A_B          , kV, kGeneral, "Vector Sum Across Partial (1/4) Unsigned Byte Saturate"                     ),
-  INSTRUCTION(0x10000788, "vsumsws"     , kVX     , D_A_B          , kV, kGeneral, "Vector Sum Across Signed Word Saturate"                                     ),
-  INSTRUCTION(0x180007f0, "vupkd3d128"  , kVX128_3, D_B_SIMM       , kV, kGeneral, "Vector128 Unpack D3Dtype"                                                   ),
-  INSTRUCTION(0x1000034e, "vupkhpx"     , kVX     , D_A_B          , kV, kGeneral, "Vector Unpack High Pixel"                                                   ),
-  INSTRUCTION(0x1000020e, "vupkhsb"     , kVX     , D_A_B          , kV, kGeneral, "Vector Unpack High Signed Byte"                                             ),
-  INSTRUCTION(0x18000380, "vupkhsb128"  , kVX128  , D_B            , kV, kGeneral, "Vector128 Unpack High Signed Byte"                                          ),
-  INSTRUCTION(0x1000024e, "vupkhsh"     , kVX     , D_A_B          , kV, kGeneral, "Vector Unpack High Signed Half Word"                                        ),
-  INSTRUCTION(0x100003ce, "vupklpx"     , kVX     , D_A_B          , kV, kGeneral, "Vector Unpack Low Pixel"                                                    ),
-  INSTRUCTION(0x1000028e, "vupklsb"     , kVX     , D_A_B          , kV, kGeneral, "Vector Unpack Low Signed Byte"                                              ),
-  INSTRUCTION(0x180003c0, "vupklsb128"  , kVX128  , D_B            , kV, kGeneral, "Vector128 Unpack Low Signed Byte"                                           ),
-  INSTRUCTION(0x100002ce, "vupklsh"     , kVX     , D_A_B          , kV, kGeneral, "Vector Unpack Low Signed Half Word"                                         ),
-  INSTRUCTION(0x100004c4, "vxor"        , kVX     , D_A_B          , kV, kGeneral, "Vector Logical XOR"                                                         ),
-  INSTRUCTION(0x14000310, "vxor128"     , kVX128  , D_A_B          , kV, kGeneral, "Vector128 Logical XOR"                                                      ),
-  INSTRUCTION(0x68000000, "xori"        , kD      , S_A_UIMM       , kI, kGeneral, "XOR Immediate"                                                              ),
-  INSTRUCTION(0x6c000000, "xoris"       , kD      , S_A_UIMM       , kI, kGeneral, "XOR Immediate Shifted"                                                      ),
-  INSTRUCTION(0x7c000278, "xorx"        , kX      , S_A_B_Rc       , kI, kGeneral, "XOR"                                                                        ),
+  INSTRUCTION(0x7c000014, "addcx"       , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c000114, "addex"       , kXO     , kI, kGeneral),
+  INSTRUCTION(0x38000000, "addi"        , kD      , kI, kGeneral),
+  INSTRUCTION(0x30000000, "addic"       , kD      , kI, kGeneral),
+  INSTRUCTION(0x34000000, "addicx"      , kD      , kI, kGeneral),
+  INSTRUCTION(0x3c000000, "addis"       , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c0001d4, "addmex"      , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c000214, "addx"        , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c000194, "addzex"      , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c000078, "andcx"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x74000000, "andisx"      , kD      , kI, kGeneral),
+  INSTRUCTION(0x70000000, "andix"       , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c000038, "andx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x4c000420, "bcctrx"      , kXL     , kI, kSync   ),
+  INSTRUCTION(0x4c000020, "bclrx"       , kXL     , kI, kSync   ),
+  INSTRUCTION(0x40000000, "bcx"         , kB      , kI, kSync   ),
+  INSTRUCTION(0x48000000, "bx"          , kI      , kI, kSync   ),
+  INSTRUCTION(0x7c000000, "cmp"         , kX      , kI, kGeneral),
+  INSTRUCTION(0x2c000000, "cmpi"        , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c000040, "cmpl"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x28000000, "cmpli"       , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c000074, "cntlzdx"     , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000034, "cntlzwx"     , kX      , kI, kGeneral),
+  INSTRUCTION(0x4c000202, "crand"       , kXL     , kI, kGeneral),
+  INSTRUCTION(0x4c000102, "crandc"      , kXL     , kI, kGeneral),
+  INSTRUCTION(0x4c000242, "creqv"       , kXL     , kI, kGeneral),
+  INSTRUCTION(0x4c0001c2, "crnand"      , kXL     , kI, kGeneral),
+  INSTRUCTION(0x4c000042, "crnor"       , kXL     , kI, kGeneral),
+  INSTRUCTION(0x4c000382, "cror"        , kXL     , kI, kGeneral),
+  INSTRUCTION(0x4c000342, "crorc"       , kXL     , kI, kGeneral),
+  INSTRUCTION(0x4c000182, "crxor"       , kXL     , kI, kGeneral),
+  INSTRUCTION(0x7c0005ec, "dcba"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c0000ac, "dcbf"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c0003ac, "dcbi"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c00006c, "dcbst"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c00022c, "dcbt"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c0001ec, "dcbtst"      , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c0007ec, "dcbz"        , kDCBZ   , kI, kGeneral),
+  INSTRUCTION(0x7c2007ec, "dcbz128"     , kDCBZ   , kI, kGeneral),
+  INSTRUCTION(0x7c000392, "divdux"      , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c0003d2, "divdx"       , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c000396, "divwux"      , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c0003d6, "divwx"       , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c0006ac, "eieio"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000238, "eqvx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000774, "extsbx"      , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000734, "extshx"      , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c0007b4, "extswx"      , kX      , kI, kGeneral),
+  INSTRUCTION(0xfc000210, "fabsx"       , kX      , kF, kGeneral),
+  INSTRUCTION(0xec00002a, "faddsx"      , kA      , kF, kGeneral),
+  INSTRUCTION(0xfc00002a, "faddx"       , kA      , kF, kGeneral),
+  INSTRUCTION(0xfc00069c, "fcfidx"      , kX      , kF, kGeneral),
+  INSTRUCTION(0xfc000040, "fcmpo"       , kX      , kF, kGeneral),
+  INSTRUCTION(0xfc000000, "fcmpu"       , kX      , kF, kGeneral),
+  INSTRUCTION(0xfc00065c, "fctidx"      , kX      , kF, kGeneral),
+  INSTRUCTION(0xfc00065e, "fctidzx"     , kX      , kF, kGeneral),
+  INSTRUCTION(0xfc00001c, "fctiwx"      , kX      , kF, kGeneral),
+  INSTRUCTION(0xfc00001e, "fctiwzx"     , kX      , kF, kGeneral),
+  INSTRUCTION(0xec000024, "fdivsx"      , kA      , kF, kGeneral),
+  INSTRUCTION(0xfc000024, "fdivx"       , kA      , kF, kGeneral),
+  INSTRUCTION(0xec00003a, "fmaddsx"     , kA      , kF, kGeneral),
+  INSTRUCTION(0xfc00003a, "fmaddx"      , kA      , kF, kGeneral),
+  INSTRUCTION(0xfc000090, "fmrx"        , kX      , kF, kGeneral),
+  INSTRUCTION(0xec000038, "fmsubsx"     , kA      , kF, kGeneral),
+  INSTRUCTION(0xfc000038, "fmsubx"      , kA      , kF, kGeneral),
+  INSTRUCTION(0xec000032, "fmulsx"      , kA      , kF, kGeneral),
+  INSTRUCTION(0xfc000032, "fmulx"       , kA      , kF, kGeneral),
+  INSTRUCTION(0xfc000110, "fnabsx"      , kX      , kF, kGeneral),
+  INSTRUCTION(0xfc000050, "fnegx"       , kX      , kF, kGeneral),
+  INSTRUCTION(0xec00003e, "fnmaddsx"    , kA      , kF, kGeneral),
+  INSTRUCTION(0xfc00003e, "fnmaddx"     , kA      , kF, kGeneral),
+  INSTRUCTION(0xec00003c, "fnmsubsx"    , kA      , kF, kGeneral),
+  INSTRUCTION(0xfc00003c, "fnmsubx"     , kA      , kF, kGeneral),
+  INSTRUCTION(0xec000030, "fresx"       , kA      , kF, kGeneral),
+  INSTRUCTION(0xfc000018, "frspx"       , kX      , kF, kGeneral),
+  INSTRUCTION(0xfc000034, "frsqrtex"    , kA      , kF, kGeneral),
+  INSTRUCTION(0xfc00002e, "fselx"       , kA      , kF, kGeneral),
+  INSTRUCTION(0xec00002c, "fsqrtsx"     , kA      , kF, kGeneral),
+  INSTRUCTION(0xfc00002c, "fsqrtx"      , kA      , kF, kGeneral),
+  INSTRUCTION(0xec000028, "fsubsx"      , kA      , kF, kGeneral),
+  INSTRUCTION(0xfc000028, "fsubx"       , kA      , kF, kGeneral),
+  INSTRUCTION(0x7c0007ac, "icbi"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x4c00012c, "isync"       , kXL     , kI, kGeneral),
+  INSTRUCTION(0x88000000, "lbz"         , kD      , kI, kGeneral),
+  INSTRUCTION(0x8c000000, "lbzu"        , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c0000ee, "lbzux"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c0000ae, "lbzx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0xe8000000, "ld"          , kDS     , kI, kGeneral),
+  INSTRUCTION(0x7c0000a8, "ldarx"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000428, "ldbrx"       , kX      , kI, kGeneral),
+  INSTRUCTION(0xe8000001, "ldu"         , kDS     , kI, kGeneral),
+  INSTRUCTION(0x7c00006a, "ldux"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c00002a, "ldx"         , kX      , kI, kGeneral),
+  INSTRUCTION(0xc8000000, "lfd"         , kD      , kF, kGeneral),
+  INSTRUCTION(0xcc000000, "lfdu"        , kD      , kF, kGeneral),
+  INSTRUCTION(0x7c0004ee, "lfdux"       , kX      , kF, kGeneral),
+  INSTRUCTION(0x7c0004ae, "lfdx"        , kX      , kF, kGeneral),
+  INSTRUCTION(0xc0000000, "lfs"         , kD      , kF, kGeneral),
+  INSTRUCTION(0xc4000000, "lfsu"        , kD      , kF, kGeneral),
+  INSTRUCTION(0x7c00046e, "lfsux"       , kX      , kF, kGeneral),
+  INSTRUCTION(0x7c00042e, "lfsx"        , kX      , kF, kGeneral),
+  INSTRUCTION(0xa8000000, "lha"         , kD      , kI, kGeneral),
+  INSTRUCTION(0xac000000, "lhau"        , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c0002ee, "lhaux"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c0002ae, "lhax"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c00062c, "lhbrx"       , kX      , kI, kGeneral),
+  INSTRUCTION(0xa0000000, "lhz"         , kD      , kI, kGeneral),
+  INSTRUCTION(0xa4000000, "lhzu"        , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c00026e, "lhzux"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c00022e, "lhzx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0xb8000000, "lmw"         , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c0004aa, "lswi"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c00042a, "lswx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c00000e, "lvebx"       , kX      , kV, kGeneral),
+  INSTRUCTION(0x7c00004e, "lvehx"       , kX      , kV, kGeneral),
+  INSTRUCTION(0x7c00008e, "lvewx"       , kX      , kV, kGeneral),
+  INSTRUCTION(0x10000083, "lvewx128"    , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0x7c00040e, "lvlx"        , kX      , kV, kGeneral),
+  INSTRUCTION(0x10000403, "lvlx128"     , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0x7c00060e, "lvlxl"       , kX      , kV, kGeneral),
+  INSTRUCTION(0x10000603, "lvlxl128"    , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0x7c00044e, "lvrx"        , kX      , kV, kGeneral),
+  INSTRUCTION(0x10000443, "lvrx128"     , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0x7c00064e, "lvrxl"       , kX      , kV, kGeneral),
+  INSTRUCTION(0x10000643, "lvrxl128"    , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0x7c00000c, "lvsl"        , kX      , kV, kGeneral),
+  INSTRUCTION(0x10000003, "lvsl128"     , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0x7c00004c, "lvsr"        , kX      , kV, kGeneral),
+  INSTRUCTION(0x10000043, "lvsr128"     , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0x7c0000ce, "lvx"         , kX      , kV, kGeneral),
+  INSTRUCTION(0x100000c3, "lvx128"      , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0x7c0002ce, "lvxl"        , kX      , kV, kGeneral),
+  INSTRUCTION(0x100002c3, "lvxl128"     , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0xe8000002, "lwa"         , kDS     , kI, kGeneral),
+  INSTRUCTION(0x7c000028, "lwarx"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c0002ea, "lwaux"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c0002aa, "lwax"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c00042c, "lwbrx"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x80000000, "lwz"         , kD      , kI, kGeneral),
+  INSTRUCTION(0x84000000, "lwzu"        , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c00006e, "lwzux"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c00002e, "lwzx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x4c000000, "mcrf"        , kXL     , kI, kGeneral),
+  INSTRUCTION(0xfc000080, "mcrfs"       , kX      , kF, kGeneral),
+  INSTRUCTION(0x7c000400, "mcrxr"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000026, "mfcr"        , kX      , kI, kGeneral),
+  INSTRUCTION(0xfc00048e, "mffsx"       , kX      , kF, kGeneral),
+  INSTRUCTION(0x7c0000a6, "mfmsr"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c0002a6, "mfspr"       , kXFX    , kI, kGeneral),
+  INSTRUCTION(0x7c0002e6, "mftb"        , kXFX    , kI, kGeneral),
+  INSTRUCTION(0x10000604, "mfvscr"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x7c000120, "mtcrf"       , kXFX    , kI, kGeneral),
+  INSTRUCTION(0xfc00008c, "mtfsb0x"     , kX      , kF, kGeneral),
+  INSTRUCTION(0xfc00004c, "mtfsb1x"     , kX      , kF, kGeneral),
+  INSTRUCTION(0xfc00010c, "mtfsfix"     , kX      , kF, kGeneral),
+  INSTRUCTION(0xfc00058e, "mtfsfx"      , kXFL    , kF, kGeneral),
+  INSTRUCTION(0x7c000124, "mtmsr"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000164, "mtmsrd"      , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c0003a6, "mtspr"       , kXFX    , kI, kGeneral),
+  INSTRUCTION(0x10000644, "mtvscr"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x7c000012, "mulhdux"     , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c000092, "mulhdx"      , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c000016, "mulhwux"     , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c000096, "mulhwx"      , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c0001d2, "mulldx"      , kXO     , kI, kGeneral),
+  INSTRUCTION(0x1c000000, "mulli"       , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c0001d6, "mullwx"      , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c0003b8, "nandx"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c0000d0, "negx"        , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c0000f8, "norx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000338, "orcx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x60000000, "ori"         , kD      , kI, kGeneral),
+  INSTRUCTION(0x64000000, "oris"        , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c000378, "orx"         , kX      , kI, kGeneral),
+  INSTRUCTION(0x78000010, "rldclx"      , kMDS    , kI, kGeneral),
+  INSTRUCTION(0x78000012, "rldcrx"      , kMDS    , kI, kGeneral),
+  INSTRUCTION(0x78000000, "rldiclx"     , kMD     , kI, kGeneral),
+  INSTRUCTION(0x78000004, "rldicrx"     , kMD     , kI, kGeneral),
+  INSTRUCTION(0x78000008, "rldicx"      , kMD     , kI, kGeneral),
+  INSTRUCTION(0x7800000c, "rldimix"     , kMD     , kI, kGeneral),
+  INSTRUCTION(0x50000000, "rlwimix"     , kM      , kI, kGeneral),
+  INSTRUCTION(0x54000000, "rlwinmx"     , kM      , kI, kGeneral),
+  INSTRUCTION(0x5c000000, "rlwnmx"      , kM      , kI, kGeneral),
+  INSTRUCTION(0x44000002, "sc"          , kSC     , kI, kSync   ),
+  INSTRUCTION(0x7c000036, "sldx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000030, "slwx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000674, "sradix"      , kXS     , kI, kGeneral),
+  INSTRUCTION(0x7c000634, "sradx"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000670, "srawix"      , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000630, "srawx"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000436, "srdx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000430, "srwx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x98000000, "stb"         , kD      , kI, kGeneral),
+  INSTRUCTION(0x9c000000, "stbu"        , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c0001ee, "stbux"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c0001ae, "stbx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0xf8000000, "std"         , kDS     , kI, kGeneral),
+  INSTRUCTION(0x7c000528, "stdbrx"      , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c0001ad, "stdcx"       , kX      , kI, kGeneral),
+  INSTRUCTION(0xf8000001, "stdu"        , kDS     , kI, kGeneral),
+  INSTRUCTION(0x7c00016a, "stdux"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c00012a, "stdx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0xd8000000, "stfd"        , kD      , kF, kGeneral),
+  INSTRUCTION(0xdc000000, "stfdu"       , kD      , kF, kGeneral),
+  INSTRUCTION(0x7c0005ee, "stfdux"      , kX      , kF, kGeneral),
+  INSTRUCTION(0x7c0005ae, "stfdx"       , kX      , kF, kGeneral),
+  INSTRUCTION(0x7c0007ae, "stfiwx"      , kX      , kF, kGeneral),
+  INSTRUCTION(0xd0000000, "stfs"        , kD      , kF, kGeneral),
+  INSTRUCTION(0xd4000000, "stfsu"       , kD      , kF, kGeneral),
+  INSTRUCTION(0x7c00056e, "stfsux"      , kX      , kF, kGeneral),
+  INSTRUCTION(0x7c00052e, "stfsx"       , kX      , kF, kGeneral),
+  INSTRUCTION(0xb0000000, "sth"         , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c00072c, "sthbrx"      , kX      , kI, kGeneral),
+  INSTRUCTION(0xb4000000, "sthu"        , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c00036e, "sthux"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c00032e, "sthx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0xbc000000, "stmw"        , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c0005aa, "stswi"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c00052a, "stswx"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c00010e, "stvebx"      , kX      , kV, kGeneral),
+  INSTRUCTION(0x7c00014e, "stvehx"      , kX      , kV, kGeneral),
+  INSTRUCTION(0x7c00018e, "stvewx"      , kX      , kV, kGeneral),
+  INSTRUCTION(0x10000183, "stvewx128"   , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0x7c00050e, "stvlx"       , kX      , kV, kGeneral),
+  INSTRUCTION(0x10000503, "stvlx128"    , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0x7c00070e, "stvlxl"      , kX      , kV, kGeneral),
+  INSTRUCTION(0x10000703, "stvlxl128"   , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0x7c00054e, "stvrx"       , kX      , kV, kGeneral),
+  INSTRUCTION(0x10000543, "stvrx128"    , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0x7c00074e, "stvrxl"      , kX      , kV, kGeneral),
+  INSTRUCTION(0x10000743, "stvrxl128"   , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0x7c0001ce, "stvx"        , kX      , kV, kGeneral),
+  INSTRUCTION(0x100001c3, "stvx128"     , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0x7c0003ce, "stvxl"       , kX      , kV, kGeneral),
+  INSTRUCTION(0x100003c3, "stvxl128"    , kVX128_1, kV, kGeneral),
+  INSTRUCTION(0x90000000, "stw"         , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c00052c, "stwbrx"      , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c00012d, "stwcx"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x94000000, "stwu"        , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c00016e, "stwux"       , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c00012e, "stwx"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000010, "subfcx"      , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c000110, "subfex"      , kXO     , kI, kGeneral),
+  INSTRUCTION(0x20000000, "subficx"     , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c0001d0, "subfmex"     , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c000050, "subfx"       , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c000190, "subfzex"     , kXO     , kI, kGeneral),
+  INSTRUCTION(0x7c0004ac, "sync"        , kX      , kI, kGeneral),
+  INSTRUCTION(0x7c000088, "td"          , kX      , kI, kGeneral),
+  INSTRUCTION(0x08000000, "tdi"         , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c000008, "tw"          , kX      , kI, kGeneral),
+  INSTRUCTION(0x0c000000, "twi"         , kD      , kI, kGeneral),
+  INSTRUCTION(0x10000180, "vaddcuw"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000000a, "vaddfp"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x14000010, "vaddfp128"   , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x10000300, "vaddsbs"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000340, "vaddshs"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000380, "vaddsws"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000000, "vaddubm"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000200, "vaddubs"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000040, "vadduhm"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000240, "vadduhs"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000080, "vadduwm"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000280, "vadduws"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000404, "vand"        , kVX     , kV, kGeneral),
+  INSTRUCTION(0x14000210, "vand128"     , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x10000444, "vandc"       , kVX     , kV, kGeneral),
+  INSTRUCTION(0x14000250, "vandc128"    , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x10000502, "vavgsb"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000542, "vavgsh"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000582, "vavgsw"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000402, "vavgub"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000442, "vavguh"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000482, "vavguw"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x18000230, "vcfpsxws128" , kVX128_3, kV, kGeneral),
+  INSTRUCTION(0x18000270, "vcfpuxws128" , kVX128_3, kV, kGeneral),
+  INSTRUCTION(0x1000034a, "vcfsx"       , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000030a, "vcfux"       , kVX     , kV, kGeneral),
+  INSTRUCTION(0x100003c6, "vcmpbfp"     , kVC     , kV, kGeneral),
+  INSTRUCTION(0x18000180, "vcmpbfp128"  , kVX128_R, kV, kGeneral),
+  INSTRUCTION(0x100000c6, "vcmpeqfp"    , kVC     , kV, kGeneral),
+  INSTRUCTION(0x18000000, "vcmpeqfp128" , kVX128_R, kV, kGeneral),
+  INSTRUCTION(0x10000006, "vcmpequb"    , kVC     , kV, kGeneral),
+  INSTRUCTION(0x10000046, "vcmpequh"    , kVC     , kV, kGeneral),
+  INSTRUCTION(0x10000086, "vcmpequw"    , kVC     , kV, kGeneral),
+  INSTRUCTION(0x18000200, "vcmpequw128" , kVX128_R, kV, kGeneral),
+  INSTRUCTION(0x100001c6, "vcmpgefp"    , kVC     , kV, kGeneral),
+  INSTRUCTION(0x18000080, "vcmpgefp128" , kVX128_R, kV, kGeneral),
+  INSTRUCTION(0x100002c6, "vcmpgtfp"    , kVC     , kV, kGeneral),
+  INSTRUCTION(0x18000100, "vcmpgtfp128" , kVX128_R, kV, kGeneral),
+  INSTRUCTION(0x10000306, "vcmpgtsb"    , kVC     , kV, kGeneral),
+  INSTRUCTION(0x10000346, "vcmpgtsh"    , kVC     , kV, kGeneral),
+  INSTRUCTION(0x10000386, "vcmpgtsw"    , kVC     , kV, kGeneral),
+  INSTRUCTION(0x10000206, "vcmpgtub"    , kVC     , kV, kGeneral),
+  INSTRUCTION(0x10000246, "vcmpgtuh"    , kVC     , kV, kGeneral),
+  INSTRUCTION(0x10000286, "vcmpgtuw"    , kVC     , kV, kGeneral),
+  INSTRUCTION(0x180002b0, "vcsxwfp128"  , kVX128_3, kV, kGeneral),
+  INSTRUCTION(0x100003ca, "vctsxs"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000038a, "vctuxs"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x180002f0, "vcuxwfp128"  , kVX128_3, kV, kGeneral),
+  INSTRUCTION(0x1000018a, "vexptefp"    , kVX     , kV, kGeneral),
+  INSTRUCTION(0x180006b0, "vexptefp128" , kVX128_3, kV, kGeneral),
+  INSTRUCTION(0x100001ca, "vlogefp"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x180006f0, "vlogefp128"  , kVX128_3, kV, kGeneral),
+  INSTRUCTION(0x14000110, "vmaddcfp128" , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x1000002e, "vmaddfp"     , kVA     , kV, kGeneral),
+  INSTRUCTION(0x140000d0, "vmaddfp128"  , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x1000040a, "vmaxfp"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x18000280, "vmaxfp128"   , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x10000102, "vmaxsb"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000142, "vmaxsh"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000182, "vmaxsw"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000002, "vmaxub"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000042, "vmaxuh"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000082, "vmaxuw"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000020, "vmhaddshs"   , kVA     , kV, kGeneral),
+  INSTRUCTION(0x10000021, "vmhraddshs"  , kVA     , kV, kGeneral),
+  INSTRUCTION(0x1000044a, "vminfp"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x180002c0, "vminfp128"   , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x10000302, "vminsb"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000342, "vminsh"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000382, "vminsw"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000202, "vminub"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000242, "vminuh"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000282, "vminuw"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000022, "vmladduhm"   , kVA     , kV, kGeneral),
+  INSTRUCTION(0x1000000c, "vmrghb"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000004c, "vmrghh"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000008c, "vmrghw"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x18000300, "vmrghw128"   , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x1000010c, "vmrglb"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000014c, "vmrglh"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000018c, "vmrglw"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x18000340, "vmrglw128"   , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x14000190, "vmsum3fp128" , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x140001d0, "vmsum4fp128" , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x10000025, "vmsummbm"    , kVA     , kV, kGeneral),
+  INSTRUCTION(0x10000028, "vmsumshm"    , kVA     , kV, kGeneral),
+  INSTRUCTION(0x10000029, "vmsumshs"    , kVA     , kV, kGeneral),
+  INSTRUCTION(0x10000024, "vmsumubm"    , kVA     , kV, kGeneral),
+  INSTRUCTION(0x10000026, "vmsumuhm"    , kVA     , kV, kGeneral),
+  INSTRUCTION(0x10000027, "vmsumuhs"    , kVA     , kV, kGeneral),
+  INSTRUCTION(0x10000308, "vmulesb"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000348, "vmulesh"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000208, "vmuleub"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000248, "vmuleuh"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x14000090, "vmulfp128"   , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x10000108, "vmulosb"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000148, "vmulosh"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000008, "vmuloub"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000048, "vmulouh"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000002f, "vnmsubfp"    , kVA     , kV, kGeneral),
+  INSTRUCTION(0x14000150, "vnmsubfp128" , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x10000504, "vnor"        , kVX     , kV, kGeneral),
+  INSTRUCTION(0x14000290, "vnor128"     , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x10000484, "vor"         , kVX     , kV, kGeneral),
+  INSTRUCTION(0x140002d0, "vor128"      , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x1000002b, "vperm"       , kVA     , kV, kGeneral),
+  INSTRUCTION(0x14000000, "vperm128"    , kVX128_2, kV, kGeneral),
+  INSTRUCTION(0x18000210, "vpermwi128"  , kVX128_P, kV, kGeneral),
+  INSTRUCTION(0x18000610, "vpkd3d128"   , kVX128_4, kV, kGeneral),
+  INSTRUCTION(0x1000030e, "vpkpx"       , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000018e, "vpkshss"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x14000200, "vpkshss128"  , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x1000010e, "vpkshus"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x14000240, "vpkshus128"  , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x100001ce, "vpkswss"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x14000280, "vpkswss128"  , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x1000014e, "vpkswus"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x140002c0, "vpkswus128"  , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x1000000e, "vpkuhum"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x14000300, "vpkuhum128"  , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x1000008e, "vpkuhus"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x14000340, "vpkuhus128"  , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x1000004e, "vpkuwum"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x14000380, "vpkuwum128"  , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x100000ce, "vpkuwus"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x140003c0, "vpkuwus128"  , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x1000010a, "vrefp"       , kVX     , kV, kGeneral),
+  INSTRUCTION(0x18000630, "vrefp128"    , kVX128_3, kV, kGeneral),
+  INSTRUCTION(0x100002ca, "vrfim"       , kVX     , kV, kGeneral),
+  INSTRUCTION(0x18000330, "vrfim128"    , kVX128_3, kV, kGeneral),
+  INSTRUCTION(0x1000020a, "vrfin"       , kVX     , kV, kGeneral),
+  INSTRUCTION(0x18000370, "vrfin128"    , kVX128_3, kV, kGeneral),
+  INSTRUCTION(0x1000028a, "vrfip"       , kVX     , kV, kGeneral),
+  INSTRUCTION(0x180003b0, "vrfip128"    , kVX128_3, kV, kGeneral),
+  INSTRUCTION(0x1000024a, "vrfiz"       , kVX     , kV, kGeneral),
+  INSTRUCTION(0x180003f0, "vrfiz128"    , kVX128_3, kV, kGeneral),
+  INSTRUCTION(0x10000004, "vrlb"        , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000044, "vrlh"        , kVX     , kV, kGeneral),
+  INSTRUCTION(0x18000710, "vrlimi128"   , kVX128_4, kV, kGeneral),
+  INSTRUCTION(0x10000084, "vrlw"        , kVX     , kV, kGeneral),
+  INSTRUCTION(0x18000050, "vrlw128"     , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x1000014a, "vrsqrtefp"   , kVX     , kV, kGeneral),
+  INSTRUCTION(0x18000670, "vrsqrtefp128", kVX128_3, kV, kGeneral),
+  INSTRUCTION(0x1000002a, "vsel"        , kVA     , kV, kGeneral),
+  INSTRUCTION(0x14000350, "vsel128"     , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x100001c4, "vsl"         , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000104, "vslb"        , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000002c, "vsldoi"      , kVA     , kV, kGeneral),
+  INSTRUCTION(0x10000010, "vsldoi128"   , kVX128_5, kV, kGeneral),
+  INSTRUCTION(0x10000144, "vslh"        , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000040c, "vslo"        , kVX     , kV, kGeneral),
+  INSTRUCTION(0x14000390, "vslo128"     , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x10000184, "vslw"        , kVX     , kV, kGeneral),
+  INSTRUCTION(0x180000d0, "vslw128"     , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x1000020c, "vspltb"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000024c, "vsplth"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000030c, "vspltisb"    , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000034c, "vspltish"    , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000038c, "vspltisw"    , kVX     , kV, kGeneral),
+  INSTRUCTION(0x18000770, "vspltisw128" , kVX128_3, kV, kGeneral),
+  INSTRUCTION(0x1000028c, "vspltw"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x18000730, "vspltw128"   , kVX128_3, kV, kGeneral),
+  INSTRUCTION(0x100002c4, "vsr"         , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000304, "vsrab"       , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000344, "vsrah"       , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000384, "vsraw"       , kVX     , kV, kGeneral),
+  INSTRUCTION(0x18000150, "vsraw128"    , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x10000204, "vsrb"        , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000244, "vsrh"        , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000044c, "vsro"        , kVX     , kV, kGeneral),
+  INSTRUCTION(0x140003d0, "vsro128"     , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x10000284, "vsrw"        , kVX     , kV, kGeneral),
+  INSTRUCTION(0x180001d0, "vsrw128"     , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x10000580, "vsubcuw"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000004a, "vsubfp"      , kVX     , kV, kGeneral),
+  INSTRUCTION(0x14000050, "vsubfp128"   , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x10000700, "vsubsbs"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000740, "vsubshs"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000780, "vsubsws"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000400, "vsububm"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000600, "vsububs"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000440, "vsubuhm"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000640, "vsubuhs"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000480, "vsubuwm"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000680, "vsubuws"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000688, "vsum2sws"    , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000708, "vsum4sbs"    , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000648, "vsum4shs"    , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000608, "vsum4ubs"    , kVX     , kV, kGeneral),
+  INSTRUCTION(0x10000788, "vsumsws"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x180007f0, "vupkd3d128"  , kVX128_3, kV, kGeneral),
+  INSTRUCTION(0x1000034e, "vupkhpx"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000020e, "vupkhsb"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x18000380, "vupkhsb128"  , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x1000024e, "vupkhsh"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x100003ce, "vupklpx"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x1000028e, "vupklsb"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x180003c0, "vupklsb128"  , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x100002ce, "vupklsh"     , kVX     , kV, kGeneral),
+  INSTRUCTION(0x100004c4, "vxor"        , kVX     , kV, kGeneral),
+  INSTRUCTION(0x14000310, "vxor128"     , kVX128  , kV, kGeneral),
+  INSTRUCTION(0x68000000, "xori"        , kD      , kI, kGeneral),
+  INSTRUCTION(0x6c000000, "xoris"       , kD      , kI, kGeneral),
+  INSTRUCTION(0x7c000278, "xorx"        , kX      , kI, kGeneral),
 };
 static_assert(sizeof(ppc_opcode_table) / sizeof(PPCOpcodeInfo) == static_cast<int>(PPCOpcode::kInvalid), "PPC table mismatch - rerun ppc-table-gen");
 
 const PPCOpcodeInfo& GetOpcodeInfo(PPCOpcode opcode) {
   return ppc_opcode_table[static_cast<int>(opcode)];
 }
-void RegisterOpcodeDisasm(PPCOpcode opcode, InstrDisasmFn1 fn) {
-  assert_null(ppc_opcode_table[static_cast<int>(opcode)].disasm);
-  ppc_opcode_table[static_cast<int>(opcode)].disasm = fn;
-}
 void RegisterOpcodeEmitter(PPCOpcode opcode, InstrEmitFn fn) {
   assert_null(ppc_opcode_table[static_cast<int>(opcode)].emit);
   ppc_opcode_table[static_cast<int>(opcode)].emit = fn;
diff --git a/src/xenia/cpu/ppc/ppc_scanner.cc b/src/xenia/cpu/ppc/ppc_scanner.cc
index 2ec6f3052..569de3494 100644
--- a/src/xenia/cpu/ppc/ppc_scanner.cc
+++ b/src/xenia/cpu/ppc/ppc_scanner.cc
@@ -15,8 +15,8 @@
 #include "xenia/base/logging.h"
 #include "xenia/base/memory.h"
 #include "xenia/base/profiling.h"
+#include "xenia/cpu/ppc/ppc_decode_data.h"
 #include "xenia/cpu/ppc/ppc_frontend.h"
-#include "xenia/cpu/ppc/ppc_instr.h"
 #include "xenia/cpu/ppc/ppc_opcode_info.h"
 #include "xenia/cpu/processor.h"
 
@@ -79,9 +79,9 @@ bool PPCScanner::Scan(GuestFunction* function, DebugInfo* debug_info) {
 
     auto opcode = LookupOpcode(code);
 
-    InstrData i;
-    i.address = address;
-    i.code = code;
+    PPCDecodeData d;
+    d.address = address;
+    d.code = code;
 
     // TODO(benvanik): switch on instruction metadata.
     ++address_reference_count;
@@ -91,7 +91,7 @@ bool PPCScanner::Scan(GuestFunction* function, DebugInfo* debug_info) {
     // of whether or not this is a normal function with a prolog/epilog.
     // Some valid leaf functions won't have this, but most will.
     if (address == start_address && opcode == PPCOpcode::mfspr &&
-        (((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F)) == 8) {
+        (((d.XFX.SPR() & 0x1F) << 5) | ((d.XFX.SPR() >> 5) & 0x1F)) == 8) {
       starts_with_mfspr_lr = true;
     }
 
@@ -135,10 +135,8 @@ bool PPCScanner::Scan(GuestFunction* function, DebugInfo* debug_info) {
       ends_block = true;
     } else if (opcode == PPCOpcode::bx) {
       // b/ba/bl/bla
-      uint32_t target =
-          (uint32_t)XEEXTS26(i.I.LI << 2) + (i.I.AA ? 0 : (int32_t)address);
-
-      if (i.I.LK) {
+      uint32_t target = d.I.ADDR();
+      if (d.I.LK()) {
         LOGPPC("bl %.8X -> %.8X", address, target);
         // Queue call target if needed.
         // GetOrInsertFunction(target);
@@ -213,9 +211,8 @@ bool PPCScanner::Scan(GuestFunction* function, DebugInfo* debug_info) {
       ends_block = true;
     } else if (opcode == PPCOpcode::bcx) {
       // bc/bca/bcl/bcla
-      uint32_t target =
-          (uint32_t)XEEXTS16(i.B.BD << 2) + (i.B.AA ? 0 : (int32_t)address);
-      if (i.B.LK) {
+      uint32_t target = d.B.ADDR();
+      if (d.B.LK()) {
         LOGPPC("bcl %.8X -> %.8X", address, target);
 
         // Queue call target if needed.
@@ -234,7 +231,7 @@ bool PPCScanner::Scan(GuestFunction* function, DebugInfo* debug_info) {
       ends_block = true;
     } else if (opcode == PPCOpcode::bclrx) {
       // bclr/bclrl
-      if (i.XL.LK) {
+      if (d.XL.LK()) {
         LOGPPC("bclrl %.8X", address);
       } else {
         LOGPPC("bclr %.8X", address);
@@ -242,7 +239,7 @@ bool PPCScanner::Scan(GuestFunction* function, DebugInfo* debug_info) {
       ends_block = true;
     } else if (opcode == PPCOpcode::bcctrx) {
       // bcctr/bcctrl
-      if (i.XL.LK) {
+      if (d.XL.LK()) {
         LOGPPC("bcctrl %.8X", address);
       } else {
         LOGPPC("bcctr %.8X", address);
diff --git a/src/xenia/cpu/ppc/ppc_translator.cc b/src/xenia/cpu/ppc/ppc_translator.cc
index 193009711..36e567ff4 100644
--- a/src/xenia/cpu/ppc/ppc_translator.cc
+++ b/src/xenia/cpu/ppc/ppc_translator.cc
@@ -18,16 +18,13 @@
 #include "xenia/base/reset_scope.h"
 #include "xenia/cpu/compiler/compiler_passes.h"
 #include "xenia/cpu/cpu_flags.h"
-#include "xenia/cpu/ppc/ppc_disasm.h"
 #include "xenia/cpu/ppc/ppc_frontend.h"
 #include "xenia/cpu/ppc/ppc_hir_builder.h"
+#include "xenia/cpu/ppc/ppc_opcode_info.h"
 #include "xenia/cpu/ppc/ppc_scanner.h"
 #include "xenia/cpu/processor.h"
 #include "xenia/debug/debugger.h"
 
-DEFINE_bool(preserve_hir_disasm, true,
-            "Preserves HIR disassembly for the debugger when it is attached.");
-
 namespace xe {
 namespace cpu {
 namespace ppc {
@@ -106,11 +103,6 @@ bool PPCTranslator::Translate(GuestFunction* function,
   xe::make_reset_scope(&string_buffer_);
 
   // NOTE: we only want to do this when required, as it's expensive to build.
-  if (FLAGS_preserve_hir_disasm && frontend_->processor()->debugger() &&
-      frontend_->processor()->debugger()->is_attached()) {
-    debug_info_flags |= DebugInfoFlags::kDebugInfoDisasmRawHir |
-                        DebugInfoFlags::kDebugInfoDisasmHir;
-  }
   if (FLAGS_disassemble_functions) {
     debug_info_flags |= DebugInfoFlags::kDebugInfoAllDisasm;
   }
@@ -167,9 +159,9 @@ bool PPCTranslator::Translate(GuestFunction* function,
 
   // Emit function.
   uint32_t emit_flags = 0;
-  // if (debug_info) {
-  emit_flags |= PPCHIRBuilder::EMIT_DEBUG_COMMENTS;
-  //}
+  if (debug_info) {
+    emit_flags |= PPCHIRBuilder::EMIT_DEBUG_COMMENTS;
+  }
   if (!builder_->Emit(function, emit_flags)) {
     return false;
   }
diff --git a/src/xenia/debug/debugger.cc b/src/xenia/debug/debugger.cc
index 2cfe0ddae..bda4082f8 100644
--- a/src/xenia/debug/debugger.cc
+++ b/src/xenia/debug/debugger.cc
@@ -19,11 +19,12 @@
 #include "xenia/base/debugging.h"
 #include "xenia/base/filesystem.h"
 #include "xenia/base/logging.h"
+#include "xenia/base/math.h"
 #include "xenia/base/string.h"
 #include "xenia/base/threading.h"
 #include "xenia/cpu/backend/code_cache.h"
 #include "xenia/cpu/function.h"
-#include "xenia/cpu/ppc/ppc_instr.h"
+#include "xenia/cpu/ppc/ppc_decode_data.h"
 #include "xenia/cpu/ppc/ppc_opcode_info.h"
 #include "xenia/cpu/processor.h"
 #include "xenia/cpu/stack_walker.h"
@@ -691,11 +692,11 @@ bool TestPpcCondition(const xe::cpu::ppc::PPCContext* context, uint32_t bo,
                       uint32_t bi, bool check_ctr, bool check_cond) {
   bool ctr_ok = true;
   if (check_ctr) {
-    if (xe::cpu::ppc::select_bits(bo, 2, 2)) {
+    if (select_bits(bo, 2, 2)) {
       ctr_ok = true;
     } else {
       uint32_t new_ctr_value = static_cast<uint32_t>(context->ctr - 1);
-      if (xe::cpu::ppc::select_bits(bo, 1, 1)) {
+      if (select_bits(bo, 1, 1)) {
         ctr_ok = new_ctr_value == 0;
       } else {
         ctr_ok = new_ctr_value != 0;
@@ -704,12 +705,12 @@ bool TestPpcCondition(const xe::cpu::ppc::PPCContext* context, uint32_t bo,
   }
   bool cond_ok = true;
   if (check_cond) {
-    if (xe::cpu::ppc::select_bits(bo, 4, 4)) {
+    if (select_bits(bo, 4, 4)) {
       cond_ok = true;
     } else {
       uint8_t cr = *(reinterpret_cast<const uint8_t*>(&context->cr0) +
                      (4 * (bi >> 2)) + (bi & 3));
-      if (xe::cpu::ppc::select_bits(bo, 3, 3)) {
+      if (select_bits(bo, 3, 3)) {
         cond_ok = cr != 0;
       } else {
         cond_ok = cr == 0;
@@ -721,44 +722,40 @@ bool TestPpcCondition(const xe::cpu::ppc::PPCContext* context, uint32_t bo,
 
 uint32_t Debugger::CalculateNextGuestInstruction(
     ThreadExecutionInfo* thread_info, uint32_t current_pc) {
-  xe::cpu::ppc::InstrData i;
-  i.address = current_pc;
-  i.code = xe::load_and_swap<uint32_t>(
-      emulator_->memory()->TranslateVirtual(i.address));
-  auto opcode = xe::cpu::ppc::LookupOpcode(i.code);
-  if (i.code == 0x4E800020) {
+  xe::cpu::ppc::PPCDecodeData d;
+  d.address = current_pc;
+  d.code = xe::load_and_swap<uint32_t>(
+      emulator_->memory()->TranslateVirtual(d.address));
+  auto opcode = xe::cpu::ppc::LookupOpcode(d.code);
+  if (d.code == 0x4E800020) {
     // blr -- unconditional branch to LR.
     uint32_t target_pc = static_cast<uint32_t>(thread_info->guest_context.lr);
     return target_pc;
-  } else if (i.code == 0x4E800420) {
+  } else if (d.code == 0x4E800420) {
     // bctr -- unconditional branch to CTR.
     uint32_t target_pc = static_cast<uint32_t>(thread_info->guest_context.ctr);
     return target_pc;
   } else if (opcode == PPCOpcode::bx) {
     // b/ba/bl/bla
-    uint32_t target_pc =
-        static_cast<uint32_t>(xe::cpu::ppc::XEEXTS26(i.I.LI << 2)) +
-        (i.I.AA ? 0u : i.address);
+    uint32_t target_pc = d.I.ADDR();
     return target_pc;
   } else if (opcode == PPCOpcode::bcx) {
     // bc/bca/bcl/bcla
-    uint32_t target_pc =
-        static_cast<uint32_t>(xe::cpu::ppc::XEEXTS16(i.B.BD << 2)) +
-        (i.B.AA ? 0u : i.address);
-    bool test_passed = TestPpcCondition(&thread_info->guest_context, i.B.BO,
-                                        i.B.BI, true, true);
+    uint32_t target_pc = d.B.ADDR();
+    bool test_passed = TestPpcCondition(&thread_info->guest_context, d.B.BO(),
+                                        d.B.BI(), true, true);
     return test_passed ? target_pc : current_pc + 4;
   } else if (opcode == PPCOpcode::bclrx) {
     // bclr/bclrl
     uint32_t target_pc = static_cast<uint32_t>(thread_info->guest_context.lr);
-    bool test_passed = TestPpcCondition(&thread_info->guest_context, i.XL.BO,
-                                        i.XL.BI, true, true);
+    bool test_passed = TestPpcCondition(&thread_info->guest_context, d.XL.BO(),
+                                        d.XL.BI(), true, true);
     return test_passed ? target_pc : current_pc + 4;
   } else if (opcode == PPCOpcode::bcctrx) {
     // bcctr/bcctrl
     uint32_t target_pc = static_cast<uint32_t>(thread_info->guest_context.ctr);
-    bool test_passed = TestPpcCondition(&thread_info->guest_context, i.XL.BO,
-                                        i.XL.BI, false, true);
+    bool test_passed = TestPpcCondition(&thread_info->guest_context, d.XL.BO(),
+                                        d.XL.BI(), false, true);
     return test_passed ? target_pc : current_pc + 4;
   } else {
     return current_pc + 4;
diff --git a/src/xenia/debug/ui/debug_window.cc b/src/xenia/debug/ui/debug_window.cc
index eb7ebda88..3eb971afe 100644
--- a/src/xenia/debug/ui/debug_window.cc
+++ b/src/xenia/debug/ui/debug_window.cc
@@ -25,7 +25,7 @@
 #include "xenia/base/platform.h"
 #include "xenia/base/string_util.h"
 #include "xenia/base/threading.h"
-#include "xenia/cpu/ppc/ppc_disasm.h"
+#include "xenia/cpu/ppc/ppc_opcode_info.h"
 #include "xenia/cpu/stack_walker.h"
 #include "xenia/gpu/graphics_system.h"
 #include "xenia/kernel/xmodule.h"
@@ -571,7 +571,7 @@ void DebugWindow::DrawMachineCodeSource(const uint8_t* machine_code_ptr,
 
     ImGui::Text("    %c ", is_current_instr ? '>' : ' ');
     ImGui::SameLine();
-    ImGui::Text(" %.8X        %-8s %s", uint32_t(insn.address), insn.mnemonic,
+    ImGui::Text(" %.8X        %-10s %s", uint32_t(insn.address), insn.mnemonic,
                 insn.op_str);
 
     if (is_current_instr) {
diff --git a/tools/ppc-instructions.xml b/tools/ppc-instructions.xml
index 4835193eb..059a0c829 100644
--- a/tools/ppc-instructions.xml
+++ b/tools/ppc-instructions.xml
@@ -1,466 +1,2928 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <root>
 <ppc-isa name="6xx_pem">
-  <insn mnem="addx"         opcode="7c000214" form="XO"       sub-form="D-A-B-OE-Rc"      group="i" desc="Add" />
-  <insn mnem="addcx"        opcode="7c000014" form="XO"       sub-form="D-A-B-OE-Rc"      group="i" desc="Add Carrying" />
-  <insn mnem="addex"        opcode="7c000114" form="XO"       sub-form="D-A-B-OE-Rc"      group="i" desc="Add Extended" />
-  <insn mnem="addi"         opcode="38000000" form="D"        sub-form="D-A-SIMM"         group="i" desc="Add Immediate" />
-  <insn mnem="addic"        opcode="30000000" form="D"        sub-form="D-A-SIMM"         group="i" desc="Add Immediate Carrying" />
-  <insn mnem="addic."       opcode="34000000" form="D"        sub-form="D-A-SIMM"         group="i" desc="Add Immediate Carrying and Record" />
-  <insn mnem="addis"        opcode="3c000000" form="D"        sub-form="D-A-SIMM"         group="i" desc="Add Immediate Shifted" />
-  <insn mnem="addmex"       opcode="7c0001d4" form="XO"       sub-form="D-A-0-OE-Rc"      group="i" desc="Add to Minus One Extended" />
-  <insn mnem="addzex"       opcode="7c000194" form="XO"       sub-form="D-A-0-OE-Rc"      group="i" desc="Add to Zero Extended" />
-  <insn mnem="andx"         opcode="7c000038" form="X"        sub-form="S-A-B-Rc"         group="i" desc="AND" />
-  <insn mnem="andcx"        opcode="7c000078" form="X"        sub-form="S-A-B-Rc"         group="i" desc="AND with Complement" />
-  <insn mnem="andi."        opcode="70000000" form="D"        sub-form="S-A-UIMM"         group="i" desc="AND Immediate" />
-  <insn mnem="andis."       opcode="74000000" form="D"        sub-form="S-A-UIMM"         group="i" desc="AND Immediate Shifted" />
-  <insn mnem="bx"           opcode="48000000" form="I"        sub-form="LI-AA-LK"         group="i" desc="Branch" sync="true" />
-  <insn mnem="bcx"          opcode="40000000" form="B"        sub-form="BO-BI-BD-AA-LK"   group="i" desc="Branch Conditional" sync="true" />
-  <insn mnem="bcctrx"       opcode="4c000420" form="XL"       sub-form="BO-BI-0-LK"       group="i" desc="Branch Conditional to Count Register" sync="true" />
-  <insn mnem="bclrx"        opcode="4c000020" form="XL"       sub-form="BO-BI-0-LK"       group="i" desc="Branch Conditional to Link Register" sync="true" />
-  <insn mnem="cmp"          opcode="7c000000" form="X"        sub-form="crfD-L-A-B"       group="i" desc="Compare" />
-  <insn mnem="cmpi"         opcode="2c000000" form="D"        sub-form="crfD-L-A-SIMM"    group="i" desc="Compare Immediate" />
-  <insn mnem="cmpl"         opcode="7c000040" form="X"        sub-form="crfD-L-A-B"       group="i" desc="Compare Logical" />
-  <insn mnem="cmpli"        opcode="28000000" form="D"        sub-form="crfD-L-A-UIMM"    group="i" desc="Compare Logical Immediate" />
-  <insn mnem="cntlzdx"      opcode="7c000074" form="X"        sub-form="S-A-0-Rc"         group="i" desc="Count Leading Zeros Doubleword" />
-  <insn mnem="cntlzwx"      opcode="7c000034" form="X"        sub-form="S-A-0-Rc"         group="i" desc="Count Leading Zeros Word" />
-  <insn mnem="crand"        opcode="4c000202" form="XL"       sub-form="crbD-crbA-crbB"   group="i" desc="Condition Register AND" />
-  <insn mnem="crandc"       opcode="4c000102" form="XL"       sub-form="crbD-crbA-crbB"   group="i" desc="Condition Register AND with Complement" />
-  <insn mnem="creqv"        opcode="4c000242" form="XL"       sub-form="crbD-crbA-crbB"   group="i" desc="Condition Register Equivalent" />
-  <insn mnem="crnand"       opcode="4c0001c2" form="XL"       sub-form="crbD-crbA-crbB"   group="i" desc="Condition Register NAND" />
-  <insn mnem="crnor"        opcode="4c000042" form="XL"       sub-form="crbD-crbA-crbB"   group="i" desc="Condition Register NOR" />
-  <insn mnem="cror"         opcode="4c000382" form="XL"       sub-form="crbD-crbA-crbB"   group="i" desc="Condition Register OR" />
-  <insn mnem="crorc"        opcode="4c000342" form="XL"       sub-form="crbD-crbA-crbB"   group="i" desc="Condition Register OR with Complement" />
-  <insn mnem="crxor"        opcode="4c000182" form="XL"       sub-form="crbD-crbA-crbB"   group="i" desc="Condition Register XOR" />
-  <insn mnem="dcba"         opcode="7c0005ec" form="X"        sub-form="0-A-B"            group="i" desc="Data Cache Block Allocate" />
-  <insn mnem="dcbf"         opcode="7c0000ac" form="X"        sub-form="0-A-B"            group="i" desc="Data Cache Block Flush" />
-  <insn mnem="dcbi"         opcode="7c0003ac" form="X"        sub-form="0-A-B"            group="i" desc="Data Cache Block Invalidate" />
-  <insn mnem="dcbst"        opcode="7c00006c" form="X"        sub-form="0-A-B"            group="i" desc="Data Cache Block Store" />
-  <insn mnem="dcbt"         opcode="7c00022c" form="X"        sub-form="0-A-B"            group="i" desc="Data Cache Block Touch" />
-  <insn mnem="dcbtst"       opcode="7c0001ec" form="X"        sub-form="0-A-B"            group="i" desc="Data Cache Block Touch for Store" />
-  <insn mnem="dcbz"         opcode="7c0007ec" form="DCBZ"     sub-form="0-A-B"            group="i" desc="Data Cache Block Clear to Zero" />
-  <insn mnem="dcbz128"      opcode="7c2007ec" form="DCBZ"     sub-form="0-A-B"            group="i" desc="Data Cache Block Clear to Zero 128" />
-  <insn mnem="divdx"        opcode="7c0003d2" form="XO"       sub-form="D-A-B-OE-Rc"      group="i" desc="Divide Doubleword" />
-  <insn mnem="divdux"       opcode="7c000392" form="XO"       sub-form="D-A-B-OE-Rc"      group="i" desc="Divide Doubleword Unsigned" />
-  <insn mnem="divwx"        opcode="7c0003d6" form="XO"       sub-form="D-A-B-OE-Rc"      group="i" desc="Divide Word" />
-  <insn mnem="divwux"       opcode="7c000396" form="XO"       sub-form="D-A-B-OE-Rc"      group="i" desc="Divide Word Unsigned" />
-  <insn mnem="eciwx"        opcode="7c00026c" form="X"        sub-form="D-A-B"            group="i" desc="External Control In Word Indexed" />
-  <insn mnem="ecowx"        opcode="7c00036c" form="X"        sub-form="S-A-B"            group="i" desc="External Control Out Word Indexed" />
-  <insn mnem="eieio"        opcode="7c0006ac" form="X"        sub-form="0-0-0"            group="i" desc="Enforce In-Order Execution of I/O" />
-  <insn mnem="eqvx"         opcode="7c000238" form="X"        sub-form="S-A-B-Rc"         group="i" desc="Equivalent" />
-  <insn mnem="extsbx"       opcode="7c000774" form="X"        sub-form="S-A-0-Rc"         group="i" desc="Extend Sign Byte" />
-  <insn mnem="extshx"       opcode="7c000734" form="X"        sub-form="S-A-0-Rc"         group="i" desc="Extend Sign Half Word" />
-  <insn mnem="extswx"       opcode="7c0007B4" form="X"        sub-form="S-A-0-Rc"         group="i" desc="Extend Sign Word" />
-  <insn mnem="fabsx"        opcode="fc000210" form="X"        sub-form="D-0-B-Rc"         group="f" desc="Floating Absolute Value" />
-  <insn mnem="faddx"        opcode="fc00002a" form="A"        sub-form="D-A-B-0-Rc"       group="f" desc="Floating Add" />
-  <insn mnem="faddsx"       opcode="ec00002a" form="A"        sub-form="D-A-B-0-Rc"       group="f" desc="Floating Add Single" />
-  <insn mnem="fcfidx"       opcode="FC00069C" form="X"        sub-form="D-A-B-Rc"         group="f" desc="Floating Convert From Integer Doubleword" />
-  <insn mnem="fcmpo"        opcode="fc000040" form="X"        sub-form="crfD-A-B"         group="f" desc="Floating Compare Ordered" />
-  <insn mnem="fcmpu"        opcode="fc000000" form="X"        sub-form="crfD-A-B"         group="f" desc="Floating Compare Unordered" />
-  <insn mnem="fctidx"       opcode="fc00065c" form="X"        sub-form="D-0-B-Rc"         group="f" desc="Floating Convert to Integer Doubleword" />
-  <insn mnem="fctidzx"      opcode="fc00065e" form="X"        sub-form="D-0-B-Rc"         group="f" desc="Floating Convert to Integer Doubleword with Round Toward Zero" />
-  <insn mnem="fctiwx"       opcode="fc00001c" form="X"        sub-form="D-0-B-Rc"         group="f" desc="Floating Convert to Integer Word" />
-  <insn mnem="fctiwzx"      opcode="fc00001e" form="X"        sub-form="D-0-B-Rc"         group="f" desc="Floating Convert to Integer Word with Round Toward Zero" />
-  <insn mnem="fdivx"        opcode="fc000024" form="A"        sub-form="D-A-B-0-Rc"       group="f" desc="Floating Divide" />
-  <insn mnem="fdivsx"       opcode="ec000024" form="A"        sub-form="D-A-B-0-Rc"       group="f" desc="Floating Divide Single" />
-  <insn mnem="fmaddx"       opcode="fc00003a" form="A"        sub-form="D-A-B-C-Rc"       group="f" desc="Floating Multiply-Add" />
-  <insn mnem="fmaddsx"      opcode="ec00003a" form="A"        sub-form="D-A-B-C-Rc"       group="f" desc="Floating Multiply-Add Single" />
-  <insn mnem="fmrx"         opcode="fc000090" form="X"        sub-form="D-0-B-Rc"         group="f" desc="Floating Move Register" />
-  <insn mnem="fmsubx"       opcode="fc000038" form="A"        sub-form="D-A-B-C-Rc"       group="f" desc="Floating Multiply-Subtract" />
-  <insn mnem="fmsubsx"      opcode="ec000038" form="A"        sub-form="D-A-B-C-Rc"       group="f" desc="Floating Multiply-Subtract Single" />
-  <insn mnem="fmulx"        opcode="fc000032" form="A"        sub-form="D-A-0-C-Rc"       group="f" desc="Floating Multiply" />
-  <insn mnem="fmulsx"       opcode="ec000032" form="A"        sub-form="D-A-0-C-Rc"       group="f" desc="Floating Multiply Single" />
-  <insn mnem="fnabsx"       opcode="fc000110" form="X"        sub-form="D-0-B-Rc"         group="f" desc="Floating Negative Absolute Value" />
-  <insn mnem="fnegx"        opcode="fc000050" form="X"        sub-form="D-0-B-Rc"         group="f" desc="Floating Negate" />
-  <insn mnem="fnmaddx"      opcode="fc00003e" form="A"        sub-form="D-A-B-C-Rc"       group="f" desc="Floating Negative Multiply-Add" />
-  <insn mnem="fnmaddsx"     opcode="ec00003e" form="A"        sub-form="D-A-B-C-Rc"       group="f" desc="Floating Negative Multiply-Add Single" />
-  <insn mnem="fnmsubx"      opcode="fc00003c" form="A"        sub-form="D-A-B-C-Rc"       group="f" desc="Floating Negative Multiply-Subtract" />
-  <insn mnem="fnmsubsx"     opcode="ec00003c" form="A"        sub-form="D-A-B-C-Rc"       group="f" desc="Floating Negative Multiply-Subtract Single" />
-  <insn mnem="fresx"        opcode="ec000030" form="A"        sub-form="D-0-B-0-Rc"       group="f" desc="Floating Reciprocal Estimate Single" />
-  <insn mnem="frspx"        opcode="fc000018" form="X"        sub-form="D-0-B-Rc"         group="f" desc="Floating Round to Single" />
-  <insn mnem="frsqrtex"     opcode="fc000034" form="A"        sub-form="D-0-B-0-Rc"       group="f" desc="Floating Reciprocal Square Root Estimate" />
-  <insn mnem="fselx"        opcode="fc00002e" form="A"        sub-form="D-A-B-C-Rc"       group="f" desc="Floating Select" />
-  <insn mnem="fsqrtx"       opcode="fc00002c" form="A"        sub-form="D-0-B-0-Rc"       group="f" desc="Floating Square Root" />
-  <insn mnem="fsqrtsx"      opcode="ec00002c" form="A"        sub-form="D-0-B-0-Rc"       group="f" desc="Floating Square Root Single" />
-  <insn mnem="fsubx"        opcode="fc000028" form="A"        sub-form="D-A-B-0-Rc"       group="f" desc="Floating Subtract" />
-  <insn mnem="fsubsx"       opcode="ec000028" form="A"        sub-form="D-A-B-0-Rc"       group="f" desc="Floating Subtract Single" />
-  <insn mnem="icbi"         opcode="7c0007ac" form="X"        sub-form="0-A-B"            group="i" desc="Instruction Cache Block Invalidate" />
-  <insn mnem="isync"        opcode="4c00012c" form="XL"       sub-form="0-0-0"            group="i" desc="Instruction Synchronize" />
-  <insn mnem="lbz"          opcode="88000000" form="D"        sub-form="D-A-d"            group="i" desc="Load Byte and Zero" />
-  <insn mnem="lbzu"         opcode="8c000000" form="D"        sub-form="D-A-d"            group="i" desc="Load Byte and Zero with Update" />
-  <insn mnem="lbzux"        opcode="7c0000ee" form="X"        sub-form="D-A-B"            group="i" desc="Load Byte and Zero with Update Indexed" />
-  <insn mnem="lbzx"         opcode="7c0000ae" form="X"        sub-form="D-A-B"            group="i" desc="Load Byte and Zero Indexed" />
-  <insn mnem="ld"           opcode="E8000000" form="DS"       sub-form="D-A-d"            group="i" desc="Load Doubleword" />
-  <insn mnem="ldarx"        opcode="7C0000A8" form="X"        sub-form="D-A-B"            group="i" desc="Load Doubleword and Reserve Indexed" />
-  <insn mnem="ldbrx"        opcode="7C000428" form="X"        sub-form="D-A-B"            group="i" desc="Load Doubleword Byte-Reverse Indexed" />
-  <insn mnem="ldu"          opcode="E8000001" form="DS"       sub-form="D-A-d"            group="i" desc="Load Doubleword with Update" />
-  <insn mnem="ldux"         opcode="7c00006a" form="X"        sub-form="D-A-B"            group="i" desc="Load Doubleword with Update Indexed" />
-  <insn mnem="ldx"          opcode="7c00002a" form="X"        sub-form="D-A-B"            group="i" desc="Load Doubleword Indexed" />
-  <insn mnem="lfd"          opcode="c8000000" form="D"        sub-form="D-A-d"            group="f" desc="Load Floating-Point Double" />
-  <insn mnem="lfdu"         opcode="cc000000" form="D"        sub-form="D-A-d"            group="f" desc="Load Floating-Point Double with Update" />
-  <insn mnem="lfdux"        opcode="7c0004ee" form="X"        sub-form="D-A-B"            group="f" desc="Load Floating-Point Double with Update Indexed" />
-  <insn mnem="lfdx"         opcode="7c0004ae" form="X"        sub-form="D-A-B"            group="f" desc="Load Floating-Point Double Indexed" />
-  <insn mnem="lfs"          opcode="c0000000" form="D"        sub-form="D-A-d"            group="f" desc="Load Floating-Point Single" />
-  <insn mnem="lfsu"         opcode="c4000000" form="D"        sub-form="D-A-d"            group="f" desc="Load Floating-Point Single with Update" />
-  <insn mnem="lfsux"        opcode="7c00046e" form="X"        sub-form="D-A-B"            group="f" desc="Load Floating-Point Single with Update Indexed" />
-  <insn mnem="lfsx"         opcode="7c00042e" form="X"        sub-form="D-A-B"            group="f" desc="Load Floating-Point Single Indexed" />
-  <insn mnem="lha"          opcode="a8000000" form="D"        sub-form="D-A-d"            group="i" desc="Load Half Word Algebraic" />
-  <insn mnem="lhau"         opcode="ac000000" form="D"        sub-form="D-A-d"            group="i" desc="Load Half Word Algebraic with Update" />
-  <insn mnem="lhaux"        opcode="7c0002ee" form="X"        sub-form="D-A-B"            group="i" desc="Load Half Word Algebraic with Update Indexed" />
-  <insn mnem="lhax"         opcode="7c0002ae" form="X"        sub-form="D-A-B"            group="i" desc="Load Half Word Algebraic Indexed" />
-  <insn mnem="lhbrx"        opcode="7c00062c" form="X"        sub-form="D-A-B"            group="i" desc="Load Half Word Byte-Reverse Indexed" />
-  <insn mnem="lhz"          opcode="a0000000" form="D"        sub-form="D-A-d"            group="i" desc="Load Half Word and Zero" />
-  <insn mnem="lhzu"         opcode="a4000000" form="D"        sub-form="D-A-d"            group="i" desc="Load Half Word and Zero with Update" />
-  <insn mnem="lhzux"        opcode="7c00026e" form="X"        sub-form="D-A-B"            group="i" desc="Load Half Word and Zero with Update Indexed" />
-  <insn mnem="lhzx"         opcode="7c00022e" form="X"        sub-form="D-A-B"            group="i" desc="Load Half Word and Zero Indexed" />
-  <insn mnem="lmw"          opcode="b8000000" form="D"        sub-form="D-A-d"            group="i" desc="Load Multiple Word" />
-  <insn mnem="lswi"         opcode="7c0004aa" form="X"        sub-form="D-A-NB"           group="i" desc="Load String Word Immediate" />
-  <insn mnem="lswx"         opcode="7c00042a" form="X"        sub-form="D-A-B"            group="i" desc="Load String Word Indexed" />
-  <insn mnem="lvebx"        opcode="7c00000e" form="X"        sub-form="D-A-B"            group="v" desc="Load Vector Element Byte Indexed" />
-  <insn mnem="lvehx"        opcode="7c00004e" form="X"        sub-form="D-A-B"            group="v" desc="Load Vector Element Half Word Indexed" />
-  <insn mnem="lvewx"        opcode="7c00008e" form="X"        sub-form="D-A-B"            group="v" desc="Load Vector Element Word Indexed" />
-  <insn mnem="lvewx128"     opcode="10000083" form="VX128_1"  sub-form="D-A-B"            group="v" desc="Load Vector Element Word Indexed 128" />
-  <insn mnem="lvsl"         opcode="7c00000c" form="X"        sub-form="D-A-B"            group="v" desc="Load Vector for Shift Left Indexed" />
-  <insn mnem="lvsl128"      opcode="10000003" form="VX128_1"  sub-form="D-A-B"            group="v" desc="Load Vector for Shift Left Indexed 128" />
-  <insn mnem="lvsr"         opcode="7c00004c" form="X"        sub-form="D-A-B"            group="v" desc="Load Vector for Shift Right Indexed" />
-  <insn mnem="lvsr128"      opcode="10000043" form="VX128_1"  sub-form="D-A-B"            group="v" desc="Load Vector for Shift Right Indexed 128" />
-  <insn mnem="lvx"          opcode="7c0000ce" form="X"        sub-form="D-A-B"            group="v" desc="Load Vector Indexed" />
-  <insn mnem="lvx128"       opcode="100000C3" form="VX128_1"  sub-form="D-A-B"            group="v" desc="Load Vector Indexed 128" />
-  <insn mnem="lvxl"         opcode="7c0002ce" form="X"        sub-form="D-A-B"            group="v" desc="Load Vector Indexed LRU" />
-  <insn mnem="lvxl128"      opcode="100002C3" form="VX128_1"  sub-form="D-A-B"            group="v" desc="Load Vector Indexed LRU 128" />
-  <insn mnem="lvlx"         opcode="7C00040E" form="X"        sub-form="D-A-B"            group="v" desc="Load Vector Left Indexed" />
-  <insn mnem="lvlx128"      opcode="10000403" form="VX128_1"  sub-form="D-A-B"            group="v" desc="Load Vector Left Indexed 128" />
-  <insn mnem="lvlxl"        opcode="7C00060E" form="X"        sub-form="D-A-B"            group="v" desc="Load Vector Left Indexed LRU" />
-  <insn mnem="lvlxl128"     opcode="10000603" form="VX128_1"  sub-form="D-A-B"            group="v" desc="Load Vector Left Indexed LRU 128" />
-  <insn mnem="lvrx"         opcode="7C00044E" form="X"        sub-form="D-A-B"            group="v" desc="Load Vector Right Indexed" />
-  <insn mnem="lvrx128"      opcode="10000443" form="VX128_1"  sub-form="D-A-B"            group="v" desc="Load Vector Right Indexed 128" />
-  <insn mnem="lvrxl"        opcode="7C00064E" form="X"        sub-form="D-A-B"            group="v" desc="Load Vector Right Indexed LRU" />
-  <insn mnem="lvrxl128"     opcode="10000643" form="VX128_1"  sub-form="D-A-B"            group="v" desc="Load Vector Right Indexed LRU 128" />
-  <insn mnem="lwa"          opcode="e8000002" form="DS"       sub-form="D-A-d"            group="i" desc="Load Word Algebraic" />
-  <insn mnem="lwarx"        opcode="7c000028" form="X"        sub-form="D-A-B"            group="i" desc="Load Word and Reserve Indexed" />
-  <insn mnem="lwaux"        opcode="7c0002ea" form="X"        sub-form="D-A-B"            group="i" desc="Load Word Algebraic with Update Indexed" />
-  <insn mnem="lwax"         opcode="7c0002aa" form="X"        sub-form="D-A-B"            group="i" desc="Load Word Algebraic Indexed" />
-  <insn mnem="lwbrx"        opcode="7c00042c" form="X"        sub-form="D-A-B"            group="i" desc="Load Word Byte-Reverse Indexed" />
-  <insn mnem="lwz"          opcode="80000000" form="D"        sub-form="D-A-d"            group="i" desc="Load Word and Zero" />
-  <insn mnem="lwzu"         opcode="84000000" form="D"        sub-form="D-A-d"            group="i" desc="Load Word and Zero with Update" />
-  <insn mnem="lwzux"        opcode="7c00006e" form="X"        sub-form="D-A-B"            group="i" desc="Load Word and Zero with Update Indexed" />
-  <insn mnem="lwzx"         opcode="7c00002e" form="X"        sub-form="D-A-B"            group="i" desc="Load Word and Zero Indexed" />
-  <insn mnem="mcrf"         opcode="4c000000" form="XL"       sub-form="crfD-crfS-0"      group="i" desc="Move Condition Register Field" />
-  <insn mnem="mcrfs"        opcode="fc000080" form="X"        sub-form="crfD-crfS-0"      group="f" desc="Move to Condition Register from FPSCR" />
-  <insn mnem="mcrxr"        opcode="7c000400" form="X"        sub-form="crfD-0-0"         group="i" desc="Move to Condition Register from XER" />
-  <insn mnem="mfcr"         opcode="7c000026" form="X"        sub-form="D-0-0"            group="i" desc="Move from Condition Register" />
-  <insn mnem="mffsx"        opcode="fc00048e" form="X"        sub-form="D-0-0-Rc"         group="f" desc="Move from FPSCR" />
-  <insn mnem="mfmsr"        opcode="7c0000a6" form="X"        sub-form="D-0-0"            group="i" desc="Move from Machine State Register" />
-  <insn mnem="mfspr"        opcode="7c0002a6" form="XFX"      sub-form="D-spr"            group="i" desc="Move from Special-Purpose Register" />
-  <insn mnem="mftb"         opcode="7c0002e6" form="XFX"      sub-form="D-tbr"            group="i" desc="Move from Time Base" />
-  <insn mnem="mfvscr"       opcode="10000604" form="VX"       sub-form="D-0-0"            group="i" desc="Move from VSCR" />
-  <insn mnem="mtcrf"        opcode="7c000120" form="XFX"      sub-form="S-CRM"            group="i" desc="Move to Condition Register Fields" />
-  <insn mnem="mtfsb0x"      opcode="fc00008c" form="X"        sub-form="crbD-0-0-Rc"      group="f" desc="Move to FPSCR Bit 0" />
-  <insn mnem="mtfsb1x"      opcode="fc00004c" form="X"        sub-form="crbD-0-0-Rc"      group="f" desc="Move to FPSCR Bit 1" />
-  <insn mnem="mtfsfx"       opcode="fc00058e" form="XFL"      sub-form="FM-B-Rc"          group="f" desc="Move to FPSCR Fields" />
-  <insn mnem="mtfsfix"      opcode="fc00010c" form="X"        sub-form="crfD-0-IMM-Rc"    group="f" desc="Move to FPSCR Field Immediate" />
-  <insn mnem="mtmsr"        opcode="7c000124" form="X"        sub-form="S-0-0"            group="i" desc="Move to Machine State Register" />
-  <insn mnem="mtmsrd"       opcode="7c000164" form="X"        sub-form="S-0-0"            group="i" desc="Move to Machine State Register Doubleword" />
-  <insn mnem="mtspr"        opcode="7c0003a6" form="XFX"      sub-form="S-spr"            group="i" desc="Move to Special-Purpose Register" />
-  <insn mnem="mtvscr"       opcode="10000644" form="VX"       sub-form="S-0-0"            group="i" desc="Move to VSCR" />
-  <insn mnem="mulhdx"       opcode="7c000092" form="XO"       sub-form="D-A-B-Rc"         group="i" desc="Multiply High Doubleword" />
-  <insn mnem="mulhdux"      opcode="7c000012" form="XO"       sub-form="D-A-B-Rc"         group="i" desc="Multiply High Doubleword Unsigned" />
-  <insn mnem="mulhwx"       opcode="7c000096" form="XO"       sub-form="D-A-B-Rc"         group="i" desc="Multiply High Word" />
-  <insn mnem="mulhwux"      opcode="7c000016" form="XO"       sub-form="D-A-B-Rc"         group="i" desc="Multiply High Word Unsigned" />
-  <insn mnem="mulldx"       opcode="7c0001d2" form="XO"       sub-form="D-A-B-OE-Rc"      group="i" desc="Multiply Low Doubleword" />
-  <insn mnem="mulli"        opcode="1c000000" form="D"        sub-form="D-A-SIMM"         group="i" desc="Multiply Low Immediate" />
-  <insn mnem="mullwx"       opcode="7c0001d6" form="XO"       sub-form="D-A-B-OE-Rc"      group="i" desc="Multiply Low Word" />
-  <insn mnem="nandx"        opcode="7c0003b8" form="X"        sub-form="S-A-B-Rc"         group="i" desc="NAND" />
-  <insn mnem="negx"         opcode="7c0000d0" form="XO"       sub-form="D-A-0-OE-Rc"      group="i" desc="Negate" />
-  <insn mnem="norx"         opcode="7c0000f8" form="X"        sub-form="S-A-B-Rc"         group="i" desc="NOR" />
-  <insn mnem="orx"          opcode="7c000378" form="X"        sub-form="S-A-B-Rc"         group="i" desc="OR" />
-  <insn mnem="orcx"         opcode="7c000338" form="X"        sub-form="S-A-B-Rc"         group="i" desc="OR with Complement" />
-  <insn mnem="ori"          opcode="60000000" form="D"        sub-form="S-A-UIMM"         group="i" desc="OR Immediate" />
-  <insn mnem="oris"         opcode="64000000" form="D"        sub-form="S-A-UIMM"         group="i" desc="OR Immediate Shifted" />
-  <insn mnem="rldclx"       opcode="78000010" form="MDS"      sub-form="S-A-B-MB-ME-Rc"   group="i" desc="Rotate Left Doubleword then Clear Left" />
-  <insn mnem="rldcrx"       opcode="78000012" form="MDS"      sub-form="S-A-B-MB-ME-Rc"   group="i" desc="Rotate Left Doubleword then Clear Right" />
-  <insn mnem="rldicx"       opcode="78000008" form="MDSH"     sub-form="S-A-SH-MB-ME-Rc"  group="i" desc="Rotate Left Doubleword Immediate then Clear" />
-  <insn mnem="rldiclx"      opcode="78000000" form="MDSH"     sub-form="S-A-SH-MB-ME-Rc"  group="i" desc="Rotate Left Doubleword Immediate then Clear Left" />
-  <insn mnem="rldicrx"      opcode="78000004" form="MDSH"     sub-form="S-A-SH-MB-ME-Rc"  group="i" desc="Rotate Left Doubleword Immediate then Clear Right" />
-  <insn mnem="rldimix"      opcode="7800000C" form="MDSH"     sub-form="S-A-SH-MB-ME-Rc"  group="i" desc="Rotate Left Doubleword Immediate then Mask Insert" />
-  <insn mnem="rlwimix"      opcode="50000000" form="M"        sub-form="S-A-SH-MB-ME-Rc"  group="i" desc="Rotate Left Word Immediate then Mask Insert" />
-  <insn mnem="rlwinmx"      opcode="54000000" form="M"        sub-form="S-A-SH-MB-ME-Rc"  group="i" desc="Rotate Left Word Immediate then AND with Mask" />
-  <insn mnem="rlwnmx"       opcode="5c000000" form="M"        sub-form="S-A-SH-MB-ME-Rc"  group="i" desc="Rotate Left Word then AND with Mask" />
-  <insn mnem="sc"           opcode="44000002" form="SC"       sub-form="sc"               group="i" desc="System Call" sync="true" />
-  <insn mnem="sldx"         opcode="7c000036" form="X"        sub-form="S-A-B-Rc"         group="i" desc="Shift Left Doubleword" />
-  <insn mnem="slwx"         opcode="7c000030" form="X"        sub-form="S-A-B-Rc"         group="i" desc="Shift Left Word" />
-  <insn mnem="sradx"        opcode="7c000634" form="X"        sub-form="S-A-B-Rc"         group="i" desc="Shift Right Algebraic Doubleword" />
-  <insn mnem="sradix"       opcode="7c000674" form="XS"       sub-form="S-A-SH-Rc"        group="i" desc="Shift Right Algebraic Doubleword Immediate" />
-  <insn mnem="srawx"        opcode="7c000630" form="X"        sub-form="S-A-B-Rc"         group="i" desc="Shift Right Algebraic Word" />
-  <insn mnem="srawix"       opcode="7c000670" form="X"        sub-form="S-A-SH-Rc"        group="i" desc="Shift Right Algebraic Word Immediate" />
-  <insn mnem="srdx"         opcode="7c000436" form="X"        sub-form="S-A-B-Rc"         group="i" desc="Shift Right Doubleword" />
-  <insn mnem="srwx"         opcode="7c000430" form="X"        sub-form="S-A-B-Rc"         group="i" desc="Shift Right Word" />
-  <insn mnem="stb"          opcode="98000000" form="D"        sub-form="S-A-d"            group="i" desc="Store Byte" />
-  <insn mnem="stbu"         opcode="9c000000" form="D"        sub-form="S-A-d"            group="i" desc="Store Byte with Update" />
-  <insn mnem="stbux"        opcode="7c0001ee" form="X"        sub-form="S-A-B"            group="i" desc="Store Byte with Update Indexed" />
-  <insn mnem="stbx"         opcode="7c0001ae" form="X"        sub-form="S-A-B"            group="i" desc="Store Byte Indexed" />
-  <insn mnem="std"          opcode="f8000000" form="DS"       sub-form="S-A-d"            group="i" desc="Store Doubleword" />
-  <insn mnem="stdbrx"       opcode="7c000528" form="X"        sub-form="S-A-B"            group="i" desc="Store Doubleword Byte-Reverse Indexed" />
-  <insn mnem="stdcx"        opcode="7c0001ad" form="X"        sub-form="S-A-B-1"          group="i" desc="Store Doubleword Conditional Indexed" />
-  <insn mnem="stdu"         opcode="f8000001" form="DS"       sub-form="S-A-d"            group="i" desc="Store Doubleword with Update" />
-  <insn mnem="stdux"        opcode="7c00016a" form="X"        sub-form="S-A-B"            group="i" desc="Store Doubleword with Update Indexed" />
-  <insn mnem="stdx"         opcode="7c00012a" form="X"        sub-form="S-A-B"            group="i" desc="Store Doubleword Indexed" />
-  <insn mnem="stfd"         opcode="d8000000" form="D"        sub-form="S-A-d"            group="f" desc="Store Floating-Point Double" />
-  <insn mnem="stfdu"        opcode="dc000000" form="D"        sub-form="S-A-d"            group="f" desc="Store Floating-Point Double with Update" />
-  <insn mnem="stfdux"       opcode="7c0005ee" form="X"        sub-form="S-A-B"            group="f" desc="Store Floating-Point Double with Update Indexed" />
-  <insn mnem="stfdx"        opcode="7c0005ae" form="X"        sub-form="S-A-B"            group="f" desc="Store Floating-Point Double Indexed" />
-  <insn mnem="stfiwx"       opcode="7c0007ae" form="X"        sub-form="S-A-B"            group="f" desc="Store Floating-Point as Integer Word Indexed" />
-  <insn mnem="stfs"         opcode="d0000000" form="D"        sub-form="S-A-d"            group="f" desc="Store Floating-Point Single" />
-  <insn mnem="stfsu"        opcode="d4000000" form="D"        sub-form="S-A-d"            group="f" desc="Store Floating-Point Single with Update" />
-  <insn mnem="stfsux"       opcode="7c00056e" form="X"        sub-form="S-A-B"            group="f" desc="Store Floating-Point Single with Update Indexed" />
-  <insn mnem="stfsx"        opcode="7c00052e" form="X"        sub-form="S-A-B"            group="f" desc="Store Floating-Point Single Indexed" />
-  <insn mnem="sth"          opcode="b0000000" form="D"        sub-form="S-A-d"            group="i" desc="Store Half Word" />
-  <insn mnem="sthbrx"       opcode="7c00072c" form="X"        sub-form="S-A-B"            group="i" desc="Store Half Word Byte-Reverse Indexed" />
-  <insn mnem="sthu"         opcode="b4000000" form="D"        sub-form="S-A-d"            group="i" desc="Store Half Word with Update" />
-  <insn mnem="sthux"        opcode="7c00036e" form="X"        sub-form="S-A-B"            group="i" desc="Store Half Word with Update Indexed" />
-  <insn mnem="sthx"         opcode="7c00032e" form="X"        sub-form="S-A-B"            group="i" desc="Store Half Word Indexed" />
-  <insn mnem="stmw"         opcode="bc000000" form="D"        sub-form="S-A-d"            group="i" desc="Store Multiple Word" />
-  <insn mnem="stswi"        opcode="7c0005aa" form="X"        sub-form="S-A-NB"           group="i" desc="Store String Word Immediate" />
-  <insn mnem="stswx"        opcode="7c00052a" form="X"        sub-form="S-A-B"            group="i" desc="Store String Word Indexed" />
-  <insn mnem="stvebx"       opcode="7c00010e" form="X"        sub-form="S-A-B"            group="v" desc="Store Vector Element Byte Indexed" />
-  <insn mnem="stvehx"       opcode="7c00014e" form="X"        sub-form="S-A-B"            group="v" desc="Store Vector Element Half Word Indexed" />
-  <insn mnem="stvewx"       opcode="7c00018e" form="X"        sub-form="S-A-B"            group="v" desc="Store Vector Element Word Indexed" />
-  <insn mnem="stvewx128"    opcode="10000183" form="VX128_1"  sub-form="S-A-B"            group="v" desc="Store Vector Element Word Indexed 128" />
-  <insn mnem="stvx"         opcode="7c0001ce" form="X"        sub-form="S-A-B"            group="v" desc="Store Vector Indexed" />
-  <insn mnem="stvx128"      opcode="100001c3" form="VX128_1"  sub-form="S-A-B"            group="v" desc="Store Vector Indexed 128" />
-  <insn mnem="stvxl"        opcode="7c0003ce" form="X"        sub-form="S-A-B"            group="v" desc="Store Vector Indexed LRU" />
-  <insn mnem="stvxl128"     opcode="100003c3" form="VX128_1"  sub-form="S-A-B"            group="v" desc="Store Vector Indexed LRU 128" />
-  <insn mnem="stvlx"        opcode="7c00050e" form="X"        sub-form="S-A-B"            group="v" desc="Store Vector Left Indexed" />
-  <insn mnem="stvlx128"     opcode="10000503" form="VX128_1"  sub-form="S-A-B"            group="v" desc="Store Vector Left Indexed 128" />
-  <insn mnem="stvlxl"       opcode="7c00070e" form="X"        sub-form="S-A-B"            group="v" desc="Store Vector Left Indexed LRU" />
-  <insn mnem="stvlxl128"    opcode="10000703" form="VX128_1"  sub-form="S-A-B"            group="v" desc="Store Vector Left Indexed LRU 128" />
-  <insn mnem="stvrx"        opcode="7c00054e" form="X"        sub-form="S-A-B"            group="v" desc="Store Vector Right Indexed" />
-  <insn mnem="stvrx128"     opcode="10000543" form="VX128_1"  sub-form="S-A-B"            group="v" desc="Store Vector Right Indexed 128" />
-  <insn mnem="stvrxl"       opcode="7c00074e" form="X"        sub-form="S-A-B"            group="v" desc="Store Vector Right Indexed LRU" />
-  <insn mnem="stvrxl128"    opcode="10000743" form="VX128_1"  sub-form="S-A-B"            group="v" desc="Store Vector Right Indexed LRU 128" />
-  <insn mnem="stw"          opcode="90000000" form="D"        sub-form="S-A-d"            group="i" desc="Store Word" />
-  <insn mnem="stwbrx"       opcode="7c00052c" form="X"        sub-form="S-A-B"            group="i" desc="Store Word Byte-Reverse Indexed" />
-  <insn mnem="stwcx"        opcode="7c00012d" form="X"        sub-form="S-A-B-1"          group="i" desc="Store Word Conditional Indexed" />
-  <insn mnem="stwu"         opcode="94000000" form="D"        sub-form="S-A-d"            group="i" desc="Store Word with Update" />
-  <insn mnem="stwux"        opcode="7c00016e" form="X"        sub-form="S-A-B"            group="i" desc="Store Word with Update Indexed" />
-  <insn mnem="stwx"         opcode="7c00012e" form="X"        sub-form="S-A-B"            group="i" desc="Store Word Indexed" />
-  <insn mnem="subfx"        opcode="7c000050" form="XO"       sub-form="D-A-B-OE-Rc"      group="i" desc="Subtract From" />
-  <insn mnem="subfcx"       opcode="7c000010" form="XO"       sub-form="D-A-B-OE-Rc"      group="i" desc="Subtract From Carrying" />
-  <insn mnem="subfex"       opcode="7c000110" form="XO"       sub-form="D-A-B-OE-Rc"      group="i" desc="Subtract From Extended" />
-  <insn mnem="subficx"      opcode="20000000" form="D"        sub-form="D-A-SIMM"         group="i" desc="Subtract From Immediate Carrying" />
-  <insn mnem="subfmex"      opcode="7c0001d0" form="XO"       sub-form="D-A-0-OE-Rc"      group="i" desc="Subtract From Minus One Extended" />
-  <insn mnem="subfzex"      opcode="7c000190" form="XO"       sub-form="D-A-0-OE-Rc"      group="i" desc="Subtract From Zero Extended" />
-  <insn mnem="sync"         opcode="7c0004ac" form="X"        sub-form="0-0-0"            group="i" desc="Synchronize" />
-  <insn mnem="td"           opcode="7c000088" form="X"        sub-form="TO-A-B"           group="i" desc="Trap Doubleword" />
-  <insn mnem="tdi"          opcode="08000000" form="D"        sub-form="TO-A-SIMM"        group="i" desc="Trap Doubleword Immediate" />
-  <insn mnem="tw"           opcode="7c000008" form="X"        sub-form="TO-A-B"           group="i" desc="Trap Word" />
-  <insn mnem="twi"          opcode="0c000000" form="D"        sub-form="TO-A-SIMM"        group="i" desc="Trap Word Immediate" />
-  <insn mnem="xorx"         opcode="7c000278" form="X"        sub-form="S-A-B-Rc"         group="i" desc="XOR" />
-  <insn mnem="xori"         opcode="68000000" form="D"        sub-form="S-A-UIMM"         group="i" desc="XOR Immediate" />
-  <insn mnem="xoris"        opcode="6c000000" form="D"        sub-form="S-A-UIMM"         group="i" desc="XOR Immediate Shifted" />
+  <!-- These match docs/ppc/core_instructions.pdf -->
+  <insn mnem="addx"         opcode="7c000214" form="XO"       group="i" desc="Add">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="OE" conditional="true" />
+    <out field="CR" conditional="true" />
+    <disasm>add[OE][Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="addcx"        opcode="7c000014" form="XO"       group="i" desc="Add Carrying">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="OE" conditional="true" />
+    <out field="CR" conditional="true" />
+    <disasm>addc[OE][Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="addex"        opcode="7c000114" form="XO"       group="i" desc="Add Extended">
+    <in field="RA" />
+    <in field="RB" />
+    <in field="CR" />
+    <out field="RD" />
+    <out field="OE" conditional="true" />
+    <out field="CR" conditional="true" />
+    <disasm>adde[OE][Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="addi"         opcode="38000000" form="D"        group="i" desc="Add Immediate">
+    <in field="RA0" />
+    <in field="SIMM" />
+    <out field="RD" />
+    <disasm>addi [RD], [RA0], [SIMM]</disasm>
+  </insn>
+  <insn mnem="addic"        opcode="30000000" form="D"        group="i" desc="Add Immediate Carrying">
+    <in field="RA" />
+    <in field="SIMM" />
+    <out field="RD" />
+    <out field="CA" />
+    <disasm>addic [RD], [RA], [SIMM]</disasm>
+  </insn>
+  <insn mnem="addic."       opcode="34000000" form="D"        group="i" desc="Add Immediate Carrying and Record">
+    <in field="RA" />
+    <in field="SIMM" />
+    <out field="RD" />
+    <out field="CA" />
+    <out field="CR" />
+    <disasm>addic. [RD], [RA], [SIMM]</disasm>
+  </insn>
+  <insn mnem="addis"        opcode="3c000000" form="D"        group="i" desc="Add Immediate Shifted">
+    <in field="RA0" />
+    <in field="SIMM" />
+    <out field="RD" />
+    <disasm>addis [RD], [RA0], [SIMM]</disasm>
+  </insn>
+  <insn mnem="addmex"       opcode="7c0001d4" form="XO"       group="i" desc="Add to Minus One Extended">
+    <in field="RA" />
+    <in field="CA" />
+    <out field="RD" />
+    <out field="CA" />
+    <out field="OE" conditional="true" />
+    <out field="CR" conditional="true" />
+    <disasm>addme[OE][Rc] [RD], [RA]</disasm>
+  </insn>
+  <insn mnem="addzex"       opcode="7c000194" form="XO"       group="i" desc="Add to Zero Extended">
+    <in field="RA" />
+    <in field="CA" />
+    <out field="RD" />
+    <out field="CA" />
+    <out field="OE" conditional="true" />
+    <out field="CR" conditional="true" />
+    <disasm>addze[OE][Rc] [RD], [RA]</disasm>
+  </insn>
+  <insn mnem="andx"         opcode="7c000038" form="X"        group="i" desc="AND">
+    <in field="RS" />
+    <in field="RB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>and[Rc] [RA], [RS], [RB]</disasm>
+  </insn>
+  <insn mnem="andcx"        opcode="7c000078" form="X"        group="i" desc="AND with Complement">
+    <in field="RS" />
+    <in field="RB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>andc[Rc] [RA], [RS], [RB]</disasm>
+  </insn>
+  <insn mnem="andi."        opcode="70000000" form="D"        group="i" desc="AND Immediate">
+    <in field="RS" />
+    <in field="UIMM" />
+    <out field="RA" />
+    <out field="CR" />
+    <disasm>andi. [RA], [RS], [UIMM]</disasm>
+  </insn>
+  <insn mnem="andis."       opcode="74000000" form="D"        group="i" desc="AND Immediate Shifted">
+    <in field="RS" />
+    <in field="UIMM" />
+    <out field="RA" />
+    <out field="CR" />
+    <disasm>andis. [RA], [RS], [UIMM]</disasm>
+  </insn>
+  <insn mnem="bx"           opcode="48000000" form="I"        group="i" desc="Branch" sync="true">
+    <in field="LK" />
+    <in field="AA" />
+    <in field="ADDR" />
+    <out field="LR" conditional="true" />
+    <disasm>b[LK][AA] [ADDR]</disasm>
+  </insn>
+  <insn mnem="bcx"          opcode="40000000" form="B"        group="i" desc="Branch Conditional" sync="true">
+    <in field="LK" />
+    <in field="AA" />
+    <in field="BO" />
+    <in field="BI" />
+    <in field="ADDR" />
+    <in field="CR" conditional="true" />
+    <in field="CTR" conditional="true" />
+    <out field="CTR" conditional="true" />
+    <out field="LR" conditional="true" />
+    <disasm>bc[LK][AA] [BO], [BI], [ADDR]</disasm>
+  </insn>
+  <insn mnem="bcctrx"       opcode="4c000420" form="XL"       group="i" desc="Branch Conditional to Count Register" sync="true">
+    <in field="LK" />
+    <in field="BO" />
+    <in field="BI" />
+    <in field="CR" />
+    <in field="CTR" />
+    <out field="LR" conditional="true" />
+    <disasm>bcctr[LK] [BO], [BI]</disasm>
+  </insn>
+  <insn mnem="bclrx"        opcode="4c000020" form="XL"       group="i" desc="Branch Conditional to Link Register" sync="true">
+    <in field="LK" />
+    <in field="BO" />
+    <in field="BI" />
+    <in field="CR" conditional="true" />
+    <in field="CTR" conditional="true" />
+    <out field="CTR" conditional="true" />
+    <out field="LR" conditional="true" />
+    <disasm>bclr[LK] [BO], [BI]</disasm>
+  </insn>
+  <insn mnem="cmp"          opcode="7c000000" form="X"        group="i" desc="Compare">
+    <in field="L" />
+    <in field="RA" />
+    <in field="RB" />
+    <out field="CRFD" />
+    <disasm>cmp [CRFD], [L], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="cmpi"         opcode="2c000000" form="D"        group="i" desc="Compare Immediate">
+    <in field="L" />
+    <in field="RA" />
+    <in field="SIMM" />
+    <out field="RD" />
+    <out field="CRFD" />
+    <disasm>cmpi [CRFD], [L], [RA], [SIMM]</disasm>
+  </insn>
+  <insn mnem="cmpl"         opcode="7c000040" form="X"        group="i" desc="Compare Logical">
+    <in field="L" />
+    <in field="RA" />
+    <in field="RB" />
+    <out field="CRFD" />
+    <disasm>cmpl [CRFD], [L], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="cmpli"        opcode="28000000" form="D"        group="i" desc="Compare Logical Immediate">
+    <in field="L" />
+    <in field="RA" />
+    <in field="UIMM" />
+    <out field="CRFD" />
+    <disasm>cmpli [CRFD], [L], [RA], [UIMM]</disasm>
+  </insn>
+  <insn mnem="cntlzdx"      opcode="7c000074" form="X"        group="i" desc="Count Leading Zeros Doubleword">
+    <in field="RS" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>cntlzd[Rc] [RA], [RS]</disasm>
+  </insn>
+  <insn mnem="cntlzwx"      opcode="7c000034" form="X"        group="i" desc="Count Leading Zeros Word">
+    <in field="RS" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>cntlzw[Rc] [RA], [RS]</disasm>
+  </insn>
+  <insn mnem="crand"        opcode="4c000202" form="XL"       group="i" desc="Condition Register AND">
+    <in field="CRBA" />
+    <in field="CRBB" />
+    <out field="CRBD" />
+    <disasm>crand [CRBD], [CRBA], [CRBB]</disasm>
+  </insn>
+  <insn mnem="crandc"       opcode="4c000102" form="XL"       group="i" desc="Condition Register AND with Complement">
+    <in field="CRBA" />
+    <in field="CRBB" />
+    <out field="CRBD" />
+    <disasm>crandc [CRBD], [CRBA], [CRBB]</disasm>
+  </insn>
+  <insn mnem="creqv"        opcode="4c000242" form="XL"       group="i" desc="Condition Register Equivalent">
+    <in field="CRBA" />
+    <in field="CRBB" />
+    <out field="CRBD" />
+    <disasm>creqv [CRBD], [CRBA], [CRBB]</disasm>
+  </insn>
+  <insn mnem="crnand"       opcode="4c0001c2" form="XL"       group="i" desc="Condition Register NAND">
+    <in field="CRBA" />
+    <in field="CRBB" />
+    <out field="CRBD" />
+    <disasm>crnand [CRBD], [CRBA], [CRBB]</disasm>
+  </insn>
+  <insn mnem="crnor"        opcode="4c000042" form="XL"       group="i" desc="Condition Register NOR">
+    <in field="CRBA" />
+    <in field="CRBB" />
+    <out field="CRBD" />
+    <disasm>crnor [CRBD], [CRBA], [CRBB]</disasm>
+  </insn>
+  <insn mnem="cror"         opcode="4c000382" form="XL"       group="i" desc="Condition Register OR">
+    <in field="CRBA" />
+    <in field="CRBB" />
+    <out field="CRBD" />
+    <disasm>cror [CRBD], [CRBA], [CRBB]</disasm>
+  </insn>
+  <insn mnem="crorc"        opcode="4c000342" form="XL"       group="i" desc="Condition Register OR with Complement">
+    <in field="CRBA" />
+    <in field="CRBB" />
+    <out field="CRBD" />
+    <disasm>crorc [CRBD], [CRBA], [CRBB]</disasm>
+  </insn>
+  <insn mnem="crxor"        opcode="4c000182" form="XL"       group="i" desc="Condition Register XOR">
+    <in field="CRBA" />
+    <in field="CRBB" />
+    <out field="CRBD" />
+    <disasm>crxor [CRBD], [CRBA], [CRBB]</disasm>
+  </insn>
+  <insn mnem="dcba"         opcode="7c0005ec" form="X"        group="i" desc="Data Cache Block Allocate">
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>dcba [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="dcbf"         opcode="7c0000ac" form="X"        group="i" desc="Data Cache Block Flush">
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>dcbf [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="dcbi"         opcode="7c0003ac" form="X"        group="i" desc="Data Cache Block Invalidate">
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>dcbi [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="dcbst"        opcode="7c00006c" form="X"        group="i" desc="Data Cache Block Store">
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>dcbst [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="dcbt"         opcode="7c00022c" form="X"        group="i" desc="Data Cache Block Touch">
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>dcbt [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="dcbtst"       opcode="7c0001ec" form="X"        group="i" desc="Data Cache Block Touch for Store">
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>dcbtst [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="dcbz"         opcode="7c0007ec" form="DCBZ"     group="i" desc="Data Cache Block Clear to Zero">
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>dcbz [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="dcbz128"      opcode="7c2007ec" form="DCBZ"     group="i" desc="Data Cache Block Clear to Zero 128">
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>dcbz128 [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="divdx"        opcode="7c0003d2" form="XO"       group="i" desc="Divide Doubleword">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="OE" conditional="true" />
+    <out field="CR" conditional="true" />
+    <disasm>divd[OE][Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="divdux"       opcode="7c000392" form="XO"       group="i" desc="Divide Doubleword Unsigned">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="OE" conditional="true" />
+    <out field="CR" conditional="true" />
+    <disasm>divdu[OE][Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="divwx"        opcode="7c0003d6" form="XO"       group="i" desc="Divide Word">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="OE" conditional="true" />
+    <out field="CR" conditional="true" />
+    <disasm>divw[OE][Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="divwux"       opcode="7c000396" form="XO"       group="i" desc="Divide Word Unsigned">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="OE" conditional="true" />
+    <out field="CR" conditional="true" />
+    <disasm>divwu[OE][Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="eieio"        opcode="7c0006ac" form="X"        group="i" desc="Enforce In-Order Execution of I/O">
+    <disasm>eieio</disasm>
+  </insn>
+  <insn mnem="eqvx"         opcode="7c000238" form="X"        group="i" desc="Equivalent">
+    <in field="RS" />
+    <in field="RB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>eqv[Rc] [RA], [RS], [RB]</disasm>
+  </insn>
+  <insn mnem="extsbx"       opcode="7c000774" form="X"        group="i" desc="Extend Sign Byte">
+    <in field="RS" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>extsb[Rc] [RA], [RS]</disasm>
+  </insn>
+  <insn mnem="extshx"       opcode="7c000734" form="X"        group="i" desc="Extend Sign Half Word">
+    <in field="RS" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>extsh[Rc] [RA], [RS]</disasm>
+  </insn>
+  <insn mnem="extswx"       opcode="7c0007B4" form="X"        group="i" desc="Extend Sign Word">
+    <in field="RS" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>extsw[Rc] [RA], [RS]</disasm>
+  </insn>
+  <insn mnem="fabsx"        opcode="fc000210" form="X"        group="f" desc="Floating Absolute Value">
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <disasm>fabs[Rc] [FD], [FB]</disasm>
+  </insn>
+  <insn mnem="faddx"        opcode="fc00002a" form="A"        group="f" desc="Floating Add">
+    <in field="FA" />
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fadd[Rc] [FD], [FA], [FB]</disasm>
+  </insn>
+  <insn mnem="faddsx"       opcode="ec00002a" form="A"        group="f" desc="Floating Add Single">
+    <in field="FA" />
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fadds[Rc] [FD], [FA], [FB]</disasm>
+  </insn>
+  <insn mnem="fcfidx"       opcode="FC00069C" form="X"        group="f" desc="Floating Convert From Integer Doubleword">
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fcfid[Rc] [FD], [FB]</disasm>
+  </insn>
+  <insn mnem="fcmpo"        opcode="fc000040" form="X"        group="f" desc="Floating Compare Ordered">
+    <in field="FA" />
+    <in field="FB" />
+    <out field="CRFD" />
+    <out field="FPSCR" />
+    <disasm>fcmpo [CRFD], [FA], [FB]</disasm>
+  </insn>
+  <insn mnem="fcmpu"        opcode="fc000000" form="X"        group="f" desc="Floating Compare Unordered">
+    <in field="FA" />
+    <in field="FB" />
+    <out field="CRFD" />
+    <out field="FPSCR" />
+    <disasm>fcmpu [CRFD], [FA], [FB]</disasm>
+  </insn>
+  <insn mnem="fctidx"       opcode="fc00065c" form="X"        group="f" desc="Floating Convert to Integer Doubleword">
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fctid[Rc] [FD], [FB]</disasm>
+  </insn>
+  <insn mnem="fctidzx"      opcode="fc00065e" form="X"        group="f" desc="Floating Convert to Integer Doubleword with Round Toward Zero">
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fctidz[Rc] [FD], [FB]</disasm>
+  </insn>
+  <insn mnem="fctiwx"       opcode="fc00001c" form="X"        group="f" desc="Floating Convert to Integer Word">
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fctiw[Rc] [FD], [FB]</disasm>
+  </insn>
+  <insn mnem="fctiwzx"      opcode="fc00001e" form="X"        group="f" desc="Floating Convert to Integer Word with Round Toward Zero">
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fctiwz[Rc] [FD], [FB]</disasm>
+  </insn>
+  <insn mnem="fdivx"        opcode="fc000024" form="A"        group="f" desc="Floating Divide">
+    <in field="FA" />
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fdiv[Rc] [FD], [FA], [FB]</disasm>
+  </insn>
+  <insn mnem="fdivsx"       opcode="ec000024" form="A"        group="f" desc="Floating Divide Single">
+    <in field="FA" />
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fdivs[Rc] [FD], [FA], [FB]</disasm>
+  </insn>
+  <insn mnem="fmaddx"       opcode="fc00003a" form="A"        group="f" desc="Floating Multiply-Add">
+    <in field="FA" />
+    <in field="FC" />
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fmadd[Rc] [FD], [FA], [FC], [FB]</disasm>
+  </insn>
+  <insn mnem="fmaddsx"      opcode="ec00003a" form="A"        group="f" desc="Floating Multiply-Add Single">
+    <in field="FA" />
+    <in field="FC" />
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fmadds[Rc] [FD], [FA], [FC], [FB]</disasm>
+  </insn>
+  <insn mnem="fmrx"         opcode="fc000090" form="X"        group="f" desc="Floating Move Register">
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <disasm>fmr[Rc] [FD], [FB]</disasm>
+  </insn>
+  <insn mnem="fmsubx"       opcode="fc000038" form="A"        group="f" desc="Floating Multiply-Subtract">
+    <in field="FA" />
+    <in field="FC" />
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fmsub[Rc] [FD], [FA], [FC], [FB]</disasm>
+  </insn>
+  <insn mnem="fmsubsx"      opcode="ec000038" form="A"        group="f" desc="Floating Multiply-Subtract Single">
+    <in field="FA" />
+    <in field="FC" />
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fmsubs[Rc] [FD], [FA], [FC], [FB]</disasm>
+  </insn>
+  <insn mnem="fmulx"        opcode="fc000032" form="A"        group="f" desc="Floating Multiply">
+    <in field="FA" />
+    <in field="FC" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fmul[Rc] [FD], [FA], [FC]</disasm>
+  </insn>
+  <insn mnem="fmulsx"       opcode="ec000032" form="A"        group="f" desc="Floating Multiply Single">
+    <in field="FA" />
+    <in field="FC" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fmuls[Rc] [FD], [FA], [FC]</disasm>
+  </insn>
+  <insn mnem="fnabsx"       opcode="fc000110" form="X"        group="f" desc="Floating Negative Absolute Value">
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <disasm>fnabs[Rc] [FD], [FB]</disasm>
+  </insn>
+  <insn mnem="fnegx"        opcode="fc000050" form="X"        group="f" desc="Floating Negate">
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <disasm>fneg[Rc] [FD], [FB]</disasm>
+  </insn>
+  <insn mnem="fnmaddx"      opcode="fc00003e" form="A"        group="f" desc="Floating Negative Multiply-Add">
+    <in field="FA" />
+    <in field="FC" />
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fnmadd[Rc] [FD], [FA], [FC], [FB]</disasm>
+  </insn>
+  <insn mnem="fnmaddsx"     opcode="ec00003e" form="A"        group="f" desc="Floating Negative Multiply-Add Single">
+    <in field="FA" />
+    <in field="FC" />
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fnmadds[Rc] [FD], [FA], [FC], [FB]</disasm>
+  </insn>
+  <insn mnem="fnmsubx"      opcode="fc00003c" form="A"        group="f" desc="Floating Negative Multiply-Subtract">
+    <in field="FA" />
+    <in field="FC" />
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fnmsub[Rc] [FD], [FA], [FC], [FB]</disasm>
+  </insn>
+  <insn mnem="fnmsubsx"     opcode="ec00003c" form="A"        group="f" desc="Floating Negative Multiply-Subtract Single">
+    <in field="FA" />
+    <in field="FC" />
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fnmsubs[Rc] [FD], [FA], [FC], [FB]</disasm>
+  </insn>
+  <insn mnem="fresx"        opcode="ec000030" form="A"        group="f" desc="Floating Reciprocal Estimate Single">
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fres[Rc] [FD], [FB]</disasm>
+  </insn>
+  <insn mnem="frspx"        opcode="fc000018" form="X"        group="f" desc="Floating Round to Single">
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>frsp[Rc] [FD], [FB]</disasm>
+  </insn>
+  <insn mnem="frsqrtex"     opcode="fc000034" form="A"        group="f" desc="Floating Reciprocal Square Root Estimate">
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>frsqrte[Rc] [FD], [FB]</disasm>
+  </insn>
+  <insn mnem="fselx"        opcode="fc00002e" form="A"        group="f" desc="Floating Select">
+    <in field="FA" />
+    <in field="FC" />
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <disasm>fsel[Rc] [FD], [FA], [FC], [FB]</disasm>
+  </insn>
+  <insn mnem="fsqrtx"       opcode="fc00002c" form="A"        group="f" desc="Floating Square Root">
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fsqrt[Rc] [FD], [FB]</disasm>
+  </insn>
+  <insn mnem="fsqrtsx"      opcode="ec00002c" form="A"        group="f" desc="Floating Square Root Single">
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fsqrts[Rc] [FD], [FB]</disasm>
+  </insn>
+  <insn mnem="fsubx"        opcode="fc000028" form="A"        group="f" desc="Floating Subtract">
+    <in field="FA" />
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fsub[Rc] [FD], [FA], [FB]</disasm>
+  </insn>
+  <insn mnem="fsubsx"       opcode="ec000028" form="A"        group="f" desc="Floating Subtract Single">
+    <in field="FA" />
+    <in field="FB" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <out field="FPSCR" />
+    <disasm>fsubs[Rc] [FD], [FA], [FB]</disasm>
+  </insn>
+  <insn mnem="icbi"         opcode="7c0007ac" form="X"        group="i" desc="Instruction Cache Block Invalidate">
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>icbi [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="isync"        opcode="4c00012c" form="XL"       group="i" desc="Instruction Synchronize">
+    <disasm>isync</disasm>
+  </insn>
+  <insn mnem="lbz"          opcode="88000000" form="D"        group="i" desc="Load Byte and Zero">
+    <in field="RA0" />
+    <in field="d" />
+    <out field="RD" />
+    <disasm>lbz [RD], [d]([RA0])</disasm>
+  </insn>
+  <insn mnem="lbzu"         opcode="8c000000" form="D"        group="i" desc="Load Byte and Zero with Update">
+    <in field="RA" />
+    <in field="d" />
+    <out field="RD" />
+    <out field="RA" />
+    <disasm>lbzu [RD], [d]([RA])</disasm>
+  </insn>
+  <insn mnem="lbzux"        opcode="7c0000ee" form="X"        group="i" desc="Load Byte and Zero with Update Indexed">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="RA" />
+    <disasm>lbzux [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="lbzx"         opcode="7c0000ae" form="X"        group="i" desc="Load Byte and Zero Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="RD" />
+    <disasm>lbzx [RD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="ld"           opcode="E8000000" form="DS"       group="i" desc="Load Doubleword">
+    <in field="RA0" />
+    <in field="ds" />
+    <out field="RD" />
+    <disasm>ld [RD], [ds]([RA0])</disasm>
+  </insn>
+  <insn mnem="ldarx"        opcode="7C0000A8" form="X"        group="i" desc="Load Doubleword and Reserve Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="RD" />
+    <disasm>ldarx [RD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="ldbrx"        opcode="7C000428" form="X"        group="i" desc="Load Doubleword Byte-Reverse Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="RD" />
+    <disasm>ldbrx [RD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="ldu"          opcode="E8000001" form="DS"       group="i" desc="Load Doubleword with Update">
+    <in field="RA" />
+    <in field="ds" />
+    <out field="RD" />
+    <out field="RA" />
+    <disasm>ldu [RD], [ds]([RA])</disasm>
+  </insn>
+  <insn mnem="ldux"         opcode="7c00006a" form="X"        group="i" desc="Load Doubleword with Update Indexed">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="RA" />
+    <disasm>ldux [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="ldx"          opcode="7c00002a" form="X"        group="i" desc="Load Doubleword Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="RD" />
+    <disasm>ldx [RD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lfd"          opcode="c8000000" form="D"        group="f" desc="Load Floating-Point Double">
+    <in field="RA0" />
+    <in field="d" />
+    <out field="FD" />
+    <disasm>lfd [FD], [d]([RA0])</disasm>
+  </insn>
+  <insn mnem="lfdu"         opcode="cc000000" form="D"        group="f" desc="Load Floating-Point Double with Update">
+    <in field="RA" />
+    <in field="d" />
+    <out field="FD" />
+    <out field="RA" />
+    <disasm>lfdu [FD], [d]([RA])</disasm>
+  </insn>
+  <insn mnem="lfdux"        opcode="7c0004ee" form="X"        group="f" desc="Load Floating-Point Double with Update Indexed">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="FD" />
+    <out field="RA" />
+    <disasm>lfdux [FD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="lfdx"         opcode="7c0004ae" form="X"        group="f" desc="Load Floating-Point Double Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="FD" />
+    <disasm>lfdx [FD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lfs"          opcode="c0000000" form="D"        group="f" desc="Load Floating-Point Single">
+    <in field="RA0" />
+    <in field="d" />
+    <out field="FD" />
+    <disasm>lfs [FD], [d]([RA0])</disasm>
+  </insn>
+  <insn mnem="lfsu"         opcode="c4000000" form="D"        group="f" desc="Load Floating-Point Single with Update">
+    <in field="RA" />
+    <in field="d" />
+    <out field="FD" />
+    <out field="RA" />
+    <disasm>lfsu [FD], [d]([RA])</disasm>
+  </insn>
+  <insn mnem="lfsux"        opcode="7c00046e" form="X"        group="f" desc="Load Floating-Point Single with Update Indexed">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="FD" />
+    <out field="RA" />
+    <disasm>lfsux [FD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="lfsx"         opcode="7c00042e" form="X"        group="f" desc="Load Floating-Point Single Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="FD" />
+    <disasm>lfsx [FD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lha"          opcode="a8000000" form="D"        group="i" desc="Load Half Word Algebraic">
+    <in field="RA0" />
+    <in field="d" />
+    <out field="RD" />
+    <disasm>lha [RD], [d]([RA0])</disasm>
+  </insn>
+  <insn mnem="lhau"         opcode="ac000000" form="D"        group="i" desc="Load Half Word Algebraic with Update">
+    <in field="RA" />
+    <in field="d" />
+    <out field="RD" />
+    <out field="RA" />
+    <disasm>lhau [RD], [d]([RA])</disasm>
+  </insn>
+  <insn mnem="lhaux"        opcode="7c0002ee" form="X"        group="i" desc="Load Half Word Algebraic with Update Indexed">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="RA" />
+    <disasm>lhaux [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="lhax"         opcode="7c0002ae" form="X"        group="i" desc="Load Half Word Algebraic Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="RD" />
+    <disasm>lhax [RD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lhbrx"        opcode="7c00062c" form="X"        group="i" desc="Load Half Word Byte-Reverse Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="RD" />
+    <disasm>lhbrx [RD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lhz"          opcode="a0000000" form="D"        group="i" desc="Load Half Word and Zero">
+    <in field="RA0" />
+    <in field="d" />
+    <out field="RD" />
+    <disasm>lhz [RD], [d]([RA0])</disasm>
+  </insn>
+  <insn mnem="lhzu"         opcode="a4000000" form="D"        group="i" desc="Load Half Word and Zero with Update">
+    <in field="RA" />
+    <in field="d" />
+    <out field="RD" />
+    <out field="RA" />
+    <disasm>lhzu [RD], [d]([RA])</disasm>
+  </insn>
+  <insn mnem="lhzux"        opcode="7c00026e" form="X"        group="i" desc="Load Half Word and Zero with Update Indexed">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="RA" />
+    <disasm>lhzux [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="lhzx"         opcode="7c00022e" form="X"        group="i" desc="Load Half Word and Zero Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="RD" />
+    <disasm>lhzx [RD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lmw"          opcode="b8000000" form="D"        group="i" desc="Load Multiple Word">
+    <!-- ? -->
+  </insn>
+  <insn mnem="lswi"         opcode="7c0004aa" form="X"        group="i" desc="Load String Word Immediate">
+    <!-- ? -->
+  </insn>
+  <insn mnem="lswx"         opcode="7c00042a" form="X"        group="i" desc="Load String Word Indexed">
+    <!-- ? -->
+  </insn>
+  <insn mnem="lwa"          opcode="e8000002" form="DS"       group="i" desc="Load Word Algebraic">
+    <in field="RA0" />
+    <in field="ds" />
+    <out field="RD" />
+    <disasm>lwa [RD], [ds]([RA0])</disasm>
+  </insn>
+  <insn mnem="lwarx"        opcode="7c000028" form="X"        group="i" desc="Load Word and Reserve Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="RD" />
+    <disasm>lwarx [RD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lwaux"        opcode="7c0002ea" form="X"        group="i" desc="Load Word Algebraic with Update Indexed">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="RA" />
+    <disasm>lwaux [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="lwax"         opcode="7c0002aa" form="X"        group="i" desc="Load Word Algebraic Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="RD" />
+    <disasm>lwax [RD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lwbrx"        opcode="7c00042c" form="X"        group="i" desc="Load Word Byte-Reverse Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="RD" />
+    <disasm>lwbrx [RD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lwz"          opcode="80000000" form="D"        group="i" desc="Load Word and Zero">
+    <in field="RA0" />
+    <in field="d" />
+    <out field="RD" />
+    <disasm>lwz [RD], [d]([RA0])</disasm>
+  </insn>
+  <insn mnem="lwzu"         opcode="84000000" form="D"        group="i" desc="Load Word and Zero with Update">
+    <in field="RA" />
+    <in field="d" />
+    <out field="RD" />
+    <out field="RA" />
+    <disasm>lwzu [RD], [d]([RA])</disasm>
+  </insn>
+  <insn mnem="lwzux"        opcode="7c00006e" form="X"        group="i" desc="Load Word and Zero with Update Indexed">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="RA" />
+    <disasm>lwzux [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="lwzx"         opcode="7c00002e" form="X"        group="i" desc="Load Word and Zero Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="RD" />
+    <disasm>lwzx [RD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="mcrf"         opcode="4c000000" form="XL"       group="i" desc="Move Condition Register Field">
+    <in field="CRFS" />
+    <out field="CRFD" />
+    <disasm>mcrf [CRFD], [CRFS]</disasm>
+  </insn>
+  <insn mnem="mcrfs"        opcode="fc000080" form="X"        group="f" desc="Move to Condition Register from FPSCR">
+    <in field="CRFS" />
+    <in field="FPSCR" />
+    <out field="CRFD" />
+    <out field="FPSCR" />
+    <disasm>mcrfs [CRFD], [CRFS]</disasm>
+  </insn>
+  <insn mnem="mcrxr"        opcode="7c000400" form="X"        group="i" desc="Move to Condition Register from XER">
+    <in field="CR" />
+    <out field="CRFD" />
+    <disasm>mcrxr [CRFD]</disasm>
+  </insn>
+  <insn mnem="mfcr"         opcode="7c000026" form="X"        group="i" desc="Move from Condition Register">
+    <in field="CR" />
+    <out field="RD" />
+    <disasm>mfcr [RD]</disasm>
+  </insn>
+  <insn mnem="mffsx"        opcode="fc00048e" form="X"        group="f" desc="Move from FPSCR">
+    <in field="FPSCR" />
+    <out field="FD" />
+    <out field="CR" conditional="true" />
+    <disasm>mffs[Rc] [RD]</disasm>
+  </insn>
+  <insn mnem="mfmsr"        opcode="7c0000a6" form="X"        group="i" desc="Move from Machine State Register">
+    <in field="MSR" />
+    <out field="RD" />
+    <disasm>mfmsr [RD]</disasm>
+  </insn>
+  <insn mnem="mfspr"        opcode="7c0002a6" form="XFX"      group="i" desc="Move from Special-Purpose Register">
+    <in field="SPR" />
+    <out field="RD" />
+    <disasm>mfspr [RD], [SPR]</disasm>
+  </insn>
+  <insn mnem="mftb"         opcode="7c0002e6" form="XFX"      group="i" desc="Move from Time Base">
+    <in field="TBR" />
+    <out field="RD" />
+    <disasm>mftb [RD], [TBR]</disasm>
+  </insn>
+  <insn mnem="mtcrf"        opcode="7c000120" form="XFX"      group="i" desc="Move to Condition Register Fields">
+    <in field="RS" />
+    <out field="CRM" />
+    <disasm>mtcrf [CRM], [RS]</disasm>
+  </insn>
+  <insn mnem="mtfsb0x"      opcode="fc00008c" form="X"        group="f" desc="Move to FPSCR Bit 0">
+    <out field="FPSCRD" />
+    <out field="CR" conditional="true" />
+    <disasm>mtfsb0[Rc] [FPSCRD]</disasm>
+  </insn>
+  <insn mnem="mtfsb1x"      opcode="fc00004c" form="X"        group="f" desc="Move to FPSCR Bit 1">
+    <out field="FPSCRD" />
+    <out field="CR" conditional="true" />
+    <disasm>mtfsb1[Rc] [FPSCRD]</disasm>
+  </insn>
+  <insn mnem="mtfsfx"       opcode="fc00058e" form="XFL"      group="f" desc="Move to FPSCR Fields">
+    <in field="FM" />
+    <in field="FB" />
+    <out field="FPSCR" />
+    <out field="CR" conditional="true" />
+    <disasm>mtfsf[Rc] [FM], [FB]</disasm>
+  </insn>
+  <insn mnem="mtfsfix"      opcode="fc00010c" form="X"        group="f" desc="Move to FPSCR Field Immediate">
+    <in field="IMM" />
+    <out field="CRFD" />
+    <out field="CR" conditional="true" />
+    <disasm>mtfsfi[Rc] [CRFD], [IMM]</disasm>
+  </insn>
+  <insn mnem="mtmsr"        opcode="7c000124" form="X"        group="i" desc="Move to Machine State Register">
+    <in field="RS" />
+    <out field="MSR" />
+    <disasm>mtmsr [RS]</disasm>
+  </insn>
+  <insn mnem="mtmsrd"       opcode="7c000164" form="X"        group="i" desc="Move to Machine State Register Doubleword">
+    <in field="RS" />
+    <out field="MSR" />
+    <disasm>mtmsrd [RS]</disasm>
+  </insn>
+  <insn mnem="mtspr"        opcode="7c0003a6" form="XFX"      group="i" desc="Move to Special-Purpose Register">
+    <in field="RS" />
+    <out field="SPR" />
+    <disasm>mtmspr [SPR], [RS]</disasm>
+  </insn>
+  <insn mnem="mulhdx"       opcode="7c000092" form="XO"       group="i" desc="Multiply High Doubleword">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="CR" conditional="true" />
+    <disasm>mulhd[Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="mulhdux"      opcode="7c000012" form="XO"       group="i" desc="Multiply High Doubleword Unsigned">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="CR" conditional="true" />
+    <disasm>mulhdu[Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="mulhwx"       opcode="7c000096" form="XO"       group="i" desc="Multiply High Word">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="CR" conditional="true" />
+    <disasm>mulhw[Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="mulhwux"      opcode="7c000016" form="XO"       group="i" desc="Multiply High Word Unsigned">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="CR" conditional="true" />
+    <disasm>mulhwu[Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="mulldx"       opcode="7c0001d2" form="XO"       group="i" desc="Multiply Low Doubleword">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="CR" conditional="true" />
+    <out field="OE" conditional="true" />
+    <disasm>mulld[OE][Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="mulli"        opcode="1c000000" form="D"        group="i" desc="Multiply Low Immediate">
+    <in field="RA" />
+    <in field="SIMM" />
+    <out field="RD" />
+    <disasm>mulli [RD], [RA], [SIMM]</disasm>
+  </insn>
+  <insn mnem="mullwx"       opcode="7c0001d6" form="XO"       group="i" desc="Multiply Low Word">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="CR" conditional="true" />
+    <out field="OE" conditional="true" />
+    <disasm>mullw[OE][Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="nandx"        opcode="7c0003b8" form="X"        group="i" desc="NAND">
+    <in field="RS" />
+    <in field="RB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>nand[Rc] [RA], [RS], [RB]</disasm>
+  </insn>
+  <insn mnem="negx"         opcode="7c0000d0" form="XO"       group="i" desc="Negate">
+    <in field="RA" />
+    <out field="RD" />
+    <out field="CR" conditional="true" />
+    <out field="OE" conditional="true" />
+    <disasm>neg[OE][Rc] [RD], [RA]</disasm>
+  </insn>
+  <insn mnem="norx"         opcode="7c0000f8" form="X"        group="i" desc="NOR">
+    <in field="RS" />
+    <in field="RB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>nor[Rc] [RA], [RS], [RB]</disasm>
+  </insn>
+  <insn mnem="orx"          opcode="7c000378" form="X"        group="i" desc="OR">
+    <in field="RS" />
+    <in field="RB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>or[Rc] [RA], [RS], [RB]</disasm>
+  </insn>
+  <insn mnem="orcx"         opcode="7c000338" form="X"        group="i" desc="OR with Complement">
+    <in field="RS" />
+    <in field="RB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>orc[Rc] [RA], [RS], [RB]</disasm>
+  </insn>
+  <insn mnem="ori"          opcode="60000000" form="D"        group="i" desc="OR Immediate">
+    <in field="RS" />
+    <in field="UIMM" />
+    <out field="RA" />
+    <disasm>ori [RA], [RS], [UIMM]</disasm>
+  </insn>
+  <insn mnem="oris"         opcode="64000000" form="D"        group="i" desc="OR Immediate Shifted">
+    <in field="RS" />
+    <in field="UIMM" />
+    <out field="RA" />
+    <disasm>oris [RA], [RS], [UIMM]</disasm>
+  </insn>
+  <insn mnem="rldclx"       opcode="78000010" form="MDS"      group="i" desc="Rotate Left Doubleword then Clear Left">
+    <in field="RS" />
+    <in field="RB" />
+    <in field="MB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>rldcl[Rc] [RA], [RS], [RB], [MB]</disasm>
+  </insn>
+  <insn mnem="rldcrx"       opcode="78000012" form="MDS"      group="i" desc="Rotate Left Doubleword then Clear Right">
+    <in field="RS" />
+    <in field="RB" />
+    <in field="ME" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>rldcr[Rc] [RA], [RS], [RB], [ME]</disasm>
+  </insn>
+  <insn mnem="rldicx"       opcode="78000008" form="MD"       group="i" desc="Rotate Left Doubleword Immediate then Clear">
+    <in field="RS" />
+    <in field="SH" />
+    <in field="MB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>rldic[Rc] [RA], [RS], [SH], [MB]</disasm>
+  </insn>
+  <insn mnem="rldiclx"      opcode="78000000" form="MD"       group="i" desc="Rotate Left Doubleword Immediate then Clear Left">
+    <in field="RS" />
+    <in field="SH" />
+    <in field="MB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>rldicl[Rc] [RA], [RS], [SH], [MB]</disasm>
+  </insn>
+  <insn mnem="rldicrx"      opcode="78000004" form="MD"       group="i" desc="Rotate Left Doubleword Immediate then Clear Right">
+    <in field="RS" />
+    <in field="SH" />
+    <in field="ME" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>rldicr[Rc] [RA], [RS], [SH], [ME]</disasm>
+  </insn>
+  <insn mnem="rldimix"      opcode="7800000C" form="MD"       group="i" desc="Rotate Left Doubleword Immediate then Mask Insert">
+    <in field="RS" />
+    <in field="SH" />
+    <in field="MB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>rldimi[Rc] [RA], [RS], [SH], [MB]</disasm>
+  </insn>
+  <insn mnem="rlwimix"      opcode="50000000" form="M"        group="i" desc="Rotate Left Word Immediate then Mask Insert">
+    <in field="RS" />
+    <in field="SH" />
+    <in field="MB" />
+    <in field="ME" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>rlwimi[Rc] [RA], [RS], [SH], [MB], [ME]</disasm>
+  </insn>
+  <insn mnem="rlwinmx"      opcode="54000000" form="M"        group="i" desc="Rotate Left Word Immediate then AND with Mask">
+    <in field="RS" />
+    <in field="SH" />
+    <in field="MB" />
+    <in field="ME" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>rlwinm[Rc] [RA], [RS], [SH], [MB], [ME]</disasm>
+  </insn>
+  <insn mnem="rlwnmx"       opcode="5c000000" form="M"        group="i" desc="Rotate Left Word then AND with Mask">
+    <in field="RS" />
+    <in field="RB" />
+    <in field="MB" />
+    <in field="ME" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>rlwnm[Rc] [RA], [RS], [RB], [MB], [ME]</disasm>
+  </insn>
+  <insn mnem="sc"           opcode="44000002" form="SC"       group="i" desc="System Call" sync="true">
+    <disasm>sc</disasm>
+  </insn>
+  <insn mnem="sldx"         opcode="7c000036" form="X"        group="i" desc="Shift Left Doubleword">
+    <in field="RS" />
+    <in field="RB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>sld[Rc] [RA], [RS], [RB]</disasm>
+  </insn>
+  <insn mnem="slwx"         opcode="7c000030" form="X"        group="i" desc="Shift Left Word">
+    <in field="RS" />
+    <in field="RB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>slw[Rc] [RA], [RS], [RB]</disasm>
+  </insn>
+  <insn mnem="sradx"        opcode="7c000634" form="X"        group="i" desc="Shift Right Algebraic Doubleword">
+    <in field="RS" />
+    <in field="RB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <out field="CA" />
+    <disasm>srad[Rc] [RA], [RS], [RB]</disasm>
+  </insn>
+  <insn mnem="sradix"       opcode="7c000674" form="XS"       group="i" desc="Shift Right Algebraic Doubleword Immediate">
+    <in field="RS" />
+    <in field="SH" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <out field="CA" />
+    <disasm>sradi[Rc] [RA], [RS], [SH]</disasm>
+  </insn>
+  <insn mnem="srawx"        opcode="7c000630" form="X"        group="i" desc="Shift Right Algebraic Word">
+    <in field="RS" />
+    <in field="RB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <out field="CA" />
+    <disasm>sraw[Rc] [RA], [RS], [RB]</disasm>
+  </insn>
+  <insn mnem="srawix"       opcode="7c000670" form="X"        group="i" desc="Shift Right Algebraic Word Immediate">
+    <in field="RS" />
+    <in field="SH" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <out field="CA" />
+    <disasm>srawi[Rc] [RA], [RS], [SH]</disasm>
+  </insn>
+  <insn mnem="srdx"         opcode="7c000436" form="X"        group="i" desc="Shift Right Doubleword">
+    <in field="RS" />
+    <in field="RB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>srd[Rc] [RA], [RS], [RB]</disasm>
+  </insn>
+  <insn mnem="srwx"         opcode="7c000430" form="X"        group="i" desc="Shift Right Word">
+    <in field="RS" />
+    <in field="RB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>srw[Rc] [RA], [RS], [RB]</disasm>
+  </insn>
+  <insn mnem="stb"          opcode="98000000" form="D"        group="i" desc="Store Byte">
+    <in field="RS" />
+    <in field="RA0" />
+    <in field="d" />
+    <disasm>stb [RS], [d]([RA0])</disasm>
+  </insn>
+  <insn mnem="stbu"         opcode="9c000000" form="D"        group="i" desc="Store Byte with Update">
+    <in field="RS" />
+    <in field="RA" />
+    <in field="d" />
+    <out field="RA" />
+    <disasm>stbu [RS], [d]([RA])</disasm>
+  </insn>
+  <insn mnem="stbux"        opcode="7c0001ee" form="X"        group="i" desc="Store Byte with Update Indexed">
+    <in field="RS" />
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RA" />
+    <disasm>stbux [RS], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="stbx"         opcode="7c0001ae" form="X"        group="i" desc="Store Byte Indexed">
+    <in field="RS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stbx [RS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="std"          opcode="f8000000" form="DS"       group="i" desc="Store Doubleword">
+    <in field="RS" />
+    <in field="RA" />
+    <in field="ds" />
+    <disasm>std [RS], [ds]([RA0])</disasm>
+  </insn>
+  <insn mnem="stdbrx"       opcode="7c000528" form="X"        group="i" desc="Store Doubleword Byte-Reverse Indexed">
+    <in field="RS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stdbrx [RS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stdcx"        opcode="7c0001ad" form="X"        group="i" desc="Store Doubleword Conditional Indexed">
+    <in field="RS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="CR" />
+    <disasm>stdcx. [RS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stdu"         opcode="f8000001" form="DS"       group="i" desc="Store Doubleword with Update">
+    <in field="RS" />
+    <in field="RA" />
+    <in field="ds" />
+    <out field="RA" />
+    <disasm>stdu [RS], [ds]([RA])</disasm>
+  </insn>
+  <insn mnem="stdux"        opcode="7c00016a" form="X"        group="i" desc="Store Doubleword with Update Indexed">
+    <in field="RS" />
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RA" />
+    <disasm>stdux [RS], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="stdx"         opcode="7c00012a" form="X"        group="i" desc="Store Doubleword Indexed">
+    <in field="RS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stdx [RS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stfd"         opcode="d8000000" form="D"        group="f" desc="Store Floating-Point Double">
+    <in field="FS" />
+    <in field="RA0" />
+    <in field="d" />
+    <disasm>stfd [FS], [d]([RA0])</disasm>
+  </insn>
+  <insn mnem="stfdu"        opcode="dc000000" form="D"        group="f" desc="Store Floating-Point Double with Update">
+    <in field="FS" />
+    <in field="RA" />
+    <in field="d" />
+    <out field="RA" />
+    <disasm>stfdu [FS], [d]([RA])</disasm>
+  </insn>
+  <insn mnem="stfdux"       opcode="7c0005ee" form="X"        group="f" desc="Store Floating-Point Double with Update Indexed">
+    <in field="FS" />
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RA" />
+    <disasm>stfdux [FS], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="stfdx"        opcode="7c0005ae" form="X"        group="f" desc="Store Floating-Point Double Indexed">
+    <in field="FS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stfdx [FS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stfiwx"       opcode="7c0007ae" form="X"        group="f" desc="Store Floating-Point as Integer Word Indexed">
+    <in field="FS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stfiwx [FS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stfs"         opcode="d0000000" form="D"        group="f" desc="Store Floating-Point Single">
+    <in field="FS" />
+    <in field="RA0" />
+    <in field="d" />
+    <disasm>stfs [FS], [d]([RA0])</disasm>
+  </insn>
+  <insn mnem="stfsu"        opcode="d4000000" form="D"        group="f" desc="Store Floating-Point Single with Update">
+    <in field="FS" />
+    <in field="RA" />
+    <in field="d" />
+    <out field="RA" />
+    <disasm>stfsu [FS], [d]([RA])</disasm>
+  </insn>
+  <insn mnem="stfsux"       opcode="7c00056e" form="X"        group="f" desc="Store Floating-Point Single with Update Indexed">
+    <in field="FS" />
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RA" />
+    <disasm>stfsux [FS], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="stfsx"        opcode="7c00052e" form="X"        group="f" desc="Store Floating-Point Single Indexed">
+    <in field="FS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stfsx [FS], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="sth"          opcode="b0000000" form="D"        group="i" desc="Store Half Word">
+    <in field="RS" />
+    <in field="RA0" />
+    <in field="d" />
+    <disasm>sth [RS], [d]([RA0])</disasm>
+  </insn>
+  <insn mnem="sthbrx"       opcode="7c00072c" form="X"        group="i" desc="Store Half Word Byte-Reverse Indexed">
+    <in field="RS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>sthbrx [RS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="sthu"         opcode="b4000000" form="D"        group="i" desc="Store Half Word with Update">
+    <in field="RS" />
+    <in field="RA" />
+    <in field="d" />
+    <out field="RA" />
+    <disasm>sthu [RS], [d]([RA])</disasm>
+  </insn>
+  <insn mnem="sthux"        opcode="7c00036e" form="X"        group="i" desc="Store Half Word with Update Indexed">
+    <in field="RS" />
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RA" />
+    <disasm>sthux [RS], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="sthx"         opcode="7c00032e" form="X"        group="i" desc="Store Half Word Indexed">
+    <in field="RS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>sthx [RS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stmw"         opcode="bc000000" form="D"        group="i" desc="Store Multiple Word">
+    <!-- ? -->
+  </insn>
+  <insn mnem="stswi"        opcode="7c0005aa" form="X"        group="i" desc="Store String Word Immediate">
+    <!-- ? -->
+  </insn>
+  <insn mnem="stswx"        opcode="7c00052a" form="X"        group="i" desc="Store String Word Indexed">
+    <!-- ? -->
+  </insn>
+  <insn mnem="stw"          opcode="90000000" form="D"        group="i" desc="Store Word">
+    <in field="RS" />
+    <in field="RA0" />
+    <in field="d" />
+    <disasm>stw [RS], [d]([RA0])</disasm>
+  </insn>
+  <insn mnem="stwbrx"       opcode="7c00052c" form="X"        group="i" desc="Store Word Byte-Reverse Indexed">
+    <in field="RS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stwbrx [RS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stwcx"        opcode="7c00012d" form="X"        group="i" desc="Store Word Conditional Indexed">
+    <in field="RS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="CR" />
+    <disasm>stwcx. [RS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stwu"         opcode="94000000" form="D"        group="i" desc="Store Word with Update">
+    <in field="RS" />
+    <in field="RA" />
+    <in field="d" />
+    <out field="RA" />
+    <disasm>stwu [RS], [d]([RA])</disasm>
+  </insn>
+  <insn mnem="stwux"        opcode="7c00016e" form="X"        group="i" desc="Store Word with Update Indexed">
+    <in field="RS" />
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RA" />
+    <disasm>stwux [RS], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="stwx"         opcode="7c00012e" form="X"        group="i" desc="Store Word Indexed">
+    <in field="RS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stwx [RS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="subfx"        opcode="7c000050" form="XO"       group="i" desc="Subtract From">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="CR" conditional="true" />
+    <out field="OE" conditional="true" />
+    <disasm>subf[OE][Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="subfcx"       opcode="7c000010" form="XO"       group="i" desc="Subtract From Carrying">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="CR" conditional="true" />
+    <out field="OE" conditional="true" />
+    <disasm>subfc[OE][Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="subfex"       opcode="7c000110" form="XO"       group="i" desc="Subtract From Extended">
+    <in field="RA" />
+    <in field="RB" />
+    <out field="RD" />
+    <out field="CR" conditional="true" />
+    <out field="OE" conditional="true" />
+    <disasm>subfe[OE][Rc] [RD], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="subficx"      opcode="20000000" form="D"        group="i" desc="Subtract From Immediate Carrying">
+    <in field="RA" />
+    <in field="SIMM" />
+    <out field="RD" />
+    <out field="CA" />
+    <disasm>subfic [RD], [RA], [SIMM]</disasm>
+  </insn>
+  <insn mnem="subfmex"      opcode="7c0001d0" form="XO"       group="i" desc="Subtract From Minus One Extended">
+    <in field="RA" />
+    <in field="CA" />
+    <out field="RD" />
+    <out field="CR" conditional="true" />
+    <out field="OE" conditional="true" />
+    <out field="CA" />
+    <disasm>subfme[OE][Rc] [RD], [RA]</disasm>
+  </insn>
+  <insn mnem="subfzex"      opcode="7c000190" form="XO"       group="i" desc="Subtract From Zero Extended">
+    <in field="RA" />
+    <in field="CA" />
+    <out field="RD" />
+    <out field="CR" conditional="true" />
+    <out field="OE" conditional="true" />
+    <out field="CA" />
+    <disasm>subfze[OE][Rc] [RD], [RA]</disasm>
+  </insn>
+  <insn mnem="sync"         opcode="7c0004ac" form="X"        group="i" desc="Synchronize">
+    <disasm>sync</disasm>
+  </insn>
+  <insn mnem="td"           opcode="7c000088" form="X"        group="i" desc="Trap Doubleword">
+    <in field="TO" />
+    <in field="RA" />
+    <in field="RB" />
+    <disasm>td [TO], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="tdi"          opcode="08000000" form="D"        group="i" desc="Trap Doubleword Immediate">
+    <in field="TO" />
+    <in field="RA" />
+    <in field="SIMM" />
+    <disasm>tdi [TO], [RA], [SIMM]</disasm>
+  </insn>
+  <insn mnem="tw"           opcode="7c000008" form="X"        group="i" desc="Trap Word">
+    <in field="TO" />
+    <in field="RA" />
+    <in field="RB" />
+    <disasm>tw [TO], [RA], [RB]</disasm>
+  </insn>
+  <insn mnem="twi"          opcode="0c000000" form="D"        group="i" desc="Trap Word Immediate">
+    <in field="TO" />
+    <in field="RA" />
+    <in field="SIMM" />
+    <disasm>tw [TO], [RA], [SIMM]</disasm>
+  </insn>
+  <insn mnem="xorx"         opcode="7c000278" form="X"        group="i" desc="XOR">
+    <in field="RS" />
+    <in field="RB" />
+    <out field="RA" />
+    <out field="CR" conditional="true" />
+    <disasm>xor[Rc] [RA], [RS], [RB]</disasm>
+  </insn>
+  <insn mnem="xori"         opcode="68000000" form="D"        group="i" desc="XOR Immediate">
+    <in field="RS" />
+    <in field="UIMM" />
+    <out field="RA" />
+    <disasm>xori [RA], [RS], [UIMM]</disasm>
+  </insn>
+  <insn mnem="xoris"        opcode="6c000000" form="D"        group="i" desc="XOR Immediate Shifted">
+    <in field="RS" />
+    <in field="UIMM" />
+    <out field="RA" />
+    <disasm>xoris [RA], [RS], [UIMM]</disasm>
+  </insn>
 </ppc-isa>
 <ppc-isa name="vmx">
-  <insn mnem="vaddcuw"      opcode="10000180" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Add Carryout Unsigned Word" />
-  <insn mnem="vaddfp"       opcode="1000000A" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Add Floating Point" />
-  <insn mnem="vaddsbs"      opcode="10000300" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Add Signed Byte Saturate" />
-  <insn mnem="vaddshs"      opcode="10000340" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Add Signed Half Word Saturate" />
-  <insn mnem="vaddsws"      opcode="10000380" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Add Signed Word Saturate" />
-  <insn mnem="vaddubm"      opcode="10000000" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Add Unsigned Byte Modulo" />
-  <insn mnem="vaddubs"      opcode="10000200" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Add Unsigned Byte Saturate" />
-  <insn mnem="vadduhm"      opcode="10000040" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Add Unsigned Half Word Modulo" />
-  <insn mnem="vadduhs"      opcode="10000240" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Add Unsigned Half Word Saturate" />
-  <insn mnem="vadduwm"      opcode="10000080" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Add Unsigned Word Modulo" />
-  <insn mnem="vadduws"      opcode="10000280" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Add Unsigned Word Saturate" />
-  <insn mnem="vand"         opcode="10000404" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Logical AND" />
-  <insn mnem="vandc"        opcode="10000444" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Logical AND with Complement" />
-  <insn mnem="vavgsb"       opcode="10000502" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Average Signed Byte" />
-  <insn mnem="vavgsh"       opcode="10000542" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Average Signed Half Word" />
-  <insn mnem="vavgsw"       opcode="10000582" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Average Signed Word" />
-  <insn mnem="vavgub"       opcode="10000402" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Average Unsigned Byte" />
-  <insn mnem="vavguh"       opcode="10000442" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Average Unsigned Half Word" />
-  <insn mnem="vavguw"       opcode="10000482" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Average Unsigned Word" />
-  <insn mnem="vcfsx"        opcode="1000034A" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Convert from Signed Fixed-Point Word" />
-  <insn mnem="vcfux"        opcode="1000030A" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Convert from Unsigned Fixed-Point Word" />
-  <insn mnem="vctsxs"       opcode="100003CA" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Convert to Signed Fixed-Point Word Saturate" />
-  <insn mnem="vctuxs"       opcode="1000038A" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Convert to Unsigned Fixed-Point Word Saturate" />
-  <insn mnem="vexptefp"     opcode="1000018A" form="VX"       sub-form="D-A-B"            group="v" desc="Vector 2 Raised to the Exponent Estimate Floating Point" />
-  <insn mnem="vlogefp"      opcode="100001CA" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Log2 Estimate Floating Point" />
-  <insn mnem="vmaxfp"       opcode="1000040A" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Maximum Floating Point" />
-  <insn mnem="vmaxsb"       opcode="10000102" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Maximum Signed Byte" />
-  <insn mnem="vmaxsh"       opcode="10000142" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Maximum Signed Half Word" />
-  <insn mnem="vmaxsw"       opcode="10000182" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Maximum Signed Word" />
-  <insn mnem="vmaxub"       opcode="10000002" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Maximum Unsigned Byte" />
-  <insn mnem="vmaxuh"       opcode="10000042" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Maximum Unsigned Half Word" />
-  <insn mnem="vmaxuw"       opcode="10000082" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Maximum Unsigned Word" />
-  <insn mnem="vminfp"       opcode="1000044A" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Minimum Floating Point" />
-  <insn mnem="vminsb"       opcode="10000302" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Minimum Signed Byte" />
-  <insn mnem="vminsh"       opcode="10000342" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Minimum Signed Half Word" />
-  <insn mnem="vminsw"       opcode="10000382" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Minimum Signed Word" />
-  <insn mnem="vminub"       opcode="10000202" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Minimum Unsigned Byte" />
-  <insn mnem="vminuh"       opcode="10000242" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Minimum Unsigned Half Word" />
-  <insn mnem="vminuw"       opcode="10000282" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Minimum Unsigned Word" />
-  <insn mnem="vmrghb"       opcode="1000000C" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Merge High Byte" />
-  <insn mnem="vmrghh"       opcode="1000004C" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Merge High Half Word" />
-  <insn mnem="vmrghw"       opcode="1000008C" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Merge High Word" />
-  <insn mnem="vmrglb"       opcode="1000010C" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Merge Low Byte" />
-  <insn mnem="vmrglh"       opcode="1000014C" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Merge Low Half Word" />
-  <insn mnem="vmrglw"       opcode="1000018C" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Merge Low Word" />
-  <insn mnem="vmulesb"      opcode="10000308" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Multiply Even Signed Byte" />
-  <insn mnem="vmulesh"      opcode="10000348" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Multiply Even Signed Half Word" />
-  <insn mnem="vmuleub"      opcode="10000208" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Multiply Even Unsigned Byte" />
-  <insn mnem="vmuleuh"      opcode="10000248" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Multiply Even Unsigned Half Word" />
-  <insn mnem="vmulosb"      opcode="10000108" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Multiply Odd Signed Byte" />
-  <insn mnem="vmulosh"      opcode="10000148" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Multiply Odd Signed Half Word" />
-  <insn mnem="vmuloub"      opcode="10000008" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Multiply Odd Unsigned Byte" />
-  <insn mnem="vmulouh"      opcode="10000048" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Multiply Odd Unsigned Half Word" />
-  <insn mnem="vnor"         opcode="10000504" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Logical NOR" />
-  <insn mnem="vor"          opcode="10000484" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Logical OR" />
-  <insn mnem="vpkpx"        opcode="1000030E" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Pack Pixel" />
-  <insn mnem="vpkshss"      opcode="1000018E" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Pack Signed Half Word Signed Saturate" />
-  <insn mnem="vpkshus"      opcode="1000010E" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Pack Signed Half Word Unsigned Saturate" />
-  <insn mnem="vpkswss"      opcode="100001CE" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Pack Signed Word Signed Saturate" />
-  <insn mnem="vpkswus"      opcode="1000014E" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Pack Signed Word Unsigned Saturate" />
-  <insn mnem="vpkuhum"      opcode="1000000E" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Pack Unsigned Half Word Unsigned Modulo" />
-  <insn mnem="vpkuhus"      opcode="1000008E" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Pack Unsigned Half Word Unsigned Saturate" />
-  <insn mnem="vpkuwum"      opcode="1000004E" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Pack Unsigned Word Unsigned Modulo" />
-  <insn mnem="vpkuwus"      opcode="100000CE" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Pack Unsigned Word Unsigned Saturate" />
-  <insn mnem="vrefp"        opcode="1000010A" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Reciprocal Estimate Floating Point" />
-  <insn mnem="vrfim"        opcode="100002CA" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Round to Floating-Point Integer toward -Infinity" />
-  <insn mnem="vrfin"        opcode="1000020A" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Round to Floating-Point Integer Nearest" />
-  <insn mnem="vrfip"        opcode="1000028A" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Round to Floating-Point Integer toward +Infinity" />
-  <insn mnem="vrfiz"        opcode="1000024A" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Round to Floating-Point Integer toward Zero" />
-  <insn mnem="vrlb"         opcode="10000004" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Rotate Left Integer Byte" />
-  <insn mnem="vrlh"         opcode="10000044" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Rotate Left Integer Half Word" />
-  <insn mnem="vrlw"         opcode="10000084" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Rotate Left Integer Word" />
-  <insn mnem="vrsqrtefp"    opcode="1000014A" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Reciprocal Square Root Estimate Floating Point" />
-  <insn mnem="vsl"          opcode="100001C4" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Shift Left" />
-  <insn mnem="vslb"         opcode="10000104" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Shift Left Integer Byte" />
-  <insn mnem="vslh"         opcode="10000144" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Shift Left Integer Half Word" />
-  <insn mnem="vslo"         opcode="1000040C" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Shift Left by Octet" />
-  <insn mnem="vslw"         opcode="10000184" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Shift Left Integer Word" />
-  <insn mnem="vspltb"       opcode="1000020C" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Splat Byte" />
-  <insn mnem="vsplth"       opcode="1000024C" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Splat Half Word" />
-  <insn mnem="vspltisb"     opcode="1000030C" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Splat Immediate Signed Byte" />
-  <insn mnem="vspltish"     opcode="1000034C" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Splat Immediate Signed Half Word" />
-  <insn mnem="vspltisw"     opcode="1000038C" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Splat Immediate Signed Word" />
-  <insn mnem="vspltw"       opcode="1000028C" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Splat Word" />
-  <insn mnem="vsr"          opcode="100002C4" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Shift Right" />
-  <insn mnem="vsrab"        opcode="10000304" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Shift Right Algebraic Byte" />
-  <insn mnem="vsrah"        opcode="10000344" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Shift Right Algebraic Half Word" />
-  <insn mnem="vsraw"        opcode="10000384" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Shift Right Algebraic Word" />
-  <insn mnem="vsrb"         opcode="10000204" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Shift Right Byte" />
-  <insn mnem="vsrh"         opcode="10000244" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Shift Right Half Word" />
-  <insn mnem="vsro"         opcode="1000044C" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Shift Right Octet" />
-  <insn mnem="vsrw"         opcode="10000284" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Shift Right Word" />
-  <insn mnem="vsubcuw"      opcode="10000580" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Subtract Carryout Unsigned Word" />
-  <insn mnem="vsubfp"       opcode="1000004A" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Subtract Floating Point" />
-  <insn mnem="vsubsbs"      opcode="10000700" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Subtract Signed Byte Saturate" />
-  <insn mnem="vsubshs"      opcode="10000740" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Subtract Signed Half Word Saturate" />
-  <insn mnem="vsubsws"      opcode="10000780" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Subtract Signed Word Saturate" />
-  <insn mnem="vsububm"      opcode="10000400" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Subtract Unsigned Byte Modulo" />
-  <insn mnem="vsububs"      opcode="10000600" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Subtract Unsigned Byte Saturate" />
-  <insn mnem="vsubuhm"      opcode="10000440" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Subtract Unsigned Half Word Modulo" />
-  <insn mnem="vsubuhs"      opcode="10000640" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Subtract Unsigned Half Word Saturate" />
-  <insn mnem="vsubuwm"      opcode="10000480" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Subtract Unsigned Word Modulo" />
-  <insn mnem="vsubuws"      opcode="10000680" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Subtract Unsigned Word Saturate" />
-  <insn mnem="vsumsws"      opcode="10000788" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Sum Across Signed Word Saturate" />
-  <insn mnem="vsum2sws"     opcode="10000688" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Sum Across Partial (1/2) Signed Word Saturate" />
-  <insn mnem="vsum4sbs"     opcode="10000708" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Sum Across Partial (1/4) Signed Byte Saturate" />
-  <insn mnem="vsum4shs"     opcode="10000648" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Sum Across Partial (1/4) Signed Half Word Saturate" />
-  <insn mnem="vsum4ubs"     opcode="10000608" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Sum Across Partial (1/4) Unsigned Byte Saturate" />
-  <insn mnem="vupkhpx"      opcode="1000034E" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Unpack High Pixel" />
-  <insn mnem="vupkhsb"      opcode="1000020E" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Unpack High Signed Byte" />
-  <insn mnem="vupkhsh"      opcode="1000024E" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Unpack High Signed Half Word" />
-  <insn mnem="vupklpx"      opcode="100003CE" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Unpack Low Pixel" />
-  <insn mnem="vupklsb"      opcode="1000028E" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Unpack Low Signed Byte" />
-  <insn mnem="vupklsh"      opcode="100002CE" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Unpack Low Signed Half Word" />
-  <insn mnem="vxor"         opcode="100004C4" form="VX"       sub-form="D-A-B"            group="v" desc="Vector Logical XOR" />
+  <!-- These match docs/ppc/altivec_instructions.pdf -->
+  <insn mnem="lvebx"        opcode="7c00000e" form="X"        group="v" desc="Load Vector Element Byte Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvebx [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvehx"        opcode="7c00004e" form="X"        group="v" desc="Load Vector Element Half Word Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvehx [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvewx"        opcode="7c00008e" form="X"        group="v" desc="Load Vector Element Word Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvewx [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvewx128"     opcode="10000083" form="VX128_1"  group="v" desc="Load Vector Element Word Indexed 128">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvewx128 [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvsl"         opcode="7c00000c" form="X"        group="v" desc="Load Vector for Shift Left Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvsl [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvsl128"      opcode="10000003" form="VX128_1"  group="v" desc="Load Vector for Shift Left Indexed 128">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvsl128 [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvsr"         opcode="7c00004c" form="X"        group="v" desc="Load Vector for Shift Right Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvsr [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvsr128"      opcode="10000043" form="VX128_1"  group="v" desc="Load Vector for Shift Right Indexed 128">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvsr128 [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvx"          opcode="7c0000ce" form="X"        group="v" desc="Load Vector Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvx [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvx128"       opcode="100000C3" form="VX128_1"  group="v" desc="Load Vector Indexed 128">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvx128 [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvxl"         opcode="7c0002ce" form="X"        group="v" desc="Load Vector Indexed LRU">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvslx [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvxl128"      opcode="100002C3" form="VX128_1"  group="v" desc="Load Vector Indexed LRU 128">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvxl128 [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvlx"         opcode="7C00040E" form="X"        group="v" desc="Load Vector Left Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvlx [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvlx128"      opcode="10000403" form="VX128_1"  group="v" desc="Load Vector Left Indexed 128">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvlx128 [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvlxl"        opcode="7C00060E" form="X"        group="v" desc="Load Vector Left Indexed LRU">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvlxl [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvlxl128"     opcode="10000603" form="VX128_1"  group="v" desc="Load Vector Left Indexed LRU 128">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvlxl128 [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvrx"         opcode="7C00044E" form="X"        group="v" desc="Load Vector Right Indexed">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvrx [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvrx128"      opcode="10000443" form="VX128_1"  group="v" desc="Load Vector Right Indexed 128">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvrx128 [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvrxl"        opcode="7C00064E" form="X"        group="v" desc="Load Vector Right Indexed LRU">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvrxl [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="lvrxl128"     opcode="10000643" form="VX128_1"  group="v" desc="Load Vector Right Indexed LRU 128">
+    <in field="RA0" />
+    <in field="RB" />
+    <out field="VD" />
+    <disasm>lvrxl128 [VD], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="mfvscr"       opcode="10000604" form="VX"       group="v" desc="Move from VSCR">
+    <in field="VSCR" />
+    <out field="VD" />
+  </insn>
+  <insn mnem="mtvscr"       opcode="10000644" form="VX"       group="v" desc="Move to VSCR">
+    <in field="VB" />
+    <out field="VSCR" />
+  </insn>
+  <insn mnem="stvebx"       opcode="7c00010e" form="X"        group="v" desc="Store Vector Element Byte Indexed">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvebx [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stvehx"       opcode="7c00014e" form="X"        group="v" desc="Store Vector Element Half Word Indexed">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvehx [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stvewx"       opcode="7c00018e" form="X"        group="v" desc="Store Vector Element Word Indexed">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvewx [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stvewx128"    opcode="10000183" form="VX128_1"  group="v" desc="Store Vector Element Word Indexed 128">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvewx128 [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stvx"         opcode="7c0001ce" form="X"        group="v" desc="Store Vector Indexed">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvx [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stvx128"      opcode="100001c3" form="VX128_1"  group="v" desc="Store Vector Indexed 128">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvx128 [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stvxl"        opcode="7c0003ce" form="X"        group="v" desc="Store Vector Indexed LRU">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvxl [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stvxl128"     opcode="100003c3" form="VX128_1"  group="v" desc="Store Vector Indexed LRU 128">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvxl128 [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stvlx"        opcode="7c00050e" form="X"        group="v" desc="Store Vector Left Indexed">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvlx [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stvlx128"     opcode="10000503" form="VX128_1"  group="v" desc="Store Vector Left Indexed 128">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvlx128 [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stvlxl"       opcode="7c00070e" form="X"        group="v" desc="Store Vector Left Indexed LRU">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvlxl [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stvlxl128"    opcode="10000703" form="VX128_1"  group="v" desc="Store Vector Left Indexed LRU 128">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvlxl128 [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stvrx"        opcode="7c00054e" form="X"        group="v" desc="Store Vector Right Indexed">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvrx [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stvrx128"     opcode="10000543" form="VX128_1"  group="v" desc="Store Vector Right Indexed 128">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvrx128 [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stvrxl"       opcode="7c00074e" form="X"        group="v" desc="Store Vector Right Indexed LRU">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvrxl [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="stvrxl128"    opcode="10000743" form="VX128_1"  group="v" desc="Store Vector Right Indexed LRU 128">
+    <in field="VS" />
+    <in field="RA0" />
+    <in field="RB" />
+    <disasm>stvrxl128 [VS], [RA0], [RB]</disasm>
+  </insn>
+  <insn mnem="vaddcuw"      opcode="10000180" form="VX"       group="v" desc="Vector Add Carryout Unsigned Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vaddcuw [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vaddfp"       opcode="1000000A" form="VX"       group="v" desc="Vector Add Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vaddfp [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vaddfp128"    opcode="14000010" form="VX128"    group="v" desc="Vector128 Add Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vaddfp128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vaddsbs"      opcode="10000300" form="VX"       group="v" desc="Vector Add Signed Byte Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vaddsbs [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vaddshs"      opcode="10000340" form="VX"       group="v" desc="Vector Add Signed Half Word Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vaddshs [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vaddsws"      opcode="10000380" form="VX"       group="v" desc="Vector Add Signed Word Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vaddsws [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vaddubm"      opcode="10000000" form="VX"       group="v" desc="Vector Add Unsigned Byte Modulo">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vaddubm [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vaddubs"      opcode="10000200" form="VX"       group="v" desc="Vector Add Unsigned Byte Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vaddubs [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vadduhm"      opcode="10000040" form="VX"       group="v" desc="Vector Add Unsigned Half Word Modulo">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vadduhm [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vadduhs"      opcode="10000240" form="VX"       group="v" desc="Vector Add Unsigned Half Word Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vadduhs [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vadduwm"      opcode="10000080" form="VX"       group="v" desc="Vector Add Unsigned Word Modulo">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vadduwm [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vadduws"      opcode="10000280" form="VX"       group="v" desc="Vector Add Unsigned Word Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vadduws [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vand"         opcode="10000404" form="VX"       group="v" desc="Vector Logical AND">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vand [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vand128"      opcode="14000210" form="VX128"    group="v" desc="Vector128 Logical AND">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vand128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vandc"        opcode="10000444" form="VX"       group="v" desc="Vector Logical AND with Complement">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vandc [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vandc128"     opcode="14000250" form="VX128"    group="v" desc="Vector128 Logical AND with Complement">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vandc128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vavgsb"       opcode="10000502" form="VX"       group="v" desc="Vector Average Signed Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vavgsb [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vavgsh"       opcode="10000542" form="VX"       group="v" desc="Vector Average Signed Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vavgsh [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vavgsw"       opcode="10000582" form="VX"       group="v" desc="Vector Average Signed Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vavgsw [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vavgub"       opcode="10000402" form="VX"       group="v" desc="Vector Average Unsigned Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vavgub [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vavguh"       opcode="10000442" form="VX"       group="v" desc="Vector Average Unsigned Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vavguh [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vavguw"       opcode="10000482" form="VX"       group="v" desc="Vector Average Unsigned Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vavguw [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcfsx"        opcode="1000034A" form="VX"       group="v" desc="Vector Convert from Signed Fixed-Point Word">
+    <in field="VB" />
+    <in field="UIMM" />
+    <out field="VD" />
+    <disasm>vcfsx [VD], [VB], [UIMM]</disasm>
+  </insn>
+  <insn mnem="vcfux"        opcode="1000030A" form="VX"       group="v" desc="Vector Convert from Unsigned Fixed-Point Word">
+    <in field="VB" />
+    <in field="UIMM" />
+    <out field="VD" />
+    <disasm>vcfux [VD], [VB], [UIMM]</disasm>
+  </insn>
+  <insn mnem="vcmpbfp"      opcode="100003C6" form="VC"       group="v" desc="Vector Compare Bounds Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpbfp[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpbfp128"   opcode="18000180" form="VX128_R"  group="v" desc="Vector128 Compare Bounds Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpbfp128[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpeqfp"     opcode="100000C6" form="VC"       group="v" desc="Vector Compare Equal-to Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpeqfp[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpeqfp128"  opcode="18000000" form="VX128_R"  group="v" desc="Vector128 Compare Equal-to Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpeqfp128[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpequb"     opcode="10000006" form="VC"       group="v" desc="Vector Compare Equal-to Unsigned Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpequb[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpequh"     opcode="10000046" form="VC"       group="v" desc="Vector Compare Equal-to Unsigned Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpequh[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpequw"     opcode="10000086" form="VC"       group="v" desc="Vector Compare Equal-to Unsigned Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpequw[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpequw128"  opcode="18000200" form="VX128_R"  group="v" desc="Vector128 Compare Equal-to Unsigned Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpequw128[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpgefp"     opcode="100001C6" form="VC"       group="v" desc="Vector Compare Greater-Than-or-Equal-to Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpgefp[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpgefp128"  opcode="18000080" form="VX128_R"  group="v" desc="Vector128 Compare Greater-Than-or-Equal-to Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpgefp128[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpgtfp"     opcode="100002C6" form="VC"       group="v" desc="Vector Compare Greater-Than Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpgtfp[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpgtfp128"  opcode="18000100" form="VX128_R"  group="v" desc="Vector128 Compare Greater-Than Floating-Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpgtfp128[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpgtsb"     opcode="10000306" form="VC"       group="v" desc="Vector Compare Greater-Than Signed Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpgtsb[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpgtsh"     opcode="10000346" form="VC"       group="v" desc="Vector Compare Greater-Than Signed Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpgtsh[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpgtsw"     opcode="10000386" form="VC"       group="v" desc="Vector Compare Greater-Than Signed Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpgtsw[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpgtub"     opcode="10000206" form="VC"       group="v" desc="Vector Compare Greater-Than Unsigned Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpgtub[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpgtuh"     opcode="10000246" form="VC"       group="v" desc="Vector Compare Greater-Than Unsigned Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpgtuh[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vcmpgtuw"     opcode="10000286" form="VC"       group="v" desc="Vector Compare Greater-Than Unsigned Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="CR" conditional="true" />
+    <disasm>vcmpgtuw[Rc] [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vctsxs"       opcode="100003CA" form="VX"       group="v" desc="Vector Convert to Signed Fixed-Point Word Saturate">
+    <in field="VB" />
+    <in field="UIMM" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vctsxs [VD], [VB], [UIMM]</disasm>
+  </insn>
+  <insn mnem="vctuxs"       opcode="1000038A" form="VX"       group="v" desc="Vector Convert to Unsigned Fixed-Point Word Saturate">
+    <in field="VB" />
+    <in field="UIMM" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vctuxs [VD], [VB], [UIMM]</disasm>
+  </insn>
+  <insn mnem="vexptefp"     opcode="1000018A" form="VX"       group="v" desc="Vector 2 Raised to the Exponent Estimate Floating Point">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vexptefp [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vexptefp128"  opcode="180006B0" form="VX128_3"  group="v" desc="Vector128 Log2 Estimate Floating Point">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vexptefp128 [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vlogefp"      opcode="100001CA" form="VX"       group="v" desc="Vector Log2 Estimate Floating Point">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vlogefp [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vlogefp128"   opcode="180006F0" form="VX128_3"  group="v" desc="Vector128 Log2 Estimate Floating Point">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vlogefp128 [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vmaddfp"      opcode="1000002E" form="VA"       group="v" desc="Vector Multiply-Add Floating Point">
+    <in field="VA" />
+    <in field="VC" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmaddfp [VD], [VA], [VC], [VB]</disasm>
+  </insn>
+  <insn mnem="vmaddfp128"   opcode="140000D0" form="VX128"    group="v" desc="Vector128 Multiply Add Floating Point">
+    <in field="VA" />
+    <in field="VC" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmaddfp128 [VD], [VA], [VB], [VD]</disasm>
+  </insn>
+  <insn mnem="vmaxfp"       opcode="1000040A" form="VX"       group="v" desc="Vector Maximum Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmaxfp [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmaxfp128"    opcode="18000280" form="VX128"    group="v" desc="Vector128 Maximum Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmaxfp128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmaxsb"       opcode="10000102" form="VX"       group="v" desc="Vector Maximum Signed Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmaxsb [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmaxsh"       opcode="10000142" form="VX"       group="v" desc="Vector Maximum Signed Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmaxsh [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmaxsw"       opcode="10000182" form="VX"       group="v" desc="Vector Maximum Signed Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmaxsw [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmaxub"       opcode="10000002" form="VX"       group="v" desc="Vector Maximum Unsigned Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmaxub [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmaxuh"       opcode="10000042" form="VX"       group="v" desc="Vector Maximum Unsigned Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmaxuh [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmaxuw"       opcode="10000082" form="VX"       group="v" desc="Vector Maximum Unsigned Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmaxuw [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmhaddshs"    opcode="10000020" form="VA"       group="v" desc="Vector Multiply-High and Add Signed Signed Half Word Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <in field="VC" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vmhaddshs [VD], [VA], [VB], [VC]</disasm>
+  </insn>
+  <insn mnem="vmhraddshs"   opcode="10000021" form="VA"       group="v" desc="Vector Multiply-High Round and Add Signed Signed Half Word Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <in field="VC" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vmhraddshs [VD], [VA], [VB], [VC]</disasm>
+  </insn>
+  <insn mnem="vminfp"       opcode="1000044A" form="VX"       group="v" desc="Vector Minimum Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vminfp [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vminfp128"    opcode="180002C0" form="VX128"    group="v" desc="Vector128 Minimum Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vminfp128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vminsb"       opcode="10000302" form="VX"       group="v" desc="Vector Minimum Signed Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vminsb [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vminsh"       opcode="10000342" form="VX"       group="v" desc="Vector Minimum Signed Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vminsh [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vminsw"       opcode="10000382" form="VX"       group="v" desc="Vector Minimum Signed Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vminsw [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vminub"       opcode="10000202" form="VX"       group="v" desc="Vector Minimum Unsigned Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vminub [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vminuh"       opcode="10000242" form="VX"       group="v" desc="Vector Minimum Unsigned Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vminuh [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vminuw"       opcode="10000282" form="VX"       group="v" desc="Vector Minimum Unsigned Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vminuw [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmladduhm"    opcode="10000022" form="VA"       group="v" desc="Vector Multiply-Low and Add Unsigned Half Word Modulo">
+    <in field="VA" />
+    <in field="VB" />
+    <in field="VC" />
+    <out field="VD" />
+    <disasm>vmladduhm [VD], [VA], [VB], [VC]</disasm>
+  </insn>
+  <insn mnem="vmrghb"       opcode="1000000C" form="VX"       group="v" desc="Vector Merge High Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmrghb [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmrghh"       opcode="1000004C" form="VX"       group="v" desc="Vector Merge High Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmrghh [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmrghw"       opcode="1000008C" form="VX"       group="v" desc="Vector Merge High Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmrghw [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmrghw128"    opcode="18000300" form="VX128"    group="v" desc="Vector128 Merge High Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmrghw128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmrglb"       opcode="1000010C" form="VX"       group="v" desc="Vector Merge Low Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmrglb [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmrglh"       opcode="1000014C" form="VX"       group="v" desc="Vector Merge Low Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmrglh [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmrglw"       opcode="1000018C" form="VX"       group="v" desc="Vector Merge Low Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmrglw [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmrglw128"    opcode="18000340" form="VX128"    group="v" desc="Vector128 Merge Low Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmrglw128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmsummbm"     opcode="10000025" form="VA"       group="v" desc="Vector Multiply-Sum Mixed-Sign Byte Modulo">
+    <in field="VA" />
+    <in field="VB" />
+    <in field="VC" />
+    <out field="VD" />
+    <disasm>vmsummbm [VD], [VA], [VB], [VC]</disasm>
+  </insn>
+  <insn mnem="vmsumshm"     opcode="10000028" form="VA"       group="v" desc="Vector Multiply-Sum Signed Half Word Modulo">
+    <in field="VA" />
+    <in field="VB" />
+    <in field="VC" />
+    <out field="VD" />
+    <disasm>vmsumshm [VD], [VA], [VB], [VC]</disasm>
+  </insn>
+  <insn mnem="vmsumshs"     opcode="10000029" form="VA"       group="v" desc="Vector Multiply-Sum Signed Half Word Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <in field="VC" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vmsumshs [VD], [VA], [VB], [VC]</disasm>
+  </insn>
+  <insn mnem="vmsumubm"     opcode="10000024" form="VA"       group="v" desc="Vector Multiply-Sum Unsigned Byte Modulo">
+    <in field="VA" />
+    <in field="VB" />
+    <in field="VC" />
+    <out field="VD" />
+    <disasm>vmsumubm [VD], [VA], [VB], [VC]</disasm>
+  </insn>
+  <insn mnem="vmsumuhm"     opcode="10000026" form="VA"       group="v" desc="Vector Multiply-Sum Unsigned Half Word Modulo">
+    <in field="VA" />
+    <in field="VB" />
+    <in field="VC" />
+    <out field="VD" />
+    <disasm>vmsumuhm [VD], [VA], [VB], [VC]</disasm>
+  </insn>
+  <insn mnem="vmsumuhs"     opcode="10000027" form="VA"       group="v" desc="Vector Multiply-Sum Unsigned Half Word Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <in field="VC" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vmsumuhs [VD], [VA], [VB], [VC]</disasm>
+  </insn>
+  <insn mnem="vmulesb"      opcode="10000308" form="VX"       group="v" desc="Vector Multiply Even Signed Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmulesb [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmulesh"      opcode="10000348" form="VX"       group="v" desc="Vector Multiply Even Signed Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmulesh [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmuleub"      opcode="10000208" form="VX"       group="v" desc="Vector Multiply Even Unsigned Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmuleub [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmuleuh"      opcode="10000248" form="VX"       group="v" desc="Vector Multiply Even Unsigned Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmuleuh [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmulosb"      opcode="10000108" form="VX"       group="v" desc="Vector Multiply Odd Signed Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmulosb [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmulosh"      opcode="10000148" form="VX"       group="v" desc="Vector Multiply Odd Signed Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmulosh [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmuloub"      opcode="10000008" form="VX"       group="v" desc="Vector Multiply Odd Unsigned Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmuloub [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmulouh"      opcode="10000048" form="VX"       group="v" desc="Vector Multiply Odd Unsigned Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmulouh [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vnmsubfp"     opcode="1000002F" form="VA"       group="v" desc="Vector Negative Multiply-Subtract Floating Point">
+    <in field="VA" />
+    <in field="VC" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vnmsubfp [VD], [VA], [VC], [VB]</disasm>
+  </insn>
+  <insn mnem="vnmsubfp128"  opcode="14000150" form="VX128"    group="v" desc="Vector128 Negative Multiply-Subtract Floating Point">
+    <in field="VA" />
+    <in field="VD" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vnmsubfp128 [VD], [VA], [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vnor"         opcode="10000504" form="VX"       group="v" desc="Vector Logical NOR">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vnor [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vnor128"      opcode="14000290" form="VX128"    group="v" desc="Vector128 Logical NOR">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vnor128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vor"          opcode="10000484" form="VX"       group="v" desc="Vector Logical OR">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vor [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vor128"       opcode="140002D0" form="VX128"    group="v" desc="Vector128 Logical OR">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vor128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vperm"        opcode="1000002B" form="VA"       group="v" desc="Vector Permute">
+    <in field="VA" />
+    <in field="VB" />
+    <in field="VC" />
+    <out field="VD" />
+    <disasm>vperm [VD], [VA], [VB], [VC]</disasm>
+  </insn>
+  <insn mnem="vperm128"     opcode="14000000" form="VX128_2"  group="v" desc="Vector128 Permute">
+    <in field="VA" />
+    <in field="VB" />
+    <in field="VC" />
+    <out field="VD" />
+    <disasm>vperm128 [VD], [VA], [VB], [VC]</disasm>
+  </insn>
+  <insn mnem="vpkpx"        opcode="1000030E" form="VX"       group="v" desc="Vector Pack Pixel">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vpkpx [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkshss"      opcode="1000018E" form="VX"       group="v" desc="Vector Pack Signed Half Word Signed Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vpkshss [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkshss128"   opcode="14000200" form="VX128"    group="v" desc="Vector128 Pack Signed Half Word Signed Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vpkshss128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkshus"      opcode="1000010E" form="VX"       group="v" desc="Vector Pack Signed Half Word Unsigned Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vpkshus [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkshus128"   opcode="14000240" form="VX128"    group="v" desc="Vector128 Pack Signed Half Word Unsigned Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vpkshus128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkswss"      opcode="100001CE" form="VX"       group="v" desc="Vector Pack Signed Word Signed Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vpkswss [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkswss128"   opcode="14000280" form="VX128"    group="v" desc="Vector128 Pack Signed Word Signed Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vpkswss128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkswus"      opcode="1000014E" form="VX"       group="v" desc="Vector Pack Signed Word Unsigned Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vpkswus [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkswus128"   opcode="140002C0" form="VX128"    group="v" desc="Vector128 Pack Signed Word Unsigned Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vpkswus128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkuhum"      opcode="1000000E" form="VX"       group="v" desc="Vector Pack Unsigned Half Word Unsigned Modulo">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vpkuhum [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkuhum128"   opcode="14000300" form="VX128"    group="v" desc="Vector128 Pack Unsigned Half Word Unsigned Modulo">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vpkuhum128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkuhus"      opcode="1000008E" form="VX"       group="v" desc="Vector Pack Unsigned Half Word Unsigned Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vpkuhus [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkuhus128"   opcode="14000340" form="VX128"    group="v" desc="Vector128 Pack Unsigned Half Word Unsigned Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vpkuhus128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkuwum"      opcode="1000004E" form="VX"       group="v" desc="Vector Pack Unsigned Word Unsigned Modulo">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vpkuwum [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkuwum128"   opcode="14000380" form="VX128"    group="v" desc="Vector128 Pack Unsigned Word Unsigned Modulo">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vpkuwum128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkuwus"      opcode="100000CE" form="VX"       group="v" desc="Vector Pack Unsigned Word Unsigned Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vpkuwus [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpkuwus128"   opcode="140003C0" form="VX128"    group="v" desc="Vector128 Pack Unsigned Word Unsigned Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vpkuwus128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vrefp"        opcode="1000010A" form="VX"       group="v" desc="Vector Reciprocal Estimate Floating Point">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrefp [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vrefp128"     opcode="18000630" form="VX128_3"  group="v" desc="Vector128 Reciprocal Estimate Floating Point">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrefp128 [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vrfim"        opcode="100002CA" form="VX"       group="v" desc="Vector Round to Floating-Point Integer toward -Infinity">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrfim [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vrfim128"     opcode="18000330" form="VX128_3"  group="v" desc="Vector128 Round to Floating-Point Integer toward -Infinity">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrfim128 [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vrfin"        opcode="1000020A" form="VX"       group="v" desc="Vector Round to Floating-Point Integer Nearest">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrfin [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vrfin128"     opcode="18000370" form="VX128_3"  group="v" desc="Vector128 Round to Floating-Point Integer Nearest">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrfin128 [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vrfip"        opcode="1000028A" form="VX"       group="v" desc="Vector Round to Floating-Point Integer toward +Infinity">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrfip [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vrfip128"     opcode="180003B0" form="VX128_3"  group="v" desc="Vector128 Round to Floating-Point Integer toward +Infinity">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrfip128 [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vrfiz"        opcode="1000024A" form="VX"       group="v" desc="Vector Round to Floating-Point Integer toward Zero">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrfiz [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vrfiz128"     opcode="180003F0" form="VX128_3"  group="v" desc="Vector128 Round to Floating-Point Integer toward Zero">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrfiz128 [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vrlb"         opcode="10000004" form="VX"       group="v" desc="Vector Rotate Left Integer Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrlb [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vrlh"         opcode="10000044" form="VX"       group="v" desc="Vector Rotate Left Integer Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrlh [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vrlw"         opcode="10000084" form="VX"       group="v" desc="Vector Rotate Left Integer Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrlw [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vrlw128"      opcode="18000050" form="VX128"    group="v" desc="Vector128 Rotate Left Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrlw128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vrsqrtefp"    opcode="1000014A" form="VX"       group="v" desc="Vector Reciprocal Square Root Estimate Floating Point">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrsqrtefp [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vrsqrtefp128" opcode="18000670" form="VX128_3"  group="v" desc="Vector128 Reciprocal Square Root Estimate Floating Point">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrsqrtefp128 [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vsel"         opcode="1000002A" form="VA"       group="v" desc="Vector Conditional Select">
+    <in field="VA" />
+    <in field="VB" />
+    <in field="VC" />
+    <out field="VD" />
+    <disasm>vsel [VD], [VA], [VB], [VC]</disasm>
+  </insn>
+  <insn mnem="vsel128"      opcode="14000350" form="VX128"    group="v" desc="Vector128 Conditional Select">
+    <in field="VA" />
+    <in field="VB" />
+    <in field="VD" />
+    <out field="VD" />
+    <disasm>vsel128 [VD], [VA], [VB], [VD]</disasm>
+  </insn>
+  <insn mnem="vsl"          opcode="100001C4" form="VX"       group="v" desc="Vector Shift Left">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsl [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vslb"         opcode="10000104" form="VX"       group="v" desc="Vector Shift Left Integer Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vslb [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsldoi"       opcode="1000002C" form="VA"       group="v" desc="Vector Shift Left Double by Octet Immediate">
+    <in field="VA" />
+    <in field="VB" />
+    <in field="SHB" />
+    <out field="VD" />
+    <disasm>vsldoi [VD], [VA], [VB], [SHB]</disasm>
+  </insn>
+  <insn mnem="vsldoi128"    opcode="10000010" form="VX128_5"  group="v" desc="Vector128 Shift Left Double by Octet Immediate">
+    <in field="VA" />
+    <in field="VB" />
+    <in field="SHB" />
+    <out field="VD" />
+    <disasm>vsldoi128 [VD], [VA], [VB], [SHB]</disasm>
+  </insn>
+  <insn mnem="vslh"         opcode="10000144" form="VX"       group="v" desc="Vector Shift Left Integer Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vslh [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vslo"         opcode="1000040C" form="VX"       group="v" desc="Vector Shift Left by Octet">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vslo [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vslo128"      opcode="14000390" form="VX128"    group="v" desc="Vector128 Shift Left Octet">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vslo128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vslw"         opcode="10000184" form="VX"       group="v" desc="Vector Shift Left Integer Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vslw [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vslw128"      opcode="180000D0" form="VX128"    group="v" desc="Vector128 Shift Left Integer Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vslw128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vspltb"       opcode="1000020C" form="VX"       group="v" desc="Vector Splat Byte">
+    <in field="VB" />
+    <in field="UIMM" />
+    <out field="VD" />
+    <disasm>vspltb [VD], [VB], [UIMM]</disasm>
+  </insn>
+  <insn mnem="vsplth"       opcode="1000024C" form="VX"       group="v" desc="Vector Splat Half Word">
+    <in field="VB" />
+    <in field="UIMM" />
+    <out field="VD" />
+    <disasm>vsplth [VD], [VB], [UIMM]</disasm>
+  </insn>
+  <insn mnem="vspltisb"     opcode="1000030C" form="VX"       group="v" desc="Vector Splat Immediate Signed Byte">
+    <in field="SIMM" />
+    <out field="VD" />
+    <disasm>vspltisb [VD], [SIMM]</disasm>
+  </insn>
+  <insn mnem="vspltish"     opcode="1000034C" form="VX"       group="v" desc="Vector Splat Immediate Signed Half Word">
+    <in field="SIMM" />
+    <out field="VD" />
+    <disasm>vspltish [VD], [SIMM]</disasm>
+  </insn>
+  <insn mnem="vspltisw"     opcode="1000038C" form="VX"       group="v" desc="Vector Splat Immediate Signed Word">
+    <in field="SIMM" />
+    <out field="VD" />
+    <disasm>vspltisw [VD], [SIMM]</disasm>
+  </insn>
+  <insn mnem="vspltisw128"  opcode="18000770" form="VX128_3"  group="v" desc="Vector128 Splat Immediate Signed Word">
+    <in field="SIMM" />
+    <out field="VD" />
+    <disasm>vspltisw128 [VD], [SIMM]</disasm>
+  </insn>
+  <insn mnem="vspltw"       opcode="1000028C" form="VX"       group="v" desc="Vector Splat Word">
+    <in field="VB" />
+    <in field="UIMM" />
+    <out field="VD" />
+    <disasm>vspltw [VD], [VB], [UIMM]</disasm>
+  </insn>
+  <insn mnem="vspltw128"    opcode="18000730" form="VX128_3"  group="v" desc="Vector128 Splat Word">
+    <in field="VB" />
+    <in field="UIMM" />
+    <out field="VD" />
+    <disasm>vspltw128 [VD], [VB], [UIMM]</disasm>
+  </insn>
+  <insn mnem="vsr"          opcode="100002C4" form="VX"       group="v" desc="Vector Shift Right">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsr [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsrab"        opcode="10000304" form="VX"       group="v" desc="Vector Shift Right Algebraic Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsrab [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsrah"        opcode="10000344" form="VX"       group="v" desc="Vector Shift Right Algebraic Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsrah [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsraw"        opcode="10000384" form="VX"       group="v" desc="Vector Shift Right Algebraic Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsraw [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsraw128"     opcode="18000150" form="VX128"    group="v" desc="Vector128 Shift Right Arithmetic Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsraw128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsrb"         opcode="10000204" form="VX"       group="v" desc="Vector Shift Right Byte">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsrb [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsrh"         opcode="10000244" form="VX"       group="v" desc="Vector Shift Right Half Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsrh [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsro"         opcode="1000044C" form="VX"       group="v" desc="Vector Shift Right Octet">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsro [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsro128"      opcode="140003D0" form="VX128"    group="v" desc="Vector128 Shift Right Octet">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsro128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsrw"         opcode="10000284" form="VX"       group="v" desc="Vector Shift Right Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsrw [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsrw128"      opcode="180001D0" form="VX128"    group="v" desc="Vector128 Shift Right Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsrw128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsubcuw"      opcode="10000580" form="VX"       group="v" desc="Vector Subtract Carryout Unsigned Word">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsubcuw [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsubfp"       opcode="1000004A" form="VX"       group="v" desc="Vector Subtract Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsubfp [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsubfp128"    opcode="14000050" form="VX128"    group="v" desc="Vector128 Subtract Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsubfp128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsubsbs"      opcode="10000700" form="VX"       group="v" desc="Vector Subtract Signed Byte Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vsubsbs [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsubshs"      opcode="10000740" form="VX"       group="v" desc="Vector Subtract Signed Half Word Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vsubshs [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsubsws"      opcode="10000780" form="VX"       group="v" desc="Vector Subtract Signed Word Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vsubsws [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsububm"      opcode="10000400" form="VX"       group="v" desc="Vector Subtract Unsigned Byte Modulo">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsububm [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsububs"      opcode="10000600" form="VX"       group="v" desc="Vector Subtract Unsigned Byte Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vsububs [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsubuhm"      opcode="10000440" form="VX"       group="v" desc="Vector Subtract Unsigned Half Word Modulo">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsubuhm [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsubuhs"      opcode="10000640" form="VX"       group="v" desc="Vector Subtract Unsigned Half Word Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vsubuhs [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsubuwm"      opcode="10000480" form="VX"       group="v" desc="Vector Subtract Unsigned Word Modulo">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vsubuwm [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsubuws"      opcode="10000680" form="VX"       group="v" desc="Vector Subtract Unsigned Word Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vsubuws [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsumsws"      opcode="10000788" form="VX"       group="v" desc="Vector Sum Across Signed Word Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vsumsws [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsum2sws"     opcode="10000688" form="VX"       group="v" desc="Vector Sum Across Partial (1/2) Signed Word Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vsum2sws [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsum4sbs"     opcode="10000708" form="VX"       group="v" desc="Vector Sum Across Partial (1/4) Signed Byte Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vsum4sbs [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsum4shs"     opcode="10000648" form="VX"       group="v" desc="Vector Sum Across Partial (1/4) Signed Half Word Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vsum4shs [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vsum4ubs"     opcode="10000608" form="VX"       group="v" desc="Vector Sum Across Partial (1/4) Unsigned Byte Saturate">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vsum4ubs [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vupkhpx"      opcode="1000034E" form="VX"       group="v" desc="Vector Unpack High Pixel">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vupkhpx [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vupkhsb"      opcode="1000020E" form="VX"       group="v" desc="Vector Unpack High Signed Byte">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vupkhsb [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vupkhsb128"   opcode="18000380" form="VX128"    group="v" desc="Vector128 Unpack High Signed Byte">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vupkhsb128 [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vupkhsh"      opcode="1000024E" form="VX"       group="v" desc="Vector Unpack High Signed Half Word">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vupkhsh [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vupklpx"      opcode="100003CE" form="VX"       group="v" desc="Vector Unpack Low Pixel">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vupklpx [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vupklsb"      opcode="1000028E" form="VX"       group="v" desc="Vector Unpack Low Signed Byte">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vupklsb [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vupklsb128"   opcode="180003C0" form="VX128"    group="v" desc="Vector128 Unpack Low Signed Byte">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vupklsb128 [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vupklsh"      opcode="100002CE" form="VX"       group="v" desc="Vector Unpack Low Signed Half Word">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vupklsh [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vxor"         opcode="100004C4" form="VX"       group="v" desc="Vector Logical XOR">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vxor [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vxor128"      opcode="14000310" form="VX128"    group="v" desc="Vector128 Logical XOR">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vxor128 [VD], [VA], [VB]</disasm>
+  </insn>
 
-  <insn mnem="vcmpbfp"      opcode="100003C6" form="VC"       sub-form="D-A-B"            group="v" desc="Vector Compare Bounds Floating Point" />
-  <insn mnem="vcmpeqfp"     opcode="100000C6" form="VC"       sub-form="D-A-B"            group="v" desc="Vector Compare Equal-to Floating Point" />
-  <insn mnem="vcmpequb"     opcode="10000006" form="VC"       sub-form="D-A-B"            group="v" desc="Vector Compare Equal-to Unsigned Byte" />
-  <insn mnem="vcmpequh"     opcode="10000046" form="VC"       sub-form="D-A-B"            group="v" desc="Vector Compare Equal-to Unsigned Half Word" />
-  <insn mnem="vcmpequw"     opcode="10000086" form="VC"       sub-form="D-A-B"            group="v" desc="Vector Compare Equal-to Unsigned Word" />
-  <insn mnem="vcmpgefp"     opcode="100001C6" form="VC"       sub-form="D-A-B"            group="v" desc="Vector Compare Greater-Than-or-Equal-to Floating Point" />
-  <insn mnem="vcmpgtfp"     opcode="100002C6" form="VC"       sub-form="D-A-B"            group="v" desc="Vector Compare Greater-Than Floating Point" />
-  <insn mnem="vcmpgtsb"     opcode="10000306" form="VC"       sub-form="D-A-B"            group="v" desc="Vector Compare Greater-Than Signed Byte" />
-  <insn mnem="vcmpgtsh"     opcode="10000346" form="VC"       sub-form="D-A-B"            group="v" desc="Vector Compare Greater-Than Signed Half Word" />
-  <insn mnem="vcmpgtsw"     opcode="10000386" form="VC"       sub-form="D-A-B"            group="v" desc="Vector Compare Greater-Than Signed Word" />
-  <insn mnem="vcmpgtub"     opcode="10000206" form="VC"       sub-form="D-A-B"            group="v" desc="Vector Compare Greater-Than Unsigned Byte" />
-  <insn mnem="vcmpgtuh"     opcode="10000246" form="VC"       sub-form="D-A-B"            group="v" desc="Vector Compare Greater-Than Unsigned Half Word" />
-  <insn mnem="vcmpgtuw"     opcode="10000286" form="VC"       sub-form="D-A-B"            group="v" desc="Vector Compare Greater-Than Unsigned Word" />
-  <insn mnem="vmaddfp"      opcode="1000002E" form="VA"       sub-form="D-A-B-C"          group="v" desc="Vector Multiply-Add Floating Point" />
-  <insn mnem="vmhaddshs"    opcode="10000020" form="VA"       sub-form="D-A-B-C"          group="v" desc="Vector Multiply-High and Add Signed Signed Half Word Saturate" />
-  <insn mnem="vmhraddshs"   opcode="10000021" form="VA"       sub-form="D-A-B-C"          group="v" desc="Vector Multiply-High Round and Add Signed Signed Half Word Saturate" />
-  <insn mnem="vmladduhm"    opcode="10000022" form="VA"       sub-form="D-A-B-C"          group="v" desc="Vector Multiply-Low and Add Unsigned Half Word Modulo" />
-  <insn mnem="vmsummbm"     opcode="10000025" form="VA"       sub-form="D-A-B-C"          group="v" desc="Vector Multiply-Sum Mixed-Sign Byte Modulo" />
-  <insn mnem="vmsumshm"     opcode="10000028" form="VA"       sub-form="D-A-B-C"          group="v" desc="Vector Multiply-Sum Signed Half Word Modulo" />
-  <insn mnem="vmsumshs"     opcode="10000029" form="VA"       sub-form="D-A-B-C"          group="v" desc="Vector Multiply-Sum Signed Half Word Saturate" />
-  <insn mnem="vmsumubm"     opcode="10000024" form="VA"       sub-form="D-A-B-C"          group="v" desc="Vector Multiply-Sum Unsigned Byte Modulo" />
-  <insn mnem="vmsumuhm"     opcode="10000026" form="VA"       sub-form="D-A-B-C"          group="v" desc="Vector Multiply-Sum Unsigned Half Word Modulo" />
-  <insn mnem="vmsumuhs"     opcode="10000027" form="VA"       sub-form="D-A-B-C"          group="v" desc="Vector Multiply-Sum Unsigned Half Word Saturate" />
-  <insn mnem="vnmsubfp"     opcode="1000002F" form="VA"       sub-form="D-A-B-C"          group="v" desc="Vector Negative Multiply-Subtract Floating Point" />
-  <insn mnem="vperm"        opcode="1000002B" form="VA"       sub-form="D-A-B-C"          group="v" desc="Vector Permute" />
-  <insn mnem="vsel"         opcode="1000002A" form="VA"       sub-form="D-A-B-C"          group="v" desc="Vector Conditional Select" />
-  <insn mnem="vsldoi"       opcode="1000002C" form="VA"       sub-form="D-A-B-C"          group="v" desc="Vector Shift Left Double by Octet Immediate" />
-  <insn mnem="vsldoi128"    opcode="10000010" form="VX128_5"  sub-form="D-A-B-I"          group="v" desc="Vector128 Shift Left Double by Octet Immediate" />
-  <insn mnem="vperm128"     opcode="14000000" form="VX128_2"  sub-form="D-A-B-C"          group="v" desc="Vector128 Permute" />
-  <insn mnem="vaddfp128"    opcode="14000010" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Add Floating Point" />
-  <insn mnem="vsubfp128"    opcode="14000050" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Subtract Floating Point" />
-  <insn mnem="vmulfp128"    opcode="14000090" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Multiply Floating-Point" />
-  <insn mnem="vmaddfp128"   opcode="140000D0" form="VX128"    sub-form="D-A-D-B"          group="v" desc="Vector128 Multiply Add Floating Point" />
-  <insn mnem="vmaddcfp128"  opcode="14000110" form="VX128"    sub-form="D-A-D-B"          group="v" desc="Vector128 Multiply Add Floating Point" />
-  <insn mnem="vnmsubfp128"  opcode="14000150" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Negative Multiply-Subtract Floating Point" />
-  <insn mnem="vmsum3fp128"  opcode="14000190" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Multiply Sum 3-way Floating Point" />
-  <insn mnem="vmsum4fp128"  opcode="140001D0" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Multiply Sum 4-way Floating-Point" />
-  <insn mnem="vpkshss128"   opcode="14000200" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Pack Signed Half Word Signed Saturate" />
-  <insn mnem="vand128"      opcode="14000210" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Logical AND" />
-  <insn mnem="vpkshus128"   opcode="14000240" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Pack Signed Half Word Unsigned Saturate" />
-  <insn mnem="vandc128"     opcode="14000250" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Logical AND with Complement" />
-  <insn mnem="vpkswss128"   opcode="14000280" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Pack Signed Word Signed Saturate" />
-  <insn mnem="vnor128"      opcode="14000290" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Logical NOR" />
-  <insn mnem="vpkswus128"   opcode="140002C0" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Pack Signed Word Unsigned Saturate" />
-  <insn mnem="vor128"       opcode="140002D0" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Logical OR" />
-  <insn mnem="vpkuhum128"   opcode="14000300" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Pack Unsigned Half Word Unsigned Modulo" />
-  <insn mnem="vxor128"      opcode="14000310" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Logical XOR" />
-  <insn mnem="vpkuhus128"   opcode="14000340" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Pack Unsigned Half Word Unsigned Saturate" />
-  <insn mnem="vsel128"      opcode="14000350" form="VX128"    sub-form="D-A-B-D"          group="v" desc="Vector128 Conditional Select" />
-  <insn mnem="vpkuwum128"   opcode="14000380" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Pack Unsigned Word Unsigned Modulo" />
-  <insn mnem="vslo128"      opcode="14000390" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Shift Left Octet" />
-  <insn mnem="vpkuwus128"   opcode="140003C0" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Pack Unsigned Word Unsigned Saturate" />
-  <insn mnem="vsro128"      opcode="140003D0" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Shift Right Octet" />
-  <insn mnem="vpermwi128"   opcode="18000210" form="VX128_P"  sub-form="D-A-B-C"          group="v" desc="Vector128 Permutate Word Immediate" />
-  <insn mnem="vcfpsxws128"  opcode="18000230" form="VX128_3"  sub-form="D-B-SIMM"         group="v" desc="Vector128 Convert From Floating-Point to Signed Fixed-Point Word Saturate" />
-  <insn mnem="vcfpuxws128"  opcode="18000270" form="VX128_3"  sub-form="D-B-UIMM"         group="v" desc="Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate" />
-  <insn mnem="vcsxwfp128"   opcode="180002B0" form="VX128_3"  sub-form="D-B-SIMM"         group="v" desc="Vector128 Convert From Signed Fixed-Point Word to Floating-Point" />
-  <insn mnem="vcuxwfp128"   opcode="180002F0" form="VX128_3"  sub-form="D-B-SIMM"         group="v" desc="Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point" />
-  <insn mnem="vrfim128"     opcode="18000330" form="VX128_3"  sub-form="D-B"              group="v" desc="Vector128 Round to Floating-Point Integer toward -Infinity" />
-  <insn mnem="vrfin128"     opcode="18000370" form="VX128_3"  sub-form="D-B"              group="v" desc="Vector128 Round to Floating-Point Integer Nearest" />
-  <insn mnem="vrfip128"     opcode="180003B0" form="VX128_3"  sub-form="D-B"              group="v" desc="Vector128 Round to Floating-Point Integer toward +Infinity" />
-  <insn mnem="vrfiz128"     opcode="180003F0" form="VX128_3"  sub-form="D-B"              group="v" desc="Vector128 Round to Floating-Point Integer toward Zero" />
-  <insn mnem="vpkd3d128"    opcode="18000610" form="VX128_4"  sub-form="D-B"              group="v" desc="Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert" />
-  <insn mnem="vrefp128"     opcode="18000630" form="VX128_3"  sub-form="D-B"              group="v" desc="Vector128 Reciprocal Estimate Floating Point" />
-  <insn mnem="vrsqrtefp128" opcode="18000670" form="VX128_3"  sub-form="D-B"              group="v" desc="Vector128 Reciprocal Square Root Estimate Floating Point" />
-  <insn mnem="vexptefp128"  opcode="180006B0" form="VX128_3"  sub-form="D-B"              group="v" desc="Vector128 Log2 Estimate Floating Point" />
-  <insn mnem="vlogefp128"   opcode="180006F0" form="VX128_3"  sub-form="D-B"              group="v" desc="Vector128 Log2 Estimate Floating Point" />
-  <insn mnem="vrlimi128"    opcode="18000710" form="VX128_4"  sub-form="D-B-UIMM"         group="v" desc="Vector128 Rotate Left Immediate and Mask Insert" />
-  <insn mnem="vspltw128"    opcode="18000730" form="VX128_3"  sub-form="D-B-SIMM"         group="v" desc="Vector128 Splat Word" />
-  <insn mnem="vspltisw128"  opcode="18000770" form="VX128_3"  sub-form="D-B-SIMM"         group="v" desc="Vector128 Splat Immediate Signed Word" />
-  <insn mnem="vupkd3d128"   opcode="180007F0" form="VX128_3"  sub-form="D-B-SIMM"         group="v" desc="Vector128 Unpack D3Dtype" />
-  <insn mnem="vcmpeqfp128"  opcode="18000000" form="VX128_R"  sub-form="D-A-B"            group="v" desc="Vector128 Compare Equal-to Floating Point" />
-  <insn mnem="vrlw128"      opcode="18000050" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Rotate Left Word" />
-  <insn mnem="vcmpgefp128"  opcode="18000080" form="VX128_R"  sub-form="D-A-B"            group="v" desc="Vector128 Compare Greater-Than-or-Equal-to Floating Point" />
-  <insn mnem="vslw128"      opcode="180000D0" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Shift Left Integer Word" />
-  <insn mnem="vcmpgtfp128"  opcode="18000100" form="VX128_R"  sub-form="D-A-B"            group="v" desc="Vector128 Compare Greater-Than Floating-Point" />
-  <insn mnem="vsraw128"     opcode="18000150" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Shift Right Arithmetic Word" />
-  <insn mnem="vcmpbfp128"   opcode="18000180" form="VX128_R"  sub-form="D-A-B"            group="v" desc="Vector128 Compare Bounds Floating Point" />
-  <insn mnem="vsrw128"      opcode="180001D0" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Shift Right Word" />
-  <insn mnem="vcmpequw128"  opcode="18000200" form="VX128_R"  sub-form="D-A-B"            group="v" desc="Vector128 Compare Equal-to Unsigned Word" />
-  <insn mnem="vmaxfp128"    opcode="18000280" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Maximum Floating Point" />
-  <insn mnem="vminfp128"    opcode="180002C0" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Minimum Floating Point" />
-  <insn mnem="vmrghw128"    opcode="18000300" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Merge High Word" />
-  <insn mnem="vmrglw128"    opcode="18000340" form="VX128"    sub-form="D-A-B"            group="v" desc="Vector128 Merge Low Word" />
-  <insn mnem="vupkhsb128"   opcode="18000380" form="VX128"    sub-form="D-B"              group="v" desc="Vector128 Unpack High Signed Byte" />
-  <insn mnem="vupklsb128"   opcode="180003C0" form="VX128"    sub-form="D-B"              group="v" desc="Vector128 Unpack Low Signed Byte" />
+  <insn mnem="vmulfp128"    opcode="14000090" form="VX128"    group="v" desc="Vector128 Multiply Floating-Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmulfp128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmaddcfp128"  opcode="14000110" form="VX128"    group="v" desc="Vector128 Multiply Add Floating Point">
+    <in field="VA" />
+    <in field="VD" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmaddcfp128 [VD], [VA], [VD], [VB]</disasm>
+  </insn>
+  <insn mnem="vmsum3fp128"  opcode="14000190" form="VX128"    group="v" desc="Vector128 Multiply Sum 3-way Floating Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmsum3fp128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vmsum4fp128"  opcode="140001D0" form="VX128"    group="v" desc="Vector128 Multiply Sum 4-way Floating-Point">
+    <in field="VA" />
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vmsum4fp128 [VD], [VA], [VB]</disasm>
+  </insn>
+  <insn mnem="vpermwi128"   opcode="18000210" form="VX128_P"  group="v" desc="Vector128 Permutate Word Immediate">
+    <in field="VB" />
+    <in field="UIMM" />
+    <out field="VD" />
+    <disasm>vpermwi128 [VD], [VB], [UIMM]</disasm>
+  </insn>
+  <insn mnem="vcfpsxws128"  opcode="18000230" form="VX128_3"  group="v" desc="Vector128 Convert From Floating-Point to Signed Fixed-Point Word Saturate">
+    <in field="VB" />
+    <in field="UIMM" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vcfpsxws128 [VD], [VB], [UIMM]</disasm>
+  </insn>
+  <insn mnem="vcfpuxws128"  opcode="18000270" form="VX128_3"  group="v" desc="Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate">
+    <in field="VB" />
+    <in field="UIMM" />
+    <out field="VD" />
+    <out field="VSCR" />
+    <disasm>vcfpuxws128 [VD], [VB], [UIMM]</disasm>
+  </insn>
+  <insn mnem="vcsxwfp128"   opcode="180002B0" form="VX128_3"  group="v" desc="Vector128 Convert From Signed Fixed-Point Word to Floating-Point">
+    <in field="VB" />
+    <in field="UIMM" />
+    <out field="VD" />
+    <disasm>vcsxwfp128 [VD], [VB], [UIMM]</disasm>
+  </insn>
+  <insn mnem="vcuxwfp128"   opcode="180002F0" form="VX128_3"  group="v" desc="Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point">
+    <in field="VB" />
+    <in field="UIMM" />
+    <out field="VD" />
+    <disasm>vcuxwfp128 [VD], [VB], [UIMM]</disasm>
+  </insn>
+  <insn mnem="vpkd3d128"    opcode="18000610" form="VX128_4"  group="v" desc="Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert">
+    <in field="VB" />
+    <out field="VD" />
+    <!-- TODO(benvanik): arg types -->
+  </insn>
+  <insn mnem="vrlimi128"    opcode="18000710" form="VX128_4"  group="v" desc="Vector128 Rotate Left Immediate and Mask Insert">
+    <in field="VB" />
+    <out field="VD" />
+    <disasm>vrlimi128 [VD], [VB], [IMM], [z]</disasm>
+  </insn>
+  <insn mnem="vupkd3d128"   opcode="180007F0" form="VX128_3"  group="v" desc="Vector128 Unpack D3Dtype">
+    <in field="VB" />
+    <out field="VD" />
+    <!-- TODO(benvanik): arg types -->
+  </insn>
 </ppc-isa>
 </root>
diff --git a/tools/ppc-table-gen.py b/tools/ppc-table-gen.py
index 41940c17c..7eaf944f4 100644
--- a/tools/ppc-table-gen.py
+++ b/tools/ppc-table-gen.py
@@ -48,9 +48,8 @@ extended_opcode_bits = {
     'XW': [(25, 30)],
     'A': [(26, 30)],
     'DS': [(30, 31)],
-    'MD': [(27, 30)],
+    'MD': [(27, 29)],
     'MDS': [(27, 30)],
-    'MDSH': [(27, 29)],
     'XS': [(21, 29)],
     'DCBZ': [(6, 10), (21, 30)],  # like X
     }
@@ -84,7 +83,6 @@ def parse_insns(filename):
     i.opcode = int(e.attrib['opcode'], 16)
     i.mnem = e.attrib['mnem']
     i.form = e.attrib['form']
-    i.subform = e.attrib['sub-form']
     i.group = e.attrib['group']
     i.desc = e.attrib['desc']
     i.type = 'General'
@@ -92,6 +90,17 @@ def parse_insns(filename):
       i.type = 'Sync'
     i.op_primary = opcode_primary(i.opcode)
     i.op_extended = opcode_extended(i.opcode, i.form)
+    i.reads = []
+    i.writes = []
+    for r in e.findall('.//in'):
+      is_conditional = 'conditional' in r.attrib and r.attrib['conditional'] == 'true'
+      i.reads.append((r.attrib['field'], is_conditional))
+    for w in e.findall('.//out'):
+      is_conditional = 'conditional' in w.attrib and w.attrib['conditional'] == 'true'
+      i.writes.append((w.attrib['field'], is_conditional))
+    i.disasm_str = None
+    for d in e.findall('.//disasm'):
+      i.disasm_str = d.text
     insns.append(i)
   return insns
 
@@ -100,13 +109,6 @@ def c_mnem(x):
   return x.replace('.', 'x')
 
 
-def c_subform(x):
-  x = x.replace('-', '_')
-  if x[0] >= '0' and x[0] <= '9':
-    x = '_' + x
-  return x
-
-
 def c_group(x):
   return 'k' + x[0].upper() + x[1:]
 
@@ -115,6 +117,12 @@ def c_bool(x):
   return 'true' if x else 'false'
 
 
+def c_field(x):
+  base_name = 'k' + x[0]
+  cond_name = 'cond' if x[1] else ''
+  return base_name + cond_name
+
+
 def generate_opcodes(insns):
   l = []
   TAB = ' ' * 2
@@ -137,7 +145,6 @@ def generate_opcodes(insns):
 
   for i in insns:
     i.mnem = c_mnem(i.mnem)
-    i.subform = c_subform(i.subform)
   insns = sorted(insns, key = lambda i: i.mnem)
 
   w0('// All PPC opcodes in the same order they appear in ppc_opcode_table.h:')
@@ -182,44 +189,34 @@ def generate_table(insns):
   for i in insns:
     i.mnem = '"' + c_mnem(i.mnem) + '"'
     i.form = c_group(i.form)
-    i.subform = c_subform(i.subform)
-    i.desc = '"' + i.desc + '"'
     i.group = c_group(i.group)
     i.type = c_group(i.type)
 
   mnem_len = len(max(insns, key = lambda i: len(i.mnem)).mnem)
   form_len = len(max(insns, key = lambda i: len(i.form)).form)
-  subform_len = len(max(insns, key = lambda i: len(i.subform)).subform)
-  desc_len = len(max(insns, key = lambda i: len(i.desc)).desc)
   group_len = len(max(insns, key = lambda i: len(i.group)).group)
   type_len = len(max(insns, key = lambda i: len(i.type)).type)
 
   insns = sorted(insns, key = lambda i: i.mnem)
 
-  w0('#define INSTRUCTION(opcode, mnem, form, subform, group, type, desc) \\')
-  w0('    {opcode, mnem, PPCOpcodeFormat::form, PPCOpcodeGroup::group, PPCOpcodeType::type, desc, nullptr, nullptr}')
+  w0('#define INSTRUCTION(opcode, mnem, form, group, type) \\')
+  w0('    {PPCOpcodeType::type, nullptr}')
   w0('PPCOpcodeInfo ppc_opcode_table[] = {')
   fmt = 'INSTRUCTION(' + ', '.join([
       '0x%08x',
       '%-' + str(mnem_len) + 's',
       '%-' + str(form_len) + 's',
-      '%-' + str(subform_len) + 's',
       '%-' + str(group_len) + 's',
       '%-' + str(type_len) + 's',
-      '%-' + str(desc_len) + 's',
       ]) + '),'
   for i in insns:
-    w1(fmt % (i.opcode, i.mnem, i.form, i.subform, i.group, i.type, i.desc))
+    w1(fmt % (i.opcode, i.mnem, i.form, i.group, i.type))
   w0('};')
   w0('static_assert(sizeof(ppc_opcode_table) / sizeof(PPCOpcodeInfo) == static_cast<int>(PPCOpcode::kInvalid), "PPC table mismatch - rerun ppc-table-gen");')
   w0('')
   w0('const PPCOpcodeInfo& GetOpcodeInfo(PPCOpcode opcode) {')
   w1('return ppc_opcode_table[static_cast<int>(opcode)];')
   w0('}')
-  w0('void RegisterOpcodeDisasm(PPCOpcode opcode, InstrDisasmFn fn) {')
-  w1('assert_null(ppc_opcode_table[static_cast<int>(opcode)].disasm);')
-  w1('ppc_opcode_table[static_cast<int>(opcode)].disasm = fn;')
-  w0('}')
   w0('void RegisterOpcodeEmitter(PPCOpcode opcode, InstrEmitFn fn) {')
   w1('assert_null(ppc_opcode_table[static_cast<int>(opcode)].emit);')
   w1('ppc_opcode_table[static_cast<int>(opcode)].emit = fn;')
@@ -234,6 +231,171 @@ def generate_table(insns):
   return '\n'.join(l)
 
 
+def literal_mnem(x):
+  x = x.replace('.', '_')
+  x = x.replace('"', '')
+  return x
+
+def generate_token_append(i, token):
+  # Rc = . iff Rc=1
+  # OE = o iff OE=1
+  if token == 'Rc':
+    return 'if (d.%s.Rc()) str->Append(\'.\');' % (i.o_form)
+  elif token == 'OE':
+    return 'if (d.%s.OE()) str->Append(\'o\');' % (i.o_form)
+  elif token == 'LK':
+    return 'if (d.%s.LK()) str->Append(\'l\');' % (i.o_form)
+  elif token == 'AA':
+    return 'if (d.%s.AA()) str->Append(\'a\');' % (i.o_form)
+  elif token in ['RA', 'RA0', 'RB', 'RC', 'RT', 'RS', 'RD']:
+    return 'str->AppendFormat("r%%d", d.%s.%s());' % (i.o_form, token)
+  elif token in ['FA', 'FB', 'FC', 'FT', 'FS', 'FD']:
+    return 'str->AppendFormat("fr%%d", d.%s.%s());' % (i.o_form, token)
+  elif token in ['VA', 'VB', 'VC', 'VT', 'VS', 'VD']:
+    return 'str->AppendFormat("vr%%d", d.%s.%s());' % (i.o_form, token)
+  elif token in ['CRFD', 'CRFS']:
+    return 'str->AppendFormat("crf%%d", d.%s.%s());' % (i.o_form, token)
+  elif token in ['CRBA', 'CRBB', 'CRBD']:
+    return 'str->AppendFormat("crb%%d", d.%s.%s());' % (i.o_form, token)
+  elif token in ['BO', 'BI', 'TO', 'SPR', 'TBR', 'L', 'FM', 'MB', 'ME', 'SH', 'IMM', 'z']:
+    return 'str->AppendFormat("%%d", d.%s.%s());' % (i.o_form, token)
+  elif token == 'UIMM':
+    return 'str->AppendFormat("0x%%X", d.%s.%s());' % (i.o_form, token)
+  elif token in ['d', 'ds', 'SIMM']:
+    return 'str->AppendFormat(d.%s.%s() < 0 ? "-0x%%X" : "0x%%X", std::abs(d.%s.%s()));' % (i.o_form, token, i.o_form, token)
+  elif token == 'ADDR':
+    return 'str->AppendFormat("0x%%X", d.%s.%s());' % (i.o_form, token)
+  return 'str->AppendFormat("(UNHANDLED %s)");' % token
+
+
+def generate_disasm(insns):
+  l = []
+  TAB = ' ' * 2
+  def w0(x): l.append(x)
+  def w1(x): w0(TAB * 1 + x)
+  def w2(x): w0(TAB * 2 + x)
+  def w3(x): w0(TAB * 3 + x)
+
+  w0('// This code was autogenerated by %s. Do not modify!' % (sys.argv[0]))
+  w0('// clang-format off')
+  w0('#include <cstdint>')
+  w0('')
+  w0('#include "xenia/base/assert.h"')
+  w0('#include "xenia/cpu/ppc/ppc_decode_data.h"')
+  w0('#include "xenia/cpu/ppc/ppc_opcode.h"')
+  w0('#include "xenia/cpu/ppc/ppc_opcode_info.h"')
+  w0('')
+  w0('namespace xe {')
+  w0('namespace cpu {')
+  w0('namespace ppc {')
+  w0('')
+  w0('constexpr size_t kNamePad = 11;')
+  w0('const uint8_t kSpaces[kNamePad] = {0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20};')
+  w0('void PadStringBuffer(StringBuffer* str, size_t base, size_t pad) {')
+  w1('size_t added_len = str->length() - base;')
+  w1('if (added_len < pad) str->AppendBytes(kSpaces, kNamePad - added_len);')
+  w0('}')
+  w0('')
+
+  for i in insns:
+    i.mnem = '"' + c_mnem(i.mnem) + '"'
+    i.o_form = i.form
+    i.form = c_group(i.form)
+    i.desc = '"' + i.desc + '"'
+    i.group = c_group(i.group)
+    i.type = c_group(i.type)
+
+  mnem_len = len(max(insns, key = lambda i: len(i.mnem)).mnem)
+  form_len = len(max(insns, key = lambda i: len(i.form)).form)
+  desc_len = len(max(insns, key = lambda i: len(i.desc)).desc)
+  group_len = len(max(insns, key = lambda i: len(i.group)).group)
+  type_len = len(max(insns, key = lambda i: len(i.type)).type)
+
+  insns = sorted(insns, key = lambda i: i.mnem)
+
+  # TODO(benvanik): support alts:
+  # <disasm cond="![RA]">li [RD], [SIMM]</disasm>
+  for i in insns:
+    if not i.disasm_str:
+      continue
+    w0('void PrintDisasm_%s(const PPCDecodeData& d, StringBuffer* str) {' % (literal_mnem(i.mnem)))
+    w1('// ' + i.disasm_str)
+    w1('size_t str_start = str->length();')
+    current_str = ''
+    j = 0
+    first_space = False
+    while j < len(i.disasm_str):
+      c = i.disasm_str[j]
+      if c == '[':
+        if current_str:
+          w1('str->Append("%s");' % (current_str))
+          current_str = ''
+        token = i.disasm_str[j + 1 : i.disasm_str.index(']', j)]
+        j += len(token) + 1
+        w1(generate_token_append(i, token))
+      else:
+        if c == ' ' and not first_space:
+          if current_str:
+            w1('str->Append("%s");' % (current_str))
+            current_str = ''
+          w1('PadStringBuffer(str, str_start, kNamePad);')
+          first_space = True
+        else:
+          current_str += c
+      j += 1
+    if current_str:
+      w1('str->Append("%s");' % (current_str))
+    if not first_space:
+      w1('PadStringBuffer(str, str_start, kNamePad);')
+    w0('}')
+
+  w0('#define INIT_LIST(...) {__VA_ARGS__}')
+  w0('#define INSTRUCTION(opcode, mnem, form, group, type, desc, reads, writes, fn) \\')
+  w0('    {PPCOpcodeGroup::group, PPCOpcodeFormat::form, opcode, mnem, desc, INIT_LIST reads, INIT_LIST writes, fn}')
+  w0('PPCOpcodeDisasmInfo ppc_opcode_disasm_table[] = {')
+  fmt = 'INSTRUCTION(' + ', '.join([
+      '0x%08x',
+      '%-' + str(mnem_len) + 's',
+      '%-' + str(form_len) + 's',
+      '%-' + str(group_len) + 's',
+      '%-' + str(type_len) + 's',
+      '%-' + str(desc_len) + 's',
+      '(%s)',
+      '(%s)',
+      '%s',
+      ]) + '),'
+  for i in insns:
+    w1(fmt % (
+        i.opcode,
+        i.mnem,
+        i.form,
+        i.group,
+        i.type,
+        i.desc,
+        ','.join(['PPCOpcodeField::' + c_field(r) for r in i.reads]),
+        ','.join(['PPCOpcodeField::' + c_field(w) for w in i.writes]),
+        ('PrintDisasm_' + literal_mnem(i.mnem)) if i.disasm_str else 'nullptr',
+        ))
+  w0('};')
+  w0('static_assert(sizeof(ppc_opcode_disasm_table) / sizeof(PPCOpcodeDisasmInfo) == static_cast<int>(PPCOpcode::kInvalid), "PPC table mismatch - rerun ppc-table-gen");')
+  w0('')
+  w0('const PPCOpcodeDisasmInfo& GetOpcodeDisasmInfo(PPCOpcode opcode) {')
+  w1('return ppc_opcode_disasm_table[static_cast<int>(opcode)];')
+  w0('}')
+  w0('void RegisterOpcodeDisasm(PPCOpcode opcode, InstrDisasmFn fn) {')
+  w1('assert_null(ppc_opcode_disasm_table[static_cast<int>(opcode)].disasm);')
+  w1('ppc_opcode_disasm_table[static_cast<int>(opcode)].disasm = fn;')
+  w0('}')
+
+  w0('')
+  w0('}  // namespace ppc')
+  w0('}  // namespace cpu')
+  w0('}  // namespace xe')
+  w0('')
+
+  return '\n'.join(l)
+
+
 def generate_lookup(insns):
   l = []
   TAB = ' ' * 2
@@ -356,5 +518,8 @@ if __name__ == '__main__':
   with open(os.path.join(ppc_src_path, 'ppc_opcode_table.cc'), 'w') as f:
     f.write(generate_table(insns))
   insns = parse_insns(os.path.join(self_path, 'ppc-instructions.xml'))
+  with open(os.path.join(ppc_src_path, 'ppc_opcode_disasm.cc'), 'w') as f:
+    f.write(generate_disasm(insns))
+  insns = parse_insns(os.path.join(self_path, 'ppc-instructions.xml'))
   with open(os.path.join(ppc_src_path, 'ppc_opcode_lookup.cc'), 'w') as f:
     f.write(generate_lookup(insns))