Test cleanup.
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59b9e9ceb0
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src/xenia/cpu/frontend/testing
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@ -287,7 +287,7 @@ test_adde_cr_2:
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adde. r3, r4, r5
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adde. r3, r4, r5
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mfcr r11
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mfcr r11
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adde. r6, r0, r0
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adde. r6, r0, r0
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mfcr 12
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mfcr r12
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blr
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blr
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#_ REGISTER_OUT r3 4
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#_ REGISTER_OUT r3 4
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r4 1
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@ -40,7 +40,7 @@ test_addic_3:
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test_addic_3_constant:
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test_addic_3_constant:
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li r4, 0xFFFFFFFF
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li r4, 0xFFFFFFFF
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srw r4, r4, 0
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srwi r4, r4, 0
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addic r4, r4, 1
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addic r4, r4, 1
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adde r6, r0, r0
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adde r6, r0, r0
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blr
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blr
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@ -2,9 +2,9 @@ test_nor_cr_1:
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#_ REGISTER_IN r3 0x00000000FFFFFFFF
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#_ REGISTER_IN r3 0x00000000FFFFFFFF
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nor. r3, r3, r3
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nor. r3, r3, r3
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li r3, 0
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li r3, 0
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bne .nor_cr_1_ne
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bne nor_cr_1_ne
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li r3, 1
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li r3, 1
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.nor_cr_1_ne:
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nor_cr_1_ne:
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blr
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r3 1
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@ -13,8 +13,8 @@ test_nor_cr_1_constant:
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clrldi r3, r3, 32
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clrldi r3, r3, 32
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nor. r3, r3, r3
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nor. r3, r3, r3
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li r3, 0
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li r3, 0
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bne .nor_cr_1_constant_ne
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bne nor_cr_1_constant_ne
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li r3, 1
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li r3, 1
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.nor_cr_1_constant_ne:
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nor_cr_1_constant_ne:
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blr
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r3 1
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@ -1,4 +1,4 @@
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.macro make_test_constant dest, a, b, c, d
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.macro make_full_test_constant dest, a, b, c, d
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lis \dest, \a
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lis \dest, \a
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ori \dest, \dest, \b
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ori \dest, \dest, \b
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sldi \dest, \dest, 32
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sldi \dest, \dest, 32
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@ -17,8 +17,8 @@ test_rlwimi:
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#_ REGISTER_OUT r6 0xDEADBEEF4000C003
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#_ REGISTER_OUT r6 0xDEADBEEF4000C003
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test_rlwimi_constant:
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test_rlwimi_constant:
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make_test_constant r4, 0xCAFE, 0xBABE, 0x9000, 0x3000
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make_full_test_constant r4, 0xCAFE, 0xBABE, 0x9000, 0x3000
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make_test_constant r6, 0xDEAD, 0xBEEF, 0x0000, 0x0003
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make_full_test_constant r6, 0xDEAD, 0xBEEF, 0x0000, 0x0003
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rlwimi r6, r4, 2, 0, 0x1D
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rlwimi r6, r4, 2, 0, 0x1D
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blr
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blr
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#_ REGISTER_OUT r4 0xCAFEBABE90003000
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#_ REGISTER_OUT r4 0xCAFEBABE90003000
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@ -1,38 +1,3 @@
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test_extrwi_1:
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# extrwi ra,rs,n,b (n > 0) == rlwinm ra,rs,b+n,32-n,31
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#_ REGISTER_IN r5 0x30
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# rlwinm r7, r5, 29, 28, 31
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extrwi r7, r5, 4, 25
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blr
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#_ REGISTER_OUT r5 0x30
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#_ REGISTER_OUT r7 0x06
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test_extrwi_1_constant:
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# extrwi ra,rs,n,b (n > 0) == rlwinm ra,rs,b+n,32-n,31
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li r5, 0x30
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# rlwinm r7, r5, 29, 28, 31
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extrwi r7, r5, 4, 25
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blr
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#_ REGISTER_OUT r5 0x30
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#_ REGISTER_OUT r7 0x06
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test_extrwi_2:
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#_ REGISTER_IN r5 0xFFFFFFFF01234567
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extrwi r7, r5, 16, 10
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blr
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#_ REGISTER_OUT r5 0xFFFFFFFF01234567
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#_ REGISTER_OUT r7 0x0000000000008D15
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test_extrwi_2_constant:
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li r5, -1
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sldi r5, r5, 32
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oris r5, r5, 0x0123
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ori r5, r5, 0x4567
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extrwi r7, r5, 16, 10
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blr
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#_ REGISTER_OUT r5 0xFFFFFFFF01234567
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#_ REGISTER_OUT r7 0x0000000000008D15
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test_rlwinm_1:
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test_rlwinm_1:
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#_ REGISTER_IN r4 0x12345678
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#_ REGISTER_IN r4 0x12345678
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rlwinm r3, r4, 24, 8, 15
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rlwinm r3, r4, 24, 8, 15
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@ -172,9 +137,50 @@ test_rlwinm_9_constant:
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#_ REGISTER_OUT r3 0x00001234
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#_ REGISTER_OUT r3 0x00001234
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#_ REGISTER_OUT r4 0x12345678
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#_ REGISTER_OUT r4 0x12345678
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# Extract and right justify immediate
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# extrwi RA, RS, n, b
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# rlwinm RA, RS, b+n, 32-n, 31
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test_extrwi_1:
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# extrwi ra,rs,n,b (n > 0) == rlwinm ra,rs,b+n,32-n,31
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#_ REGISTER_IN r5 0x30
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rlwinm r7, r5, 29, 28, 31
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#extrwi r7, r5, 4, 25
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blr
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#_ REGISTER_OUT r5 0x30
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#_ REGISTER_OUT r7 0x06
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test_extrwi_1_constant:
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# extrwi ra,rs,n,b (n > 0) == rlwinm ra,rs,b+n,32-n,31
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li r5, 0x30
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rlwinm r7, r5, 29, 28, 31
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#extrwi r7, r5, 4, 25
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blr
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#_ REGISTER_OUT r5 0x30
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#_ REGISTER_OUT r7 0x06
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test_extrwi_2:
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#_ REGISTER_IN r5 0xFFFFFFFF01234567
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rlwinm r7, r5, 26, 16, 31
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#extrwi r7, r5, 16, 10
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blr
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#_ REGISTER_OUT r5 0xFFFFFFFF01234567
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#_ REGISTER_OUT r7 0x0000000000008D15
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test_extrwi_2_constant:
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li r5, -1
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sldi r5, r5, 32
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oris r5, r5, 0x0123
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ori r5, r5, 0x4567
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rlwinm r7, r5, 26, 16, 31
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#extrwi r7, r5, 16, 10
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blr
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#_ REGISTER_OUT r5 0xFFFFFFFF01234567
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#_ REGISTER_OUT r7 0x0000000000008D15
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test_extrwi_cr_1:
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test_extrwi_cr_1:
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#_ REGISTER_IN r5 0x30
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#_ REGISTER_IN r5 0x30
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extrwi. r7, r5, 4, 25
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rlwinm. r7, r5, 29, 28, 31
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#extrwi. r7, r5, 4, 25
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mfcr r12
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mfcr r12
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blr
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blr
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#_ REGISTER_OUT r5 0x30
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#_ REGISTER_OUT r5 0x30
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@ -183,7 +189,8 @@ test_extrwi_cr_1:
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test_extrwi_cr_1_constant:
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test_extrwi_cr_1_constant:
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li r5, 0x30
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li r5, 0x30
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extrwi. r7, r5, 4, 25
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rlwinm. r7, r5, 29, 28, 31
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#extrwi. r7, r5, 4, 25
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mfcr r12
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mfcr r12
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blr
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blr
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#_ REGISTER_OUT r5 0x30
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#_ REGISTER_OUT r5 0x30
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@ -192,7 +199,8 @@ test_extrwi_cr_1_constant:
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test_extrwi_cr_2:
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test_extrwi_cr_2:
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#_ REGISTER_IN r5 0xFFFFFFFF01234567
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#_ REGISTER_IN r5 0xFFFFFFFF01234567
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extrwi. r7, r5, 16, 10
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rlwinm. r7, r5, 26, 16, 31
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#extrwi. r7, r5, 16, 10
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mfcr r12
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mfcr r12
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blr
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blr
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#_ REGISTER_OUT r5 0xFFFFFFFF01234567
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#_ REGISTER_OUT r5 0xFFFFFFFF01234567
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@ -204,7 +212,8 @@ test_extrwi_cr_2_constant:
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sldi r5, r5, 32
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sldi r5, r5, 32
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oris r5, r5, 0x0123
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oris r5, r5, 0x0123
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ori r5, r5, 0x4567
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ori r5, r5, 0x4567
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extrwi. r7, r5, 16, 10
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rlwinm. r7, r5, 26, 16, 31
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#extrwi. r7, r5, 16, 10
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mfcr r12
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mfcr r12
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blr
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blr
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#_ REGISTER_OUT r5 0xFFFFFFFF01234567
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#_ REGISTER_OUT r5 0xFFFFFFFF01234567
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@ -213,7 +222,8 @@ test_extrwi_cr_2_constant:
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test_extrwi_cr_3:
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test_extrwi_cr_3:
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#_ REGISTER_IN r5 0xFFFFFFFF00000000
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#_ REGISTER_IN r5 0xFFFFFFFF00000000
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extrwi. r7, r5, 16, 10
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rlwinm. r7, r5, 26, 16, 31
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#extrwi. r7, r5, 16, 10
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mfcr r12
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mfcr r12
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blr
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blr
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#_ REGISTER_OUT r5 0xFFFFFFFF00000000
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#_ REGISTER_OUT r5 0xFFFFFFFF00000000
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@ -223,7 +233,8 @@ test_extrwi_cr_3:
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test_extrwi_cr_3_constant:
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test_extrwi_cr_3_constant:
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li r5, -1
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li r5, -1
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sldi r5, r5, 32
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sldi r5, r5, 32
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extrwi. r7, r5, 16, 10
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rlwinm. r7, r5, 26, 16, 31
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#extrwi. r7, r5, 16, 10
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mfcr r12
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mfcr r12
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blr
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blr
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#_ REGISTER_OUT r5 0xFFFFFFFF00000000
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#_ REGISTER_OUT r5 0xFFFFFFFF00000000
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@ -5,10 +5,10 @@ test_equiv_1:
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subf r8, r11, r30
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subf r8, r11, r30
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addic r7, r8, -1
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addic r7, r8, -1
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subfe. r31, r7, r8
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subfe. r31, r7, r8
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beq .test_equiv_1_good
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beq equiv_1_good
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li r12, 0
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li r12, 0
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blr
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blr
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.test_equiv_1_good:
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equiv_1_good:
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li r12, 1
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li r12, 1
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blr
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blr
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#_ REGISTER_OUT r7 0xfffffffeffffffff
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#_ REGISTER_OUT r7 0xfffffffeffffffff
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@ -26,10 +26,10 @@ test_equiv_2:
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subf r8, r11, r30
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subf r8, r11, r30
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addic r7, r8, -1
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addic r7, r8, -1
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subfe. r31, r7, r8
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subfe. r31, r7, r8
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beq .test_equiv_2_good
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beq equiv_2_good
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li r12, 0
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li r12, 0
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blr
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blr
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.test_equiv_2_good:
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equiv_2_good:
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li r12, 1
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li r12, 1
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blr
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blr
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#_ REGISTER_OUT r7 0xffffffffffffffff
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#_ REGISTER_OUT r7 0xffffffffffffffff
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