Test cleanup.

src/xenia/cpu/frontend/testing/instr_adde.s

@@ -287,7 +287,7 @@ test_adde_cr_2:
   adde. r3, r4, r5
   mfcr r11
   adde. r6, r0, r0
-  mfcr 12
+  mfcr r12
   blr
   #_ REGISTER_OUT r3 4
   #_ REGISTER_OUT r4 1

src/xenia/cpu/frontend/testing/instr_addic.s

@@ -40,7 +40,7 @@ test_addic_3:
 
 test_addic_3_constant:
   li r4, 0xFFFFFFFF
-  srw r4, r4, 0
+  srwi r4, r4, 0
   addic r4, r4, 1
   adde r6, r0, r0
   blr

src/xenia/cpu/frontend/testing/instr_nor.s

@@ -2,9 +2,9 @@ test_nor_cr_1:
   #_ REGISTER_IN r3 0x00000000FFFFFFFF
   nor. r3, r3, r3
   li r3, 0
-  bne .nor_cr_1_ne
+  bne nor_cr_1_ne
   li r3, 1
-  .nor_cr_1_ne:
+nor_cr_1_ne:
   blr
   #_ REGISTER_OUT r3 1
 
@@ -13,8 +13,8 @@ test_nor_cr_1_constant:
   clrldi r3, r3, 32
   nor. r3, r3, r3
   li r3, 0
-  bne .nor_cr_1_constant_ne
+  bne nor_cr_1_constant_ne
   li r3, 1
-  .nor_cr_1_constant_ne:
+nor_cr_1_constant_ne:
   blr
   #_ REGISTER_OUT r3 1

src/xenia/cpu/frontend/testing/instr_rlwimi.s

@@ -1,4 +1,4 @@
-.macro make_test_constant dest, a, b, c, d
+.macro make_full_test_constant dest, a, b, c, d
   lis \dest, \a
   ori \dest, \dest, \b
   sldi \dest, \dest, 32
@@ -17,8 +17,8 @@ test_rlwimi:
   #_ REGISTER_OUT r6 0xDEADBEEF4000C003
 
 test_rlwimi_constant:
-  make_test_constant r4, 0xCAFE, 0xBABE, 0x9000, 0x3000
-  make_test_constant r6, 0xDEAD, 0xBEEF, 0x0000, 0x0003
+  make_full_test_constant r4, 0xCAFE, 0xBABE, 0x9000, 0x3000
+  make_full_test_constant r6, 0xDEAD, 0xBEEF, 0x0000, 0x0003
   rlwimi r6, r4, 2, 0, 0x1D
   blr
   #_ REGISTER_OUT r4 0xCAFEBABE90003000

src/xenia/cpu/frontend/testing/instr_rlwinm.s

@@ -1,38 +1,3 @@
-test_extrwi_1:
-  # extrwi ra,rs,n,b (n > 0) == rlwinm ra,rs,b+n,32-n,31
-  #_ REGISTER_IN r5 0x30
-  # rlwinm r7, r5, 29, 28, 31
-  extrwi r7, r5, 4, 25
-  blr
-  #_ REGISTER_OUT r5 0x30
-  #_ REGISTER_OUT r7 0x06
-
-test_extrwi_1_constant:
-  # extrwi ra,rs,n,b (n > 0) == rlwinm ra,rs,b+n,32-n,31
-  li r5, 0x30
-  # rlwinm r7, r5, 29, 28, 31
-  extrwi r7, r5, 4, 25
-  blr
-  #_ REGISTER_OUT r5 0x30
-  #_ REGISTER_OUT r7 0x06
-
-test_extrwi_2:
-  #_ REGISTER_IN r5 0xFFFFFFFF01234567
-  extrwi r7, r5, 16, 10
-  blr
-  #_ REGISTER_OUT r5 0xFFFFFFFF01234567
-  #_ REGISTER_OUT r7 0x0000000000008D15
-
-test_extrwi_2_constant:
-  li r5, -1
-  sldi r5, r5, 32
-  oris r5, r5, 0x0123
-  ori r5, r5, 0x4567
-  extrwi r7, r5, 16, 10
-  blr
-  #_ REGISTER_OUT r5 0xFFFFFFFF01234567
-  #_ REGISTER_OUT r7 0x0000000000008D15
-
 test_rlwinm_1:
   #_ REGISTER_IN r4 0x12345678
   rlwinm r3, r4, 24, 8, 15
@@ -172,9 +137,50 @@ test_rlwinm_9_constant:
   #_ REGISTER_OUT r3 0x00001234
   #_ REGISTER_OUT r4 0x12345678
 
+# Extract and right justify immediate
+# extrwi RA, RS, n, b
+# rlwinm RA, RS, b+n, 32-n, 31
+test_extrwi_1:
+  # extrwi ra,rs,n,b (n > 0) == rlwinm ra,rs,b+n,32-n,31
+  #_ REGISTER_IN r5 0x30
+  rlwinm r7, r5, 29, 28, 31
+  #extrwi r7, r5, 4, 25
+  blr
+  #_ REGISTER_OUT r5 0x30
+  #_ REGISTER_OUT r7 0x06
+
+test_extrwi_1_constant:
+  # extrwi ra,rs,n,b (n > 0) == rlwinm ra,rs,b+n,32-n,31
+  li r5, 0x30
+  rlwinm r7, r5, 29, 28, 31
+  #extrwi r7, r5, 4, 25
+  blr
+  #_ REGISTER_OUT r5 0x30
+  #_ REGISTER_OUT r7 0x06
+
+test_extrwi_2:
+  #_ REGISTER_IN r5 0xFFFFFFFF01234567
+  rlwinm r7, r5, 26, 16, 31
+  #extrwi r7, r5, 16, 10
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFF01234567
+  #_ REGISTER_OUT r7 0x0000000000008D15
+
+test_extrwi_2_constant:
+  li r5, -1
+  sldi r5, r5, 32
+  oris r5, r5, 0x0123
+  ori r5, r5, 0x4567
+  rlwinm r7, r5, 26, 16, 31
+  #extrwi r7, r5, 16, 10
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFF01234567
+  #_ REGISTER_OUT r7 0x0000000000008D15
+
 test_extrwi_cr_1:
   #_ REGISTER_IN r5 0x30
-  extrwi. r7, r5, 4, 25
+  rlwinm. r7, r5, 29, 28, 31
+  #extrwi. r7, r5, 4, 25
   mfcr r12
   blr
   #_ REGISTER_OUT r5 0x30
@@ -183,7 +189,8 @@ test_extrwi_cr_1:
 
 test_extrwi_cr_1_constant:
   li r5, 0x30
-  extrwi. r7, r5, 4, 25
+  rlwinm. r7, r5, 29, 28, 31
+  #extrwi. r7, r5, 4, 25
   mfcr r12
   blr
   #_ REGISTER_OUT r5 0x30
@@ -192,7 +199,8 @@ test_extrwi_cr_1_constant:
 
 test_extrwi_cr_2:
   #_ REGISTER_IN r5 0xFFFFFFFF01234567
-  extrwi. r7, r5, 16, 10
+  rlwinm. r7, r5, 26, 16, 31
+  #extrwi. r7, r5, 16, 10
   mfcr r12
   blr
   #_ REGISTER_OUT r5 0xFFFFFFFF01234567
@@ -204,7 +212,8 @@ test_extrwi_cr_2_constant:
   sldi r5, r5, 32
   oris r5, r5, 0x0123
   ori r5, r5, 0x4567
-  extrwi. r7, r5, 16, 10
+  rlwinm. r7, r5, 26, 16, 31
+  #extrwi. r7, r5, 16, 10
   mfcr r12
   blr
   #_ REGISTER_OUT r5 0xFFFFFFFF01234567
@@ -213,7 +222,8 @@ test_extrwi_cr_2_constant:
 
 test_extrwi_cr_3:
   #_ REGISTER_IN r5 0xFFFFFFFF00000000
-  extrwi. r7, r5, 16, 10
+  rlwinm. r7, r5, 26, 16, 31
+  #extrwi. r7, r5, 16, 10
   mfcr r12
   blr
   #_ REGISTER_OUT r5 0xFFFFFFFF00000000
@@ -223,7 +233,8 @@ test_extrwi_cr_3:
 test_extrwi_cr_3_constant:
   li r5, -1
   sldi r5, r5, 32
-  extrwi. r7, r5, 16, 10
+  rlwinm. r7, r5, 26, 16, 31
+  #extrwi. r7, r5, 16, 10
   mfcr r12
   blr
   #_ REGISTER_OUT r5 0xFFFFFFFF00000000

src/xenia/cpu/frontend/testing/sequence_branch_carry.s

@@ -5,10 +5,10 @@ test_equiv_1:
   subf r8, r11, r30
   addic r7, r8, -1
   subfe. r31, r7, r8
-  beq .test_equiv_1_good
+  beq equiv_1_good
   li r12, 0
   blr
-.test_equiv_1_good:
+equiv_1_good:
   li r12, 1
   blr
   #_ REGISTER_OUT r7 0xfffffffeffffffff
@@ -26,10 +26,10 @@ test_equiv_2:
   subf r8, r11, r30
   addic r7, r8, -1
   subfe. r31, r7, r8
-  beq .test_equiv_2_good
+  beq equiv_2_good
   li r12, 0
   blr
-.test_equiv_2_good:
+equiv_2_good:
   li r12, 1
   blr
   #_ REGISTER_OUT r7 0xffffffffffffffff