[GPU] Depth bias support
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@ -714,6 +714,66 @@ bool PipelineCache::SetDynamicState(VkCommandBuffer command_buffer,
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vkCmdSetViewport(command_buffer, 0, 1, &viewport_rect);
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}
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// VK_DYNAMIC_STATE_DEPTH_BIAS
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// No separate front/back bias in Vulkan - using what's more expected to work.
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// No need to reset to 0 if not enabled in the pipeline - recheck conditions.
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float depth_bias_scales[2] = {0}, depth_bias_offsets[2] = {0};
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auto cull_mode = regs.pa_su_sc_mode_cntl & 3;
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if (cull_mode != 1) {
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// Front faces are not culled.
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depth_bias_scales[0] =
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register_file_->values[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_SCALE].f32;
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depth_bias_offsets[0] =
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register_file_->values[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_OFFSET].f32;
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}
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if (cull_mode != 2) {
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// Back faces are not culled.
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depth_bias_scales[1] =
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register_file_->values[XE_GPU_REG_PA_SU_POLY_OFFSET_BACK_SCALE].f32;
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depth_bias_offsets[1] =
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register_file_->values[XE_GPU_REG_PA_SU_POLY_OFFSET_BACK_OFFSET].f32;
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}
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if (depth_bias_scales[0] != 0.0f || depth_bias_scales[1] != 0.0f ||
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depth_bias_offsets[0] != 0.0f || depth_bias_offsets[1] != 0.0f) {
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float depth_bias_scale, depth_bias_offset;
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// Prefer front if not culled and offset for both is enabled.
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// However, if none are culled, and there's no front offset, use back offset
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// (since there was an intention to enable depth offset at all).
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// As SetRenderState sets for both sides, this should be very rare anyway.
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// TODO(Triang3l): Verify the intentions if this happens in real games.
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if (depth_bias_scales[0] != 0.0f || depth_bias_offsets[0] != 0.0f) {
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depth_bias_scale = depth_bias_scales[0];
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depth_bias_offset = depth_bias_offsets[0];
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} else {
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depth_bias_scale = depth_bias_scales[1];
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depth_bias_offset = depth_bias_offsets[1];
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}
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// Convert to Vulkan units based on the values in Call of Duty 4:
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// r_polygonOffsetScale is -1 there, but 32 in the register.
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// r_polygonOffsetBias is -1 also, but passing 2/65536.
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// 1/65536 and 2 scales are applied separately, however, and for shadow maps
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// 0.5/65536 is passed (while sm_polygonOffsetBias is 0.5), and with 32768
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// it would be 0.25, which seems too small. So using 65536, assuming it's a
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// common scale value (which also looks less arbitrary than 32768).
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// TODO(Triang3l): Investigate, also considering the depth format (kD24FS8).
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// Possibly refer to:
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// https://www.winehq.org/pipermail/wine-patches/2015-July/141200.html
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float depth_bias_scale_vulkan = depth_bias_scale * (1.0f / 32.0f);
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float depth_bias_offset_vulkan = depth_bias_offset * 65536.0f;
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if (full_update ||
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regs.pa_su_poly_offset_scale != depth_bias_scale_vulkan ||
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regs.pa_su_poly_offset_offset != depth_bias_offset_vulkan) {
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regs.pa_su_poly_offset_scale = depth_bias_scale_vulkan;
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regs.pa_su_poly_offset_offset = depth_bias_offset_vulkan;
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vkCmdSetDepthBias(command_buffer, depth_bias_offset_vulkan, 0.0f,
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depth_bias_scale_vulkan);
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}
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} else if (full_update) {
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regs.pa_su_poly_offset_scale = 0.0f;
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regs.pa_su_poly_offset_offset = 0.0f;
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vkCmdSetDepthBias(command_buffer, 0.0f, 0.0f, 0.0f);
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}
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// VK_DYNAMIC_STATE_BLEND_CONSTANTS
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bool blend_constant_state_dirty = full_update;
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blend_constant_state_dirty |=
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@ -864,9 +924,6 @@ bool PipelineCache::SetDynamicState(VkCommandBuffer command_buffer,
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// VK_DYNAMIC_STATE_LINE_WIDTH
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vkCmdSetLineWidth(command_buffer, 1.0f);
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// VK_DYNAMIC_STATE_DEPTH_BIAS
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vkCmdSetDepthBias(command_buffer, 0.0f, 0.0f, 0.0f);
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// VK_DYNAMIC_STATE_DEPTH_BOUNDS
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vkCmdSetDepthBounds(command_buffer, 0.0f, 1.0f);
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}
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@ -1218,6 +1275,33 @@ PipelineCache::UpdateStatus PipelineCache::UpdateRasterizationState(
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dirty |= SetShadowRegister(®s.multi_prim_ib_reset_index,
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XE_GPU_REG_VGT_MULTI_PRIM_IB_RESET_INDX);
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regs.primitive_type = primitive_type;
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// Vulkan doesn't support separate depth biases for different sides.
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// SetRenderState also accepts only one argument, so they should be rare.
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// The culling mode must match the one in SetDynamicState, so not applying
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// the primitive type exceptions to this (very unlikely to happen anyway).
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bool depth_bias_enable = false;
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uint32_t cull_mode = regs.pa_su_sc_mode_cntl & 0x3;
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if (cull_mode != 1) {
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float depth_bias_scale =
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register_file_->values[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_SCALE].f32;
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float depth_bias_offset =
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register_file_->values[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_OFFSET].f32;
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depth_bias_enable = (depth_bias_scale != 0.0f && depth_bias_offset != 0.0f);
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}
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if (!depth_bias_enable && cull_mode != 2) {
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float depth_bias_scale =
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register_file_->values[XE_GPU_REG_PA_SU_POLY_OFFSET_BACK_SCALE].f32;
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float depth_bias_offset =
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register_file_->values[XE_GPU_REG_PA_SU_POLY_OFFSET_BACK_OFFSET].f32;
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depth_bias_enable = (depth_bias_scale != 0.0f && depth_bias_offset != 0.0f);
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}
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if (regs.pa_su_poly_offset_enable !=
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static_cast<uint32_t>(depth_bias_enable)) {
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regs.pa_su_poly_offset_enable = static_cast<uint32_t>(depth_bias_enable);
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dirty = true;
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}
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XXH64_update(&hash_state_, ®s, sizeof(regs));
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if (!dirty) {
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return UpdateStatus::kCompatible;
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@ -1252,7 +1336,7 @@ PipelineCache::UpdateStatus PipelineCache::UpdateRasterizationState(
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state_info.polygonMode = VK_POLYGON_MODE_FILL;
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}
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switch (regs.pa_su_sc_mode_cntl & 0x3) {
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switch (cull_mode) {
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case 0:
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state_info.cullMode = VK_CULL_MODE_NONE;
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break;
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@ -1280,7 +1364,7 @@ PipelineCache::UpdateStatus PipelineCache::UpdateRasterizationState(
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state_info.cullMode = VK_CULL_MODE_NONE;
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}
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state_info.depthBiasEnable = VK_FALSE;
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state_info.depthBiasEnable = depth_bias_enable ? VK_TRUE : VK_FALSE;
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// Ignored; set dynamically:
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state_info.depthBiasConstantFactor = 0;
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@ -228,6 +228,7 @@ class PipelineCache {
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uint32_t pa_sc_screen_scissor_tl;
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uint32_t pa_sc_screen_scissor_br;
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uint32_t pa_sc_viz_query;
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uint32_t pa_su_poly_offset_enable;
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uint32_t multi_prim_ib_reset_index;
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UpdateRasterizationStateRegisters() { Reset(); }
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@ -275,6 +276,9 @@ class PipelineCache {
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uint32_t rb_surface_info;
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uint32_t pa_su_sc_vtx_cntl;
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// Bias is in Vulkan units because depth format may potentially effect it.
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float pa_su_poly_offset_scale;
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float pa_su_poly_offset_offset;
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uint32_t pa_cl_vte_cntl;
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float pa_cl_vport_xoffset;
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float pa_cl_vport_yoffset;
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