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[CPU] Added constant propagation pass for: OPCODE_AND_NOT

This commit is contained in:
Gliniak 2022-03-07 08:17:51 +01:00 committed by Triang3l
parent 1887ea0795
commit c5e6352c34
2 changed files with 24 additions and 21 deletions
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36
src/xenia/cpu/backend/x64/x64_sequences.cc
View File

@ -2697,34 +2697,28 @@ EMITTER_OPCODE_TABLE(OPCODE_AND, AND_I8, AND_I16, AND_I32, AND_I64, AND_V128);
template <typename SEQ, typename REG, typename ARGS> template <typename SEQ, typename REG, typename ARGS>
void EmitAndNotXX(X64Emitter& e, const ARGS& i) { void EmitAndNotXX(X64Emitter& e, const ARGS& i) {
if (i.src1.is_constant) { if (i.src1.is_constant) {
if (i.src2.is_constant) { // src1 constant.
// Both constants. // `and` instruction only supports up to 32-bit immediate constants
e.mov(i.dest, i.src1.constant() & ~i.src2.constant()); // 64-bit constants will need a temp register
} else { if (i.dest.reg().getBit() == 64) {
// src1 constant. auto temp = GetTempReg<typename decltype(i.src1)::reg_type>(e);
e.mov(temp, i.src1.constant());
// `and` instruction only supports up to 32-bit immediate constants if (e.IsFeatureEnabled(kX64EmitBMI1)) {
// 64-bit constants will need a temp register if (i.dest.reg().getBit() == 64) {
if (i.dest.reg().getBit() == 64) { e.andn(i.dest.reg().cvt64(), i.src2.reg().cvt64(), temp.cvt64());
auto temp = GetTempReg<typename decltype(i.src1)::reg_type>(e);
e.mov(temp, i.src1.constant());
if (e.IsFeatureEnabled(kX64EmitBMI1)) {
if (i.dest.reg().getBit() == 64) {
e.andn(i.dest.reg().cvt64(), i.src2.reg().cvt64(), temp.cvt64());
} else {
e.andn(i.dest.reg().cvt32(), i.src2.reg().cvt32(), temp.cvt32());
}
} else { } else {
e.mov(i.dest, i.src2); e.andn(i.dest.reg().cvt32(), i.src2.reg().cvt32(), temp.cvt32());
e.not_(i.dest);
e.and_(i.dest, temp);
} }
} else { } else {
e.mov(i.dest, i.src2); e.mov(i.dest, i.src2);
e.not_(i.dest); e.not_(i.dest);
e.and_(i.dest, uint32_t(i.src1.constant())); e.and_(i.dest, temp);
} }
} else {
e.mov(i.dest, i.src2);
e.not_(i.dest);
e.and_(i.dest, uint32_t(i.src1.constant()));
} }
} else if (i.src2.is_constant) { } else if (i.src2.is_constant) {
// src2 constant. // src2 constant.

9
src/xenia/cpu/compiler/passes/constant_propagation_pass.cc
View File

@ -648,6 +648,15 @@ bool ConstantPropagationPass::Run(HIRBuilder* builder, bool& result) {
result = true; result = true;
} }
break; break;
case OPCODE_AND_NOT:
if (i->src1.value->IsConstant() && i->src2.value->IsConstant()) {
v->set_from(i->src2.value);
v->Not();
v->And(i->src1.value);
i->Remove();
result = true;
}
break;
case OPCODE_OR: case OPCODE_OR:
if (i->src1.value->IsConstant() && i->src2.value->IsConstant()) { if (i->src1.value->IsConstant() && i->src2.value->IsConstant()) {
v->set_from(i->src1.value); v->set_from(i->src1.value);