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Fixing div.

This commit is contained in:
Ben Vanik 2014-02-06 22:18:15 -08:00
parent 5309356908
commit c5b70e615f
1 changed files with 2 additions and 0 deletions
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2
src/alloy/backend/x64/lowering/lowering_sequences.cc
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@ -2199,7 +2199,9 @@ table->AddSequence(OPCODE_DIV, [](X64Emitter& e, Instr*& i) {
// RAX = value, RDX = clobbered
// TODO(benvanik): make the register allocator put dest_src in RAX?
auto Nax = LIKE_REG(e.rax, dest_src);
auto Ndx = LIKE_REG(e.rdx, dest_src);
e.mov(Nax, dest_src);
e.xor(Ndx, Ndx);
if (i.flags & ARITHMETIC_UNSIGNED) {
e.div(src);
} else {